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Rev 1246 Rev 1268
Line 46... Line 46...
46 
	int blank_width;
 46 
	int blank_width;
47 
	u32 scale, inc, crtc_more_cntl;
 47 
	u32 scale, inc, crtc_more_cntl;
48 
	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
 48 
	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
49 
	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
 49 
	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
50 
	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
 50 
	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
51 
	struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;
 51 
	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
Line 52... Line 52...
52 
 
 52 
 
53 
	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
 53 
	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
54 
		(RADEON_VERT_STRETCH_RESERVED |
 54 
		(RADEON_VERT_STRETCH_RESERVED |
55 
		 RADEON_VERT_AUTO_RATIO_INC);
 55 
		 RADEON_VERT_AUTO_RATIO_INC);
Line 93... Line 93...
93 
				 ? RADEON_CRTC_V_SYNC_POL
 93 
				 ? RADEON_CRTC_V_SYNC_POL
94 
				 : 0));
 94 
				 : 0));
Line 95... Line 95...
95 
 
 95 
 
Line 96... Line 96...
96 
	fp_horz_vert_active = 0;
 96 
	fp_horz_vert_active = 0;
97 
 
 97 
 
98 
	if (native_mode->panel_xres == 0 ||
 98 
	if (native_mode->hdisplay == 0 ||
99 
	    native_mode->panel_yres == 0) {
 99 
	    native_mode->vdisplay == 0) {
100 
		hscale = false;
 100 
		hscale = false;
101 
		vscale = false;
 101 
		vscale = false;
102 
	} else {
 102 
	} else {
103 
		if (xres > native_mode->panel_xres)
 103 
		if (xres > native_mode->hdisplay)
104 
			xres = native_mode->panel_xres;
 104 
			xres = native_mode->hdisplay;
Line 105... Line 105...
105 
		if (yres > native_mode->panel_yres)
 105 
		if (yres > native_mode->vdisplay)
106 
			yres = native_mode->panel_yres;
 106 
			yres = native_mode->vdisplay;
107 
 
 107 
 
108 
		if (xres == native_mode->panel_xres)
 108 
		if (xres == native_mode->hdisplay)
109 
			hscale = false;
 109 
			hscale = false;
Line 110... Line 110...
110 
		if (yres == native_mode->panel_yres)
 110 
		if (yres == native_mode->vdisplay)
111 
			vscale = false;
 111 
			vscale = false;
Line 117... Line 117...
117 
		if (!hscale)
 117 
		if (!hscale)
118 
			fp_horz_stretch |= ((xres/8-1) << 16);
 118 
			fp_horz_stretch |= ((xres/8-1) << 16);
119 
		else {
 119 
		else {
120 
			inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 120 
			inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
121 
			scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 121 
			scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
122 
				/ native_mode->panel_xres + 1;
 122 
				/ native_mode->hdisplay + 1;
123 
			fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 123 
			fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
124 
					RADEON_HORZ_STRETCH_BLEND |
 124 
					RADEON_HORZ_STRETCH_BLEND |
125 
					RADEON_HORZ_STRETCH_ENABLE |
 125 
					RADEON_HORZ_STRETCH_ENABLE |
126 
					((native_mode->panel_xres/8-1) << 16));
 126 
					((native_mode->hdisplay/8-1) << 16));
127 
		}
 127 
		}
Line 128... Line 128...
128 
 
 128 
 
129 
		if (!vscale)
 129 
		if (!vscale)
130 
			fp_vert_stretch |= ((yres-1) << 12);
 130 
			fp_vert_stretch |= ((yres-1) << 12);
131 
		else {
 131 
		else {
132 
			inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 132 
			inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
133 
			scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 133 
			scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
134 
				/ native_mode->panel_yres + 1;
 134 
				/ native_mode->vdisplay + 1;
135 
			fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 135 
			fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
136 
					RADEON_VERT_STRETCH_ENABLE |
 136 
					RADEON_VERT_STRETCH_ENABLE |
137 
					RADEON_VERT_STRETCH_BLEND |
 137 
					RADEON_VERT_STRETCH_BLEND |
138 
					((native_mode->panel_yres-1) << 12));
 138 
					((native_mode->vdisplay-1) << 12));
139 
		}
 139 
		}
140 
		break;
 140 
		break;
141 
	case RMX_CENTER:
 141 
	case RMX_CENTER:
142 
		fp_horz_stretch |= ((xres/8-1) << 16);
 142 
		fp_horz_stretch |= ((xres/8-1) << 16);
Line 173... Line 173...
173 
					| ((vsync_wid & 0x1f) << 16)
 173 
					| ((vsync_wid & 0x1f) << 16)
174 
					| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 174 
					| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
175 
						? RADEON_CRTC_V_SYNC_POL
 175 
						? RADEON_CRTC_V_SYNC_POL
176 
						: 0)));
 176 
						: 0)));
Line 177... Line 177...
177 
 
 177 
 
178 
		fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) |
 178 
		fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
179 
				(((native_mode->panel_xres / 8) & 0x1ff) << 16));
 179 
				(((native_mode->hdisplay / 8) & 0x1ff) << 16));
180 
		break;
 180 
		break;
181 
	case RMX_OFF:
 181 
	case RMX_OFF:
182 
	default:
 182 
	default:
183 
		fp_horz_stretch |= ((xres/8-1) << 16);
 183 
		fp_horz_stretch |= ((xres/8-1) << 16);
Line 532... Line 532...
532 
 
 532 
 
533 
	if (old_fb && old_fb != crtc->fb) {
 533 
	if (old_fb && old_fb != crtc->fb) {
534 
		radeon_fb = to_radeon_framebuffer(old_fb);
 534 
		radeon_fb = to_radeon_framebuffer(old_fb);
535 
//       radeon_gem_object_unpin(radeon_fb->obj);
 535 
//       radeon_gem_object_unpin(radeon_fb->obj);
- 
 
 536 
	}
- 
 
 537 
 
- 
 
 538 
	/* Bytes per pixel may have changed */
- 
 
 539 
	radeon_bandwidth_update(rdev);
536 
	}
 540 
 
537 
	return 0;
 541 
	return 0;
Line 538... Line 542...
538 
}
 542 
}
539 
 
 543 
 
Line 664... Line 668...
664 
		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 668 
		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
665 
		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 669 
		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
Line 666... Line 670...
666 
 
 670 
 
667 
		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 671 
		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
- 
 
 672 
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
- 
 
 673 
 
- 
 
 674 
		WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
668 
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 675 
		WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
669 
	} else {
 676 
	} else {
670 
		uint32_t crtc_gen_cntl;
 677 
		uint32_t crtc_gen_cntl;
671 
		uint32_t crtc_ext_cntl;
 678 
		uint32_t crtc_ext_cntl;
Line 1015... Line 1022...
1015 
				 struct drm_display_mode *mode,
 1022 
				 struct drm_display_mode *mode,
1016 
				 struct drm_display_mode *adjusted_mode,
 1023 
				 struct drm_display_mode *adjusted_mode,
1017 
				 int x, int y, struct drm_framebuffer *old_fb)
 1024 
				 int x, int y, struct drm_framebuffer *old_fb)
1018 
{
 1025 
{
1019 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 1026 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1020 
	struct drm_device *dev = crtc->dev;
 - 
 
1021 
	struct radeon_device *rdev = dev->dev_private;
 - 
 
Line 1022... Line 1027...
1022 
 
 1027 
 
1023 
	/* TODO TV */
 1028 
	/* TODO TV */
1024 
	radeon_crtc_set_base(crtc, x, y, old_fb);
 1029 
	radeon_crtc_set_base(crtc, x, y, old_fb);
1025 
	radeon_set_crtc_timing(crtc, adjusted_mode);
 1030 
	radeon_set_crtc_timing(crtc, adjusted_mode);
1026 
	radeon_set_pll(crtc, adjusted_mode);
 - 
 
1027 
	radeon_bandwidth_update(rdev);
 1031 
	radeon_set_pll(crtc, adjusted_mode);
1028 
	if (radeon_crtc->crtc_id == 0) {
 1032 
	if (radeon_crtc->crtc_id == 0) {
1029 
		radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
 1033 
		radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1030 
	} else {
 1034 
	} else {
1031 
		if (radeon_crtc->rmx_type != RMX_OFF) {
 1035 
		if (radeon_crtc->rmx_type != RMX_OFF) {