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Rev 3192 Rev 3764
Line 247... Line 247...
247
	}
247
	}
248
	t = offset / RADEON_GPU_PAGE_SIZE;
248
	t = offset / RADEON_GPU_PAGE_SIZE;
249
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
249
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
250
	for (i = 0; i < pages; i++, p++) {
250
	for (i = 0; i < pages; i++, p++) {
251
		if (rdev->gart.pages[p]) {
251
		if (rdev->gart.pages[p]) {
252
//           pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
-
 
253
//                      PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-
 
254
			rdev->gart.pages[p] = NULL;
252
			rdev->gart.pages[p] = NULL;
255
			rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
253
			rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
256
			page_base = rdev->gart.pages_addr[p];
254
			page_base = rdev->gart.pages_addr[p];
257
			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
255
			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
258
				if (rdev->gart.ptr) {
256
				if (rdev->gart.ptr) {
Line 938... Line 936...
938
 *
936
 *
939
 * Global and local mutex must be locked!
937
 * Global and local mutex must be locked!
940
 */
938
 */
941
static int radeon_vm_update_pdes(struct radeon_device *rdev,
939
static int radeon_vm_update_pdes(struct radeon_device *rdev,
942
				 struct radeon_vm *vm,
940
				 struct radeon_vm *vm,
-
 
941
				 struct radeon_ib *ib,
943
				 uint64_t start, uint64_t end)
942
				 uint64_t start, uint64_t end)
944
{
943
{
945
	static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
944
	static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
Line 946... Line 945...
946
 
945
 
Line 980... Line 979...
980
 
979
 
981
		if (((last_pde + 8 * count) != pde) ||
980
		if (((last_pde + 8 * count) != pde) ||
Line 982... Line 981...
982
		    ((last_pt + incr * count) != pt)) {
981
		    ((last_pt + incr * count) != pt)) {
983
 
982
 
984
			if (count) {
983
			if (count) {
985
				radeon_asic_vm_set_page(rdev, last_pde,
984
				radeon_asic_vm_set_page(rdev, ib, last_pde,
986
							last_pt, count, incr,
985
							last_pt, count, incr,
Line 987... Line 986...
987
							RADEON_VM_PAGE_VALID);
986
							RADEON_VM_PAGE_VALID);
Line 994... Line 993...
994
			++count;
993
			++count;
995
		}
994
		}
996
	}
995
	}
Line 997... Line 996...
997
 
996
 
998
	if (count) {
997
	if (count) {
999
		radeon_asic_vm_set_page(rdev, last_pde, last_pt, count,
998
		radeon_asic_vm_set_page(rdev, ib, last_pde, last_pt, count,
Line 1000... Line 999...
1000
					incr, RADEON_VM_PAGE_VALID);
999
					incr, RADEON_VM_PAGE_VALID);
Line 1001... Line 1000...
1001
 
1000
 
Line 1018... Line 1017...
1018
 *
1017
 *
1019
 * Global and local mutex must be locked!
1018
 * Global and local mutex must be locked!
1020
 */
1019
 */
1021
static void radeon_vm_update_ptes(struct radeon_device *rdev,
1020
static void radeon_vm_update_ptes(struct radeon_device *rdev,
1022
				  struct radeon_vm *vm,
1021
				  struct radeon_vm *vm,
-
 
1022
				  struct radeon_ib *ib,
1023
				  uint64_t start, uint64_t end,
1023
				  uint64_t start, uint64_t end,
1024
				  uint64_t dst, uint32_t flags)
1024
				  uint64_t dst, uint32_t flags)
1025
{
1025
{
1026
	static const uint64_t mask = RADEON_VM_PTE_COUNT - 1;
1026
	static const uint64_t mask = RADEON_VM_PTE_COUNT - 1;
Line 1047... Line 1047...
1047
		pte += (addr & mask) * 8;
1047
		pte += (addr & mask) * 8;
Line 1048... Line 1048...
1048
 
1048
 
Line 1049... Line 1049...
1049
		if ((last_pte + 8 * count) != pte) {
1049
		if ((last_pte + 8 * count) != pte) {
1050
 
1050
 
1051
			if (count) {
1051
			if (count) {
1052
				radeon_asic_vm_set_page(rdev, last_pte,
1052
				radeon_asic_vm_set_page(rdev, ib, last_pte,
1053
							last_dst, count,
1053
							last_dst, count,
1054
							RADEON_GPU_PAGE_SIZE,
1054
							RADEON_GPU_PAGE_SIZE,
Line 1065... Line 1065...
1065
		addr += nptes;
1065
		addr += nptes;
1066
		dst += nptes * RADEON_GPU_PAGE_SIZE;
1066
		dst += nptes * RADEON_GPU_PAGE_SIZE;
1067
	}
1067
	}
Line 1068... Line 1068...
1068
 
1068
 
1069
	if (count) {
1069
	if (count) {
-
 
1070
		radeon_asic_vm_set_page(rdev, ib, last_pte,
1070
		radeon_asic_vm_set_page(rdev, last_pte,	last_dst, count,
1071
					last_dst, count,
1071
					RADEON_GPU_PAGE_SIZE, flags);
1072
					RADEON_GPU_PAGE_SIZE, flags);
1072
	}
1073
	}
Line 1073... Line 1074...
1073
}
1074
}
Line 1089... Line 1090...
1089
			    struct radeon_vm *vm,
1090
			    struct radeon_vm *vm,
1090
			    struct radeon_bo *bo,
1091
			    struct radeon_bo *bo,
1091
			    struct ttm_mem_reg *mem)
1092
			    struct ttm_mem_reg *mem)
1092
{
1093
{
1093
	unsigned ridx = rdev->asic->vm.pt_ring_index;
1094
	unsigned ridx = rdev->asic->vm.pt_ring_index;
1094
	struct radeon_ring *ring = &rdev->ring[ridx];
-
 
1095
	struct radeon_semaphore *sem = NULL;
1095
	struct radeon_ib ib;
1096
	struct radeon_bo_va *bo_va;
1096
	struct radeon_bo_va *bo_va;
1097
	unsigned nptes, npdes, ndw;
1097
	unsigned nptes, npdes, ndw;
1098
	uint64_t addr;
1098
	uint64_t addr;
1099
	int r;
1099
	int r;
Line 1133... Line 1133...
1133
	} else {
1133
	} else {
1134
		addr = 0;
1134
		addr = 0;
1135
		bo_va->valid = false;
1135
		bo_va->valid = false;
1136
	}
1136
	}
Line 1137... Line -...
1137
 
-
 
1138
	if (vm->fence && radeon_fence_signaled(vm->fence)) {
-
 
1139
		radeon_fence_unref(&vm->fence);
-
 
1140
	}
-
 
1141
 
-
 
1142
	if (vm->fence && vm->fence->ring != ridx) {
-
 
1143
		r = radeon_semaphore_create(rdev, &sem);
-
 
1144
		if (r) {
-
 
1145
			return r;
-
 
1146
		}
-
 
1147
	}
-
 
1148
 
1137
 
Line 1149... Line 1138...
1149
	nptes = radeon_bo_ngpu_pages(bo);
1138
	nptes = radeon_bo_ngpu_pages(bo);
1150
 
1139
 
Line 1151... Line -...
1151
	/* assume two extra pdes in case the mapping overlaps the borders */
-
 
1152
	npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 2;
1140
	/* assume two extra pdes in case the mapping overlaps the borders */
1153
 
1141
	npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 2;
Line 1154... Line 1142...
1154
	/* estimate number of dw needed */
1142
 
1155
	/* semaphore, fence and padding */
1143
	/* padding, etc. */
1156
	ndw = 32;
1144
	ndw = 64;
1157
 
1145
 
Line 1170... Line 1158...
1170
	ndw += (npdes >> 11) * 4;
1158
	ndw += (npdes >> 11) * 4;
Line 1171... Line 1159...
1171
 
1159
 
1172
	/* reserve space for pde addresses */
1160
	/* reserve space for pde addresses */
Line 1173... Line 1161...
1173
	ndw += npdes * 2;
1161
	ndw += npdes * 2;
1174
 
1162
 
1175
	r = radeon_ring_lock(rdev, ring, ndw);
1163
	/* update too big for an IB */
1176
	if (r) {
-
 
Line 1177... Line -...
1177
		return r;
-
 
1178
	}
1164
	if (ndw > 0xfffff)
1179
 
1165
		return -ENOMEM;
1180
	if (sem && radeon_fence_need_sync(vm->fence, ridx)) {
-
 
Line 1181... Line 1166...
1181
		radeon_semaphore_sync_rings(rdev, sem, vm->fence->ring, ridx);
1166
 
1182
		radeon_fence_note_sync(vm->fence, ridx);
1167
	r = radeon_ib_get(rdev, ridx, &ib, NULL, ndw * 4);
1183
	}
1168
	ib.length_dw = 0;
1184
 
1169
 
1185
	r = radeon_vm_update_pdes(rdev, vm, bo_va->soffset, bo_va->eoffset);
1170
	r = radeon_vm_update_pdes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset);
Line 1186... Line 1171...
1186
	if (r) {
1171
	if (r) {
1187
		radeon_ring_unlock_undo(rdev, ring);
1172
		radeon_ib_free(rdev, &ib);
Line 1188... Line 1173...
1188
		return r;
1173
		return r;
1189
	}
1174
	}
1190
 
1175
 
1191
	radeon_vm_update_ptes(rdev, vm, bo_va->soffset, bo_va->eoffset,
1176
	radeon_vm_update_ptes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset,
1192
			      addr, bo_va->flags);
1177
			      addr, bo_va->flags);
1193
 
1178
 
1194
	radeon_fence_unref(&vm->fence);
1179
	radeon_ib_sync_to(&ib, vm->fence);
-
 
1180
	r = radeon_ib_schedule(rdev, &ib, NULL);
1195
	r = radeon_fence_emit(rdev, &vm->fence, ridx);
1181
	if (r) {
1196
	if (r) {
1182
		radeon_ib_free(rdev, &ib);
Line 1197... Line 1183...
1197
		radeon_ring_unlock_undo(rdev, ring);
1183
		return r;
1198
		return r;
1184
	}
Line 1218... Line 1204...
1218
 * Object have to be reserved!
1204
 * Object have to be reserved!
1219
 */
1205
 */
1220
int radeon_vm_bo_rmv(struct radeon_device *rdev,
1206
int radeon_vm_bo_rmv(struct radeon_device *rdev,
1221
		     struct radeon_bo_va *bo_va)
1207
		     struct radeon_bo_va *bo_va)
1222
{
1208
{
1223
	int r;
1209
	int r = 0;
Line 1224... Line 1210...
1224
 
1210
 
1225
	mutex_lock(&rdev->vm_manager.lock);
1211
	mutex_lock(&rdev->vm_manager.lock);
-
 
1212
	mutex_lock(&bo_va->vm->mutex);
1226
	mutex_lock(&bo_va->vm->mutex);
1213
	if (bo_va->soffset) {
-
 
1214
	r = radeon_vm_bo_update_pte(rdev, bo_va->vm, bo_va->bo, NULL);
1227
	r = radeon_vm_bo_update_pte(rdev, bo_va->vm, bo_va->bo, NULL);
1215
	}
1228
	mutex_unlock(&rdev->vm_manager.lock);
1216
	mutex_unlock(&rdev->vm_manager.lock);
1229
	list_del(&bo_va->vm_list);
1217
	list_del(&bo_va->vm_list);
1230
	mutex_unlock(&bo_va->vm->mutex);
1218
	mutex_unlock(&bo_va->vm->mutex);