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| Rev 1321 | Rev 1404 | ||
|---|---|---|---|
| Line 138... | Line 138... | ||
| 138 | } |
138 | } |
| Line 139... | Line 139... | ||
| 139 | 139 | ||
| 140 | 140 | ||
| 141 | bool radeon_fence_signaled(struct radeon_fence *fence) |
- | |
| 142 | { |
141 | bool radeon_fence_signaled(struct radeon_fence *fence) |
| 143 | struct radeon_device *rdev = fence->rdev; |
142 | { |
| Line 144... | Line 143... | ||
| 144 | unsigned long irq_flags; |
143 | unsigned long irq_flags; |
| 145 | bool signaled = false; |
144 | bool signaled = false; |
| 146 | 145 | ||
| 147 | if (rdev->gpu_lockup) { |
146 | if (!fence) |
| 148 | return true; |
147 | return true; |
| 149 | } |
148 | |
| 150 | if (fence == NULL) { |
149 | if (fence->rdev->gpu_lockup) |
| 151 | return true; |
150 | return true; |
| 152 | } |
151 | |
| 153 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
152 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
| 154 | signaled = fence->signaled; |
153 | signaled = fence->signaled; |
| Line 322... | Line 321... | ||
| 322 | int r; |
321 | int r; |
| Line 323... | Line 322... | ||
| 323 | 322 | ||
| 324 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
323 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
| 325 | r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); |
324 | r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); |
| 326 | if (r) { |
325 | if (r) { |
| 327 | DRM_ERROR("Fence failed to get a scratch register."); |
326 | dev_err(rdev->dev, "fence failed to get scratch register\n"); |
| 328 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
327 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
| 329 | return r; |
328 | return r; |
| 330 | } |
329 | } |
| 331 | WREG32(rdev->fence_drv.scratch_reg, 0); |
330 | WREG32(rdev->fence_drv.scratch_reg, 0); |
| 332 | atomic_set(&rdev->fence_drv.seq, 0); |
331 | atomic_set(&rdev->fence_drv.seq, 0); |
| 333 | INIT_LIST_HEAD(&rdev->fence_drv.created); |
332 | INIT_LIST_HEAD(&rdev->fence_drv.created); |
| 334 | INIT_LIST_HEAD(&rdev->fence_drv.emited); |
333 | INIT_LIST_HEAD(&rdev->fence_drv.emited); |
| 335 | INIT_LIST_HEAD(&rdev->fence_drv.signaled); |
334 | INIT_LIST_HEAD(&rdev->fence_drv.signaled); |
| 336 | rdev->fence_drv.count_timeout = 0; |
335 | rdev->fence_drv.count_timeout = 0; |
| - | 336 | init_waitqueue_head(&rdev->fence_drv.queue); |
|
| 337 | init_waitqueue_head(&rdev->fence_drv.queue); |
337 | rdev->fence_drv.initialized = true; |
| 338 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
338 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
| 339 | if (radeon_debugfs_fence_init(rdev)) { |
339 | if (radeon_debugfs_fence_init(rdev)) { |
| 340 | DRM_ERROR("Failed to register debugfs file for fence !\n"); |
340 | dev_err(rdev->dev, "fence debugfs file creation failed\n"); |
| 341 | } |
341 | } |
| 342 | return 0; |
342 | return 0; |
| Line 343... | Line 343... | ||
| 343 | } |
343 | } |
| 344 | 344 | ||
| 345 | void radeon_fence_driver_fini(struct radeon_device *rdev) |
345 | void radeon_fence_driver_fini(struct radeon_device *rdev) |
| Line -... | Line 346... | ||
| - | 346 | { |
|
| - | 347 | unsigned long irq_flags; |
|
| 346 | { |
348 | |
| 347 | unsigned long irq_flags; |
349 | if (!rdev->fence_drv.initialized) |
| 348 | 350 | return; |
|
| 349 | wake_up_all(&rdev->fence_drv.queue); |
351 | wake_up_all(&rdev->fence_drv.queue); |
| 350 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
352 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
| 351 | radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); |
353 | radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); |
| Line 352... | Line 354... | ||
| 352 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
354 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
| 353 | DRM_INFO("radeon: fence finalized\n"); |
355 | rdev->fence_drv.initialized = false; |