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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include "drmP.h" |
26 | #include "drmP.h" |
27 | #include "drm_crtc_helper.h" |
27 | #include "drm_crtc_helper.h" |
28 | #include "radeon_drm.h" |
28 | #include "radeon_drm.h" |
29 | #include "radeon.h" |
29 | #include "radeon.h" |
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | 31 | ||
32 | extern int atom_debug; |
32 | extern int atom_debug; |
33 | 33 | ||
34 | /* evil but including atombios.h is much worse */ |
34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
36 | struct drm_display_mode *mode); |
36 | struct drm_display_mode *mode); |
37 | 37 | ||
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
39 | { |
39 | { |
40 | struct drm_device *dev = encoder->dev; |
40 | struct drm_device *dev = encoder->dev; |
41 | struct radeon_device *rdev = dev->dev_private; |
41 | struct radeon_device *rdev = dev->dev_private; |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
43 | struct drm_encoder *clone_encoder; |
43 | struct drm_encoder *clone_encoder; |
44 | uint32_t index_mask = 0; |
44 | uint32_t index_mask = 0; |
45 | int count; |
45 | int count; |
46 | 46 | ||
47 | /* DIG routing gets problematic */ |
47 | /* DIG routing gets problematic */ |
48 | if (rdev->family >= CHIP_R600) |
48 | if (rdev->family >= CHIP_R600) |
49 | return index_mask; |
49 | return index_mask; |
50 | /* LVDS/TV are too wacky */ |
50 | /* LVDS/TV are too wacky */ |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
52 | return index_mask; |
52 | return index_mask; |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) |
55 | return index_mask; |
55 | return index_mask; |
56 | 56 | ||
57 | count = -1; |
57 | count = -1; |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); |
60 | count++; |
60 | count++; |
61 | 61 | ||
62 | if (clone_encoder == encoder) |
62 | if (clone_encoder == encoder) |
63 | continue; |
63 | continue; |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
65 | continue; |
65 | continue; |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) |
67 | continue; |
67 | continue; |
68 | else |
68 | else |
69 | index_mask |= (1 << count); |
69 | index_mask |= (1 << count); |
70 | } |
70 | } |
71 | return index_mask; |
71 | return index_mask; |
72 | } |
72 | } |
73 | 73 | ||
74 | void radeon_setup_encoder_clones(struct drm_device *dev) |
74 | void radeon_setup_encoder_clones(struct drm_device *dev) |
75 | { |
75 | { |
76 | struct drm_encoder *encoder; |
76 | struct drm_encoder *encoder; |
77 | 77 | ||
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); |
80 | } |
80 | } |
81 | } |
81 | } |
82 | 82 | ||
83 | uint32_t |
83 | uint32_t |
84 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
84 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
85 | { |
85 | { |
86 | struct radeon_device *rdev = dev->dev_private; |
86 | struct radeon_device *rdev = dev->dev_private; |
87 | uint32_t ret = 0; |
87 | uint32_t ret = 0; |
88 | 88 | ||
89 | switch (supported_device) { |
89 | switch (supported_device) { |
90 | case ATOM_DEVICE_CRT1_SUPPORT: |
90 | case ATOM_DEVICE_CRT1_SUPPORT: |
91 | case ATOM_DEVICE_TV1_SUPPORT: |
91 | case ATOM_DEVICE_TV1_SUPPORT: |
92 | case ATOM_DEVICE_TV2_SUPPORT: |
92 | case ATOM_DEVICE_TV2_SUPPORT: |
93 | case ATOM_DEVICE_CRT2_SUPPORT: |
93 | case ATOM_DEVICE_CRT2_SUPPORT: |
94 | case ATOM_DEVICE_CV_SUPPORT: |
94 | case ATOM_DEVICE_CV_SUPPORT: |
95 | switch (dac) { |
95 | switch (dac) { |
96 | case 1: /* dac a */ |
96 | case 1: /* dac a */ |
97 | if ((rdev->family == CHIP_RS300) || |
97 | if ((rdev->family == CHIP_RS300) || |
98 | (rdev->family == CHIP_RS400) || |
98 | (rdev->family == CHIP_RS400) || |
99 | (rdev->family == CHIP_RS480)) |
99 | (rdev->family == CHIP_RS480)) |
100 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
100 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
101 | else if (ASIC_IS_AVIVO(rdev)) |
101 | else if (ASIC_IS_AVIVO(rdev)) |
102 | ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; |
102 | ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; |
103 | else |
103 | else |
104 | ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; |
104 | ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; |
105 | break; |
105 | break; |
106 | case 2: /* dac b */ |
106 | case 2: /* dac b */ |
107 | if (ASIC_IS_AVIVO(rdev)) |
107 | if (ASIC_IS_AVIVO(rdev)) |
108 | ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; |
108 | ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; |
109 | else { |
109 | else { |
110 | /*if (rdev->family == CHIP_R200) |
110 | /*if (rdev->family == CHIP_R200) |
111 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
111 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
112 | else*/ |
112 | else*/ |
113 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
113 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
114 | } |
114 | } |
115 | break; |
115 | break; |
116 | case 3: /* external dac */ |
116 | case 3: /* external dac */ |
117 | if (ASIC_IS_AVIVO(rdev)) |
117 | if (ASIC_IS_AVIVO(rdev)) |
118 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
118 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
119 | else |
119 | else |
120 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
120 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
121 | break; |
121 | break; |
122 | } |
122 | } |
123 | break; |
123 | break; |
124 | case ATOM_DEVICE_LCD1_SUPPORT: |
124 | case ATOM_DEVICE_LCD1_SUPPORT: |
125 | if (ASIC_IS_AVIVO(rdev)) |
125 | if (ASIC_IS_AVIVO(rdev)) |
126 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
126 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
127 | else |
127 | else |
128 | ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; |
128 | ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; |
129 | break; |
129 | break; |
130 | case ATOM_DEVICE_DFP1_SUPPORT: |
130 | case ATOM_DEVICE_DFP1_SUPPORT: |
131 | if ((rdev->family == CHIP_RS300) || |
131 | if ((rdev->family == CHIP_RS300) || |
132 | (rdev->family == CHIP_RS400) || |
132 | (rdev->family == CHIP_RS400) || |
133 | (rdev->family == CHIP_RS480)) |
133 | (rdev->family == CHIP_RS480)) |
134 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
134 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
135 | else if (ASIC_IS_AVIVO(rdev)) |
135 | else if (ASIC_IS_AVIVO(rdev)) |
136 | ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; |
136 | ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; |
137 | else |
137 | else |
138 | ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; |
138 | ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; |
139 | break; |
139 | break; |
140 | case ATOM_DEVICE_LCD2_SUPPORT: |
140 | case ATOM_DEVICE_LCD2_SUPPORT: |
141 | case ATOM_DEVICE_DFP2_SUPPORT: |
141 | case ATOM_DEVICE_DFP2_SUPPORT: |
142 | if ((rdev->family == CHIP_RS600) || |
142 | if ((rdev->family == CHIP_RS600) || |
143 | (rdev->family == CHIP_RS690) || |
143 | (rdev->family == CHIP_RS690) || |
144 | (rdev->family == CHIP_RS740)) |
144 | (rdev->family == CHIP_RS740)) |
145 | ret = ENCODER_INTERNAL_DDI_ENUM_ID1; |
145 | ret = ENCODER_INTERNAL_DDI_ENUM_ID1; |
146 | else if (ASIC_IS_AVIVO(rdev)) |
146 | else if (ASIC_IS_AVIVO(rdev)) |
147 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
147 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
148 | else |
148 | else |
149 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
149 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
150 | break; |
150 | break; |
151 | case ATOM_DEVICE_DFP3_SUPPORT: |
151 | case ATOM_DEVICE_DFP3_SUPPORT: |
152 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
152 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
153 | break; |
153 | break; |
154 | } |
154 | } |
155 | 155 | ||
156 | return ret; |
156 | return ret; |
157 | } |
157 | } |
158 | 158 | ||
159 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
159 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
160 | { |
160 | { |
161 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
161 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
162 | switch (radeon_encoder->encoder_id) { |
162 | switch (radeon_encoder->encoder_id) { |
163 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
163 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
164 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
164 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
167 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
167 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
169 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
169 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
173 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
173 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
174 | return true; |
174 | return true; |
175 | default: |
175 | default: |
176 | return false; |
176 | return false; |
177 | } |
177 | } |
178 | } |
178 | } |
179 | 179 | ||
180 | void |
180 | void |
181 | radeon_link_encoder_connector(struct drm_device *dev) |
181 | radeon_link_encoder_connector(struct drm_device *dev) |
182 | { |
182 | { |
183 | struct drm_connector *connector; |
183 | struct drm_connector *connector; |
184 | struct radeon_connector *radeon_connector; |
184 | struct radeon_connector *radeon_connector; |
185 | struct drm_encoder *encoder; |
185 | struct drm_encoder *encoder; |
186 | struct radeon_encoder *radeon_encoder; |
186 | struct radeon_encoder *radeon_encoder; |
187 | 187 | ||
188 | /* walk the list and link encoders to connectors */ |
188 | /* walk the list and link encoders to connectors */ |
189 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
189 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
190 | radeon_connector = to_radeon_connector(connector); |
190 | radeon_connector = to_radeon_connector(connector); |
191 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
191 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
192 | radeon_encoder = to_radeon_encoder(encoder); |
192 | radeon_encoder = to_radeon_encoder(encoder); |
193 | if (radeon_encoder->devices & radeon_connector->devices) |
193 | if (radeon_encoder->devices & radeon_connector->devices) |
194 | drm_mode_connector_attach_encoder(connector, encoder); |
194 | drm_mode_connector_attach_encoder(connector, encoder); |
195 | } |
195 | } |
196 | } |
196 | } |
197 | } |
197 | } |
198 | 198 | ||
199 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
199 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
200 | { |
200 | { |
201 | struct drm_device *dev = encoder->dev; |
201 | struct drm_device *dev = encoder->dev; |
202 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
202 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
203 | struct drm_connector *connector; |
203 | struct drm_connector *connector; |
204 | 204 | ||
205 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
205 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
206 | if (connector->encoder == encoder) { |
206 | if (connector->encoder == encoder) { |
207 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
207 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
208 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
208 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
209 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
209 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
210 | radeon_encoder->active_device, radeon_encoder->devices, |
210 | radeon_encoder->active_device, radeon_encoder->devices, |
211 | radeon_connector->devices, encoder->encoder_type); |
211 | radeon_connector->devices, encoder->encoder_type); |
212 | } |
212 | } |
213 | } |
213 | } |
214 | } |
214 | } |
215 | 215 | ||
216 | struct drm_connector * |
216 | struct drm_connector * |
217 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
217 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
218 | { |
218 | { |
219 | struct drm_device *dev = encoder->dev; |
219 | struct drm_device *dev = encoder->dev; |
220 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
220 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
221 | struct drm_connector *connector; |
221 | struct drm_connector *connector; |
222 | struct radeon_connector *radeon_connector; |
222 | struct radeon_connector *radeon_connector; |
223 | 223 | ||
224 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
224 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
225 | radeon_connector = to_radeon_connector(connector); |
225 | radeon_connector = to_radeon_connector(connector); |
226 | if (radeon_encoder->active_device & radeon_connector->devices) |
226 | if (radeon_encoder->active_device & radeon_connector->devices) |
227 | return connector; |
227 | return connector; |
228 | } |
228 | } |
229 | return NULL; |
229 | return NULL; |
230 | } |
230 | } |
231 | 231 | ||
232 | static struct drm_connector * |
232 | static struct drm_connector * |
233 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder) |
233 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder) |
234 | { |
234 | { |
235 | struct drm_device *dev = encoder->dev; |
235 | struct drm_device *dev = encoder->dev; |
236 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
236 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
237 | struct drm_connector *connector; |
237 | struct drm_connector *connector; |
238 | struct radeon_connector *radeon_connector; |
238 | struct radeon_connector *radeon_connector; |
239 | 239 | ||
240 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
240 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
241 | radeon_connector = to_radeon_connector(connector); |
241 | radeon_connector = to_radeon_connector(connector); |
242 | if (radeon_encoder->devices & radeon_connector->devices) |
242 | if (radeon_encoder->devices & radeon_connector->devices) |
243 | return connector; |
243 | return connector; |
244 | } |
244 | } |
245 | return NULL; |
245 | return NULL; |
246 | } |
246 | } |
247 | 247 | ||
248 | struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder) |
248 | struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder) |
249 | { |
249 | { |
250 | struct drm_device *dev = encoder->dev; |
250 | struct drm_device *dev = encoder->dev; |
251 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
251 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
252 | struct drm_encoder *other_encoder; |
252 | struct drm_encoder *other_encoder; |
253 | struct radeon_encoder *other_radeon_encoder; |
253 | struct radeon_encoder *other_radeon_encoder; |
254 | 254 | ||
255 | if (radeon_encoder->is_ext_encoder) |
255 | if (radeon_encoder->is_ext_encoder) |
256 | return NULL; |
256 | return NULL; |
257 | 257 | ||
258 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
258 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
259 | if (other_encoder == encoder) |
259 | if (other_encoder == encoder) |
260 | continue; |
260 | continue; |
261 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
261 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
262 | if (other_radeon_encoder->is_ext_encoder && |
262 | if (other_radeon_encoder->is_ext_encoder && |
263 | (radeon_encoder->devices & other_radeon_encoder->devices)) |
263 | (radeon_encoder->devices & other_radeon_encoder->devices)) |
264 | return other_encoder; |
264 | return other_encoder; |
265 | } |
265 | } |
266 | return NULL; |
266 | return NULL; |
267 | } |
267 | } |
268 | 268 | ||
269 | bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder) |
269 | bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder) |
270 | { |
270 | { |
271 | struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder); |
271 | struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder); |
272 | 272 | ||
273 | if (other_encoder) { |
273 | if (other_encoder) { |
274 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder); |
274 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder); |
275 | 275 | ||
276 | switch (radeon_encoder->encoder_id) { |
276 | switch (radeon_encoder->encoder_id) { |
277 | case ENCODER_OBJECT_ID_TRAVIS: |
277 | case ENCODER_OBJECT_ID_TRAVIS: |
278 | case ENCODER_OBJECT_ID_NUTMEG: |
278 | case ENCODER_OBJECT_ID_NUTMEG: |
279 | return true; |
279 | return true; |
280 | default: |
280 | default: |
281 | return false; |
281 | return false; |
282 | } |
282 | } |
283 | } |
283 | } |
284 | 284 | ||
285 | return false; |
285 | return false; |
286 | } |
286 | } |
287 | 287 | ||
288 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
288 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
289 | struct drm_display_mode *adjusted_mode) |
289 | struct drm_display_mode *adjusted_mode) |
290 | { |
290 | { |
291 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
291 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
292 | struct drm_device *dev = encoder->dev; |
292 | struct drm_device *dev = encoder->dev; |
293 | struct radeon_device *rdev = dev->dev_private; |
293 | struct radeon_device *rdev = dev->dev_private; |
294 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
294 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
295 | unsigned hblank = native_mode->htotal - native_mode->hdisplay; |
295 | unsigned hblank = native_mode->htotal - native_mode->hdisplay; |
296 | unsigned vblank = native_mode->vtotal - native_mode->vdisplay; |
296 | unsigned vblank = native_mode->vtotal - native_mode->vdisplay; |
297 | unsigned hover = native_mode->hsync_start - native_mode->hdisplay; |
297 | unsigned hover = native_mode->hsync_start - native_mode->hdisplay; |
298 | unsigned vover = native_mode->vsync_start - native_mode->vdisplay; |
298 | unsigned vover = native_mode->vsync_start - native_mode->vdisplay; |
299 | unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; |
299 | unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; |
300 | unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; |
300 | unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; |
301 | 301 | ||
302 | adjusted_mode->clock = native_mode->clock; |
302 | adjusted_mode->clock = native_mode->clock; |
303 | adjusted_mode->flags = native_mode->flags; |
303 | adjusted_mode->flags = native_mode->flags; |
304 | 304 | ||
305 | if (ASIC_IS_AVIVO(rdev)) { |
305 | if (ASIC_IS_AVIVO(rdev)) { |
306 | adjusted_mode->hdisplay = native_mode->hdisplay; |
306 | adjusted_mode->hdisplay = native_mode->hdisplay; |
307 | adjusted_mode->vdisplay = native_mode->vdisplay; |
307 | adjusted_mode->vdisplay = native_mode->vdisplay; |
308 | } |
308 | } |
309 | 309 | ||
310 | adjusted_mode->htotal = native_mode->hdisplay + hblank; |
310 | adjusted_mode->htotal = native_mode->hdisplay + hblank; |
311 | adjusted_mode->hsync_start = native_mode->hdisplay + hover; |
311 | adjusted_mode->hsync_start = native_mode->hdisplay + hover; |
312 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; |
312 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; |
313 | 313 | ||
314 | adjusted_mode->vtotal = native_mode->vdisplay + vblank; |
314 | adjusted_mode->vtotal = native_mode->vdisplay + vblank; |
315 | adjusted_mode->vsync_start = native_mode->vdisplay + vover; |
315 | adjusted_mode->vsync_start = native_mode->vdisplay + vover; |
316 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; |
316 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; |
317 | 317 | ||
318 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
318 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
319 | 319 | ||
320 | if (ASIC_IS_AVIVO(rdev)) { |
320 | if (ASIC_IS_AVIVO(rdev)) { |
321 | adjusted_mode->crtc_hdisplay = native_mode->hdisplay; |
321 | adjusted_mode->crtc_hdisplay = native_mode->hdisplay; |
322 | adjusted_mode->crtc_vdisplay = native_mode->vdisplay; |
322 | adjusted_mode->crtc_vdisplay = native_mode->vdisplay; |
323 | } |
323 | } |
324 | 324 | ||
325 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; |
325 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; |
326 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; |
326 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; |
327 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; |
327 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; |
328 | 328 | ||
329 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; |
329 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; |
330 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; |
330 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; |
331 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; |
331 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; |
332 | 332 | ||
333 | } |
333 | } |
334 | 334 | ||
335 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
335 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
336 | struct drm_display_mode *mode, |
336 | struct drm_display_mode *mode, |
337 | struct drm_display_mode *adjusted_mode) |
337 | struct drm_display_mode *adjusted_mode) |
338 | { |
338 | { |
339 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
339 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
340 | struct drm_device *dev = encoder->dev; |
340 | struct drm_device *dev = encoder->dev; |
341 | struct radeon_device *rdev = dev->dev_private; |
341 | struct radeon_device *rdev = dev->dev_private; |
342 | 342 | ||
343 | /* set the active encoder to connector routing */ |
343 | /* set the active encoder to connector routing */ |
344 | radeon_encoder_set_active_device(encoder); |
344 | radeon_encoder_set_active_device(encoder); |
345 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
345 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
346 | 346 | ||
347 | /* hw bug */ |
347 | /* hw bug */ |
348 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
348 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
349 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
349 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
350 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
350 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
351 | 351 | ||
352 | /* get the native mode for LVDS */ |
352 | /* get the native mode for LVDS */ |
353 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
353 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
354 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
354 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
355 | 355 | ||
356 | /* get the native mode for TV */ |
356 | /* get the native mode for TV */ |
357 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
357 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
358 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
358 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
359 | if (tv_dac) { |
359 | if (tv_dac) { |
360 | if (tv_dac->tv_std == TV_STD_NTSC || |
360 | if (tv_dac->tv_std == TV_STD_NTSC || |
361 | tv_dac->tv_std == TV_STD_NTSC_J || |
361 | tv_dac->tv_std == TV_STD_NTSC_J || |
362 | tv_dac->tv_std == TV_STD_PAL_M) |
362 | tv_dac->tv_std == TV_STD_PAL_M) |
363 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
363 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
364 | else |
364 | else |
365 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
365 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
366 | } |
366 | } |
367 | } |
367 | } |
368 | 368 | ||
369 | if (ASIC_IS_DCE3(rdev) && |
369 | if (ASIC_IS_DCE3(rdev) && |
370 | (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { |
370 | ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
- | 371 | radeon_encoder_is_dp_bridge(encoder))) { |
|
371 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
372 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
372 | radeon_dp_set_link_config(connector, mode); |
373 | radeon_dp_set_link_config(connector, mode); |
373 | } |
374 | } |
374 | 375 | ||
375 | return true; |
376 | return true; |
376 | } |
377 | } |
377 | 378 | ||
378 | static void |
379 | static void |
379 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
380 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
380 | { |
381 | { |
381 | struct drm_device *dev = encoder->dev; |
382 | struct drm_device *dev = encoder->dev; |
382 | struct radeon_device *rdev = dev->dev_private; |
383 | struct radeon_device *rdev = dev->dev_private; |
383 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
384 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
384 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
385 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
385 | int index = 0; |
386 | int index = 0; |
386 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
387 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
387 | 388 | ||
388 | memset(&args, 0, sizeof(args)); |
389 | memset(&args, 0, sizeof(args)); |
389 | 390 | ||
390 | switch (radeon_encoder->encoder_id) { |
391 | switch (radeon_encoder->encoder_id) { |
391 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
392 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
392 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
393 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
393 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
394 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
394 | break; |
395 | break; |
395 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
396 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
396 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
397 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
397 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
398 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
398 | break; |
399 | break; |
399 | } |
400 | } |
400 | 401 | ||
401 | args.ucAction = action; |
402 | args.ucAction = action; |
402 | 403 | ||
403 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
404 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
404 | args.ucDacStandard = ATOM_DAC1_PS2; |
405 | args.ucDacStandard = ATOM_DAC1_PS2; |
405 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
406 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
406 | args.ucDacStandard = ATOM_DAC1_CV; |
407 | args.ucDacStandard = ATOM_DAC1_CV; |
407 | else { |
408 | else { |
408 | switch (dac_info->tv_std) { |
409 | switch (dac_info->tv_std) { |
409 | case TV_STD_PAL: |
410 | case TV_STD_PAL: |
410 | case TV_STD_PAL_M: |
411 | case TV_STD_PAL_M: |
411 | case TV_STD_SCART_PAL: |
412 | case TV_STD_SCART_PAL: |
412 | case TV_STD_SECAM: |
413 | case TV_STD_SECAM: |
413 | case TV_STD_PAL_CN: |
414 | case TV_STD_PAL_CN: |
414 | args.ucDacStandard = ATOM_DAC1_PAL; |
415 | args.ucDacStandard = ATOM_DAC1_PAL; |
415 | break; |
416 | break; |
416 | case TV_STD_NTSC: |
417 | case TV_STD_NTSC: |
417 | case TV_STD_NTSC_J: |
418 | case TV_STD_NTSC_J: |
418 | case TV_STD_PAL_60: |
419 | case TV_STD_PAL_60: |
419 | default: |
420 | default: |
420 | args.ucDacStandard = ATOM_DAC1_NTSC; |
421 | args.ucDacStandard = ATOM_DAC1_NTSC; |
421 | break; |
422 | break; |
422 | } |
423 | } |
423 | } |
424 | } |
424 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
425 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
425 | 426 | ||
426 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
427 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
427 | 428 | ||
428 | } |
429 | } |
429 | 430 | ||
430 | static void |
431 | static void |
431 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
432 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
432 | { |
433 | { |
433 | struct drm_device *dev = encoder->dev; |
434 | struct drm_device *dev = encoder->dev; |
434 | struct radeon_device *rdev = dev->dev_private; |
435 | struct radeon_device *rdev = dev->dev_private; |
435 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
436 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
436 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
437 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
437 | int index = 0; |
438 | int index = 0; |
438 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
439 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
439 | 440 | ||
440 | memset(&args, 0, sizeof(args)); |
441 | memset(&args, 0, sizeof(args)); |
441 | 442 | ||
442 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
443 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
443 | 444 | ||
444 | args.sTVEncoder.ucAction = action; |
445 | args.sTVEncoder.ucAction = action; |
445 | 446 | ||
446 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
447 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
447 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
448 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
448 | else { |
449 | else { |
449 | switch (dac_info->tv_std) { |
450 | switch (dac_info->tv_std) { |
450 | case TV_STD_NTSC: |
451 | case TV_STD_NTSC: |
451 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
452 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
452 | break; |
453 | break; |
453 | case TV_STD_PAL: |
454 | case TV_STD_PAL: |
454 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
455 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
455 | break; |
456 | break; |
456 | case TV_STD_PAL_M: |
457 | case TV_STD_PAL_M: |
457 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
458 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
458 | break; |
459 | break; |
459 | case TV_STD_PAL_60: |
460 | case TV_STD_PAL_60: |
460 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
461 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
461 | break; |
462 | break; |
462 | case TV_STD_NTSC_J: |
463 | case TV_STD_NTSC_J: |
463 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
464 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
464 | break; |
465 | break; |
465 | case TV_STD_SCART_PAL: |
466 | case TV_STD_SCART_PAL: |
466 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
467 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
467 | break; |
468 | break; |
468 | case TV_STD_SECAM: |
469 | case TV_STD_SECAM: |
469 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
470 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
470 | break; |
471 | break; |
471 | case TV_STD_PAL_CN: |
472 | case TV_STD_PAL_CN: |
472 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
473 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
473 | break; |
474 | break; |
474 | default: |
475 | default: |
475 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
476 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
476 | break; |
477 | break; |
477 | } |
478 | } |
478 | } |
479 | } |
479 | 480 | ||
480 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
481 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
481 | 482 | ||
482 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
483 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
483 | 484 | ||
484 | } |
485 | } |
485 | 486 | ||
486 | union dvo_encoder_control { |
487 | union dvo_encoder_control { |
487 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
488 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
488 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
489 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
489 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
490 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
490 | }; |
491 | }; |
491 | 492 | ||
492 | void |
493 | void |
493 | atombios_dvo_setup(struct drm_encoder *encoder, int action) |
494 | atombios_dvo_setup(struct drm_encoder *encoder, int action) |
494 | { |
495 | { |
495 | struct drm_device *dev = encoder->dev; |
496 | struct drm_device *dev = encoder->dev; |
496 | struct radeon_device *rdev = dev->dev_private; |
497 | struct radeon_device *rdev = dev->dev_private; |
497 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
498 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
498 | union dvo_encoder_control args; |
499 | union dvo_encoder_control args; |
499 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
500 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
500 | 501 | ||
501 | memset(&args, 0, sizeof(args)); |
502 | memset(&args, 0, sizeof(args)); |
502 | 503 | ||
503 | if (ASIC_IS_DCE3(rdev)) { |
504 | if (ASIC_IS_DCE3(rdev)) { |
504 | /* DCE3+ */ |
505 | /* DCE3+ */ |
505 | args.dvo_v3.ucAction = action; |
506 | args.dvo_v3.ucAction = action; |
506 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
507 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
507 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
508 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
508 | } else if (ASIC_IS_DCE2(rdev)) { |
509 | } else if (ASIC_IS_DCE2(rdev)) { |
509 | /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */ |
510 | /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */ |
510 | args.dvo.sDVOEncoder.ucAction = action; |
511 | args.dvo.sDVOEncoder.ucAction = action; |
511 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
512 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
512 | /* DFP1, CRT1, TV1 depending on the type of port */ |
513 | /* DFP1, CRT1, TV1 depending on the type of port */ |
513 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; |
514 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; |
514 | 515 | ||
515 | if (radeon_encoder->pixel_clock > 165000) |
516 | if (radeon_encoder->pixel_clock > 165000) |
516 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
517 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
517 | } else { |
518 | } else { |
518 | /* R4xx, R5xx */ |
519 | /* R4xx, R5xx */ |
519 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; |
520 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; |
520 | 521 | ||
521 | if (radeon_encoder->pixel_clock > 165000) |
522 | if (radeon_encoder->pixel_clock > 165000) |
522 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
523 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
523 | 524 | ||
524 | /*if (pScrn->rgbBits == 8)*/ |
525 | /*if (pScrn->rgbBits == 8)*/ |
525 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; |
526 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; |
526 | } |
527 | } |
527 | 528 | ||
528 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
529 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
529 | } |
530 | } |
530 | 531 | ||
531 | union lvds_encoder_control { |
532 | union lvds_encoder_control { |
532 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
533 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
533 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
534 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
534 | }; |
535 | }; |
535 | 536 | ||
536 | void |
537 | void |
537 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
538 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
538 | { |
539 | { |
539 | struct drm_device *dev = encoder->dev; |
540 | struct drm_device *dev = encoder->dev; |
540 | struct radeon_device *rdev = dev->dev_private; |
541 | struct radeon_device *rdev = dev->dev_private; |
541 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
542 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
542 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
543 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
543 | union lvds_encoder_control args; |
544 | union lvds_encoder_control args; |
544 | int index = 0; |
545 | int index = 0; |
545 | int hdmi_detected = 0; |
546 | int hdmi_detected = 0; |
546 | uint8_t frev, crev; |
547 | uint8_t frev, crev; |
547 | 548 | ||
548 | if (!dig) |
549 | if (!dig) |
549 | return; |
550 | return; |
550 | 551 | ||
551 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
552 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
552 | hdmi_detected = 1; |
553 | hdmi_detected = 1; |
553 | 554 | ||
554 | memset(&args, 0, sizeof(args)); |
555 | memset(&args, 0, sizeof(args)); |
555 | 556 | ||
556 | switch (radeon_encoder->encoder_id) { |
557 | switch (radeon_encoder->encoder_id) { |
557 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
558 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
558 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
559 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
559 | break; |
560 | break; |
560 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
561 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
561 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
562 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
562 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
563 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
563 | break; |
564 | break; |
564 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
565 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
565 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
566 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
566 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
567 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
567 | else |
568 | else |
568 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
569 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
569 | break; |
570 | break; |
570 | } |
571 | } |
571 | 572 | ||
572 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
573 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
573 | return; |
574 | return; |
574 | 575 | ||
575 | switch (frev) { |
576 | switch (frev) { |
576 | case 1: |
577 | case 1: |
577 | case 2: |
578 | case 2: |
578 | switch (crev) { |
579 | switch (crev) { |
579 | case 1: |
580 | case 1: |
580 | args.v1.ucMisc = 0; |
581 | args.v1.ucMisc = 0; |
581 | args.v1.ucAction = action; |
582 | args.v1.ucAction = action; |
582 | if (hdmi_detected) |
583 | if (hdmi_detected) |
583 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
584 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
584 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
585 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
585 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
586 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
586 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
587 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
587 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
588 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
588 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
589 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
589 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
590 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
590 | } else { |
591 | } else { |
591 | if (dig->linkb) |
592 | if (dig->linkb) |
592 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
593 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
593 | if (radeon_encoder->pixel_clock > 165000) |
594 | if (radeon_encoder->pixel_clock > 165000) |
594 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
595 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
595 | /*if (pScrn->rgbBits == 8) */ |
596 | /*if (pScrn->rgbBits == 8) */ |
596 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
597 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
597 | } |
598 | } |
598 | break; |
599 | break; |
599 | case 2: |
600 | case 2: |
600 | case 3: |
601 | case 3: |
601 | args.v2.ucMisc = 0; |
602 | args.v2.ucMisc = 0; |
602 | args.v2.ucAction = action; |
603 | args.v2.ucAction = action; |
603 | if (crev == 3) { |
604 | if (crev == 3) { |
604 | if (dig->coherent_mode) |
605 | if (dig->coherent_mode) |
605 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
606 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
606 | } |
607 | } |
607 | if (hdmi_detected) |
608 | if (hdmi_detected) |
608 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
609 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
609 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
610 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
610 | args.v2.ucTruncate = 0; |
611 | args.v2.ucTruncate = 0; |
611 | args.v2.ucSpatial = 0; |
612 | args.v2.ucSpatial = 0; |
612 | args.v2.ucTemporal = 0; |
613 | args.v2.ucTemporal = 0; |
613 | args.v2.ucFRC = 0; |
614 | args.v2.ucFRC = 0; |
614 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
615 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
615 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
616 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
616 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
617 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
617 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { |
618 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { |
618 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
619 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
619 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
620 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
620 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
621 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
621 | } |
622 | } |
622 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { |
623 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { |
623 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
624 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
624 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
625 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
625 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
626 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
626 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
627 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
627 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
628 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
628 | } |
629 | } |
629 | } else { |
630 | } else { |
630 | if (dig->linkb) |
631 | if (dig->linkb) |
631 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
632 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
632 | if (radeon_encoder->pixel_clock > 165000) |
633 | if (radeon_encoder->pixel_clock > 165000) |
633 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
634 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
634 | } |
635 | } |
635 | break; |
636 | break; |
636 | default: |
637 | default: |
637 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
638 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
638 | break; |
639 | break; |
639 | } |
640 | } |
640 | break; |
641 | break; |
641 | default: |
642 | default: |
642 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
643 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
643 | break; |
644 | break; |
644 | } |
645 | } |
645 | 646 | ||
646 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
647 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
647 | } |
648 | } |
648 | 649 | ||
649 | int |
650 | int |
650 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
651 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
651 | { |
652 | { |
652 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
653 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
653 | struct drm_device *dev = encoder->dev; |
654 | struct drm_device *dev = encoder->dev; |
654 | struct radeon_device *rdev = dev->dev_private; |
655 | struct radeon_device *rdev = dev->dev_private; |
655 | struct drm_connector *connector; |
656 | struct drm_connector *connector; |
656 | struct radeon_connector *radeon_connector; |
657 | struct radeon_connector *radeon_connector; |
657 | struct radeon_connector_atom_dig *dig_connector; |
658 | struct radeon_connector_atom_dig *dig_connector; |
658 | 659 | ||
659 | /* dp bridges are always DP */ |
660 | /* dp bridges are always DP */ |
660 | if (radeon_encoder_is_dp_bridge(encoder)) |
661 | if (radeon_encoder_is_dp_bridge(encoder)) |
661 | return ATOM_ENCODER_MODE_DP; |
662 | return ATOM_ENCODER_MODE_DP; |
- | 663 | ||
- | 664 | /* DVO is always DVO */ |
|
- | 665 | if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO) |
|
- | 666 | return ATOM_ENCODER_MODE_DVO; |
|
662 | 667 | ||
663 | connector = radeon_get_connector_for_encoder(encoder); |
- | |
664 | if (!connector) { |
668 | connector = radeon_get_connector_for_encoder(encoder); |
665 | switch (radeon_encoder->encoder_id) { |
669 | /* if we don't have an active device yet, just use one of |
666 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
- | |
667 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
- | |
668 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | |
669 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
- | |
670 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
670 | * the connectors tied to the encoder. |
671 | return ATOM_ENCODER_MODE_DVI; |
- | |
672 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
- | |
673 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
671 | */ |
674 | default: |
672 | if (!connector) |
675 | return ATOM_ENCODER_MODE_CRT; |
- | |
676 | } |
- | |
677 | } |
673 | connector = radeon_get_connector_for_encoder_init(encoder); |
678 | radeon_connector = to_radeon_connector(connector); |
674 | radeon_connector = to_radeon_connector(connector); |
679 | 675 | ||
680 | switch (connector->connector_type) { |
676 | switch (connector->connector_type) { |
681 | case DRM_MODE_CONNECTOR_DVII: |
677 | case DRM_MODE_CONNECTOR_DVII: |
682 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
678 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
683 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
679 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
684 | /* fix me */ |
680 | /* fix me */ |
685 | if (ASIC_IS_DCE4(rdev)) |
681 | if (ASIC_IS_DCE4(rdev)) |
686 | return ATOM_ENCODER_MODE_DVI; |
682 | return ATOM_ENCODER_MODE_DVI; |
687 | else |
683 | else |
688 | return ATOM_ENCODER_MODE_HDMI; |
684 | return ATOM_ENCODER_MODE_HDMI; |
689 | } else if (radeon_connector->use_digital) |
685 | } else if (radeon_connector->use_digital) |
690 | return ATOM_ENCODER_MODE_DVI; |
686 | return ATOM_ENCODER_MODE_DVI; |
691 | else |
687 | else |
692 | return ATOM_ENCODER_MODE_CRT; |
688 | return ATOM_ENCODER_MODE_CRT; |
693 | break; |
689 | break; |
694 | case DRM_MODE_CONNECTOR_DVID: |
690 | case DRM_MODE_CONNECTOR_DVID: |
695 | case DRM_MODE_CONNECTOR_HDMIA: |
691 | case DRM_MODE_CONNECTOR_HDMIA: |
696 | default: |
692 | default: |
697 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
693 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
698 | /* fix me */ |
694 | /* fix me */ |
699 | if (ASIC_IS_DCE4(rdev)) |
695 | if (ASIC_IS_DCE4(rdev)) |
700 | return ATOM_ENCODER_MODE_DVI; |
696 | return ATOM_ENCODER_MODE_DVI; |
701 | else |
697 | else |
702 | return ATOM_ENCODER_MODE_HDMI; |
698 | return ATOM_ENCODER_MODE_HDMI; |
703 | } else |
699 | } else |
704 | return ATOM_ENCODER_MODE_DVI; |
700 | return ATOM_ENCODER_MODE_DVI; |
705 | break; |
701 | break; |
706 | case DRM_MODE_CONNECTOR_LVDS: |
702 | case DRM_MODE_CONNECTOR_LVDS: |
707 | return ATOM_ENCODER_MODE_LVDS; |
703 | return ATOM_ENCODER_MODE_LVDS; |
708 | break; |
704 | break; |
709 | case DRM_MODE_CONNECTOR_DisplayPort: |
705 | case DRM_MODE_CONNECTOR_DisplayPort: |
710 | dig_connector = radeon_connector->con_priv; |
706 | dig_connector = radeon_connector->con_priv; |
711 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
707 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
712 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
708 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
713 | return ATOM_ENCODER_MODE_DP; |
709 | return ATOM_ENCODER_MODE_DP; |
714 | else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
710 | else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
715 | /* fix me */ |
711 | /* fix me */ |
716 | if (ASIC_IS_DCE4(rdev)) |
712 | if (ASIC_IS_DCE4(rdev)) |
717 | return ATOM_ENCODER_MODE_DVI; |
713 | return ATOM_ENCODER_MODE_DVI; |
718 | else |
714 | else |
719 | return ATOM_ENCODER_MODE_HDMI; |
715 | return ATOM_ENCODER_MODE_HDMI; |
720 | } else |
716 | } else |
721 | return ATOM_ENCODER_MODE_DVI; |
717 | return ATOM_ENCODER_MODE_DVI; |
722 | break; |
718 | break; |
723 | case DRM_MODE_CONNECTOR_eDP: |
719 | case DRM_MODE_CONNECTOR_eDP: |
724 | return ATOM_ENCODER_MODE_DP; |
720 | return ATOM_ENCODER_MODE_DP; |
725 | case DRM_MODE_CONNECTOR_DVIA: |
721 | case DRM_MODE_CONNECTOR_DVIA: |
726 | case DRM_MODE_CONNECTOR_VGA: |
722 | case DRM_MODE_CONNECTOR_VGA: |
727 | return ATOM_ENCODER_MODE_CRT; |
723 | return ATOM_ENCODER_MODE_CRT; |
728 | break; |
724 | break; |
729 | case DRM_MODE_CONNECTOR_Composite: |
725 | case DRM_MODE_CONNECTOR_Composite: |
730 | case DRM_MODE_CONNECTOR_SVIDEO: |
726 | case DRM_MODE_CONNECTOR_SVIDEO: |
731 | case DRM_MODE_CONNECTOR_9PinDIN: |
727 | case DRM_MODE_CONNECTOR_9PinDIN: |
732 | /* fix me */ |
728 | /* fix me */ |
733 | return ATOM_ENCODER_MODE_TV; |
729 | return ATOM_ENCODER_MODE_TV; |
734 | /*return ATOM_ENCODER_MODE_CV;*/ |
730 | /*return ATOM_ENCODER_MODE_CV;*/ |
735 | break; |
731 | break; |
736 | } |
732 | } |
737 | } |
733 | } |
738 | 734 | ||
739 | /* |
735 | /* |
740 | * DIG Encoder/Transmitter Setup |
736 | * DIG Encoder/Transmitter Setup |
741 | * |
737 | * |
742 | * DCE 3.0/3.1 |
738 | * DCE 3.0/3.1 |
743 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. |
739 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. |
744 | * Supports up to 3 digital outputs |
740 | * Supports up to 3 digital outputs |
745 | * - 2 DIG encoder blocks. |
741 | * - 2 DIG encoder blocks. |
746 | * DIG1 can drive UNIPHY link A or link B |
742 | * DIG1 can drive UNIPHY link A or link B |
747 | * DIG2 can drive UNIPHY link B or LVTMA |
743 | * DIG2 can drive UNIPHY link B or LVTMA |
748 | * |
744 | * |
749 | * DCE 3.2 |
745 | * DCE 3.2 |
750 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). |
746 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). |
751 | * Supports up to 5 digital outputs |
747 | * Supports up to 5 digital outputs |
752 | * - 2 DIG encoder blocks. |
748 | * - 2 DIG encoder blocks. |
753 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
749 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
754 | * |
750 | * |
755 | * DCE 4.0/5.0 |
751 | * DCE 4.0/5.0 |
756 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
752 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
757 | * Supports up to 6 digital outputs |
753 | * Supports up to 6 digital outputs |
758 | * - 6 DIG encoder blocks. |
754 | * - 6 DIG encoder blocks. |
759 | * - DIG to PHY mapping is hardcoded |
755 | * - DIG to PHY mapping is hardcoded |
760 | * DIG1 drives UNIPHY0 link A, A+B |
756 | * DIG1 drives UNIPHY0 link A, A+B |
761 | * DIG2 drives UNIPHY0 link B |
757 | * DIG2 drives UNIPHY0 link B |
762 | * DIG3 drives UNIPHY1 link A, A+B |
758 | * DIG3 drives UNIPHY1 link A, A+B |
763 | * DIG4 drives UNIPHY1 link B |
759 | * DIG4 drives UNIPHY1 link B |
764 | * DIG5 drives UNIPHY2 link A, A+B |
760 | * DIG5 drives UNIPHY2 link A, A+B |
765 | * DIG6 drives UNIPHY2 link B |
761 | * DIG6 drives UNIPHY2 link B |
766 | * |
762 | * |
767 | * DCE 4.1 |
763 | * DCE 4.1 |
768 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
764 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
769 | * Supports up to 6 digital outputs |
765 | * Supports up to 6 digital outputs |
770 | * - 2 DIG encoder blocks. |
766 | * - 2 DIG encoder blocks. |
771 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
767 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
772 | * |
768 | * |
773 | * Routing |
769 | * Routing |
774 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) |
770 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) |
775 | * Examples: |
771 | * Examples: |
776 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI |
772 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI |
777 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP |
773 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP |
778 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS |
774 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS |
779 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI |
775 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI |
780 | */ |
776 | */ |
781 | 777 | ||
782 | union dig_encoder_control { |
778 | union dig_encoder_control { |
783 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
779 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
784 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
780 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
785 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
781 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
786 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; |
782 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; |
787 | }; |
783 | }; |
788 | 784 | ||
789 | void |
785 | void |
790 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) |
786 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) |
791 | { |
787 | { |
792 | struct drm_device *dev = encoder->dev; |
788 | struct drm_device *dev = encoder->dev; |
793 | struct radeon_device *rdev = dev->dev_private; |
789 | struct radeon_device *rdev = dev->dev_private; |
794 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
790 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
795 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
791 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
796 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
792 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
797 | union dig_encoder_control args; |
793 | union dig_encoder_control args; |
798 | int index = 0; |
794 | int index = 0; |
799 | uint8_t frev, crev; |
795 | uint8_t frev, crev; |
800 | int dp_clock = 0; |
796 | int dp_clock = 0; |
801 | int dp_lane_count = 0; |
797 | int dp_lane_count = 0; |
802 | int hpd_id = RADEON_HPD_NONE; |
798 | int hpd_id = RADEON_HPD_NONE; |
803 | int bpc = 8; |
799 | int bpc = 8; |
804 | 800 | ||
805 | if (connector) { |
801 | if (connector) { |
806 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
802 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
807 | struct radeon_connector_atom_dig *dig_connector = |
803 | struct radeon_connector_atom_dig *dig_connector = |
808 | radeon_connector->con_priv; |
804 | radeon_connector->con_priv; |
809 | 805 | ||
810 | dp_clock = dig_connector->dp_clock; |
806 | dp_clock = dig_connector->dp_clock; |
811 | dp_lane_count = dig_connector->dp_lane_count; |
807 | dp_lane_count = dig_connector->dp_lane_count; |
812 | hpd_id = radeon_connector->hpd.hpd; |
808 | hpd_id = radeon_connector->hpd.hpd; |
813 | bpc = connector->display_info.bpc; |
809 | bpc = connector->display_info.bpc; |
814 | } |
810 | } |
815 | 811 | ||
816 | /* no dig encoder assigned */ |
812 | /* no dig encoder assigned */ |
817 | if (dig->dig_encoder == -1) |
813 | if (dig->dig_encoder == -1) |
818 | return; |
814 | return; |
819 | 815 | ||
820 | memset(&args, 0, sizeof(args)); |
816 | memset(&args, 0, sizeof(args)); |
821 | 817 | ||
822 | if (ASIC_IS_DCE4(rdev)) |
818 | if (ASIC_IS_DCE4(rdev)) |
823 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); |
819 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); |
824 | else { |
820 | else { |
825 | if (dig->dig_encoder) |
821 | if (dig->dig_encoder) |
826 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
822 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
827 | else |
823 | else |
828 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
824 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
829 | } |
825 | } |
830 | 826 | ||
831 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
827 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
832 | return; |
828 | return; |
833 | 829 | ||
834 | args.v1.ucAction = action; |
830 | args.v1.ucAction = action; |
835 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
831 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
836 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
832 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
837 | args.v3.ucPanelMode = panel_mode; |
833 | args.v3.ucPanelMode = panel_mode; |
838 | else |
834 | else |
839 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
835 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
840 | 836 | ||
841 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
837 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
842 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) |
838 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) |
843 | args.v1.ucLaneNum = dp_lane_count; |
839 | args.v1.ucLaneNum = dp_lane_count; |
844 | else if (radeon_encoder->pixel_clock > 165000) |
840 | else if (radeon_encoder->pixel_clock > 165000) |
845 | args.v1.ucLaneNum = 8; |
841 | args.v1.ucLaneNum = 8; |
846 | else |
842 | else |
847 | args.v1.ucLaneNum = 4; |
843 | args.v1.ucLaneNum = 4; |
848 | 844 | ||
849 | if (ASIC_IS_DCE5(rdev)) { |
845 | if (ASIC_IS_DCE5(rdev)) { |
850 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
846 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
851 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) { |
847 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) { |
852 | if (dp_clock == 270000) |
848 | if (dp_clock == 270000) |
853 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
849 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
854 | else if (dp_clock == 540000) |
850 | else if (dp_clock == 540000) |
855 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
851 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
856 | } |
852 | } |
857 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
853 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
858 | switch (bpc) { |
854 | switch (bpc) { |
859 | case 0: |
855 | case 0: |
860 | args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; |
856 | args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; |
861 | break; |
857 | break; |
862 | case 6: |
858 | case 6: |
863 | args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
859 | args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
864 | break; |
860 | break; |
865 | case 8: |
861 | case 8: |
866 | default: |
862 | default: |
867 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
863 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
868 | break; |
864 | break; |
869 | case 10: |
865 | case 10: |
870 | args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
866 | args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
871 | break; |
867 | break; |
872 | case 12: |
868 | case 12: |
873 | args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
869 | args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
874 | break; |
870 | break; |
875 | case 16: |
871 | case 16: |
876 | args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
872 | args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
877 | break; |
873 | break; |
878 | } |
874 | } |
879 | if (hpd_id == RADEON_HPD_NONE) |
875 | if (hpd_id == RADEON_HPD_NONE) |
880 | args.v4.ucHPD_ID = 0; |
876 | args.v4.ucHPD_ID = 0; |
881 | else |
877 | else |
882 | args.v4.ucHPD_ID = hpd_id + 1; |
878 | args.v4.ucHPD_ID = hpd_id + 1; |
883 | } else if (ASIC_IS_DCE4(rdev)) { |
879 | } else if (ASIC_IS_DCE4(rdev)) { |
884 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
880 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
885 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
881 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
886 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
882 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
887 | switch (bpc) { |
883 | switch (bpc) { |
888 | case 0: |
884 | case 0: |
889 | args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; |
885 | args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; |
890 | break; |
886 | break; |
891 | case 6: |
887 | case 6: |
892 | args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
888 | args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
893 | break; |
889 | break; |
894 | case 8: |
890 | case 8: |
895 | default: |
891 | default: |
896 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
892 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
897 | break; |
893 | break; |
898 | case 10: |
894 | case 10: |
899 | args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
895 | args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
900 | break; |
896 | break; |
901 | case 12: |
897 | case 12: |
902 | args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
898 | args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
903 | break; |
899 | break; |
904 | case 16: |
900 | case 16: |
905 | args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
901 | args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
906 | break; |
902 | break; |
907 | } |
903 | } |
908 | } else { |
904 | } else { |
909 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
905 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
910 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
906 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
911 | switch (radeon_encoder->encoder_id) { |
907 | switch (radeon_encoder->encoder_id) { |
912 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
908 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
913 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
909 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
914 | break; |
910 | break; |
915 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
911 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
916 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
912 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
917 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
913 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
918 | break; |
914 | break; |
919 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
915 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
920 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
916 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
921 | break; |
917 | break; |
922 | } |
918 | } |
923 | if (dig->linkb) |
919 | if (dig->linkb) |
924 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
920 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
925 | else |
921 | else |
926 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
922 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
927 | } |
923 | } |
928 | 924 | ||
929 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
925 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
930 | 926 | ||
931 | } |
927 | } |
932 | 928 | ||
933 | union dig_transmitter_control { |
929 | union dig_transmitter_control { |
934 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
930 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
935 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
931 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
936 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
932 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
937 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; |
933 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; |
938 | }; |
934 | }; |
939 | 935 | ||
940 | void |
936 | void |
941 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
937 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
942 | { |
938 | { |
943 | struct drm_device *dev = encoder->dev; |
939 | struct drm_device *dev = encoder->dev; |
944 | struct radeon_device *rdev = dev->dev_private; |
940 | struct radeon_device *rdev = dev->dev_private; |
945 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
941 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
946 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
942 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
947 | struct drm_connector *connector; |
943 | struct drm_connector *connector; |
948 | union dig_transmitter_control args; |
944 | union dig_transmitter_control args; |
949 | int index = 0; |
945 | int index = 0; |
950 | uint8_t frev, crev; |
946 | uint8_t frev, crev; |
951 | bool is_dp = false; |
947 | bool is_dp = false; |
952 | int pll_id = 0; |
948 | int pll_id = 0; |
953 | int dp_clock = 0; |
949 | int dp_clock = 0; |
954 | int dp_lane_count = 0; |
950 | int dp_lane_count = 0; |
955 | int connector_object_id = 0; |
951 | int connector_object_id = 0; |
956 | int igp_lane_info = 0; |
952 | int igp_lane_info = 0; |
957 | int dig_encoder = dig->dig_encoder; |
953 | int dig_encoder = dig->dig_encoder; |
958 | 954 | ||
959 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
955 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
960 | connector = radeon_get_connector_for_encoder_init(encoder); |
956 | connector = radeon_get_connector_for_encoder_init(encoder); |
961 | /* just needed to avoid bailing in the encoder check. the encoder |
957 | /* just needed to avoid bailing in the encoder check. the encoder |
962 | * isn't used for init |
958 | * isn't used for init |
963 | */ |
959 | */ |
964 | dig_encoder = 0; |
960 | dig_encoder = 0; |
965 | } else |
961 | } else |
966 | connector = radeon_get_connector_for_encoder(encoder); |
962 | connector = radeon_get_connector_for_encoder(encoder); |
967 | 963 | ||
968 | if (connector) { |
964 | if (connector) { |
969 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
965 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
970 | struct radeon_connector_atom_dig *dig_connector = |
966 | struct radeon_connector_atom_dig *dig_connector = |
971 | radeon_connector->con_priv; |
967 | radeon_connector->con_priv; |
972 | 968 | ||
973 | dp_clock = dig_connector->dp_clock; |
969 | dp_clock = dig_connector->dp_clock; |
974 | dp_lane_count = dig_connector->dp_lane_count; |
970 | dp_lane_count = dig_connector->dp_lane_count; |
975 | connector_object_id = |
971 | connector_object_id = |
976 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
972 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
977 | igp_lane_info = dig_connector->igp_lane_info; |
973 | igp_lane_info = dig_connector->igp_lane_info; |
978 | } |
974 | } |
979 | 975 | ||
980 | /* no dig encoder assigned */ |
976 | /* no dig encoder assigned */ |
981 | if (dig_encoder == -1) |
977 | if (dig_encoder == -1) |
982 | return; |
978 | return; |
983 | 979 | ||
984 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
980 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
985 | is_dp = true; |
981 | is_dp = true; |
986 | 982 | ||
987 | memset(&args, 0, sizeof(args)); |
983 | memset(&args, 0, sizeof(args)); |
988 | 984 | ||
989 | switch (radeon_encoder->encoder_id) { |
985 | switch (radeon_encoder->encoder_id) { |
990 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
986 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
991 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
987 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
992 | break; |
988 | break; |
993 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
989 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
994 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
990 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
995 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
991 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
996 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
992 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
997 | break; |
993 | break; |
998 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
994 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
999 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
995 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
1000 | break; |
996 | break; |
1001 | } |
997 | } |
1002 | 998 | ||
1003 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
999 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1004 | return; |
1000 | return; |
1005 | 1001 | ||
1006 | args.v1.ucAction = action; |
1002 | args.v1.ucAction = action; |
1007 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1003 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1008 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
1004 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
1009 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1005 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1010 | args.v1.asMode.ucLaneSel = lane_num; |
1006 | args.v1.asMode.ucLaneSel = lane_num; |
1011 | args.v1.asMode.ucLaneSet = lane_set; |
1007 | args.v1.asMode.ucLaneSet = lane_set; |
1012 | } else { |
1008 | } else { |
1013 | if (is_dp) |
1009 | if (is_dp) |
1014 | args.v1.usPixelClock = |
1010 | args.v1.usPixelClock = |
1015 | cpu_to_le16(dp_clock / 10); |
1011 | cpu_to_le16(dp_clock / 10); |
1016 | else if (radeon_encoder->pixel_clock > 165000) |
1012 | else if (radeon_encoder->pixel_clock > 165000) |
1017 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1013 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1018 | else |
1014 | else |
1019 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1015 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1020 | } |
1016 | } |
1021 | if (ASIC_IS_DCE4(rdev)) { |
1017 | if (ASIC_IS_DCE4(rdev)) { |
1022 | if (is_dp) |
1018 | if (is_dp) |
1023 | args.v3.ucLaneNum = dp_lane_count; |
1019 | args.v3.ucLaneNum = dp_lane_count; |
1024 | else if (radeon_encoder->pixel_clock > 165000) |
1020 | else if (radeon_encoder->pixel_clock > 165000) |
1025 | args.v3.ucLaneNum = 8; |
1021 | args.v3.ucLaneNum = 8; |
1026 | else |
1022 | else |
1027 | args.v3.ucLaneNum = 4; |
1023 | args.v3.ucLaneNum = 4; |
1028 | 1024 | ||
1029 | if (dig->linkb) |
1025 | if (dig->linkb) |
1030 | args.v3.acConfig.ucLinkSel = 1; |
1026 | args.v3.acConfig.ucLinkSel = 1; |
1031 | if (dig_encoder & 1) |
1027 | if (dig_encoder & 1) |
1032 | args.v3.acConfig.ucEncoderSel = 1; |
1028 | args.v3.acConfig.ucEncoderSel = 1; |
1033 | 1029 | ||
1034 | /* Select the PLL for the PHY |
1030 | /* Select the PLL for the PHY |
1035 | * DP PHY should be clocked from external src if there is |
1031 | * DP PHY should be clocked from external src if there is |
1036 | * one. |
1032 | * one. |
1037 | */ |
1033 | */ |
1038 | if (encoder->crtc) { |
1034 | if (encoder->crtc) { |
1039 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1035 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1040 | pll_id = radeon_crtc->pll_id; |
1036 | pll_id = radeon_crtc->pll_id; |
1041 | } |
1037 | } |
1042 | 1038 | ||
1043 | if (ASIC_IS_DCE5(rdev)) { |
1039 | if (ASIC_IS_DCE5(rdev)) { |
1044 | /* On DCE5 DCPLL usually generates the DP ref clock */ |
1040 | /* On DCE5 DCPLL usually generates the DP ref clock */ |
1045 | if (is_dp) { |
1041 | if (is_dp) { |
1046 | if (rdev->clock.dp_extclk) |
1042 | if (rdev->clock.dp_extclk) |
1047 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; |
1043 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; |
1048 | else |
1044 | else |
1049 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; |
1045 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; |
1050 | } else |
1046 | } else |
1051 | args.v4.acConfig.ucRefClkSource = pll_id; |
1047 | args.v4.acConfig.ucRefClkSource = pll_id; |
1052 | } else { |
1048 | } else { |
1053 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
1049 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
1054 | if (is_dp && rdev->clock.dp_extclk) |
1050 | if (is_dp && rdev->clock.dp_extclk) |
1055 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ |
1051 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ |
1056 | else |
1052 | else |
1057 | args.v3.acConfig.ucRefClkSource = pll_id; |
1053 | args.v3.acConfig.ucRefClkSource = pll_id; |
1058 | } |
1054 | } |
1059 | 1055 | ||
1060 | switch (radeon_encoder->encoder_id) { |
1056 | switch (radeon_encoder->encoder_id) { |
1061 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1057 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1062 | args.v3.acConfig.ucTransmitterSel = 0; |
1058 | args.v3.acConfig.ucTransmitterSel = 0; |
1063 | break; |
1059 | break; |
1064 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1060 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1065 | args.v3.acConfig.ucTransmitterSel = 1; |
1061 | args.v3.acConfig.ucTransmitterSel = 1; |
1066 | break; |
1062 | break; |
1067 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1063 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1068 | args.v3.acConfig.ucTransmitterSel = 2; |
1064 | args.v3.acConfig.ucTransmitterSel = 2; |
1069 | break; |
1065 | break; |
1070 | } |
1066 | } |
1071 | 1067 | ||
1072 | if (is_dp) |
1068 | if (is_dp) |
1073 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
1069 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
1074 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1070 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1075 | if (dig->coherent_mode) |
1071 | if (dig->coherent_mode) |
1076 | args.v3.acConfig.fCoherentMode = 1; |
1072 | args.v3.acConfig.fCoherentMode = 1; |
1077 | if (radeon_encoder->pixel_clock > 165000) |
1073 | if (radeon_encoder->pixel_clock > 165000) |
1078 | args.v3.acConfig.fDualLinkConnector = 1; |
1074 | args.v3.acConfig.fDualLinkConnector = 1; |
1079 | } |
1075 | } |
1080 | } else if (ASIC_IS_DCE32(rdev)) { |
1076 | } else if (ASIC_IS_DCE32(rdev)) { |
1081 | args.v2.acConfig.ucEncoderSel = dig_encoder; |
1077 | args.v2.acConfig.ucEncoderSel = dig_encoder; |
1082 | if (dig->linkb) |
1078 | if (dig->linkb) |
1083 | args.v2.acConfig.ucLinkSel = 1; |
1079 | args.v2.acConfig.ucLinkSel = 1; |
1084 | 1080 | ||
1085 | switch (radeon_encoder->encoder_id) { |
1081 | switch (radeon_encoder->encoder_id) { |
1086 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1082 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1087 | args.v2.acConfig.ucTransmitterSel = 0; |
1083 | args.v2.acConfig.ucTransmitterSel = 0; |
1088 | break; |
1084 | break; |
1089 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1085 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1090 | args.v2.acConfig.ucTransmitterSel = 1; |
1086 | args.v2.acConfig.ucTransmitterSel = 1; |
1091 | break; |
1087 | break; |
1092 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1088 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1093 | args.v2.acConfig.ucTransmitterSel = 2; |
1089 | args.v2.acConfig.ucTransmitterSel = 2; |
1094 | break; |
1090 | break; |
1095 | } |
1091 | } |
1096 | 1092 | ||
1097 | if (is_dp) |
1093 | if (is_dp) { |
- | 1094 | args.v2.acConfig.fCoherentMode = 1; |
|
1098 | args.v2.acConfig.fCoherentMode = 1; |
1095 | args.v2.acConfig.fDPConnector = 1; |
1099 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1096 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1100 | if (dig->coherent_mode) |
1097 | if (dig->coherent_mode) |
1101 | args.v2.acConfig.fCoherentMode = 1; |
1098 | args.v2.acConfig.fCoherentMode = 1; |
1102 | if (radeon_encoder->pixel_clock > 165000) |
1099 | if (radeon_encoder->pixel_clock > 165000) |
1103 | args.v2.acConfig.fDualLinkConnector = 1; |
1100 | args.v2.acConfig.fDualLinkConnector = 1; |
1104 | } |
1101 | } |
1105 | } else { |
1102 | } else { |
1106 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
1103 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
1107 | 1104 | ||
1108 | if (dig_encoder) |
1105 | if (dig_encoder) |
1109 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
1106 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
1110 | else |
1107 | else |
1111 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
1108 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
1112 | 1109 | ||
1113 | if ((rdev->flags & RADEON_IS_IGP) && |
1110 | if ((rdev->flags & RADEON_IS_IGP) && |
1114 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
1111 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
1115 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { |
1112 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { |
1116 | if (igp_lane_info & 0x1) |
1113 | if (igp_lane_info & 0x1) |
1117 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
1114 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
1118 | else if (igp_lane_info & 0x2) |
1115 | else if (igp_lane_info & 0x2) |
1119 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
1116 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
1120 | else if (igp_lane_info & 0x4) |
1117 | else if (igp_lane_info & 0x4) |
1121 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
1118 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
1122 | else if (igp_lane_info & 0x8) |
1119 | else if (igp_lane_info & 0x8) |
1123 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
1120 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
1124 | } else { |
1121 | } else { |
1125 | if (igp_lane_info & 0x3) |
1122 | if (igp_lane_info & 0x3) |
1126 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
1123 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
1127 | else if (igp_lane_info & 0xc) |
1124 | else if (igp_lane_info & 0xc) |
1128 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
1125 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
1129 | } |
1126 | } |
1130 | } |
1127 | } |
1131 | 1128 | ||
1132 | if (dig->linkb) |
1129 | if (dig->linkb) |
1133 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
1130 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
1134 | else |
1131 | else |
1135 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
1132 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
1136 | 1133 | ||
1137 | if (is_dp) |
1134 | if (is_dp) |
1138 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1135 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1139 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1136 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1140 | if (dig->coherent_mode) |
1137 | if (dig->coherent_mode) |
1141 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1138 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1142 | if (radeon_encoder->pixel_clock > 165000) |
1139 | if (radeon_encoder->pixel_clock > 165000) |
1143 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
1140 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
1144 | } |
1141 | } |
1145 | } |
1142 | } |
1146 | 1143 | ||
1147 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1144 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1148 | } |
1145 | } |
1149 | 1146 | ||
1150 | bool |
1147 | bool |
1151 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) |
1148 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) |
1152 | { |
1149 | { |
1153 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1150 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1154 | struct drm_device *dev = radeon_connector->base.dev; |
1151 | struct drm_device *dev = radeon_connector->base.dev; |
1155 | struct radeon_device *rdev = dev->dev_private; |
1152 | struct radeon_device *rdev = dev->dev_private; |
1156 | union dig_transmitter_control args; |
1153 | union dig_transmitter_control args; |
1157 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1154 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1158 | uint8_t frev, crev; |
1155 | uint8_t frev, crev; |
1159 | 1156 | ||
1160 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) |
1157 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) |
1161 | goto done; |
1158 | goto done; |
1162 | 1159 | ||
1163 | if (!ASIC_IS_DCE4(rdev)) |
1160 | if (!ASIC_IS_DCE4(rdev)) |
1164 | goto done; |
1161 | goto done; |
1165 | 1162 | ||
1166 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && |
1163 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && |
1167 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) |
1164 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) |
1168 | goto done; |
1165 | goto done; |
1169 | 1166 | ||
1170 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1167 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1171 | goto done; |
1168 | goto done; |
1172 | 1169 | ||
1173 | memset(&args, 0, sizeof(args)); |
1170 | memset(&args, 0, sizeof(args)); |
1174 | 1171 | ||
1175 | args.v1.ucAction = action; |
1172 | args.v1.ucAction = action; |
1176 | 1173 | ||
1177 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1174 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1178 | 1175 | ||
1179 | /* wait for the panel to power up */ |
1176 | /* wait for the panel to power up */ |
1180 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { |
1177 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { |
1181 | int i; |
1178 | int i; |
1182 | 1179 | ||
1183 | for (i = 0; i < 300; i++) { |
1180 | for (i = 0; i < 300; i++) { |
1184 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) |
1181 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) |
1185 | return true; |
1182 | return true; |
1186 | mdelay(1); |
1183 | mdelay(1); |
1187 | } |
1184 | } |
1188 | return false; |
1185 | return false; |
1189 | } |
1186 | } |
1190 | done: |
1187 | done: |
1191 | return true; |
1188 | return true; |
1192 | } |
1189 | } |
1193 | 1190 | ||
1194 | union external_encoder_control { |
1191 | union external_encoder_control { |
1195 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; |
1192 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; |
1196 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; |
1193 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; |
1197 | }; |
1194 | }; |
1198 | 1195 | ||
1199 | static void |
1196 | static void |
1200 | atombios_external_encoder_setup(struct drm_encoder *encoder, |
1197 | atombios_external_encoder_setup(struct drm_encoder *encoder, |
1201 | struct drm_encoder *ext_encoder, |
1198 | struct drm_encoder *ext_encoder, |
1202 | int action) |
1199 | int action) |
1203 | { |
1200 | { |
1204 | struct drm_device *dev = encoder->dev; |
1201 | struct drm_device *dev = encoder->dev; |
1205 | struct radeon_device *rdev = dev->dev_private; |
1202 | struct radeon_device *rdev = dev->dev_private; |
1206 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1203 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1207 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); |
1204 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); |
1208 | union external_encoder_control args; |
1205 | union external_encoder_control args; |
1209 | struct drm_connector *connector; |
1206 | struct drm_connector *connector; |
1210 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); |
1207 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); |
1211 | u8 frev, crev; |
1208 | u8 frev, crev; |
1212 | int dp_clock = 0; |
1209 | int dp_clock = 0; |
1213 | int dp_lane_count = 0; |
1210 | int dp_lane_count = 0; |
1214 | int connector_object_id = 0; |
1211 | int connector_object_id = 0; |
1215 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
1212 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
1216 | int bpc = 8; |
1213 | int bpc = 8; |
1217 | 1214 | ||
1218 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1215 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1219 | connector = radeon_get_connector_for_encoder_init(encoder); |
1216 | connector = radeon_get_connector_for_encoder_init(encoder); |
1220 | else |
1217 | else |
1221 | connector = radeon_get_connector_for_encoder(encoder); |
1218 | connector = radeon_get_connector_for_encoder(encoder); |
1222 | 1219 | ||
1223 | if (connector) { |
1220 | if (connector) { |
1224 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1221 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1225 | struct radeon_connector_atom_dig *dig_connector = |
1222 | struct radeon_connector_atom_dig *dig_connector = |
1226 | radeon_connector->con_priv; |
1223 | radeon_connector->con_priv; |
1227 | 1224 | ||
1228 | dp_clock = dig_connector->dp_clock; |
1225 | dp_clock = dig_connector->dp_clock; |
1229 | dp_lane_count = dig_connector->dp_lane_count; |
1226 | dp_lane_count = dig_connector->dp_lane_count; |
1230 | connector_object_id = |
1227 | connector_object_id = |
1231 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1228 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1232 | bpc = connector->display_info.bpc; |
1229 | bpc = connector->display_info.bpc; |
1233 | } |
1230 | } |
1234 | 1231 | ||
1235 | memset(&args, 0, sizeof(args)); |
1232 | memset(&args, 0, sizeof(args)); |
1236 | 1233 | ||
1237 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1234 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1238 | return; |
1235 | return; |
1239 | 1236 | ||
1240 | switch (frev) { |
1237 | switch (frev) { |
1241 | case 1: |
1238 | case 1: |
1242 | /* no params on frev 1 */ |
1239 | /* no params on frev 1 */ |
1243 | break; |
1240 | break; |
1244 | case 2: |
1241 | case 2: |
1245 | switch (crev) { |
1242 | switch (crev) { |
1246 | case 1: |
1243 | case 1: |
1247 | case 2: |
1244 | case 2: |
1248 | args.v1.sDigEncoder.ucAction = action; |
1245 | args.v1.sDigEncoder.ucAction = action; |
1249 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1246 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1250 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1247 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1251 | 1248 | ||
1252 | if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
1249 | if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
1253 | if (dp_clock == 270000) |
1250 | if (dp_clock == 270000) |
1254 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
1251 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
1255 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; |
1252 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; |
1256 | } else if (radeon_encoder->pixel_clock > 165000) |
1253 | } else if (radeon_encoder->pixel_clock > 165000) |
1257 | args.v1.sDigEncoder.ucLaneNum = 8; |
1254 | args.v1.sDigEncoder.ucLaneNum = 8; |
1258 | else |
1255 | else |
1259 | args.v1.sDigEncoder.ucLaneNum = 4; |
1256 | args.v1.sDigEncoder.ucLaneNum = 4; |
1260 | break; |
1257 | break; |
1261 | case 3: |
1258 | case 3: |
1262 | args.v3.sExtEncoder.ucAction = action; |
1259 | args.v3.sExtEncoder.ucAction = action; |
1263 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1260 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1264 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
1261 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
1265 | else |
1262 | else |
1266 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1263 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1267 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1264 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1268 | 1265 | ||
1269 | if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
1266 | if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
1270 | if (dp_clock == 270000) |
1267 | if (dp_clock == 270000) |
1271 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
1268 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
1272 | else if (dp_clock == 540000) |
1269 | else if (dp_clock == 540000) |
1273 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; |
1270 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; |
1274 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; |
1271 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; |
1275 | } else if (radeon_encoder->pixel_clock > 165000) |
1272 | } else if (radeon_encoder->pixel_clock > 165000) |
1276 | args.v3.sExtEncoder.ucLaneNum = 8; |
1273 | args.v3.sExtEncoder.ucLaneNum = 8; |
1277 | else |
1274 | else |
1278 | args.v3.sExtEncoder.ucLaneNum = 4; |
1275 | args.v3.sExtEncoder.ucLaneNum = 4; |
1279 | switch (ext_enum) { |
1276 | switch (ext_enum) { |
1280 | case GRAPH_OBJECT_ENUM_ID1: |
1277 | case GRAPH_OBJECT_ENUM_ID1: |
1281 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; |
1278 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; |
1282 | break; |
1279 | break; |
1283 | case GRAPH_OBJECT_ENUM_ID2: |
1280 | case GRAPH_OBJECT_ENUM_ID2: |
1284 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; |
1281 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; |
1285 | break; |
1282 | break; |
1286 | case GRAPH_OBJECT_ENUM_ID3: |
1283 | case GRAPH_OBJECT_ENUM_ID3: |
1287 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; |
1284 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; |
1288 | break; |
1285 | break; |
1289 | } |
1286 | } |
1290 | switch (bpc) { |
1287 | switch (bpc) { |
1291 | case 0: |
1288 | case 0: |
1292 | args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; |
1289 | args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; |
1293 | break; |
1290 | break; |
1294 | case 6: |
1291 | case 6: |
1295 | args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
1292 | args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
1296 | break; |
1293 | break; |
1297 | case 8: |
1294 | case 8: |
1298 | default: |
1295 | default: |
1299 | args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
1296 | args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
1300 | break; |
1297 | break; |
1301 | case 10: |
1298 | case 10: |
1302 | args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
1299 | args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
1303 | break; |
1300 | break; |
1304 | case 12: |
1301 | case 12: |
1305 | args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
1302 | args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
1306 | break; |
1303 | break; |
1307 | case 16: |
1304 | case 16: |
1308 | args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
1305 | args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
1309 | break; |
1306 | break; |
1310 | } |
1307 | } |
1311 | break; |
1308 | break; |
1312 | default: |
1309 | default: |
1313 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1310 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1314 | return; |
1311 | return; |
1315 | } |
1312 | } |
1316 | break; |
1313 | break; |
1317 | default: |
1314 | default: |
1318 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1315 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1319 | return; |
1316 | return; |
1320 | } |
1317 | } |
1321 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1318 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1322 | } |
1319 | } |
1323 | 1320 | ||
1324 | static void |
1321 | static void |
1325 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
1322 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
1326 | { |
1323 | { |
1327 | struct drm_device *dev = encoder->dev; |
1324 | struct drm_device *dev = encoder->dev; |
1328 | struct radeon_device *rdev = dev->dev_private; |
1325 | struct radeon_device *rdev = dev->dev_private; |
1329 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1326 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1330 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1327 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1331 | ENABLE_YUV_PS_ALLOCATION args; |
1328 | ENABLE_YUV_PS_ALLOCATION args; |
1332 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
1329 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
1333 | uint32_t temp, reg; |
1330 | uint32_t temp, reg; |
1334 | 1331 | ||
1335 | memset(&args, 0, sizeof(args)); |
1332 | memset(&args, 0, sizeof(args)); |
1336 | 1333 | ||
1337 | if (rdev->family >= CHIP_R600) |
1334 | if (rdev->family >= CHIP_R600) |
1338 | reg = R600_BIOS_3_SCRATCH; |
1335 | reg = R600_BIOS_3_SCRATCH; |
1339 | else |
1336 | else |
1340 | reg = RADEON_BIOS_3_SCRATCH; |
1337 | reg = RADEON_BIOS_3_SCRATCH; |
1341 | 1338 | ||
1342 | /* XXX: fix up scratch reg handling */ |
1339 | /* XXX: fix up scratch reg handling */ |
1343 | temp = RREG32(reg); |
1340 | temp = RREG32(reg); |
1344 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1341 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1345 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
1342 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
1346 | (radeon_crtc->crtc_id << 18))); |
1343 | (radeon_crtc->crtc_id << 18))); |
1347 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1344 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1348 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1345 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1349 | else |
1346 | else |
1350 | WREG32(reg, 0); |
1347 | WREG32(reg, 0); |
1351 | 1348 | ||
1352 | if (enable) |
1349 | if (enable) |
1353 | args.ucEnable = ATOM_ENABLE; |
1350 | args.ucEnable = ATOM_ENABLE; |
1354 | args.ucCRTC = radeon_crtc->crtc_id; |
1351 | args.ucCRTC = radeon_crtc->crtc_id; |
1355 | 1352 | ||
1356 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1353 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1357 | 1354 | ||
1358 | WREG32(reg, temp); |
1355 | WREG32(reg, temp); |
1359 | } |
1356 | } |
1360 | 1357 | ||
1361 | static void |
1358 | static void |
1362 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1359 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1363 | { |
1360 | { |
1364 | struct drm_device *dev = encoder->dev; |
1361 | struct drm_device *dev = encoder->dev; |
1365 | struct radeon_device *rdev = dev->dev_private; |
1362 | struct radeon_device *rdev = dev->dev_private; |
1366 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1363 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1367 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
1364 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
1368 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
1365 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
1369 | int index = 0; |
1366 | int index = 0; |
1370 | bool is_dig = false; |
1367 | bool is_dig = false; |
1371 | bool is_dce5_dac = false; |
1368 | bool is_dce5_dac = false; |
1372 | bool is_dce5_dvo = false; |
1369 | bool is_dce5_dvo = false; |
1373 | 1370 | ||
1374 | memset(&args, 0, sizeof(args)); |
1371 | memset(&args, 0, sizeof(args)); |
1375 | 1372 | ||
1376 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1373 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1377 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1374 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1378 | radeon_encoder->active_device); |
1375 | radeon_encoder->active_device); |
1379 | switch (radeon_encoder->encoder_id) { |
1376 | switch (radeon_encoder->encoder_id) { |
1380 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1377 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1381 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1378 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1382 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
1379 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
1383 | break; |
1380 | break; |
1384 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1381 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1385 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1382 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1386 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1383 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1387 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1384 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1388 | is_dig = true; |
1385 | is_dig = true; |
1389 | break; |
1386 | break; |
1390 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1387 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1391 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1388 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1392 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1389 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1393 | break; |
1390 | break; |
1394 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1391 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1395 | if (ASIC_IS_DCE5(rdev)) |
1392 | if (ASIC_IS_DCE5(rdev)) |
1396 | is_dce5_dvo = true; |
1393 | is_dce5_dvo = true; |
1397 | else if (ASIC_IS_DCE3(rdev)) |
1394 | else if (ASIC_IS_DCE3(rdev)) |
1398 | is_dig = true; |
1395 | is_dig = true; |
1399 | else |
1396 | else |
1400 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1397 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1401 | break; |
1398 | break; |
1402 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1399 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1403 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1400 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1404 | break; |
1401 | break; |
1405 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1402 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1406 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1403 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1407 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1404 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1408 | else |
1405 | else |
1409 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
1406 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
1410 | break; |
1407 | break; |
1411 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1408 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1412 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1409 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1413 | if (ASIC_IS_DCE5(rdev)) |
1410 | if (ASIC_IS_DCE5(rdev)) |
1414 | is_dce5_dac = true; |
1411 | is_dce5_dac = true; |
1415 | else { |
1412 | else { |
1416 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1413 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1417 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1414 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1418 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1415 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1419 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1416 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1420 | else |
1417 | else |
1421 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
1418 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
1422 | } |
1419 | } |
1423 | break; |
1420 | break; |
1424 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1421 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1425 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1422 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1426 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1423 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1427 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1424 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1428 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1425 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1429 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1426 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1430 | else |
1427 | else |
1431 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
1428 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
1432 | break; |
1429 | break; |
1433 | } |
1430 | } |
1434 | 1431 | ||
1435 | if (is_dig) { |
1432 | if (is_dig) { |
1436 | switch (mode) { |
1433 | switch (mode) { |
1437 | case DRM_MODE_DPMS_ON: |
1434 | case DRM_MODE_DPMS_ON: |
- | 1435 | /* some early dce3.2 boards have a bug in their transmitter control table */ |
|
- | 1436 | if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) |
|
- | 1437 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
|
- | 1438 | else |
|
1438 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
1439 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
1439 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
1440 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
1440 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1441 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1441 | 1442 | ||
1442 | if (connector && |
1443 | if (connector && |
1443 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { |
1444 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { |
1444 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1445 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1445 | struct radeon_connector_atom_dig *radeon_dig_connector = |
1446 | struct radeon_connector_atom_dig *radeon_dig_connector = |
1446 | radeon_connector->con_priv; |
1447 | radeon_connector->con_priv; |
1447 | atombios_set_edp_panel_power(connector, |
1448 | atombios_set_edp_panel_power(connector, |
1448 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
1449 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
1449 | radeon_dig_connector->edp_on = true; |
1450 | radeon_dig_connector->edp_on = true; |
1450 | } |
1451 | } |
1451 | if (ASIC_IS_DCE4(rdev)) |
1452 | if (ASIC_IS_DCE4(rdev)) |
1452 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
1453 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
1453 | radeon_dp_link_train(encoder, connector); |
1454 | radeon_dp_link_train(encoder, connector); |
1454 | if (ASIC_IS_DCE4(rdev)) |
1455 | if (ASIC_IS_DCE4(rdev)) |
1455 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
1456 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
1456 | } |
1457 | } |
1457 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1458 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1458 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
1459 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
1459 | break; |
1460 | break; |
1460 | case DRM_MODE_DPMS_STANDBY: |
1461 | case DRM_MODE_DPMS_STANDBY: |
1461 | case DRM_MODE_DPMS_SUSPEND: |
1462 | case DRM_MODE_DPMS_SUSPEND: |
1462 | case DRM_MODE_DPMS_OFF: |
1463 | case DRM_MODE_DPMS_OFF: |
1463 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
1464 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
1464 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
1465 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
1465 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1466 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1466 | 1467 | ||
1467 | if (ASIC_IS_DCE4(rdev)) |
1468 | if (ASIC_IS_DCE4(rdev)) |
1468 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
1469 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
1469 | if (connector && |
1470 | if (connector && |
1470 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { |
1471 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { |
1471 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1472 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1472 | struct radeon_connector_atom_dig *radeon_dig_connector = |
1473 | struct radeon_connector_atom_dig *radeon_dig_connector = |
1473 | radeon_connector->con_priv; |
1474 | radeon_connector->con_priv; |
1474 | atombios_set_edp_panel_power(connector, |
1475 | atombios_set_edp_panel_power(connector, |
1475 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1476 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1476 | radeon_dig_connector->edp_on = false; |
1477 | radeon_dig_connector->edp_on = false; |
1477 | } |
1478 | } |
1478 | } |
1479 | } |
1479 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1480 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1480 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
1481 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
1481 | break; |
1482 | break; |
1482 | } |
1483 | } |
1483 | } else if (is_dce5_dac) { |
1484 | } else if (is_dce5_dac) { |
1484 | switch (mode) { |
1485 | switch (mode) { |
1485 | case DRM_MODE_DPMS_ON: |
1486 | case DRM_MODE_DPMS_ON: |
1486 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1487 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1487 | break; |
1488 | break; |
1488 | case DRM_MODE_DPMS_STANDBY: |
1489 | case DRM_MODE_DPMS_STANDBY: |
1489 | case DRM_MODE_DPMS_SUSPEND: |
1490 | case DRM_MODE_DPMS_SUSPEND: |
1490 | case DRM_MODE_DPMS_OFF: |
1491 | case DRM_MODE_DPMS_OFF: |
1491 | atombios_dac_setup(encoder, ATOM_DISABLE); |
1492 | atombios_dac_setup(encoder, ATOM_DISABLE); |
1492 | break; |
1493 | break; |
1493 | } |
1494 | } |
1494 | } else if (is_dce5_dvo) { |
1495 | } else if (is_dce5_dvo) { |
1495 | switch (mode) { |
1496 | switch (mode) { |
1496 | case DRM_MODE_DPMS_ON: |
1497 | case DRM_MODE_DPMS_ON: |
1497 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1498 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1498 | break; |
1499 | break; |
1499 | case DRM_MODE_DPMS_STANDBY: |
1500 | case DRM_MODE_DPMS_STANDBY: |
1500 | case DRM_MODE_DPMS_SUSPEND: |
1501 | case DRM_MODE_DPMS_SUSPEND: |
1501 | case DRM_MODE_DPMS_OFF: |
1502 | case DRM_MODE_DPMS_OFF: |
1502 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
1503 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
1503 | break; |
1504 | break; |
1504 | } |
1505 | } |
1505 | } else { |
1506 | } else { |
1506 | switch (mode) { |
1507 | switch (mode) { |
1507 | case DRM_MODE_DPMS_ON: |
1508 | case DRM_MODE_DPMS_ON: |
1508 | args.ucAction = ATOM_ENABLE; |
1509 | args.ucAction = ATOM_ENABLE; |
1509 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1510 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1510 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1511 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1511 | args.ucAction = ATOM_LCD_BLON; |
1512 | args.ucAction = ATOM_LCD_BLON; |
1512 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1513 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1513 | } |
1514 | } |
1514 | break; |
1515 | break; |
1515 | case DRM_MODE_DPMS_STANDBY: |
1516 | case DRM_MODE_DPMS_STANDBY: |
1516 | case DRM_MODE_DPMS_SUSPEND: |
1517 | case DRM_MODE_DPMS_SUSPEND: |
1517 | case DRM_MODE_DPMS_OFF: |
1518 | case DRM_MODE_DPMS_OFF: |
1518 | args.ucAction = ATOM_DISABLE; |
1519 | args.ucAction = ATOM_DISABLE; |
1519 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1520 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1520 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1521 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1521 | args.ucAction = ATOM_LCD_BLOFF; |
1522 | args.ucAction = ATOM_LCD_BLOFF; |
1522 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1523 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1523 | } |
1524 | } |
1524 | break; |
1525 | break; |
1525 | } |
1526 | } |
1526 | } |
1527 | } |
1527 | 1528 | ||
1528 | if (ext_encoder) { |
1529 | if (ext_encoder) { |
1529 | int action; |
- | |
1530 | - | ||
1531 | switch (mode) { |
1530 | switch (mode) { |
1532 | case DRM_MODE_DPMS_ON: |
1531 | case DRM_MODE_DPMS_ON: |
1533 | default: |
1532 | default: |
1534 | if (ASIC_IS_DCE41(rdev)) |
1533 | if (ASIC_IS_DCE41(rdev)) { |
- | 1534 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
1535 | action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; |
1535 | EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); |
- | 1536 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
- | 1537 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); |
|
1536 | else |
1538 | } else |
1537 | action = ATOM_ENABLE; |
1539 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
1538 | break; |
1540 | break; |
1539 | case DRM_MODE_DPMS_STANDBY: |
1541 | case DRM_MODE_DPMS_STANDBY: |
1540 | case DRM_MODE_DPMS_SUSPEND: |
1542 | case DRM_MODE_DPMS_SUSPEND: |
1541 | case DRM_MODE_DPMS_OFF: |
1543 | case DRM_MODE_DPMS_OFF: |
1542 | if (ASIC_IS_DCE41(rdev)) |
1544 | if (ASIC_IS_DCE41(rdev)) { |
- | 1545 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
- | 1546 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); |
|
- | 1547 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
1543 | action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; |
1548 | EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); |
1544 | else |
1549 | } else |
1545 | action = ATOM_DISABLE; |
1550 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
1546 | break; |
1551 | break; |
1547 | } |
1552 | } |
1548 | atombios_external_encoder_setup(encoder, ext_encoder, action); |
- | |
1549 | } |
1553 | } |
1550 | 1554 | ||
1551 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1555 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1552 | 1556 | ||
1553 | } |
1557 | } |
1554 | 1558 | ||
1555 | union crtc_source_param { |
1559 | union crtc_source_param { |
1556 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1560 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1557 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
1561 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
1558 | }; |
1562 | }; |
1559 | 1563 | ||
1560 | static void |
1564 | static void |
1561 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
1565 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
1562 | { |
1566 | { |
1563 | struct drm_device *dev = encoder->dev; |
1567 | struct drm_device *dev = encoder->dev; |
1564 | struct radeon_device *rdev = dev->dev_private; |
1568 | struct radeon_device *rdev = dev->dev_private; |
1565 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1569 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1566 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1570 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1567 | union crtc_source_param args; |
1571 | union crtc_source_param args; |
1568 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1572 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1569 | uint8_t frev, crev; |
1573 | uint8_t frev, crev; |
1570 | struct radeon_encoder_atom_dig *dig; |
1574 | struct radeon_encoder_atom_dig *dig; |
1571 | 1575 | ||
1572 | memset(&args, 0, sizeof(args)); |
1576 | memset(&args, 0, sizeof(args)); |
1573 | 1577 | ||
1574 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1578 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1575 | return; |
1579 | return; |
1576 | 1580 | ||
1577 | switch (frev) { |
1581 | switch (frev) { |
1578 | case 1: |
1582 | case 1: |
1579 | switch (crev) { |
1583 | switch (crev) { |
1580 | case 1: |
1584 | case 1: |
1581 | default: |
1585 | default: |
1582 | if (ASIC_IS_AVIVO(rdev)) |
1586 | if (ASIC_IS_AVIVO(rdev)) |
1583 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1587 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1584 | else { |
1588 | else { |
1585 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
1589 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
1586 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1590 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1587 | } else { |
1591 | } else { |
1588 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
1592 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
1589 | } |
1593 | } |
1590 | } |
1594 | } |
1591 | switch (radeon_encoder->encoder_id) { |
1595 | switch (radeon_encoder->encoder_id) { |
1592 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1596 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1593 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1597 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1594 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
1598 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
1595 | break; |
1599 | break; |
1596 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1600 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1597 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1601 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1598 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1602 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1599 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1603 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1600 | else |
1604 | else |
1601 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1605 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1602 | break; |
1606 | break; |
1603 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1607 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1604 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1608 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1605 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1609 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1606 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1610 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1607 | break; |
1611 | break; |
1608 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1612 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1609 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1613 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1610 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1614 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1611 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1615 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1612 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1616 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1613 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1617 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1614 | else |
1618 | else |
1615 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1619 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1616 | break; |
1620 | break; |
1617 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1621 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1618 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1622 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1619 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1623 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1620 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1624 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1621 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1625 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1622 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1626 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1623 | else |
1627 | else |
1624 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1628 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1625 | break; |
1629 | break; |
1626 | } |
1630 | } |
1627 | break; |
1631 | break; |
1628 | case 2: |
1632 | case 2: |
1629 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1633 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1630 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1634 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1631 | switch (radeon_encoder->encoder_id) { |
1635 | switch (radeon_encoder->encoder_id) { |
1632 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1636 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1633 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1637 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1634 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1638 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1635 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1639 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1636 | dig = radeon_encoder->enc_priv; |
1640 | dig = radeon_encoder->enc_priv; |
1637 | switch (dig->dig_encoder) { |
1641 | switch (dig->dig_encoder) { |
1638 | case 0: |
1642 | case 0: |
1639 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1643 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1640 | break; |
1644 | break; |
1641 | case 1: |
1645 | case 1: |
1642 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1646 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1643 | break; |
1647 | break; |
1644 | case 2: |
1648 | case 2: |
1645 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; |
1649 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; |
1646 | break; |
1650 | break; |
1647 | case 3: |
1651 | case 3: |
1648 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; |
1652 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; |
1649 | break; |
1653 | break; |
1650 | case 4: |
1654 | case 4: |
1651 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1655 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1652 | break; |
1656 | break; |
1653 | case 5: |
1657 | case 5: |
1654 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1658 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1655 | break; |
1659 | break; |
1656 | } |
1660 | } |
1657 | break; |
1661 | break; |
1658 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1662 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1659 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1663 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1660 | break; |
1664 | break; |
1661 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1665 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1662 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1666 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1663 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1667 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1664 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1668 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1665 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1669 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1666 | else |
1670 | else |
1667 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1671 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1668 | break; |
1672 | break; |
1669 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1673 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1670 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1674 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1671 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1675 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1672 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1676 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1673 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1677 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1674 | else |
1678 | else |
1675 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1679 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1676 | break; |
1680 | break; |
1677 | } |
1681 | } |
1678 | break; |
1682 | break; |
1679 | } |
1683 | } |
1680 | break; |
1684 | break; |
1681 | default: |
1685 | default: |
1682 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1686 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1683 | return; |
1687 | return; |
1684 | } |
1688 | } |
1685 | 1689 | ||
1686 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1690 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1687 | 1691 | ||
1688 | /* update scratch regs with new routing */ |
1692 | /* update scratch regs with new routing */ |
1689 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
1693 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
1690 | } |
1694 | } |
1691 | 1695 | ||
1692 | static void |
1696 | static void |
1693 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1697 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1694 | struct drm_display_mode *mode) |
1698 | struct drm_display_mode *mode) |
1695 | { |
1699 | { |
1696 | struct drm_device *dev = encoder->dev; |
1700 | struct drm_device *dev = encoder->dev; |
1697 | struct radeon_device *rdev = dev->dev_private; |
1701 | struct radeon_device *rdev = dev->dev_private; |
1698 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1702 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1699 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1703 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1700 | 1704 | ||
1701 | /* Funky macbooks */ |
1705 | /* Funky macbooks */ |
1702 | if ((dev->pdev->device == 0x71C5) && |
1706 | if ((dev->pdev->device == 0x71C5) && |
1703 | (dev->pdev->subsystem_vendor == 0x106b) && |
1707 | (dev->pdev->subsystem_vendor == 0x106b) && |
1704 | (dev->pdev->subsystem_device == 0x0080)) { |
1708 | (dev->pdev->subsystem_device == 0x0080)) { |
1705 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1709 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1706 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1710 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1707 | 1711 | ||
1708 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1712 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1709 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1713 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1710 | 1714 | ||
1711 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1715 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1712 | } |
1716 | } |
1713 | } |
1717 | } |
1714 | 1718 | ||
1715 | /* set scaler clears this on some chips */ |
1719 | /* set scaler clears this on some chips */ |
1716 | if (ASIC_IS_AVIVO(rdev) && |
1720 | if (ASIC_IS_AVIVO(rdev) && |
1717 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
1721 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
1718 | if (ASIC_IS_DCE4(rdev)) { |
1722 | if (ASIC_IS_DCE4(rdev)) { |
1719 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1723 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1720 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
1724 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
1721 | EVERGREEN_INTERLEAVE_EN); |
1725 | EVERGREEN_INTERLEAVE_EN); |
1722 | else |
1726 | else |
1723 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1727 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1724 | } else { |
1728 | } else { |
1725 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1729 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1726 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
1730 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
1727 | AVIVO_D1MODE_INTERLEAVE_EN); |
1731 | AVIVO_D1MODE_INTERLEAVE_EN); |
1728 | else |
1732 | else |
1729 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1733 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1730 | } |
1734 | } |
1731 | } |
1735 | } |
1732 | } |
1736 | } |
1733 | 1737 | ||
1734 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1738 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1735 | { |
1739 | { |
1736 | struct drm_device *dev = encoder->dev; |
1740 | struct drm_device *dev = encoder->dev; |
1737 | struct radeon_device *rdev = dev->dev_private; |
1741 | struct radeon_device *rdev = dev->dev_private; |
1738 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1742 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1739 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1743 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1740 | struct drm_encoder *test_encoder; |
1744 | struct drm_encoder *test_encoder; |
1741 | struct radeon_encoder_atom_dig *dig; |
1745 | struct radeon_encoder_atom_dig *dig; |
1742 | uint32_t dig_enc_in_use = 0; |
1746 | uint32_t dig_enc_in_use = 0; |
1743 | 1747 | ||
1744 | /* DCE4/5 */ |
1748 | /* DCE4/5 */ |
1745 | if (ASIC_IS_DCE4(rdev)) { |
1749 | if (ASIC_IS_DCE4(rdev)) { |
1746 | dig = radeon_encoder->enc_priv; |
1750 | dig = radeon_encoder->enc_priv; |
1747 | if (ASIC_IS_DCE41(rdev)) |
1751 | if (ASIC_IS_DCE41(rdev)) |
1748 | return radeon_crtc->crtc_id; |
1752 | return radeon_crtc->crtc_id; |
1749 | else { |
1753 | else { |
1750 | switch (radeon_encoder->encoder_id) { |
1754 | switch (radeon_encoder->encoder_id) { |
1751 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1755 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1752 | if (dig->linkb) |
1756 | if (dig->linkb) |
1753 | return 1; |
1757 | return 1; |
1754 | else |
1758 | else |
1755 | return 0; |
1759 | return 0; |
1756 | break; |
1760 | break; |
1757 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1761 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1758 | if (dig->linkb) |
1762 | if (dig->linkb) |
1759 | return 3; |
1763 | return 3; |
1760 | else |
1764 | else |
1761 | return 2; |
1765 | return 2; |
1762 | break; |
1766 | break; |
1763 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1767 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1764 | if (dig->linkb) |
1768 | if (dig->linkb) |
1765 | return 5; |
1769 | return 5; |
1766 | else |
1770 | else |
1767 | return 4; |
1771 | return 4; |
1768 | break; |
1772 | break; |
1769 | } |
1773 | } |
1770 | } |
1774 | } |
1771 | } |
1775 | } |
1772 | 1776 | ||
1773 | /* on DCE32 and encoder can driver any block so just crtc id */ |
1777 | /* on DCE32 and encoder can driver any block so just crtc id */ |
1774 | if (ASIC_IS_DCE32(rdev)) { |
1778 | if (ASIC_IS_DCE32(rdev)) { |
1775 | return radeon_crtc->crtc_id; |
1779 | return radeon_crtc->crtc_id; |
1776 | } |
1780 | } |
1777 | 1781 | ||
1778 | /* on DCE3 - LVTMA can only be driven by DIGB */ |
1782 | /* on DCE3 - LVTMA can only be driven by DIGB */ |
1779 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1783 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1780 | struct radeon_encoder *radeon_test_encoder; |
1784 | struct radeon_encoder *radeon_test_encoder; |
1781 | 1785 | ||
1782 | if (encoder == test_encoder) |
1786 | if (encoder == test_encoder) |
1783 | continue; |
1787 | continue; |
1784 | 1788 | ||
1785 | if (!radeon_encoder_is_digital(test_encoder)) |
1789 | if (!radeon_encoder_is_digital(test_encoder)) |
1786 | continue; |
1790 | continue; |
1787 | 1791 | ||
1788 | radeon_test_encoder = to_radeon_encoder(test_encoder); |
1792 | radeon_test_encoder = to_radeon_encoder(test_encoder); |
1789 | dig = radeon_test_encoder->enc_priv; |
1793 | dig = radeon_test_encoder->enc_priv; |
1790 | 1794 | ||
1791 | if (dig->dig_encoder >= 0) |
1795 | if (dig->dig_encoder >= 0) |
1792 | dig_enc_in_use |= (1 << dig->dig_encoder); |
1796 | dig_enc_in_use |= (1 << dig->dig_encoder); |
1793 | } |
1797 | } |
1794 | 1798 | ||
1795 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { |
1799 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { |
1796 | if (dig_enc_in_use & 0x2) |
1800 | if (dig_enc_in_use & 0x2) |
1797 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); |
1801 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); |
1798 | return 1; |
1802 | return 1; |
1799 | } |
1803 | } |
1800 | if (!(dig_enc_in_use & 1)) |
1804 | if (!(dig_enc_in_use & 1)) |
1801 | return 0; |
1805 | return 0; |
1802 | return 1; |
1806 | return 1; |
1803 | } |
1807 | } |
1804 | 1808 | ||
1805 | /* This only needs to be called once at startup */ |
1809 | /* This only needs to be called once at startup */ |
1806 | void |
1810 | void |
1807 | radeon_atom_encoder_init(struct radeon_device *rdev) |
1811 | radeon_atom_encoder_init(struct radeon_device *rdev) |
1808 | { |
1812 | { |
1809 | struct drm_device *dev = rdev->ddev; |
1813 | struct drm_device *dev = rdev->ddev; |
1810 | struct drm_encoder *encoder; |
1814 | struct drm_encoder *encoder; |
1811 | 1815 | ||
1812 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1816 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1813 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1817 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1814 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
1818 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
1815 | 1819 | ||
1816 | switch (radeon_encoder->encoder_id) { |
1820 | switch (radeon_encoder->encoder_id) { |
1817 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1821 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1818 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1822 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1819 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1823 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1820 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1824 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1821 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
1825 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
1822 | break; |
1826 | break; |
1823 | default: |
1827 | default: |
1824 | break; |
1828 | break; |
1825 | } |
1829 | } |
1826 | 1830 | ||
1827 | if (ext_encoder && ASIC_IS_DCE41(rdev)) |
1831 | if (ext_encoder && ASIC_IS_DCE41(rdev)) |
1828 | atombios_external_encoder_setup(encoder, ext_encoder, |
1832 | atombios_external_encoder_setup(encoder, ext_encoder, |
1829 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); |
1833 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); |
1830 | } |
1834 | } |
1831 | } |
1835 | } |
1832 | 1836 | ||
1833 | static void |
1837 | static void |
1834 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
1838 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
1835 | struct drm_display_mode *mode, |
1839 | struct drm_display_mode *mode, |
1836 | struct drm_display_mode *adjusted_mode) |
1840 | struct drm_display_mode *adjusted_mode) |
1837 | { |
1841 | { |
1838 | struct drm_device *dev = encoder->dev; |
1842 | struct drm_device *dev = encoder->dev; |
1839 | struct radeon_device *rdev = dev->dev_private; |
1843 | struct radeon_device *rdev = dev->dev_private; |
1840 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1844 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1841 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
1845 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
1842 | 1846 | ||
1843 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1847 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1844 | 1848 | ||
1845 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
1849 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
1846 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1850 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1847 | atombios_yuv_setup(encoder, true); |
1851 | atombios_yuv_setup(encoder, true); |
1848 | else |
1852 | else |
1849 | atombios_yuv_setup(encoder, false); |
1853 | atombios_yuv_setup(encoder, false); |
1850 | } |
1854 | } |
1851 | 1855 | ||
1852 | switch (radeon_encoder->encoder_id) { |
1856 | switch (radeon_encoder->encoder_id) { |
1853 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1857 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1854 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1858 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1855 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1859 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1856 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1860 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1857 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
1861 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
1858 | break; |
1862 | break; |
1859 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1863 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1860 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1864 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1861 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1865 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1862 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1866 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1863 | if (ASIC_IS_DCE4(rdev)) { |
1867 | if (ASIC_IS_DCE4(rdev)) { |
1864 | /* disable the transmitter */ |
1868 | /* disable the transmitter */ |
1865 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1869 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1866 | /* setup and enable the encoder */ |
1870 | /* setup and enable the encoder */ |
1867 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1871 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1868 | 1872 | ||
1869 | /* enable the transmitter */ |
1873 | /* enable the transmitter */ |
1870 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1874 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1871 | } else { |
1875 | } else { |
1872 | /* disable the encoder and transmitter */ |
1876 | /* disable the encoder and transmitter */ |
1873 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1877 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1874 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1878 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1875 | 1879 | ||
1876 | /* setup and enable the encoder and transmitter */ |
1880 | /* setup and enable the encoder and transmitter */ |
1877 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
1881 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
1878 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1882 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1879 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1883 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1880 | } |
1884 | } |
1881 | break; |
1885 | break; |
1882 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1886 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1883 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1887 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1884 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1888 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1885 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1889 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1886 | break; |
1890 | break; |
1887 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1891 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1888 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1892 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1889 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1893 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1890 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1894 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1891 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1895 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1892 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
1896 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
1893 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1897 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1894 | atombios_tv_setup(encoder, ATOM_ENABLE); |
1898 | atombios_tv_setup(encoder, ATOM_ENABLE); |
1895 | else |
1899 | else |
1896 | atombios_tv_setup(encoder, ATOM_DISABLE); |
1900 | atombios_tv_setup(encoder, ATOM_DISABLE); |
1897 | } |
1901 | } |
1898 | break; |
1902 | break; |
1899 | } |
1903 | } |
1900 | 1904 | ||
1901 | if (ext_encoder) { |
1905 | if (ext_encoder) { |
1902 | if (ASIC_IS_DCE41(rdev)) |
1906 | if (ASIC_IS_DCE41(rdev)) |
1903 | atombios_external_encoder_setup(encoder, ext_encoder, |
1907 | atombios_external_encoder_setup(encoder, ext_encoder, |
1904 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
1908 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
1905 | else |
1909 | else |
1906 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
1910 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
1907 | } |
1911 | } |
1908 | 1912 | ||
1909 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
1913 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
1910 | 1914 | ||
1911 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
1915 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
1912 | r600_hdmi_enable(encoder); |
1916 | r600_hdmi_enable(encoder); |
1913 | r600_hdmi_setmode(encoder, adjusted_mode); |
1917 | r600_hdmi_setmode(encoder, adjusted_mode); |
1914 | } |
1918 | } |
1915 | } |
1919 | } |
1916 | 1920 | ||
1917 | static bool |
1921 | static bool |
1918 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1922 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1919 | { |
1923 | { |
1920 | struct drm_device *dev = encoder->dev; |
1924 | struct drm_device *dev = encoder->dev; |
1921 | struct radeon_device *rdev = dev->dev_private; |
1925 | struct radeon_device *rdev = dev->dev_private; |
1922 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1926 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1923 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1927 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1924 | 1928 | ||
1925 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
1929 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
1926 | ATOM_DEVICE_CV_SUPPORT | |
1930 | ATOM_DEVICE_CV_SUPPORT | |
1927 | ATOM_DEVICE_CRT_SUPPORT)) { |
1931 | ATOM_DEVICE_CRT_SUPPORT)) { |
1928 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
1932 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
1929 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
1933 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
1930 | uint8_t frev, crev; |
1934 | uint8_t frev, crev; |
1931 | 1935 | ||
1932 | memset(&args, 0, sizeof(args)); |
1936 | memset(&args, 0, sizeof(args)); |
1933 | 1937 | ||
1934 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1938 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1935 | return false; |
1939 | return false; |
1936 | 1940 | ||
1937 | args.sDacload.ucMisc = 0; |
1941 | args.sDacload.ucMisc = 0; |
1938 | 1942 | ||
1939 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
1943 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
1940 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
1944 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
1941 | args.sDacload.ucDacType = ATOM_DAC_A; |
1945 | args.sDacload.ucDacType = ATOM_DAC_A; |
1942 | else |
1946 | else |
1943 | args.sDacload.ucDacType = ATOM_DAC_B; |
1947 | args.sDacload.ucDacType = ATOM_DAC_B; |
1944 | 1948 | ||
1945 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
1949 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
1946 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
1950 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
1947 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
1951 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
1948 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
1952 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
1949 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1953 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1950 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1954 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1951 | if (crev >= 3) |
1955 | if (crev >= 3) |
1952 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1956 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1953 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1957 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1954 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1958 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1955 | if (crev >= 3) |
1959 | if (crev >= 3) |
1956 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1960 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1957 | } |
1961 | } |
1958 | 1962 | ||
1959 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1963 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1960 | 1964 | ||
1961 | return true; |
1965 | return true; |
1962 | } else |
1966 | } else |
1963 | return false; |
1967 | return false; |
1964 | } |
1968 | } |
1965 | 1969 | ||
1966 | static enum drm_connector_status |
1970 | static enum drm_connector_status |
1967 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1971 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1968 | { |
1972 | { |
1969 | struct drm_device *dev = encoder->dev; |
1973 | struct drm_device *dev = encoder->dev; |
1970 | struct radeon_device *rdev = dev->dev_private; |
1974 | struct radeon_device *rdev = dev->dev_private; |
1971 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1975 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1972 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1976 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1973 | uint32_t bios_0_scratch; |
1977 | uint32_t bios_0_scratch; |
1974 | 1978 | ||
1975 | if (!atombios_dac_load_detect(encoder, connector)) { |
1979 | if (!atombios_dac_load_detect(encoder, connector)) { |
1976 | DRM_DEBUG_KMS("detect returned false \n"); |
1980 | DRM_DEBUG_KMS("detect returned false \n"); |
1977 | return connector_status_unknown; |
1981 | return connector_status_unknown; |
1978 | } |
1982 | } |
1979 | 1983 | ||
1980 | if (rdev->family >= CHIP_R600) |
1984 | if (rdev->family >= CHIP_R600) |
1981 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1985 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1982 | else |
1986 | else |
1983 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1987 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1984 | 1988 | ||
1985 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1989 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1986 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1990 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1987 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1991 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1988 | return connector_status_connected; |
1992 | return connector_status_connected; |
1989 | } |
1993 | } |
1990 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
1994 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
1991 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1995 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1992 | return connector_status_connected; |
1996 | return connector_status_connected; |
1993 | } |
1997 | } |
1994 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1998 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1995 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1999 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1996 | return connector_status_connected; |
2000 | return connector_status_connected; |
1997 | } |
2001 | } |
1998 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
2002 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1999 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
2003 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
2000 | return connector_status_connected; /* CTV */ |
2004 | return connector_status_connected; /* CTV */ |
2001 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
2005 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
2002 | return connector_status_connected; /* STV */ |
2006 | return connector_status_connected; /* STV */ |
2003 | } |
2007 | } |
2004 | return connector_status_disconnected; |
2008 | return connector_status_disconnected; |
2005 | } |
2009 | } |
- | 2010 | ||
- | 2011 | static enum drm_connector_status |
|
- | 2012 | radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
|
- | 2013 | { |
|
- | 2014 | struct drm_device *dev = encoder->dev; |
|
- | 2015 | struct radeon_device *rdev = dev->dev_private; |
|
- | 2016 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 2017 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 2018 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
|
- | 2019 | u32 bios_0_scratch; |
|
- | 2020 | ||
- | 2021 | if (!ASIC_IS_DCE4(rdev)) |
|
- | 2022 | return connector_status_unknown; |
|
- | 2023 | ||
- | 2024 | if (!ext_encoder) |
|
- | 2025 | return connector_status_unknown; |
|
- | 2026 | ||
- | 2027 | if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) |
|
- | 2028 | return connector_status_unknown; |
|
- | 2029 | ||
- | 2030 | /* load detect on the dp bridge */ |
|
- | 2031 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
- | 2032 | EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); |
|
- | 2033 | ||
- | 2034 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
|
- | 2035 | ||
- | 2036 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
|
- | 2037 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
|
- | 2038 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
|
- | 2039 | return connector_status_connected; |
|
- | 2040 | } |
|
- | 2041 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
|
- | 2042 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
|
- | 2043 | return connector_status_connected; |
|
- | 2044 | } |
|
- | 2045 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
|
- | 2046 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
|
- | 2047 | return connector_status_connected; |
|
- | 2048 | } |
|
- | 2049 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
|
- | 2050 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
|
- | 2051 | return connector_status_connected; /* CTV */ |
|
- | 2052 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
|
- | 2053 | return connector_status_connected; /* STV */ |
|
- | 2054 | } |
|
- | 2055 | return connector_status_disconnected; |
|
- | 2056 | } |
|
- | 2057 | ||
- | 2058 | void |
|
- | 2059 | radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) |
|
- | 2060 | { |
|
- | 2061 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
|
- | 2062 | ||
- | 2063 | if (ext_encoder) |
|
- | 2064 | /* ddc_setup on the dp bridge */ |
|
- | 2065 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
- | 2066 | EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); |
|
- | 2067 | ||
- | 2068 | } |
|
2006 | 2069 | ||
2007 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
2070 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
2008 | { |
2071 | { |
2009 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2072 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2010 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
2073 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
2011 | 2074 | ||
2012 | if ((radeon_encoder->active_device & |
2075 | if ((radeon_encoder->active_device & |
2013 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
2076 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
2014 | radeon_encoder_is_dp_bridge(encoder)) { |
2077 | radeon_encoder_is_dp_bridge(encoder)) { |
2015 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
2078 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
2016 | if (dig) |
2079 | if (dig) |
2017 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
2080 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
2018 | } |
2081 | } |
2019 | 2082 | ||
2020 | radeon_atom_output_lock(encoder, true); |
2083 | radeon_atom_output_lock(encoder, true); |
2021 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2084 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2022 | 2085 | ||
2023 | if (connector) { |
2086 | if (connector) { |
2024 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2087 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2025 | 2088 | ||
2026 | /* select the clock/data port if it uses a router */ |
2089 | /* select the clock/data port if it uses a router */ |
2027 | if (radeon_connector->router.cd_valid) |
2090 | if (radeon_connector->router.cd_valid) |
2028 | radeon_router_select_cd_port(radeon_connector); |
2091 | radeon_router_select_cd_port(radeon_connector); |
2029 | 2092 | ||
2030 | /* turn eDP panel on for mode set */ |
2093 | /* turn eDP panel on for mode set */ |
2031 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
2094 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
2032 | atombios_set_edp_panel_power(connector, |
2095 | atombios_set_edp_panel_power(connector, |
2033 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
2096 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
2034 | } |
2097 | } |
2035 | 2098 | ||
2036 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
2099 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
2037 | atombios_set_encoder_crtc_source(encoder); |
2100 | atombios_set_encoder_crtc_source(encoder); |
2038 | } |
2101 | } |
2039 | 2102 | ||
2040 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
2103 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
2041 | { |
2104 | { |
2042 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
2105 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
2043 | radeon_atom_output_lock(encoder, false); |
2106 | radeon_atom_output_lock(encoder, false); |
2044 | } |
2107 | } |
2045 | 2108 | ||
2046 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
2109 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
2047 | { |
2110 | { |
2048 | struct drm_device *dev = encoder->dev; |
2111 | struct drm_device *dev = encoder->dev; |
2049 | struct radeon_device *rdev = dev->dev_private; |
2112 | struct radeon_device *rdev = dev->dev_private; |
2050 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2113 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2051 | struct radeon_encoder_atom_dig *dig; |
2114 | struct radeon_encoder_atom_dig *dig; |
2052 | 2115 | ||
2053 | /* check for pre-DCE3 cards with shared encoders; |
2116 | /* check for pre-DCE3 cards with shared encoders; |
2054 | * can't really use the links individually, so don't disable |
2117 | * can't really use the links individually, so don't disable |
2055 | * the encoder if it's in use by another connector |
2118 | * the encoder if it's in use by another connector |
2056 | */ |
2119 | */ |
2057 | if (!ASIC_IS_DCE3(rdev)) { |
2120 | if (!ASIC_IS_DCE3(rdev)) { |
2058 | struct drm_encoder *other_encoder; |
2121 | struct drm_encoder *other_encoder; |
2059 | struct radeon_encoder *other_radeon_encoder; |
2122 | struct radeon_encoder *other_radeon_encoder; |
2060 | 2123 | ||
2061 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
2124 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
2062 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
2125 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
2063 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && |
2126 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && |
2064 | drm_helper_encoder_in_use(other_encoder)) |
2127 | drm_helper_encoder_in_use(other_encoder)) |
2065 | goto disable_done; |
2128 | goto disable_done; |
2066 | } |
2129 | } |
2067 | } |
2130 | } |
2068 | 2131 | ||
2069 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2132 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2070 | 2133 | ||
2071 | switch (radeon_encoder->encoder_id) { |
2134 | switch (radeon_encoder->encoder_id) { |
2072 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2135 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2073 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2136 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2074 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2137 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2075 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2138 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2076 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
2139 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
2077 | break; |
2140 | break; |
2078 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2141 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2079 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2142 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2080 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2143 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2081 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2144 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2082 | if (ASIC_IS_DCE4(rdev)) |
2145 | if (ASIC_IS_DCE4(rdev)) |
2083 | /* disable the transmitter */ |
2146 | /* disable the transmitter */ |
2084 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
2147 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
2085 | else { |
2148 | else { |
2086 | /* disable the encoder and transmitter */ |
2149 | /* disable the encoder and transmitter */ |
2087 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
2150 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
2088 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
2151 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
2089 | } |
2152 | } |
2090 | break; |
2153 | break; |
2091 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2154 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2092 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2155 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2093 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2156 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2094 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
2157 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
2095 | break; |
2158 | break; |
2096 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2159 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2097 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2160 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2098 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2161 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2099 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2162 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2100 | atombios_dac_setup(encoder, ATOM_DISABLE); |
2163 | atombios_dac_setup(encoder, ATOM_DISABLE); |
2101 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2164 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2102 | atombios_tv_setup(encoder, ATOM_DISABLE); |
2165 | atombios_tv_setup(encoder, ATOM_DISABLE); |
2103 | break; |
2166 | break; |
2104 | } |
2167 | } |
2105 | 2168 | ||
2106 | disable_done: |
2169 | disable_done: |
2107 | if (radeon_encoder_is_digital(encoder)) { |
2170 | if (radeon_encoder_is_digital(encoder)) { |
2108 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
2171 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
2109 | r600_hdmi_disable(encoder); |
2172 | r600_hdmi_disable(encoder); |
2110 | dig = radeon_encoder->enc_priv; |
2173 | dig = radeon_encoder->enc_priv; |
2111 | dig->dig_encoder = -1; |
2174 | dig->dig_encoder = -1; |
2112 | } |
2175 | } |
2113 | radeon_encoder->active_device = 0; |
2176 | radeon_encoder->active_device = 0; |
2114 | } |
2177 | } |
2115 | 2178 | ||
2116 | /* these are handled by the primary encoders */ |
2179 | /* these are handled by the primary encoders */ |
2117 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) |
2180 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) |
2118 | { |
2181 | { |
2119 | 2182 | ||
2120 | } |
2183 | } |
2121 | 2184 | ||
2122 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) |
2185 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) |
2123 | { |
2186 | { |
2124 | 2187 | ||
2125 | } |
2188 | } |
2126 | 2189 | ||
2127 | static void |
2190 | static void |
2128 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, |
2191 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, |
2129 | struct drm_display_mode *mode, |
2192 | struct drm_display_mode *mode, |
2130 | struct drm_display_mode *adjusted_mode) |
2193 | struct drm_display_mode *adjusted_mode) |
2131 | { |
2194 | { |
2132 | 2195 | ||
2133 | } |
2196 | } |
2134 | 2197 | ||
2135 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) |
2198 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) |
2136 | { |
2199 | { |
2137 | 2200 | ||
2138 | } |
2201 | } |
2139 | 2202 | ||
2140 | static void |
2203 | static void |
2141 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) |
2204 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) |
2142 | { |
2205 | { |
2143 | 2206 | ||
2144 | } |
2207 | } |
2145 | 2208 | ||
2146 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, |
2209 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, |
2147 | struct drm_display_mode *mode, |
2210 | struct drm_display_mode *mode, |
2148 | struct drm_display_mode *adjusted_mode) |
2211 | struct drm_display_mode *adjusted_mode) |
2149 | { |
2212 | { |
2150 | return true; |
2213 | return true; |
2151 | } |
2214 | } |
2152 | 2215 | ||
2153 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { |
2216 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { |
2154 | .dpms = radeon_atom_ext_dpms, |
2217 | .dpms = radeon_atom_ext_dpms, |
2155 | .mode_fixup = radeon_atom_ext_mode_fixup, |
2218 | .mode_fixup = radeon_atom_ext_mode_fixup, |
2156 | .prepare = radeon_atom_ext_prepare, |
2219 | .prepare = radeon_atom_ext_prepare, |
2157 | .mode_set = radeon_atom_ext_mode_set, |
2220 | .mode_set = radeon_atom_ext_mode_set, |
2158 | .commit = radeon_atom_ext_commit, |
2221 | .commit = radeon_atom_ext_commit, |
2159 | .disable = radeon_atom_ext_disable, |
2222 | .disable = radeon_atom_ext_disable, |
2160 | /* no detect for TMDS/LVDS yet */ |
2223 | /* no detect for TMDS/LVDS yet */ |
2161 | }; |
2224 | }; |
2162 | 2225 | ||
2163 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
2226 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
2164 | .dpms = radeon_atom_encoder_dpms, |
2227 | .dpms = radeon_atom_encoder_dpms, |
2165 | .mode_fixup = radeon_atom_mode_fixup, |
2228 | .mode_fixup = radeon_atom_mode_fixup, |
2166 | .prepare = radeon_atom_encoder_prepare, |
2229 | .prepare = radeon_atom_encoder_prepare, |
2167 | .mode_set = radeon_atom_encoder_mode_set, |
2230 | .mode_set = radeon_atom_encoder_mode_set, |
2168 | .commit = radeon_atom_encoder_commit, |
2231 | .commit = radeon_atom_encoder_commit, |
2169 | .disable = radeon_atom_encoder_disable, |
2232 | .disable = radeon_atom_encoder_disable, |
2170 | /* no detect for TMDS/LVDS yet */ |
2233 | .detect = radeon_atom_dig_detect, |
2171 | }; |
2234 | }; |
2172 | 2235 | ||
2173 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
2236 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
2174 | .dpms = radeon_atom_encoder_dpms, |
2237 | .dpms = radeon_atom_encoder_dpms, |
2175 | .mode_fixup = radeon_atom_mode_fixup, |
2238 | .mode_fixup = radeon_atom_mode_fixup, |
2176 | .prepare = radeon_atom_encoder_prepare, |
2239 | .prepare = radeon_atom_encoder_prepare, |
2177 | .mode_set = radeon_atom_encoder_mode_set, |
2240 | .mode_set = radeon_atom_encoder_mode_set, |
2178 | .commit = radeon_atom_encoder_commit, |
2241 | .commit = radeon_atom_encoder_commit, |
2179 | .detect = radeon_atom_dac_detect, |
2242 | .detect = radeon_atom_dac_detect, |
2180 | }; |
2243 | }; |
2181 | 2244 | ||
2182 | void radeon_enc_destroy(struct drm_encoder *encoder) |
2245 | void radeon_enc_destroy(struct drm_encoder *encoder) |
2183 | { |
2246 | { |
2184 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2247 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2185 | kfree(radeon_encoder->enc_priv); |
2248 | kfree(radeon_encoder->enc_priv); |
2186 | drm_encoder_cleanup(encoder); |
2249 | drm_encoder_cleanup(encoder); |
2187 | kfree(radeon_encoder); |
2250 | kfree(radeon_encoder); |
2188 | } |
2251 | } |
2189 | 2252 | ||
2190 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
2253 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
2191 | .destroy = radeon_enc_destroy, |
2254 | .destroy = radeon_enc_destroy, |
2192 | }; |
2255 | }; |
2193 | 2256 | ||
2194 | struct radeon_encoder_atom_dac * |
2257 | struct radeon_encoder_atom_dac * |
2195 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
2258 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
2196 | { |
2259 | { |
2197 | struct drm_device *dev = radeon_encoder->base.dev; |
2260 | struct drm_device *dev = radeon_encoder->base.dev; |
2198 | struct radeon_device *rdev = dev->dev_private; |
2261 | struct radeon_device *rdev = dev->dev_private; |
2199 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
2262 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
2200 | 2263 | ||
2201 | if (!dac) |
2264 | if (!dac) |
2202 | return NULL; |
2265 | return NULL; |
2203 | 2266 | ||
2204 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
2267 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
2205 | return dac; |
2268 | return dac; |
2206 | } |
2269 | } |
2207 | 2270 | ||
2208 | struct radeon_encoder_atom_dig * |
2271 | struct radeon_encoder_atom_dig * |
2209 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
2272 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
2210 | { |
2273 | { |
2211 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
2274 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
2212 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
2275 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
2213 | 2276 | ||
2214 | if (!dig) |
2277 | if (!dig) |
2215 | return NULL; |
2278 | return NULL; |
2216 | 2279 | ||
2217 | /* coherent mode by default */ |
2280 | /* coherent mode by default */ |
2218 | dig->coherent_mode = true; |
2281 | dig->coherent_mode = true; |
2219 | dig->dig_encoder = -1; |
2282 | dig->dig_encoder = -1; |
2220 | 2283 | ||
2221 | if (encoder_enum == 2) |
2284 | if (encoder_enum == 2) |
2222 | dig->linkb = true; |
2285 | dig->linkb = true; |
2223 | else |
2286 | else |
2224 | dig->linkb = false; |
2287 | dig->linkb = false; |
2225 | 2288 | ||
2226 | return dig; |
2289 | return dig; |
2227 | } |
2290 | } |
2228 | 2291 | ||
2229 | void |
2292 | void |
2230 | radeon_add_atom_encoder(struct drm_device *dev, |
2293 | radeon_add_atom_encoder(struct drm_device *dev, |
2231 | uint32_t encoder_enum, |
2294 | uint32_t encoder_enum, |
2232 | uint32_t supported_device, |
2295 | uint32_t supported_device, |
2233 | u16 caps) |
2296 | u16 caps) |
2234 | { |
2297 | { |
2235 | struct radeon_device *rdev = dev->dev_private; |
2298 | struct radeon_device *rdev = dev->dev_private; |
2236 | struct drm_encoder *encoder; |
2299 | struct drm_encoder *encoder; |
2237 | struct radeon_encoder *radeon_encoder; |
2300 | struct radeon_encoder *radeon_encoder; |
2238 | 2301 | ||
2239 | /* see if we already added it */ |
2302 | /* see if we already added it */ |
2240 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2303 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2241 | radeon_encoder = to_radeon_encoder(encoder); |
2304 | radeon_encoder = to_radeon_encoder(encoder); |
2242 | if (radeon_encoder->encoder_enum == encoder_enum) { |
2305 | if (radeon_encoder->encoder_enum == encoder_enum) { |
2243 | radeon_encoder->devices |= supported_device; |
2306 | radeon_encoder->devices |= supported_device; |
2244 | return; |
2307 | return; |
2245 | } |
2308 | } |
2246 | 2309 | ||
2247 | } |
2310 | } |
2248 | 2311 | ||
2249 | /* add a new one */ |
2312 | /* add a new one */ |
2250 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
2313 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
2251 | if (!radeon_encoder) |
2314 | if (!radeon_encoder) |
2252 | return; |
2315 | return; |
2253 | 2316 | ||
2254 | encoder = &radeon_encoder->base; |
2317 | encoder = &radeon_encoder->base; |
2255 | switch (rdev->num_crtc) { |
2318 | switch (rdev->num_crtc) { |
2256 | case 1: |
2319 | case 1: |
2257 | encoder->possible_crtcs = 0x1; |
2320 | encoder->possible_crtcs = 0x1; |
2258 | break; |
2321 | break; |
2259 | case 2: |
2322 | case 2: |
2260 | default: |
2323 | default: |
2261 | encoder->possible_crtcs = 0x3; |
2324 | encoder->possible_crtcs = 0x3; |
2262 | break; |
2325 | break; |
2263 | case 6: |
2326 | case 6: |
2264 | encoder->possible_crtcs = 0x3f; |
2327 | encoder->possible_crtcs = 0x3f; |
2265 | break; |
2328 | break; |
2266 | } |
2329 | } |
2267 | 2330 | ||
2268 | radeon_encoder->enc_priv = NULL; |
2331 | radeon_encoder->enc_priv = NULL; |
2269 | 2332 | ||
2270 | radeon_encoder->encoder_enum = encoder_enum; |
2333 | radeon_encoder->encoder_enum = encoder_enum; |
2271 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
2334 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
2272 | radeon_encoder->devices = supported_device; |
2335 | radeon_encoder->devices = supported_device; |
2273 | radeon_encoder->rmx_type = RMX_OFF; |
2336 | radeon_encoder->rmx_type = RMX_OFF; |
2274 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
2337 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
2275 | radeon_encoder->is_ext_encoder = false; |
2338 | radeon_encoder->is_ext_encoder = false; |
2276 | radeon_encoder->caps = caps; |
2339 | radeon_encoder->caps = caps; |
2277 | 2340 | ||
2278 | switch (radeon_encoder->encoder_id) { |
2341 | switch (radeon_encoder->encoder_id) { |
2279 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2342 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2280 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2343 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2281 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2344 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2282 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2345 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2283 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2346 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2284 | radeon_encoder->rmx_type = RMX_FULL; |
2347 | radeon_encoder->rmx_type = RMX_FULL; |
2285 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2348 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2286 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2349 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2287 | } else { |
2350 | } else { |
2288 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2351 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2289 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2352 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2290 | } |
2353 | } |
2291 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2354 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2292 | break; |
2355 | break; |
2293 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2356 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2294 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2357 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2295 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2358 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2296 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2359 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2297 | break; |
2360 | break; |
2298 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2361 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2299 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2362 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2300 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2363 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2301 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
2364 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
2302 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2365 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2303 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2366 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2304 | break; |
2367 | break; |
2305 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2368 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2306 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2369 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2307 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2370 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2308 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2371 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2309 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2372 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2310 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2373 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2311 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2374 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2312 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2375 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2313 | radeon_encoder->rmx_type = RMX_FULL; |
2376 | radeon_encoder->rmx_type = RMX_FULL; |
2314 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2377 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2315 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2378 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2316 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
2379 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
2317 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2380 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2318 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2381 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2319 | } else { |
2382 | } else { |
2320 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2383 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2321 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2384 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2322 | } |
2385 | } |
2323 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2386 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2324 | break; |
2387 | break; |
2325 | case ENCODER_OBJECT_ID_SI170B: |
2388 | case ENCODER_OBJECT_ID_SI170B: |
2326 | case ENCODER_OBJECT_ID_CH7303: |
2389 | case ENCODER_OBJECT_ID_CH7303: |
2327 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: |
2390 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: |
2328 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: |
2391 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: |
2329 | case ENCODER_OBJECT_ID_TITFP513: |
2392 | case ENCODER_OBJECT_ID_TITFP513: |
2330 | case ENCODER_OBJECT_ID_VT1623: |
2393 | case ENCODER_OBJECT_ID_VT1623: |
2331 | case ENCODER_OBJECT_ID_HDMI_SI1930: |
2394 | case ENCODER_OBJECT_ID_HDMI_SI1930: |
2332 | case ENCODER_OBJECT_ID_TRAVIS: |
2395 | case ENCODER_OBJECT_ID_TRAVIS: |
2333 | case ENCODER_OBJECT_ID_NUTMEG: |
2396 | case ENCODER_OBJECT_ID_NUTMEG: |
2334 | /* these are handled by the primary encoders */ |
2397 | /* these are handled by the primary encoders */ |
2335 | radeon_encoder->is_ext_encoder = true; |
2398 | radeon_encoder->is_ext_encoder = true; |
2336 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2399 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2337 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2400 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2338 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
2401 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
2339 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2402 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2340 | else |
2403 | else |
2341 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2404 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2342 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); |
2405 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); |
2343 | break; |
2406 | break; |
2344 | } |
2407 | } |
2345 | }><>><>><>><>>=>>><> |
2408 | }><>><>><>><>>=>>><> |