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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include "drmP.h" |
26 | #include "drmP.h" |
27 | #include "drm_crtc_helper.h" |
27 | #include "drm_crtc_helper.h" |
28 | #include "radeon_drm.h" |
28 | #include "radeon_drm.h" |
29 | #include "radeon.h" |
29 | #include "radeon.h" |
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | 31 | ||
32 | extern int atom_debug; |
32 | extern int atom_debug; |
33 | 33 | ||
34 | /* evil but including atombios.h is much worse */ |
34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
36 | struct drm_display_mode *mode); |
36 | struct drm_display_mode *mode); |
37 | 37 | ||
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
39 | { |
39 | { |
40 | struct drm_device *dev = encoder->dev; |
40 | struct drm_device *dev = encoder->dev; |
41 | struct radeon_device *rdev = dev->dev_private; |
41 | struct radeon_device *rdev = dev->dev_private; |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
43 | struct drm_encoder *clone_encoder; |
43 | struct drm_encoder *clone_encoder; |
44 | uint32_t index_mask = 0; |
44 | uint32_t index_mask = 0; |
45 | int count; |
45 | int count; |
46 | 46 | ||
47 | /* DIG routing gets problematic */ |
47 | /* DIG routing gets problematic */ |
48 | if (rdev->family >= CHIP_R600) |
48 | if (rdev->family >= CHIP_R600) |
49 | return index_mask; |
49 | return index_mask; |
50 | /* LVDS/TV are too wacky */ |
50 | /* LVDS/TV are too wacky */ |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
52 | return index_mask; |
52 | return index_mask; |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) |
55 | return index_mask; |
55 | return index_mask; |
56 | 56 | ||
57 | count = -1; |
57 | count = -1; |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); |
60 | count++; |
60 | count++; |
61 | 61 | ||
62 | if (clone_encoder == encoder) |
62 | if (clone_encoder == encoder) |
63 | continue; |
63 | continue; |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
65 | continue; |
65 | continue; |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) |
67 | continue; |
67 | continue; |
68 | else |
68 | else |
69 | index_mask |= (1 << count); |
69 | index_mask |= (1 << count); |
70 | } |
70 | } |
71 | return index_mask; |
71 | return index_mask; |
72 | } |
72 | } |
73 | 73 | ||
74 | void radeon_setup_encoder_clones(struct drm_device *dev) |
74 | void radeon_setup_encoder_clones(struct drm_device *dev) |
75 | { |
75 | { |
76 | struct drm_encoder *encoder; |
76 | struct drm_encoder *encoder; |
77 | 77 | ||
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); |
80 | } |
80 | } |
81 | } |
81 | } |
82 | 82 | ||
83 | uint32_t |
83 | uint32_t |
84 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
84 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
85 | { |
85 | { |
86 | struct radeon_device *rdev = dev->dev_private; |
86 | struct radeon_device *rdev = dev->dev_private; |
87 | uint32_t ret = 0; |
87 | uint32_t ret = 0; |
88 | 88 | ||
89 | switch (supported_device) { |
89 | switch (supported_device) { |
90 | case ATOM_DEVICE_CRT1_SUPPORT: |
90 | case ATOM_DEVICE_CRT1_SUPPORT: |
91 | case ATOM_DEVICE_TV1_SUPPORT: |
91 | case ATOM_DEVICE_TV1_SUPPORT: |
92 | case ATOM_DEVICE_TV2_SUPPORT: |
92 | case ATOM_DEVICE_TV2_SUPPORT: |
93 | case ATOM_DEVICE_CRT2_SUPPORT: |
93 | case ATOM_DEVICE_CRT2_SUPPORT: |
94 | case ATOM_DEVICE_CV_SUPPORT: |
94 | case ATOM_DEVICE_CV_SUPPORT: |
95 | switch (dac) { |
95 | switch (dac) { |
96 | case 1: /* dac a */ |
96 | case 1: /* dac a */ |
97 | if ((rdev->family == CHIP_RS300) || |
97 | if ((rdev->family == CHIP_RS300) || |
98 | (rdev->family == CHIP_RS400) || |
98 | (rdev->family == CHIP_RS400) || |
99 | (rdev->family == CHIP_RS480)) |
99 | (rdev->family == CHIP_RS480)) |
100 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
100 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
101 | else if (ASIC_IS_AVIVO(rdev)) |
101 | else if (ASIC_IS_AVIVO(rdev)) |
102 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; |
102 | ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; |
103 | else |
103 | else |
104 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; |
104 | ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; |
105 | break; |
105 | break; |
106 | case 2: /* dac b */ |
106 | case 2: /* dac b */ |
107 | if (ASIC_IS_AVIVO(rdev)) |
107 | if (ASIC_IS_AVIVO(rdev)) |
108 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; |
108 | ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; |
109 | else { |
109 | else { |
110 | /*if (rdev->family == CHIP_R200) |
110 | /*if (rdev->family == CHIP_R200) |
111 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
111 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
112 | else*/ |
112 | else*/ |
113 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
113 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
114 | } |
114 | } |
115 | break; |
115 | break; |
116 | case 3: /* external dac */ |
116 | case 3: /* external dac */ |
117 | if (ASIC_IS_AVIVO(rdev)) |
117 | if (ASIC_IS_AVIVO(rdev)) |
118 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
118 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
119 | else |
119 | else |
120 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
120 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
121 | break; |
121 | break; |
122 | } |
122 | } |
123 | break; |
123 | break; |
124 | case ATOM_DEVICE_LCD1_SUPPORT: |
124 | case ATOM_DEVICE_LCD1_SUPPORT: |
125 | if (ASIC_IS_AVIVO(rdev)) |
125 | if (ASIC_IS_AVIVO(rdev)) |
126 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
126 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
127 | else |
127 | else |
128 | ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; |
128 | ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; |
129 | break; |
129 | break; |
130 | case ATOM_DEVICE_DFP1_SUPPORT: |
130 | case ATOM_DEVICE_DFP1_SUPPORT: |
131 | if ((rdev->family == CHIP_RS300) || |
131 | if ((rdev->family == CHIP_RS300) || |
132 | (rdev->family == CHIP_RS400) || |
132 | (rdev->family == CHIP_RS400) || |
133 | (rdev->family == CHIP_RS480)) |
133 | (rdev->family == CHIP_RS480)) |
134 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
134 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
135 | else if (ASIC_IS_AVIVO(rdev)) |
135 | else if (ASIC_IS_AVIVO(rdev)) |
136 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; |
136 | ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; |
137 | else |
137 | else |
138 | ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; |
138 | ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; |
139 | break; |
139 | break; |
140 | case ATOM_DEVICE_LCD2_SUPPORT: |
140 | case ATOM_DEVICE_LCD2_SUPPORT: |
141 | case ATOM_DEVICE_DFP2_SUPPORT: |
141 | case ATOM_DEVICE_DFP2_SUPPORT: |
142 | if ((rdev->family == CHIP_RS600) || |
142 | if ((rdev->family == CHIP_RS600) || |
143 | (rdev->family == CHIP_RS690) || |
143 | (rdev->family == CHIP_RS690) || |
144 | (rdev->family == CHIP_RS740)) |
144 | (rdev->family == CHIP_RS740)) |
145 | ret = ENCODER_OBJECT_ID_INTERNAL_DDI; |
145 | ret = ENCODER_INTERNAL_DDI_ENUM_ID1; |
146 | else if (ASIC_IS_AVIVO(rdev)) |
146 | else if (ASIC_IS_AVIVO(rdev)) |
147 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
147 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
148 | else |
148 | else |
149 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
149 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
150 | break; |
150 | break; |
151 | case ATOM_DEVICE_DFP3_SUPPORT: |
151 | case ATOM_DEVICE_DFP3_SUPPORT: |
152 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
152 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
153 | break; |
153 | break; |
154 | } |
154 | } |
155 | 155 | ||
156 | return ret; |
156 | return ret; |
157 | } |
157 | } |
158 | 158 | ||
159 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
159 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
160 | { |
160 | { |
161 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
161 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
162 | switch (radeon_encoder->encoder_id) { |
162 | switch (radeon_encoder->encoder_id) { |
163 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
163 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
164 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
164 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
167 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
167 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
169 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
169 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
173 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
173 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
174 | return true; |
174 | return true; |
175 | default: |
175 | default: |
176 | return false; |
176 | return false; |
177 | } |
177 | } |
178 | } |
178 | } |
- | 179 | ||
179 | void |
180 | void |
180 | radeon_link_encoder_connector(struct drm_device *dev) |
181 | radeon_link_encoder_connector(struct drm_device *dev) |
181 | { |
182 | { |
182 | struct drm_connector *connector; |
183 | struct drm_connector *connector; |
183 | struct radeon_connector *radeon_connector; |
184 | struct radeon_connector *radeon_connector; |
184 | struct drm_encoder *encoder; |
185 | struct drm_encoder *encoder; |
185 | struct radeon_encoder *radeon_encoder; |
186 | struct radeon_encoder *radeon_encoder; |
186 | 187 | ||
187 | /* walk the list and link encoders to connectors */ |
188 | /* walk the list and link encoders to connectors */ |
188 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
189 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
189 | radeon_connector = to_radeon_connector(connector); |
190 | radeon_connector = to_radeon_connector(connector); |
190 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
191 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
191 | radeon_encoder = to_radeon_encoder(encoder); |
192 | radeon_encoder = to_radeon_encoder(encoder); |
192 | if (radeon_encoder->devices & radeon_connector->devices) |
193 | if (radeon_encoder->devices & radeon_connector->devices) |
193 | drm_mode_connector_attach_encoder(connector, encoder); |
194 | drm_mode_connector_attach_encoder(connector, encoder); |
194 | } |
195 | } |
195 | } |
196 | } |
196 | } |
197 | } |
197 | 198 | ||
198 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
199 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
199 | { |
200 | { |
200 | struct drm_device *dev = encoder->dev; |
201 | struct drm_device *dev = encoder->dev; |
201 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
202 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
202 | struct drm_connector *connector; |
203 | struct drm_connector *connector; |
203 | 204 | ||
204 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
205 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
205 | if (connector->encoder == encoder) { |
206 | if (connector->encoder == encoder) { |
206 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
207 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
207 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
208 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
208 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", |
209 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
209 | radeon_encoder->active_device, radeon_encoder->devices, |
210 | radeon_encoder->active_device, radeon_encoder->devices, |
210 | radeon_connector->devices, encoder->encoder_type); |
211 | radeon_connector->devices, encoder->encoder_type); |
211 | } |
212 | } |
212 | } |
213 | } |
213 | } |
214 | } |
214 | 215 | ||
215 | static struct drm_connector * |
216 | struct drm_connector * |
216 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
217 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
217 | { |
218 | { |
218 | struct drm_device *dev = encoder->dev; |
219 | struct drm_device *dev = encoder->dev; |
219 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
220 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
220 | struct drm_connector *connector; |
221 | struct drm_connector *connector; |
221 | struct radeon_connector *radeon_connector; |
222 | struct radeon_connector *radeon_connector; |
222 | 223 | ||
223 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
224 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
224 | radeon_connector = to_radeon_connector(connector); |
225 | radeon_connector = to_radeon_connector(connector); |
225 | if (radeon_encoder->active_device & radeon_connector->devices) |
226 | if (radeon_encoder->active_device & radeon_connector->devices) |
226 | return connector; |
227 | return connector; |
227 | } |
228 | } |
228 | return NULL; |
229 | return NULL; |
229 | } |
230 | } |
230 | 231 | ||
231 | static struct radeon_connector_atom_dig * |
232 | static struct drm_connector * |
232 | radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder) |
233 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder) |
233 | { |
234 | { |
234 | struct drm_device *dev = encoder->dev; |
235 | struct drm_device *dev = encoder->dev; |
235 | struct radeon_device *rdev = dev->dev_private; |
236 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
236 | struct drm_connector *connector; |
237 | struct drm_connector *connector; |
237 | struct radeon_connector *radeon_connector; |
- | |
- | 238 | struct radeon_connector *radeon_connector; |
|
- | 239 | ||
- | 240 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
238 | struct radeon_connector_atom_dig *dig_connector; |
241 | radeon_connector = to_radeon_connector(connector); |
- | 242 | if (radeon_encoder->devices & radeon_connector->devices) |
|
239 | 243 | return connector; |
|
- | 244 | } |
|
- | 245 | return NULL; |
|
- | 246 | } |
|
- | 247 | ||
240 | if (!rdev->is_atom_bios) |
248 | struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder) |
241 | return NULL; |
249 | { |
242 | 250 | struct drm_device *dev = encoder->dev; |
|
243 | connector = radeon_get_connector_for_encoder(encoder); |
251 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | 252 | struct drm_encoder *other_encoder; |
|
- | 253 | struct radeon_encoder *other_radeon_encoder; |
|
244 | if (!connector) |
254 | |
- | 255 | if (radeon_encoder->is_ext_encoder) |
|
- | 256 | return NULL; |
|
- | 257 | ||
- | 258 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
|
- | 259 | if (other_encoder == encoder) |
|
- | 260 | continue; |
|
245 | return NULL; |
261 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
- | 262 | if (other_radeon_encoder->is_ext_encoder && |
|
- | 263 | (radeon_encoder->devices & other_radeon_encoder->devices)) |
|
- | 264 | return other_encoder; |
|
- | 265 | } |
|
- | 266 | return NULL; |
|
- | 267 | } |
|
- | 268 | ||
- | 269 | bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder) |
|
246 | 270 | { |
|
- | 271 | struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder); |
|
- | 272 | ||
- | 273 | if (other_encoder) { |
|
- | 274 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder); |
|
- | 275 | ||
- | 276 | switch (radeon_encoder->encoder_id) { |
|
- | 277 | case ENCODER_OBJECT_ID_TRAVIS: |
|
- | 278 | case ENCODER_OBJECT_ID_NUTMEG: |
|
- | 279 | return true; |
|
- | 280 | default: |
|
- | 281 | return false; |
|
- | 282 | } |
|
- | 283 | } |
|
- | 284 | ||
- | 285 | return false; |
|
- | 286 | } |
|
- | 287 | ||
- | 288 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
|
- | 289 | struct drm_display_mode *adjusted_mode) |
|
- | 290 | { |
|
- | 291 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 292 | struct drm_device *dev = encoder->dev; |
|
- | 293 | struct radeon_device *rdev = dev->dev_private; |
|
- | 294 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
|
- | 295 | unsigned hblank = native_mode->htotal - native_mode->hdisplay; |
|
- | 296 | unsigned vblank = native_mode->vtotal - native_mode->vdisplay; |
|
- | 297 | unsigned hover = native_mode->hsync_start - native_mode->hdisplay; |
|
- | 298 | unsigned vover = native_mode->vsync_start - native_mode->vdisplay; |
|
- | 299 | unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; |
|
- | 300 | unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; |
|
- | 301 | ||
- | 302 | adjusted_mode->clock = native_mode->clock; |
|
- | 303 | adjusted_mode->flags = native_mode->flags; |
|
- | 304 | ||
- | 305 | if (ASIC_IS_AVIVO(rdev)) { |
|
- | 306 | adjusted_mode->hdisplay = native_mode->hdisplay; |
|
- | 307 | adjusted_mode->vdisplay = native_mode->vdisplay; |
|
- | 308 | } |
|
- | 309 | ||
- | 310 | adjusted_mode->htotal = native_mode->hdisplay + hblank; |
|
- | 311 | adjusted_mode->hsync_start = native_mode->hdisplay + hover; |
|
- | 312 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; |
|
- | 313 | ||
- | 314 | adjusted_mode->vtotal = native_mode->vdisplay + vblank; |
|
- | 315 | adjusted_mode->vsync_start = native_mode->vdisplay + vover; |
|
- | 316 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; |
|
- | 317 | ||
- | 318 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
|
- | 319 | ||
- | 320 | if (ASIC_IS_AVIVO(rdev)) { |
|
- | 321 | adjusted_mode->crtc_hdisplay = native_mode->hdisplay; |
|
- | 322 | adjusted_mode->crtc_vdisplay = native_mode->vdisplay; |
|
- | 323 | } |
|
- | 324 | ||
- | 325 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; |
|
247 | radeon_connector = to_radeon_connector(connector); |
- | |
248 | 326 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; |
|
249 | if (!radeon_connector->con_priv) |
327 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; |
250 | return NULL; |
328 | |
251 | 329 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; |
|
252 | dig_connector = radeon_connector->con_priv; |
330 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; |
253 | 331 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; |
|
254 | return dig_connector; |
332 | |
255 | } |
333 | } |
256 | 334 | ||
257 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
335 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
258 | struct drm_display_mode *mode, |
336 | struct drm_display_mode *mode, |
259 | struct drm_display_mode *adjusted_mode) |
337 | struct drm_display_mode *adjusted_mode) |
260 | { |
338 | { |
261 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
339 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
262 | struct drm_device *dev = encoder->dev; |
340 | struct drm_device *dev = encoder->dev; |
263 | struct radeon_device *rdev = dev->dev_private; |
341 | struct radeon_device *rdev = dev->dev_private; |
264 | - | ||
265 | /* adjust pm to upcoming mode change */ |
- | |
266 | radeon_pm_compute_clocks(rdev); |
- | |
267 | 342 | ||
268 | /* set the active encoder to connector routing */ |
343 | /* set the active encoder to connector routing */ |
269 | radeon_encoder_set_active_device(encoder); |
344 | radeon_encoder_set_active_device(encoder); |
270 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
345 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
271 | 346 | ||
272 | /* hw bug */ |
347 | /* hw bug */ |
273 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
348 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
274 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
349 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
275 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
350 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
276 | 351 | ||
277 | /* get the native mode for LVDS */ |
352 | /* get the native mode for LVDS */ |
278 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { |
353 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
279 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
- | |
280 | int mode_id = adjusted_mode->base.id; |
354 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
281 | *adjusted_mode = *native_mode; |
- | |
282 | if (!ASIC_IS_AVIVO(rdev)) { |
- | |
283 | adjusted_mode->hdisplay = mode->hdisplay; |
- | |
284 | adjusted_mode->vdisplay = mode->vdisplay; |
- | |
285 | adjusted_mode->crtc_hdisplay = mode->hdisplay; |
- | |
286 | adjusted_mode->crtc_vdisplay = mode->vdisplay; |
- | |
287 | } |
- | |
288 | adjusted_mode->base.id = mode_id; |
- | |
289 | } |
- | |
290 | 355 | ||
291 | /* get the native mode for TV */ |
356 | /* get the native mode for TV */ |
292 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
357 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
293 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
358 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
294 | if (tv_dac) { |
359 | if (tv_dac) { |
295 | if (tv_dac->tv_std == TV_STD_NTSC || |
360 | if (tv_dac->tv_std == TV_STD_NTSC || |
296 | tv_dac->tv_std == TV_STD_NTSC_J || |
361 | tv_dac->tv_std == TV_STD_NTSC_J || |
297 | tv_dac->tv_std == TV_STD_PAL_M) |
362 | tv_dac->tv_std == TV_STD_PAL_M) |
298 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
363 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
299 | else |
364 | else |
300 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
365 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
301 | } |
366 | } |
302 | } |
367 | } |
303 | 368 | ||
304 | if (ASIC_IS_DCE3(rdev) && |
369 | if (ASIC_IS_DCE3(rdev) && |
305 | (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { |
370 | (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { |
306 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
371 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
307 | radeon_dp_set_link_config(connector, mode); |
372 | radeon_dp_set_link_config(connector, mode); |
308 | } |
373 | } |
309 | 374 | ||
310 | return true; |
375 | return true; |
311 | } |
376 | } |
312 | 377 | ||
313 | static void |
378 | static void |
314 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
379 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
315 | { |
380 | { |
316 | struct drm_device *dev = encoder->dev; |
381 | struct drm_device *dev = encoder->dev; |
317 | struct radeon_device *rdev = dev->dev_private; |
382 | struct radeon_device *rdev = dev->dev_private; |
318 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
383 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
319 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
384 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
320 | int index = 0, num = 0; |
385 | int index = 0; |
321 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
386 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
322 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
- | |
323 | - | ||
324 | if (dac_info->tv_std) |
- | |
325 | tv_std = dac_info->tv_std; |
- | |
326 | 387 | ||
327 | memset(&args, 0, sizeof(args)); |
388 | memset(&args, 0, sizeof(args)); |
328 | 389 | ||
329 | switch (radeon_encoder->encoder_id) { |
390 | switch (radeon_encoder->encoder_id) { |
330 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
391 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
331 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
392 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
332 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
393 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
333 | num = 1; |
- | |
334 | break; |
394 | break; |
335 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
395 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
336 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
396 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
337 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
397 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
338 | num = 2; |
- | |
339 | break; |
398 | break; |
340 | } |
399 | } |
341 | 400 | ||
342 | args.ucAction = action; |
401 | args.ucAction = action; |
343 | 402 | ||
344 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
403 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
345 | args.ucDacStandard = ATOM_DAC1_PS2; |
404 | args.ucDacStandard = ATOM_DAC1_PS2; |
346 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
405 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
347 | args.ucDacStandard = ATOM_DAC1_CV; |
406 | args.ucDacStandard = ATOM_DAC1_CV; |
348 | else { |
407 | else { |
349 | switch (tv_std) { |
408 | switch (dac_info->tv_std) { |
350 | case TV_STD_PAL: |
409 | case TV_STD_PAL: |
351 | case TV_STD_PAL_M: |
410 | case TV_STD_PAL_M: |
352 | case TV_STD_SCART_PAL: |
411 | case TV_STD_SCART_PAL: |
353 | case TV_STD_SECAM: |
412 | case TV_STD_SECAM: |
354 | case TV_STD_PAL_CN: |
413 | case TV_STD_PAL_CN: |
355 | args.ucDacStandard = ATOM_DAC1_PAL; |
414 | args.ucDacStandard = ATOM_DAC1_PAL; |
356 | break; |
415 | break; |
357 | case TV_STD_NTSC: |
416 | case TV_STD_NTSC: |
358 | case TV_STD_NTSC_J: |
417 | case TV_STD_NTSC_J: |
359 | case TV_STD_PAL_60: |
418 | case TV_STD_PAL_60: |
360 | default: |
419 | default: |
361 | args.ucDacStandard = ATOM_DAC1_NTSC; |
420 | args.ucDacStandard = ATOM_DAC1_NTSC; |
362 | break; |
421 | break; |
363 | } |
422 | } |
364 | } |
423 | } |
365 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
424 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
366 | 425 | ||
367 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
426 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
368 | 427 | ||
369 | } |
428 | } |
370 | 429 | ||
371 | static void |
430 | static void |
372 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
431 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
373 | { |
432 | { |
374 | struct drm_device *dev = encoder->dev; |
433 | struct drm_device *dev = encoder->dev; |
375 | struct radeon_device *rdev = dev->dev_private; |
434 | struct radeon_device *rdev = dev->dev_private; |
376 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
435 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
377 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
436 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
378 | int index = 0; |
437 | int index = 0; |
379 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
438 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
380 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
- | |
381 | - | ||
382 | if (dac_info->tv_std) |
- | |
383 | tv_std = dac_info->tv_std; |
- | |
384 | 439 | ||
385 | memset(&args, 0, sizeof(args)); |
440 | memset(&args, 0, sizeof(args)); |
386 | 441 | ||
387 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
442 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
388 | 443 | ||
389 | args.sTVEncoder.ucAction = action; |
444 | args.sTVEncoder.ucAction = action; |
390 | 445 | ||
391 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
446 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
392 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
447 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
393 | else { |
448 | else { |
394 | switch (tv_std) { |
449 | switch (dac_info->tv_std) { |
395 | case TV_STD_NTSC: |
450 | case TV_STD_NTSC: |
396 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
451 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
397 | break; |
452 | break; |
398 | case TV_STD_PAL: |
453 | case TV_STD_PAL: |
399 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
454 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
400 | break; |
455 | break; |
401 | case TV_STD_PAL_M: |
456 | case TV_STD_PAL_M: |
402 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
457 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
403 | break; |
458 | break; |
404 | case TV_STD_PAL_60: |
459 | case TV_STD_PAL_60: |
405 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
460 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
406 | break; |
461 | break; |
407 | case TV_STD_NTSC_J: |
462 | case TV_STD_NTSC_J: |
408 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
463 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
409 | break; |
464 | break; |
410 | case TV_STD_SCART_PAL: |
465 | case TV_STD_SCART_PAL: |
411 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
466 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
412 | break; |
467 | break; |
413 | case TV_STD_SECAM: |
468 | case TV_STD_SECAM: |
414 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
469 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
415 | break; |
470 | break; |
416 | case TV_STD_PAL_CN: |
471 | case TV_STD_PAL_CN: |
417 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
472 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
418 | break; |
473 | break; |
419 | default: |
474 | default: |
420 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
475 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
421 | break; |
476 | break; |
422 | } |
477 | } |
423 | } |
478 | } |
424 | 479 | ||
425 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
480 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
426 | 481 | ||
427 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
482 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
428 | 483 | ||
429 | } |
484 | } |
- | 485 | ||
- | 486 | union dvo_encoder_control { |
|
- | 487 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
|
- | 488 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
|
- | 489 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
|
- | 490 | }; |
|
430 | 491 | ||
431 | void |
492 | void |
432 | atombios_external_tmds_setup(struct drm_encoder *encoder, int action) |
493 | atombios_dvo_setup(struct drm_encoder *encoder, int action) |
433 | { |
494 | { |
434 | struct drm_device *dev = encoder->dev; |
495 | struct drm_device *dev = encoder->dev; |
435 | struct radeon_device *rdev = dev->dev_private; |
496 | struct radeon_device *rdev = dev->dev_private; |
436 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
497 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
437 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; |
498 | union dvo_encoder_control args; |
438 | int index = 0; |
499 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
439 | 500 | ||
440 | memset(&args, 0, sizeof(args)); |
501 | memset(&args, 0, sizeof(args)); |
- | 502 | ||
- | 503 | if (ASIC_IS_DCE3(rdev)) { |
|
- | 504 | /* DCE3+ */ |
|
- | 505 | args.dvo_v3.ucAction = action; |
|
- | 506 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
|
- | 507 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
|
- | 508 | } else if (ASIC_IS_DCE2(rdev)) { |
|
- | 509 | /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */ |
|
- | 510 | args.dvo.sDVOEncoder.ucAction = action; |
|
- | 511 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
|
441 | 512 | /* DFP1, CRT1, TV1 depending on the type of port */ |
|
- | 513 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; |
|
- | 514 | ||
- | 515 | if (radeon_encoder->pixel_clock > 165000) |
|
- | 516 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
|
442 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
517 | } else { |
443 | 518 | /* R4xx, R5xx */ |
|
444 | args.sXTmdsEncoder.ucEnable = action; |
519 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; |
445 | 520 | ||
446 | if (radeon_encoder->pixel_clock > 165000) |
521 | if (radeon_encoder->pixel_clock > 165000) |
447 | args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; |
- | |
448 | - | ||
449 | /*if (pScrn->rgbBits == 8)*/ |
- | |
450 | args.sXTmdsEncoder.ucMisc |= (1 << 1); |
522 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
451 | - | ||
452 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
- | |
453 | - | ||
454 | } |
- | |
455 | - | ||
456 | static void |
- | |
457 | atombios_ddia_setup(struct drm_encoder *encoder, int action) |
- | |
458 | { |
- | |
459 | struct drm_device *dev = encoder->dev; |
- | |
460 | struct radeon_device *rdev = dev->dev_private; |
- | |
461 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | |
462 | DVO_ENCODER_CONTROL_PS_ALLOCATION args; |
- | |
463 | int index = 0; |
- | |
464 | - | ||
465 | memset(&args, 0, sizeof(args)); |
- | |
466 | - | ||
467 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
- | |
468 | - | ||
469 | args.sDVOEncoder.ucAction = action; |
- | |
470 | args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
523 | |
471 | - | ||
472 | if (radeon_encoder->pixel_clock > 165000) |
524 | /*if (pScrn->rgbBits == 8)*/ |
473 | args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; |
525 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; |
474 | 526 | } |
|
475 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
527 | |
476 | 528 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
477 | } |
529 | } |
478 | 530 | ||
479 | union lvds_encoder_control { |
531 | union lvds_encoder_control { |
480 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
532 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
481 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
533 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
482 | }; |
534 | }; |
483 | 535 | ||
484 | void |
536 | void |
485 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
537 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
486 | { |
538 | { |
487 | struct drm_device *dev = encoder->dev; |
539 | struct drm_device *dev = encoder->dev; |
488 | struct radeon_device *rdev = dev->dev_private; |
540 | struct radeon_device *rdev = dev->dev_private; |
489 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
541 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
490 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
542 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
491 | struct radeon_connector_atom_dig *dig_connector = |
- | |
492 | radeon_get_atom_connector_priv_from_encoder(encoder); |
- | |
493 | union lvds_encoder_control args; |
543 | union lvds_encoder_control args; |
494 | int index = 0; |
544 | int index = 0; |
495 | int hdmi_detected = 0; |
545 | int hdmi_detected = 0; |
496 | uint8_t frev, crev; |
546 | uint8_t frev, crev; |
497 | 547 | ||
498 | if (!dig || !dig_connector) |
548 | if (!dig) |
499 | return; |
549 | return; |
500 | 550 | ||
501 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
551 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
502 | hdmi_detected = 1; |
552 | hdmi_detected = 1; |
503 | 553 | ||
504 | memset(&args, 0, sizeof(args)); |
554 | memset(&args, 0, sizeof(args)); |
505 | 555 | ||
506 | switch (radeon_encoder->encoder_id) { |
556 | switch (radeon_encoder->encoder_id) { |
507 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
557 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
508 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
558 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
509 | break; |
559 | break; |
510 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
560 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
511 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
561 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
512 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
562 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
513 | break; |
563 | break; |
514 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
564 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
515 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
565 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
516 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
566 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
517 | else |
567 | else |
518 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
568 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
519 | break; |
569 | break; |
520 | } |
570 | } |
521 | 571 | ||
- | 572 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
|
522 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
573 | return; |
523 | 574 | ||
524 | switch (frev) { |
575 | switch (frev) { |
525 | case 1: |
576 | case 1: |
526 | case 2: |
577 | case 2: |
527 | switch (crev) { |
578 | switch (crev) { |
528 | case 1: |
579 | case 1: |
529 | args.v1.ucMisc = 0; |
580 | args.v1.ucMisc = 0; |
530 | args.v1.ucAction = action; |
581 | args.v1.ucAction = action; |
531 | if (hdmi_detected) |
582 | if (hdmi_detected) |
532 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
583 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
533 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
584 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
534 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
585 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
535 | if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) |
586 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
536 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
587 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
537 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
588 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
538 | args.v1.ucMisc |= (1 << 1); |
589 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
539 | } else { |
590 | } else { |
540 | if (dig_connector->linkb) |
591 | if (dig->linkb) |
541 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
592 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
542 | if (radeon_encoder->pixel_clock > 165000) |
593 | if (radeon_encoder->pixel_clock > 165000) |
543 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
594 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
544 | /*if (pScrn->rgbBits == 8) */ |
595 | /*if (pScrn->rgbBits == 8) */ |
545 | args.v1.ucMisc |= (1 << 1); |
596 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
546 | } |
597 | } |
547 | break; |
598 | break; |
548 | case 2: |
599 | case 2: |
549 | case 3: |
600 | case 3: |
550 | args.v2.ucMisc = 0; |
601 | args.v2.ucMisc = 0; |
551 | args.v2.ucAction = action; |
602 | args.v2.ucAction = action; |
552 | if (crev == 3) { |
603 | if (crev == 3) { |
553 | if (dig->coherent_mode) |
604 | if (dig->coherent_mode) |
554 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
605 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
555 | } |
606 | } |
556 | if (hdmi_detected) |
607 | if (hdmi_detected) |
557 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
608 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
558 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
609 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
559 | args.v2.ucTruncate = 0; |
610 | args.v2.ucTruncate = 0; |
560 | args.v2.ucSpatial = 0; |
611 | args.v2.ucSpatial = 0; |
561 | args.v2.ucTemporal = 0; |
612 | args.v2.ucTemporal = 0; |
562 | args.v2.ucFRC = 0; |
613 | args.v2.ucFRC = 0; |
563 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
614 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
564 | if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) |
615 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
565 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
616 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
566 | if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) { |
617 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { |
567 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
618 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
568 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
619 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
569 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
620 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
570 | } |
621 | } |
571 | if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) { |
622 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { |
572 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
623 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
573 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
624 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
574 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
625 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
575 | if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
626 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
576 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
627 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
577 | } |
628 | } |
578 | } else { |
629 | } else { |
579 | if (dig_connector->linkb) |
630 | if (dig->linkb) |
580 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
631 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
581 | if (radeon_encoder->pixel_clock > 165000) |
632 | if (radeon_encoder->pixel_clock > 165000) |
582 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
633 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
583 | } |
634 | } |
584 | break; |
635 | break; |
585 | default: |
636 | default: |
586 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
637 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
587 | break; |
638 | break; |
588 | } |
639 | } |
589 | break; |
640 | break; |
590 | default: |
641 | default: |
591 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
642 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
592 | break; |
643 | break; |
593 | } |
644 | } |
594 | 645 | ||
595 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
646 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
596 | r600_hdmi_enable(encoder, hdmi_detected); |
- | |
597 | } |
647 | } |
598 | 648 | ||
599 | int |
649 | int |
600 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
650 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
601 | { |
651 | { |
- | 652 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 653 | struct drm_device *dev = encoder->dev; |
|
- | 654 | struct radeon_device *rdev = dev->dev_private; |
|
602 | struct drm_connector *connector; |
655 | struct drm_connector *connector; |
603 | struct radeon_connector *radeon_connector; |
656 | struct radeon_connector *radeon_connector; |
604 | struct radeon_connector_atom_dig *dig_connector; |
657 | struct radeon_connector_atom_dig *dig_connector; |
605 | 658 | ||
606 | connector = radeon_get_connector_for_encoder(encoder); |
659 | /* dp bridges are always DP */ |
607 | if (!connector) |
660 | if (radeon_encoder_is_dp_bridge(encoder)) |
- | 661 | return ATOM_ENCODER_MODE_DP; |
|
- | 662 | ||
- | 663 | connector = radeon_get_connector_for_encoder(encoder); |
|
- | 664 | if (!connector) { |
|
- | 665 | switch (radeon_encoder->encoder_id) { |
|
- | 666 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
|
- | 667 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
|
- | 668 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
|
- | 669 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
|
- | 670 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
|
- | 671 | return ATOM_ENCODER_MODE_DVI; |
|
- | 672 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
|
- | 673 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
|
- | 674 | default: |
|
- | 675 | return ATOM_ENCODER_MODE_CRT; |
|
608 | return 0; |
676 | } |
609 | 677 | } |
|
610 | radeon_connector = to_radeon_connector(connector); |
678 | radeon_connector = to_radeon_connector(connector); |
611 | 679 | ||
612 | switch (connector->connector_type) { |
680 | switch (connector->connector_type) { |
613 | case DRM_MODE_CONNECTOR_DVII: |
681 | case DRM_MODE_CONNECTOR_DVII: |
614 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
682 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
615 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
683 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
- | 684 | /* fix me */ |
|
- | 685 | if (ASIC_IS_DCE4(rdev)) |
|
- | 686 | return ATOM_ENCODER_MODE_DVI; |
|
- | 687 | else |
|
616 | return ATOM_ENCODER_MODE_HDMI; |
688 | return ATOM_ENCODER_MODE_HDMI; |
617 | else if (radeon_connector->use_digital) |
689 | } else if (radeon_connector->use_digital) |
618 | return ATOM_ENCODER_MODE_DVI; |
690 | return ATOM_ENCODER_MODE_DVI; |
619 | else |
691 | else |
620 | return ATOM_ENCODER_MODE_CRT; |
692 | return ATOM_ENCODER_MODE_CRT; |
621 | break; |
693 | break; |
622 | case DRM_MODE_CONNECTOR_DVID: |
694 | case DRM_MODE_CONNECTOR_DVID: |
623 | case DRM_MODE_CONNECTOR_HDMIA: |
695 | case DRM_MODE_CONNECTOR_HDMIA: |
624 | default: |
696 | default: |
625 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
697 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
- | 698 | /* fix me */ |
|
- | 699 | if (ASIC_IS_DCE4(rdev)) |
|
626 | return ATOM_ENCODER_MODE_HDMI; |
700 | return ATOM_ENCODER_MODE_DVI; |
627 | else |
701 | else |
- | 702 | return ATOM_ENCODER_MODE_HDMI; |
|
- | 703 | } else |
|
628 | return ATOM_ENCODER_MODE_DVI; |
704 | return ATOM_ENCODER_MODE_DVI; |
629 | break; |
705 | break; |
630 | case DRM_MODE_CONNECTOR_LVDS: |
706 | case DRM_MODE_CONNECTOR_LVDS: |
631 | return ATOM_ENCODER_MODE_LVDS; |
707 | return ATOM_ENCODER_MODE_LVDS; |
632 | break; |
708 | break; |
633 | case DRM_MODE_CONNECTOR_DisplayPort: |
709 | case DRM_MODE_CONNECTOR_DisplayPort: |
634 | case DRM_MODE_CONNECTOR_eDP: |
- | |
635 | dig_connector = radeon_connector->con_priv; |
710 | dig_connector = radeon_connector->con_priv; |
636 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
711 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
637 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
712 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
638 | return ATOM_ENCODER_MODE_DP; |
713 | return ATOM_ENCODER_MODE_DP; |
639 | else if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
714 | else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
- | 715 | /* fix me */ |
|
- | 716 | if (ASIC_IS_DCE4(rdev)) |
|
640 | return ATOM_ENCODER_MODE_HDMI; |
717 | return ATOM_ENCODER_MODE_DVI; |
641 | else |
718 | else |
- | 719 | return ATOM_ENCODER_MODE_HDMI; |
|
- | 720 | } else |
|
642 | return ATOM_ENCODER_MODE_DVI; |
721 | return ATOM_ENCODER_MODE_DVI; |
643 | break; |
722 | break; |
- | 723 | case DRM_MODE_CONNECTOR_eDP: |
|
- | 724 | return ATOM_ENCODER_MODE_DP; |
|
644 | case DRM_MODE_CONNECTOR_DVIA: |
725 | case DRM_MODE_CONNECTOR_DVIA: |
645 | case DRM_MODE_CONNECTOR_VGA: |
726 | case DRM_MODE_CONNECTOR_VGA: |
646 | return ATOM_ENCODER_MODE_CRT; |
727 | return ATOM_ENCODER_MODE_CRT; |
647 | break; |
728 | break; |
648 | case DRM_MODE_CONNECTOR_Composite: |
729 | case DRM_MODE_CONNECTOR_Composite: |
649 | case DRM_MODE_CONNECTOR_SVIDEO: |
730 | case DRM_MODE_CONNECTOR_SVIDEO: |
650 | case DRM_MODE_CONNECTOR_9PinDIN: |
731 | case DRM_MODE_CONNECTOR_9PinDIN: |
651 | /* fix me */ |
732 | /* fix me */ |
652 | return ATOM_ENCODER_MODE_TV; |
733 | return ATOM_ENCODER_MODE_TV; |
653 | /*return ATOM_ENCODER_MODE_CV;*/ |
734 | /*return ATOM_ENCODER_MODE_CV;*/ |
654 | break; |
735 | break; |
655 | } |
736 | } |
656 | } |
737 | } |
657 | 738 | ||
658 | /* |
739 | /* |
659 | * DIG Encoder/Transmitter Setup |
740 | * DIG Encoder/Transmitter Setup |
660 | * |
741 | * |
661 | * DCE 3.0/3.1 |
742 | * DCE 3.0/3.1 |
662 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. |
743 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. |
663 | * Supports up to 3 digital outputs |
744 | * Supports up to 3 digital outputs |
664 | * - 2 DIG encoder blocks. |
745 | * - 2 DIG encoder blocks. |
665 | * DIG1 can drive UNIPHY link A or link B |
746 | * DIG1 can drive UNIPHY link A or link B |
666 | * DIG2 can drive UNIPHY link B or LVTMA |
747 | * DIG2 can drive UNIPHY link B or LVTMA |
667 | * |
748 | * |
668 | * DCE 3.2 |
749 | * DCE 3.2 |
669 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). |
750 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). |
670 | * Supports up to 5 digital outputs |
751 | * Supports up to 5 digital outputs |
671 | * - 2 DIG encoder blocks. |
752 | * - 2 DIG encoder blocks. |
672 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
753 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
673 | * |
754 | * |
674 | * DCE 4.0 |
755 | * DCE 4.0/5.0 |
675 | * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). |
756 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
676 | * Supports up to 6 digital outputs |
757 | * Supports up to 6 digital outputs |
677 | * - 6 DIG encoder blocks. |
758 | * - 6 DIG encoder blocks. |
678 | * - DIG to PHY mapping is hardcoded |
759 | * - DIG to PHY mapping is hardcoded |
679 | * DIG1 drives UNIPHY0 link A, A+B |
760 | * DIG1 drives UNIPHY0 link A, A+B |
680 | * DIG2 drives UNIPHY0 link B |
761 | * DIG2 drives UNIPHY0 link B |
681 | * DIG3 drives UNIPHY1 link A, A+B |
762 | * DIG3 drives UNIPHY1 link A, A+B |
682 | * DIG4 drives UNIPHY1 link B |
763 | * DIG4 drives UNIPHY1 link B |
683 | * DIG5 drives UNIPHY2 link A, A+B |
764 | * DIG5 drives UNIPHY2 link A, A+B |
684 | * DIG6 drives UNIPHY2 link B |
765 | * DIG6 drives UNIPHY2 link B |
685 | * |
766 | * |
- | 767 | * DCE 4.1 |
|
- | 768 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
|
- | 769 | * Supports up to 6 digital outputs |
|
- | 770 | * - 2 DIG encoder blocks. |
|
- | 771 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
|
- | 772 | * |
|
686 | * Routing |
773 | * Routing |
687 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) |
774 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) |
688 | * Examples: |
775 | * Examples: |
689 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI |
776 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI |
690 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP |
777 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP |
691 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS |
778 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS |
692 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI |
779 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI |
693 | */ |
780 | */ |
694 | 781 | ||
695 | union dig_encoder_control { |
782 | union dig_encoder_control { |
696 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
783 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
697 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
784 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
698 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
785 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
- | 786 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; |
|
699 | }; |
787 | }; |
700 | 788 | ||
701 | void |
789 | void |
702 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) |
790 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) |
703 | { |
791 | { |
704 | struct drm_device *dev = encoder->dev; |
792 | struct drm_device *dev = encoder->dev; |
705 | struct radeon_device *rdev = dev->dev_private; |
793 | struct radeon_device *rdev = dev->dev_private; |
706 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
794 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
707 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
795 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
708 | struct radeon_connector_atom_dig *dig_connector = |
- | |
709 | radeon_get_atom_connector_priv_from_encoder(encoder); |
796 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
710 | union dig_encoder_control args; |
797 | union dig_encoder_control args; |
711 | int index = 0, num = 0; |
798 | int index = 0; |
712 | uint8_t frev, crev; |
799 | uint8_t frev, crev; |
- | 800 | int dp_clock = 0; |
|
- | 801 | int dp_lane_count = 0; |
|
- | 802 | int hpd_id = RADEON_HPD_NONE; |
|
- | 803 | int bpc = 8; |
|
- | 804 | ||
- | 805 | if (connector) { |
|
- | 806 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 807 | struct radeon_connector_atom_dig *dig_connector = |
|
- | 808 | radeon_connector->con_priv; |
|
- | 809 | ||
- | 810 | dp_clock = dig_connector->dp_clock; |
|
- | 811 | dp_lane_count = dig_connector->dp_lane_count; |
|
- | 812 | hpd_id = radeon_connector->hpd.hpd; |
|
- | 813 | bpc = connector->display_info.bpc; |
|
- | 814 | } |
|
- | 815 | ||
713 | 816 | /* no dig encoder assigned */ |
|
714 | if (!dig || !dig_connector) |
817 | if (dig->dig_encoder == -1) |
715 | return; |
818 | return; |
716 | 819 | ||
717 | memset(&args, 0, sizeof(args)); |
820 | memset(&args, 0, sizeof(args)); |
718 | 821 | ||
719 | if (ASIC_IS_DCE4(rdev)) |
822 | if (ASIC_IS_DCE4(rdev)) |
720 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); |
823 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); |
721 | else { |
824 | else { |
722 | if (dig->dig_encoder) |
825 | if (dig->dig_encoder) |
723 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
826 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
724 | else |
827 | else |
725 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
828 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
726 | } |
829 | } |
727 | num = dig->dig_encoder + 1; |
- | |
728 | 830 | ||
- | 831 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
|
729 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
832 | return; |
730 | 833 | ||
731 | args.v1.ucAction = action; |
834 | args.v1.ucAction = action; |
732 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
835 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
- | 836 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
|
- | 837 | args.v3.ucPanelMode = panel_mode; |
|
- | 838 | else |
|
733 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
839 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
734 | 840 | ||
735 | if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
- | |
736 | if (dig_connector->dp_clock == 270000) |
841 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
737 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
842 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) |
738 | args.v1.ucLaneNum = dig_connector->dp_lane_count; |
843 | args.v1.ucLaneNum = dp_lane_count; |
739 | } else if (radeon_encoder->pixel_clock > 165000) |
844 | else if (radeon_encoder->pixel_clock > 165000) |
740 | args.v1.ucLaneNum = 8; |
845 | args.v1.ucLaneNum = 8; |
741 | else |
846 | else |
742 | args.v1.ucLaneNum = 4; |
847 | args.v1.ucLaneNum = 4; |
743 | 848 | ||
- | 849 | if (ASIC_IS_DCE5(rdev)) { |
|
- | 850 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
|
- | 851 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) { |
|
- | 852 | if (dp_clock == 270000) |
|
- | 853 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
|
- | 854 | else if (dp_clock == 540000) |
|
- | 855 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
|
- | 856 | } |
|
- | 857 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
|
- | 858 | switch (bpc) { |
|
- | 859 | case 0: |
|
- | 860 | args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; |
|
- | 861 | break; |
|
- | 862 | case 6: |
|
- | 863 | args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
|
- | 864 | break; |
|
- | 865 | case 8: |
|
- | 866 | default: |
|
- | 867 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
|
- | 868 | break; |
|
- | 869 | case 10: |
|
- | 870 | args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
|
- | 871 | break; |
|
- | 872 | case 12: |
|
- | 873 | args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
|
- | 874 | break; |
|
- | 875 | case 16: |
|
- | 876 | args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
|
- | 877 | break; |
|
- | 878 | } |
|
- | 879 | if (hpd_id == RADEON_HPD_NONE) |
|
- | 880 | args.v4.ucHPD_ID = 0; |
|
- | 881 | else |
|
- | 882 | args.v4.ucHPD_ID = hpd_id + 1; |
|
- | 883 | } else if (ASIC_IS_DCE4(rdev)) { |
|
- | 884 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
|
744 | if (ASIC_IS_DCE4(rdev)) { |
885 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
- | 886 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
|
- | 887 | switch (bpc) { |
|
- | 888 | case 0: |
|
- | 889 | args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; |
|
- | 890 | break; |
|
- | 891 | case 6: |
|
- | 892 | args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
|
- | 893 | break; |
|
- | 894 | case 8: |
|
745 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
895 | default: |
- | 896 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
|
- | 897 | break; |
|
- | 898 | case 10: |
|
- | 899 | args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
|
- | 900 | break; |
|
- | 901 | case 12: |
|
- | 902 | args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
|
- | 903 | break; |
|
- | 904 | case 16: |
|
- | 905 | args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
|
- | 906 | break; |
|
746 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
907 | } |
- | 908 | } else { |
|
- | 909 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
|
747 | } else { |
910 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
748 | switch (radeon_encoder->encoder_id) { |
911 | switch (radeon_encoder->encoder_id) { |
749 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
912 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
750 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
913 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
751 | break; |
914 | break; |
752 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
915 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
753 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
916 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
754 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
917 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
755 | break; |
918 | break; |
756 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
919 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
757 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
920 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
758 | break; |
921 | break; |
759 | } |
922 | } |
760 | if (dig_connector->linkb) |
923 | if (dig->linkb) |
761 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
924 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
762 | else |
925 | else |
763 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
926 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
764 | } |
927 | } |
765 | 928 | ||
766 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
929 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
767 | 930 | ||
768 | } |
931 | } |
769 | 932 | ||
770 | union dig_transmitter_control { |
933 | union dig_transmitter_control { |
771 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
934 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
772 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
935 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
773 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
936 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
- | 937 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; |
|
774 | }; |
938 | }; |
775 | 939 | ||
776 | void |
940 | void |
777 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
941 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
778 | { |
942 | { |
779 | struct drm_device *dev = encoder->dev; |
943 | struct drm_device *dev = encoder->dev; |
780 | struct radeon_device *rdev = dev->dev_private; |
944 | struct radeon_device *rdev = dev->dev_private; |
781 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
945 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
782 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
946 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
783 | struct radeon_connector_atom_dig *dig_connector = |
- | |
784 | radeon_get_atom_connector_priv_from_encoder(encoder); |
- | |
785 | struct drm_connector *connector; |
947 | struct drm_connector *connector; |
786 | struct radeon_connector *radeon_connector; |
- | |
787 | union dig_transmitter_control args; |
948 | union dig_transmitter_control args; |
788 | int index = 0, num = 0; |
949 | int index = 0; |
789 | uint8_t frev, crev; |
950 | uint8_t frev, crev; |
790 | bool is_dp = false; |
951 | bool is_dp = false; |
791 | int pll_id = 0; |
952 | int pll_id = 0; |
- | 953 | int dp_clock = 0; |
|
- | 954 | int dp_lane_count = 0; |
|
- | 955 | int connector_object_id = 0; |
|
- | 956 | int igp_lane_info = 0; |
|
- | 957 | int dig_encoder = dig->dig_encoder; |
|
- | 958 | ||
- | 959 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
|
- | 960 | connector = radeon_get_connector_for_encoder_init(encoder); |
|
792 | 961 | /* just needed to avoid bailing in the encoder check. the encoder |
|
793 | if (!dig || !dig_connector) |
962 | * isn't used for init |
- | 963 | */ |
|
794 | return; |
964 | dig_encoder = 0; |
795 | 965 | } else |
|
- | 966 | connector = radeon_get_connector_for_encoder(encoder); |
|
- | 967 | ||
796 | connector = radeon_get_connector_for_encoder(encoder); |
968 | if (connector) { |
- | 969 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 970 | struct radeon_connector_atom_dig *dig_connector = |
|
- | 971 | radeon_connector->con_priv; |
|
- | 972 | ||
- | 973 | dp_clock = dig_connector->dp_clock; |
|
- | 974 | dp_lane_count = dig_connector->dp_lane_count; |
|
- | 975 | connector_object_id = |
|
- | 976 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
|
- | 977 | igp_lane_info = dig_connector->igp_lane_info; |
|
- | 978 | } |
|
- | 979 | ||
- | 980 | /* no dig encoder assigned */ |
|
- | 981 | if (dig_encoder == -1) |
|
797 | radeon_connector = to_radeon_connector(connector); |
982 | return; |
798 | 983 | ||
799 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
984 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
800 | is_dp = true; |
985 | is_dp = true; |
801 | 986 | ||
802 | memset(&args, 0, sizeof(args)); |
987 | memset(&args, 0, sizeof(args)); |
803 | - | ||
804 | if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) |
- | |
805 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
- | |
806 | else { |
988 | |
- | 989 | switch (radeon_encoder->encoder_id) { |
|
- | 990 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
|
- | 991 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
|
807 | switch (radeon_encoder->encoder_id) { |
992 | break; |
- | 993 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
|
- | 994 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
|
808 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
995 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
809 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); |
996 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
810 | break; |
997 | break; |
811 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
998 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
812 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); |
999 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
813 | break; |
1000 | break; |
814 | } |
- | |
815 | } |
1001 | } |
- | 1002 | ||
816 | 1003 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
|
817 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
1004 | return; |
818 | 1005 | ||
819 | args.v1.ucAction = action; |
1006 | args.v1.ucAction = action; |
820 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1007 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
821 | args.v1.usInitInfo = radeon_connector->connector_object_id; |
1008 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
822 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1009 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
823 | args.v1.asMode.ucLaneSel = lane_num; |
1010 | args.v1.asMode.ucLaneSel = lane_num; |
824 | args.v1.asMode.ucLaneSet = lane_set; |
1011 | args.v1.asMode.ucLaneSet = lane_set; |
825 | } else { |
1012 | } else { |
826 | if (is_dp) |
1013 | if (is_dp) |
827 | args.v1.usPixelClock = |
1014 | args.v1.usPixelClock = |
828 | cpu_to_le16(dig_connector->dp_clock / 10); |
1015 | cpu_to_le16(dp_clock / 10); |
829 | else if (radeon_encoder->pixel_clock > 165000) |
1016 | else if (radeon_encoder->pixel_clock > 165000) |
830 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1017 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
831 | else |
1018 | else |
832 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1019 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
833 | } |
1020 | } |
834 | if (ASIC_IS_DCE4(rdev)) { |
1021 | if (ASIC_IS_DCE4(rdev)) { |
835 | if (is_dp) |
1022 | if (is_dp) |
836 | args.v3.ucLaneNum = dig_connector->dp_lane_count; |
1023 | args.v3.ucLaneNum = dp_lane_count; |
837 | else if (radeon_encoder->pixel_clock > 165000) |
1024 | else if (radeon_encoder->pixel_clock > 165000) |
838 | args.v3.ucLaneNum = 8; |
1025 | args.v3.ucLaneNum = 8; |
839 | else |
1026 | else |
840 | args.v3.ucLaneNum = 4; |
1027 | args.v3.ucLaneNum = 4; |
841 | 1028 | ||
842 | if (dig_connector->linkb) { |
1029 | if (dig->linkb) |
- | 1030 | args.v3.acConfig.ucLinkSel = 1; |
|
843 | args.v3.acConfig.ucLinkSel = 1; |
1031 | if (dig_encoder & 1) |
844 | args.v3.acConfig.ucEncoderSel = 1; |
- | |
845 | } |
1032 | args.v3.acConfig.ucEncoderSel = 1; |
846 | 1033 | ||
847 | /* Select the PLL for the PHY |
1034 | /* Select the PLL for the PHY |
848 | * DP PHY should be clocked from external src if there is |
1035 | * DP PHY should be clocked from external src if there is |
849 | * one. |
1036 | * one. |
850 | */ |
1037 | */ |
851 | if (encoder->crtc) { |
1038 | if (encoder->crtc) { |
852 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1039 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
853 | pll_id = radeon_crtc->pll_id; |
1040 | pll_id = radeon_crtc->pll_id; |
854 | } |
1041 | } |
- | 1042 | ||
- | 1043 | if (ASIC_IS_DCE5(rdev)) { |
|
- | 1044 | /* On DCE5 DCPLL usually generates the DP ref clock */ |
|
- | 1045 | if (is_dp) { |
|
- | 1046 | if (rdev->clock.dp_extclk) |
|
- | 1047 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; |
|
- | 1048 | else |
|
- | 1049 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; |
|
- | 1050 | } else |
|
- | 1051 | args.v4.acConfig.ucRefClkSource = pll_id; |
|
- | 1052 | } else { |
|
- | 1053 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
|
855 | if (is_dp && rdev->clock.dp_extclk) |
1054 | if (is_dp && rdev->clock.dp_extclk) |
856 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ |
1055 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ |
857 | else |
1056 | else |
858 | args.v3.acConfig.ucRefClkSource = pll_id; |
1057 | args.v3.acConfig.ucRefClkSource = pll_id; |
- | 1058 | } |
|
859 | 1059 | ||
860 | switch (radeon_encoder->encoder_id) { |
1060 | switch (radeon_encoder->encoder_id) { |
861 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1061 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
862 | args.v3.acConfig.ucTransmitterSel = 0; |
1062 | args.v3.acConfig.ucTransmitterSel = 0; |
863 | num = 0; |
- | |
864 | break; |
1063 | break; |
865 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1064 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
866 | args.v3.acConfig.ucTransmitterSel = 1; |
1065 | args.v3.acConfig.ucTransmitterSel = 1; |
867 | num = 1; |
- | |
868 | break; |
1066 | break; |
869 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1067 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
870 | args.v3.acConfig.ucTransmitterSel = 2; |
1068 | args.v3.acConfig.ucTransmitterSel = 2; |
871 | num = 2; |
- | |
872 | break; |
1069 | break; |
873 | } |
1070 | } |
874 | 1071 | ||
875 | if (is_dp) |
1072 | if (is_dp) |
876 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
1073 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
877 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1074 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
878 | if (dig->coherent_mode) |
1075 | if (dig->coherent_mode) |
879 | args.v3.acConfig.fCoherentMode = 1; |
1076 | args.v3.acConfig.fCoherentMode = 1; |
- | 1077 | if (radeon_encoder->pixel_clock > 165000) |
|
- | 1078 | args.v3.acConfig.fDualLinkConnector = 1; |
|
880 | } |
1079 | } |
881 | } else if (ASIC_IS_DCE32(rdev)) { |
1080 | } else if (ASIC_IS_DCE32(rdev)) { |
882 | if (dig->dig_encoder == 1) |
- | |
883 | args.v2.acConfig.ucEncoderSel = 1; |
1081 | args.v2.acConfig.ucEncoderSel = dig_encoder; |
884 | if (dig_connector->linkb) |
1082 | if (dig->linkb) |
885 | args.v2.acConfig.ucLinkSel = 1; |
1083 | args.v2.acConfig.ucLinkSel = 1; |
886 | 1084 | ||
887 | switch (radeon_encoder->encoder_id) { |
1085 | switch (radeon_encoder->encoder_id) { |
888 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1086 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
889 | args.v2.acConfig.ucTransmitterSel = 0; |
1087 | args.v2.acConfig.ucTransmitterSel = 0; |
890 | num = 0; |
- | |
891 | break; |
1088 | break; |
892 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1089 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
893 | args.v2.acConfig.ucTransmitterSel = 1; |
1090 | args.v2.acConfig.ucTransmitterSel = 1; |
894 | num = 1; |
- | |
895 | break; |
1091 | break; |
896 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1092 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
897 | args.v2.acConfig.ucTransmitterSel = 2; |
1093 | args.v2.acConfig.ucTransmitterSel = 2; |
898 | num = 2; |
- | |
899 | break; |
1094 | break; |
900 | } |
1095 | } |
901 | 1096 | ||
902 | if (is_dp) |
1097 | if (is_dp) |
903 | args.v2.acConfig.fCoherentMode = 1; |
1098 | args.v2.acConfig.fCoherentMode = 1; |
904 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1099 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
905 | if (dig->coherent_mode) |
1100 | if (dig->coherent_mode) |
906 | args.v2.acConfig.fCoherentMode = 1; |
1101 | args.v2.acConfig.fCoherentMode = 1; |
- | 1102 | if (radeon_encoder->pixel_clock > 165000) |
|
- | 1103 | args.v2.acConfig.fDualLinkConnector = 1; |
|
907 | } |
1104 | } |
908 | } else { |
1105 | } else { |
909 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
1106 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
910 | 1107 | ||
911 | if (dig->dig_encoder) |
1108 | if (dig_encoder) |
912 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
1109 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
913 | else |
1110 | else |
914 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
1111 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
915 | - | ||
916 | switch (radeon_encoder->encoder_id) { |
- | |
917 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1112 | |
918 | if (rdev->flags & RADEON_IS_IGP) { |
1113 | if ((rdev->flags & RADEON_IS_IGP) && |
919 | if (radeon_encoder->pixel_clock > 165000) { |
- | |
920 | if (dig_connector->igp_lane_info & 0x3) |
- | |
921 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
1114 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
922 | else if (dig_connector->igp_lane_info & 0xc) |
- | |
923 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
- | |
924 | } else { |
1115 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { |
925 | if (dig_connector->igp_lane_info & 0x1) |
1116 | if (igp_lane_info & 0x1) |
926 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
1117 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
927 | else if (dig_connector->igp_lane_info & 0x2) |
1118 | else if (igp_lane_info & 0x2) |
928 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
1119 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
929 | else if (dig_connector->igp_lane_info & 0x4) |
1120 | else if (igp_lane_info & 0x4) |
930 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
1121 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
931 | else if (dig_connector->igp_lane_info & 0x8) |
1122 | else if (igp_lane_info & 0x8) |
- | 1123 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
|
- | 1124 | } else { |
|
- | 1125 | if (igp_lane_info & 0x3) |
|
- | 1126 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
|
- | 1127 | else if (igp_lane_info & 0xc) |
|
932 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
1128 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
933 | } |
1129 | } |
934 | } |
- | |
935 | break; |
- | |
936 | } |
- | |
937 | - | ||
938 | if (radeon_encoder->pixel_clock > 165000) |
- | |
939 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
1130 | } |
940 | 1131 | ||
941 | if (dig_connector->linkb) |
1132 | if (dig->linkb) |
942 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
1133 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
943 | else |
1134 | else |
944 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
1135 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
945 | 1136 | ||
946 | if (is_dp) |
1137 | if (is_dp) |
947 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1138 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
948 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1139 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
949 | if (dig->coherent_mode) |
1140 | if (dig->coherent_mode) |
950 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1141 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
- | 1142 | if (radeon_encoder->pixel_clock > 165000) |
|
- | 1143 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
|
951 | } |
1144 | } |
952 | } |
1145 | } |
953 | 1146 | ||
954 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1147 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
955 | } |
1148 | } |
- | 1149 | ||
- | 1150 | bool |
|
- | 1151 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) |
|
- | 1152 | { |
|
- | 1153 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 1154 | struct drm_device *dev = radeon_connector->base.dev; |
|
- | 1155 | struct radeon_device *rdev = dev->dev_private; |
|
- | 1156 | union dig_transmitter_control args; |
|
- | 1157 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
|
- | 1158 | uint8_t frev, crev; |
|
- | 1159 | ||
- | 1160 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) |
|
- | 1161 | goto done; |
|
- | 1162 | ||
- | 1163 | if (!ASIC_IS_DCE4(rdev)) |
|
- | 1164 | goto done; |
|
- | 1165 | ||
- | 1166 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && |
|
- | 1167 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) |
|
- | 1168 | goto done; |
|
- | 1169 | ||
- | 1170 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
|
- | 1171 | goto done; |
|
- | 1172 | ||
- | 1173 | memset(&args, 0, sizeof(args)); |
|
- | 1174 | ||
- | 1175 | args.v1.ucAction = action; |
|
- | 1176 | ||
- | 1177 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
- | 1178 | ||
- | 1179 | /* wait for the panel to power up */ |
|
- | 1180 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { |
|
- | 1181 | int i; |
|
- | 1182 | ||
- | 1183 | for (i = 0; i < 300; i++) { |
|
- | 1184 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) |
|
- | 1185 | return true; |
|
- | 1186 | mdelay(1); |
|
- | 1187 | } |
|
- | 1188 | return false; |
|
- | 1189 | } |
|
- | 1190 | done: |
|
- | 1191 | return true; |
|
- | 1192 | } |
|
- | 1193 | ||
- | 1194 | union external_encoder_control { |
|
- | 1195 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; |
|
- | 1196 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; |
|
- | 1197 | }; |
|
- | 1198 | ||
- | 1199 | static void |
|
- | 1200 | atombios_external_encoder_setup(struct drm_encoder *encoder, |
|
- | 1201 | struct drm_encoder *ext_encoder, |
|
- | 1202 | int action) |
|
- | 1203 | { |
|
- | 1204 | struct drm_device *dev = encoder->dev; |
|
- | 1205 | struct radeon_device *rdev = dev->dev_private; |
|
- | 1206 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 1207 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); |
|
- | 1208 | union external_encoder_control args; |
|
- | 1209 | struct drm_connector *connector; |
|
- | 1210 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); |
|
- | 1211 | u8 frev, crev; |
|
- | 1212 | int dp_clock = 0; |
|
- | 1213 | int dp_lane_count = 0; |
|
- | 1214 | int connector_object_id = 0; |
|
- | 1215 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
|
- | 1216 | int bpc = 8; |
|
- | 1217 | ||
- | 1218 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
|
- | 1219 | connector = radeon_get_connector_for_encoder_init(encoder); |
|
- | 1220 | else |
|
- | 1221 | connector = radeon_get_connector_for_encoder(encoder); |
|
- | 1222 | ||
- | 1223 | if (connector) { |
|
- | 1224 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 1225 | struct radeon_connector_atom_dig *dig_connector = |
|
- | 1226 | radeon_connector->con_priv; |
|
- | 1227 | ||
- | 1228 | dp_clock = dig_connector->dp_clock; |
|
- | 1229 | dp_lane_count = dig_connector->dp_lane_count; |
|
- | 1230 | connector_object_id = |
|
- | 1231 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
|
- | 1232 | bpc = connector->display_info.bpc; |
|
- | 1233 | } |
|
- | 1234 | ||
- | 1235 | memset(&args, 0, sizeof(args)); |
|
- | 1236 | ||
- | 1237 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
|
- | 1238 | return; |
|
- | 1239 | ||
- | 1240 | switch (frev) { |
|
- | 1241 | case 1: |
|
- | 1242 | /* no params on frev 1 */ |
|
- | 1243 | break; |
|
- | 1244 | case 2: |
|
- | 1245 | switch (crev) { |
|
- | 1246 | case 1: |
|
- | 1247 | case 2: |
|
- | 1248 | args.v1.sDigEncoder.ucAction = action; |
|
- | 1249 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
|
- | 1250 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
|
- | 1251 | ||
- | 1252 | if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
|
- | 1253 | if (dp_clock == 270000) |
|
- | 1254 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
|
- | 1255 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; |
|
- | 1256 | } else if (radeon_encoder->pixel_clock > 165000) |
|
- | 1257 | args.v1.sDigEncoder.ucLaneNum = 8; |
|
- | 1258 | else |
|
- | 1259 | args.v1.sDigEncoder.ucLaneNum = 4; |
|
- | 1260 | break; |
|
- | 1261 | case 3: |
|
- | 1262 | args.v3.sExtEncoder.ucAction = action; |
|
- | 1263 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
|
- | 1264 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
|
- | 1265 | else |
|
- | 1266 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
|
- | 1267 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
|
- | 1268 | ||
- | 1269 | if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
|
- | 1270 | if (dp_clock == 270000) |
|
- | 1271 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
|
- | 1272 | else if (dp_clock == 540000) |
|
- | 1273 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; |
|
- | 1274 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; |
|
- | 1275 | } else if (radeon_encoder->pixel_clock > 165000) |
|
- | 1276 | args.v3.sExtEncoder.ucLaneNum = 8; |
|
- | 1277 | else |
|
- | 1278 | args.v3.sExtEncoder.ucLaneNum = 4; |
|
- | 1279 | switch (ext_enum) { |
|
- | 1280 | case GRAPH_OBJECT_ENUM_ID1: |
|
- | 1281 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; |
|
- | 1282 | break; |
|
- | 1283 | case GRAPH_OBJECT_ENUM_ID2: |
|
- | 1284 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; |
|
- | 1285 | break; |
|
- | 1286 | case GRAPH_OBJECT_ENUM_ID3: |
|
- | 1287 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; |
|
- | 1288 | break; |
|
- | 1289 | } |
|
- | 1290 | switch (bpc) { |
|
- | 1291 | case 0: |
|
- | 1292 | args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; |
|
- | 1293 | break; |
|
- | 1294 | case 6: |
|
- | 1295 | args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; |
|
- | 1296 | break; |
|
- | 1297 | case 8: |
|
- | 1298 | default: |
|
- | 1299 | args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
|
- | 1300 | break; |
|
- | 1301 | case 10: |
|
- | 1302 | args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
|
- | 1303 | break; |
|
- | 1304 | case 12: |
|
- | 1305 | args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
|
- | 1306 | break; |
|
- | 1307 | case 16: |
|
- | 1308 | args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
|
- | 1309 | break; |
|
- | 1310 | } |
|
- | 1311 | break; |
|
- | 1312 | default: |
|
- | 1313 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
|
- | 1314 | return; |
|
- | 1315 | } |
|
- | 1316 | break; |
|
- | 1317 | default: |
|
- | 1318 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
|
- | 1319 | return; |
|
- | 1320 | } |
|
- | 1321 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
- | 1322 | } |
|
956 | 1323 | ||
957 | static void |
1324 | static void |
958 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
1325 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
959 | { |
1326 | { |
960 | struct drm_device *dev = encoder->dev; |
1327 | struct drm_device *dev = encoder->dev; |
961 | struct radeon_device *rdev = dev->dev_private; |
1328 | struct radeon_device *rdev = dev->dev_private; |
962 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1329 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
963 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1330 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
964 | ENABLE_YUV_PS_ALLOCATION args; |
1331 | ENABLE_YUV_PS_ALLOCATION args; |
965 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
1332 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
966 | uint32_t temp, reg; |
1333 | uint32_t temp, reg; |
967 | 1334 | ||
968 | memset(&args, 0, sizeof(args)); |
1335 | memset(&args, 0, sizeof(args)); |
969 | 1336 | ||
970 | if (rdev->family >= CHIP_R600) |
1337 | if (rdev->family >= CHIP_R600) |
971 | reg = R600_BIOS_3_SCRATCH; |
1338 | reg = R600_BIOS_3_SCRATCH; |
972 | else |
1339 | else |
973 | reg = RADEON_BIOS_3_SCRATCH; |
1340 | reg = RADEON_BIOS_3_SCRATCH; |
974 | 1341 | ||
975 | /* XXX: fix up scratch reg handling */ |
1342 | /* XXX: fix up scratch reg handling */ |
976 | temp = RREG32(reg); |
1343 | temp = RREG32(reg); |
977 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1344 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
978 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
1345 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
979 | (radeon_crtc->crtc_id << 18))); |
1346 | (radeon_crtc->crtc_id << 18))); |
980 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1347 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
981 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1348 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
982 | else |
1349 | else |
983 | WREG32(reg, 0); |
1350 | WREG32(reg, 0); |
984 | 1351 | ||
985 | if (enable) |
1352 | if (enable) |
986 | args.ucEnable = ATOM_ENABLE; |
1353 | args.ucEnable = ATOM_ENABLE; |
987 | args.ucCRTC = radeon_crtc->crtc_id; |
1354 | args.ucCRTC = radeon_crtc->crtc_id; |
988 | 1355 | ||
989 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1356 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
990 | 1357 | ||
991 | WREG32(reg, temp); |
1358 | WREG32(reg, temp); |
992 | } |
1359 | } |
993 | 1360 | ||
994 | static void |
1361 | static void |
995 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1362 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
996 | { |
1363 | { |
997 | struct drm_device *dev = encoder->dev; |
1364 | struct drm_device *dev = encoder->dev; |
998 | struct radeon_device *rdev = dev->dev_private; |
1365 | struct radeon_device *rdev = dev->dev_private; |
999 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1366 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | 1367 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
|
1000 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
1368 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
1001 | int index = 0; |
1369 | int index = 0; |
1002 | bool is_dig = false; |
1370 | bool is_dig = false; |
- | 1371 | bool is_dce5_dac = false; |
|
- | 1372 | bool is_dce5_dvo = false; |
|
1003 | 1373 | ||
1004 | memset(&args, 0, sizeof(args)); |
1374 | memset(&args, 0, sizeof(args)); |
1005 | 1375 | ||
1006 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1376 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1007 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1377 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1008 | radeon_encoder->active_device); |
1378 | radeon_encoder->active_device); |
1009 | switch (radeon_encoder->encoder_id) { |
1379 | switch (radeon_encoder->encoder_id) { |
1010 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1380 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1011 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1381 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1012 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
1382 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
1013 | break; |
1383 | break; |
1014 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1384 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1015 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1385 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1016 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1386 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1017 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1387 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1018 | is_dig = true; |
1388 | is_dig = true; |
1019 | break; |
1389 | break; |
1020 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1390 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1021 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1391 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
- | 1392 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
|
- | 1393 | break; |
|
1022 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1394 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
- | 1395 | if (ASIC_IS_DCE5(rdev)) |
|
- | 1396 | is_dce5_dvo = true; |
|
- | 1397 | else if (ASIC_IS_DCE3(rdev)) |
|
- | 1398 | is_dig = true; |
|
- | 1399 | else |
|
1023 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1400 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1024 | break; |
1401 | break; |
1025 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1402 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1026 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1403 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1027 | break; |
1404 | break; |
1028 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1405 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1029 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1406 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1030 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1407 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1031 | else |
1408 | else |
1032 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
1409 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
1033 | break; |
1410 | break; |
1034 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1411 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1035 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1412 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
- | 1413 | if (ASIC_IS_DCE5(rdev)) |
|
- | 1414 | is_dce5_dac = true; |
|
- | 1415 | else { |
|
1036 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1416 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1037 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1417 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1038 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1418 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1039 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1419 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1040 | else |
1420 | else |
1041 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
1421 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
- | 1422 | } |
|
1042 | break; |
1423 | break; |
1043 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1424 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1044 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1425 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1045 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1426 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1046 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1427 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1047 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1428 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1048 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1429 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1049 | else |
1430 | else |
1050 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
1431 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
1051 | break; |
1432 | break; |
1052 | } |
1433 | } |
1053 | 1434 | ||
1054 | if (is_dig) { |
1435 | if (is_dig) { |
1055 | switch (mode) { |
1436 | switch (mode) { |
1056 | case DRM_MODE_DPMS_ON: |
1437 | case DRM_MODE_DPMS_ON: |
1057 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
1438 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
1058 | { |
- | |
- | 1439 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
|
1059 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1440 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
- | 1441 | ||
- | 1442 | if (connector && |
|
- | 1443 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { |
|
- | 1444 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 1445 | struct radeon_connector_atom_dig *radeon_dig_connector = |
|
- | 1446 | radeon_connector->con_priv; |
|
- | 1447 | atombios_set_edp_panel_power(connector, |
|
- | 1448 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
|
- | 1449 | radeon_dig_connector->edp_on = true; |
|
- | 1450 | } |
|
- | 1451 | if (ASIC_IS_DCE4(rdev)) |
|
- | 1452 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
|
1060 | dp_link_train(encoder, connector); |
1453 | radeon_dp_link_train(encoder, connector); |
- | 1454 | if (ASIC_IS_DCE4(rdev)) |
|
- | 1455 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
|
1061 | } |
1456 | } |
- | 1457 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
|
- | 1458 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
|
1062 | break; |
1459 | break; |
1063 | case DRM_MODE_DPMS_STANDBY: |
1460 | case DRM_MODE_DPMS_STANDBY: |
1064 | case DRM_MODE_DPMS_SUSPEND: |
1461 | case DRM_MODE_DPMS_SUSPEND: |
1065 | case DRM_MODE_DPMS_OFF: |
1462 | case DRM_MODE_DPMS_OFF: |
1066 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
1463 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
- | 1464 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
|
- | 1465 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
|
- | 1466 | ||
- | 1467 | if (ASIC_IS_DCE4(rdev)) |
|
- | 1468 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
|
- | 1469 | if (connector && |
|
- | 1470 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { |
|
- | 1471 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 1472 | struct radeon_connector_atom_dig *radeon_dig_connector = |
|
- | 1473 | radeon_connector->con_priv; |
|
- | 1474 | atombios_set_edp_panel_power(connector, |
|
- | 1475 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
|
- | 1476 | radeon_dig_connector->edp_on = false; |
|
- | 1477 | } |
|
- | 1478 | } |
|
- | 1479 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
|
- | 1480 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
|
- | 1481 | break; |
|
- | 1482 | } |
|
- | 1483 | } else if (is_dce5_dac) { |
|
- | 1484 | switch (mode) { |
|
- | 1485 | case DRM_MODE_DPMS_ON: |
|
- | 1486 | atombios_dac_setup(encoder, ATOM_ENABLE); |
|
- | 1487 | break; |
|
- | 1488 | case DRM_MODE_DPMS_STANDBY: |
|
- | 1489 | case DRM_MODE_DPMS_SUSPEND: |
|
- | 1490 | case DRM_MODE_DPMS_OFF: |
|
- | 1491 | atombios_dac_setup(encoder, ATOM_DISABLE); |
|
- | 1492 | break; |
|
- | 1493 | } |
|
- | 1494 | } else if (is_dce5_dvo) { |
|
- | 1495 | switch (mode) { |
|
- | 1496 | case DRM_MODE_DPMS_ON: |
|
- | 1497 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
|
- | 1498 | break; |
|
- | 1499 | case DRM_MODE_DPMS_STANDBY: |
|
- | 1500 | case DRM_MODE_DPMS_SUSPEND: |
|
- | 1501 | case DRM_MODE_DPMS_OFF: |
|
- | 1502 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
|
1067 | break; |
1503 | break; |
1068 | } |
1504 | } |
1069 | } else { |
1505 | } else { |
1070 | switch (mode) { |
1506 | switch (mode) { |
1071 | case DRM_MODE_DPMS_ON: |
1507 | case DRM_MODE_DPMS_ON: |
1072 | args.ucAction = ATOM_ENABLE; |
1508 | args.ucAction = ATOM_ENABLE; |
- | 1509 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
- | 1510 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
|
- | 1511 | args.ucAction = ATOM_LCD_BLON; |
|
- | 1512 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
- | 1513 | } |
|
1073 | break; |
1514 | break; |
1074 | case DRM_MODE_DPMS_STANDBY: |
1515 | case DRM_MODE_DPMS_STANDBY: |
1075 | case DRM_MODE_DPMS_SUSPEND: |
1516 | case DRM_MODE_DPMS_SUSPEND: |
1076 | case DRM_MODE_DPMS_OFF: |
1517 | case DRM_MODE_DPMS_OFF: |
1077 | args.ucAction = ATOM_DISABLE; |
1518 | args.ucAction = ATOM_DISABLE; |
- | 1519 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
- | 1520 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
|
- | 1521 | args.ucAction = ATOM_LCD_BLOFF; |
|
- | 1522 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
- | 1523 | } |
|
1078 | break; |
1524 | break; |
1079 | } |
1525 | } |
1080 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
- | |
1081 | } |
1526 | } |
- | 1527 | ||
- | 1528 | if (ext_encoder) { |
|
- | 1529 | int action; |
|
- | 1530 | ||
- | 1531 | switch (mode) { |
|
- | 1532 | case DRM_MODE_DPMS_ON: |
|
- | 1533 | default: |
|
- | 1534 | if (ASIC_IS_DCE41(rdev)) |
|
- | 1535 | action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; |
|
- | 1536 | else |
|
- | 1537 | action = ATOM_ENABLE; |
|
- | 1538 | break; |
|
- | 1539 | case DRM_MODE_DPMS_STANDBY: |
|
- | 1540 | case DRM_MODE_DPMS_SUSPEND: |
|
- | 1541 | case DRM_MODE_DPMS_OFF: |
|
- | 1542 | if (ASIC_IS_DCE41(rdev)) |
|
- | 1543 | action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; |
|
- | 1544 | else |
|
- | 1545 | action = ATOM_DISABLE; |
|
- | 1546 | break; |
|
- | 1547 | } |
|
- | 1548 | atombios_external_encoder_setup(encoder, ext_encoder, action); |
|
- | 1549 | } |
|
- | 1550 | ||
1082 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1551 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1083 | - | ||
1084 | /* adjust pm to dpms change */ |
- | |
1085 | radeon_pm_compute_clocks(rdev); |
1552 | |
1086 | } |
1553 | } |
1087 | 1554 | ||
1088 | union crtc_source_param { |
1555 | union crtc_source_param { |
1089 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1556 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1090 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
1557 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
1091 | }; |
1558 | }; |
1092 | 1559 | ||
1093 | static void |
1560 | static void |
1094 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
1561 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
1095 | { |
1562 | { |
1096 | struct drm_device *dev = encoder->dev; |
1563 | struct drm_device *dev = encoder->dev; |
1097 | struct radeon_device *rdev = dev->dev_private; |
1564 | struct radeon_device *rdev = dev->dev_private; |
1098 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1565 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1099 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1566 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1100 | union crtc_source_param args; |
1567 | union crtc_source_param args; |
1101 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1568 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1102 | uint8_t frev, crev; |
1569 | uint8_t frev, crev; |
1103 | struct radeon_encoder_atom_dig *dig; |
1570 | struct radeon_encoder_atom_dig *dig; |
1104 | 1571 | ||
1105 | memset(&args, 0, sizeof(args)); |
1572 | memset(&args, 0, sizeof(args)); |
1106 | 1573 | ||
- | 1574 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
|
1107 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
1575 | return; |
1108 | 1576 | ||
1109 | switch (frev) { |
1577 | switch (frev) { |
1110 | case 1: |
1578 | case 1: |
1111 | switch (crev) { |
1579 | switch (crev) { |
1112 | case 1: |
1580 | case 1: |
1113 | default: |
1581 | default: |
1114 | if (ASIC_IS_AVIVO(rdev)) |
1582 | if (ASIC_IS_AVIVO(rdev)) |
1115 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1583 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1116 | else { |
1584 | else { |
1117 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
1585 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
1118 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1586 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1119 | } else { |
1587 | } else { |
1120 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
1588 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
1121 | } |
1589 | } |
1122 | } |
1590 | } |
1123 | switch (radeon_encoder->encoder_id) { |
1591 | switch (radeon_encoder->encoder_id) { |
1124 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1592 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1125 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1593 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1126 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
1594 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
1127 | break; |
1595 | break; |
1128 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1596 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1129 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1597 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1130 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1598 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1131 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1599 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1132 | else |
1600 | else |
1133 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1601 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1134 | break; |
1602 | break; |
1135 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1603 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1136 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1604 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1137 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1605 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1138 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1606 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1139 | break; |
1607 | break; |
1140 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1608 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1141 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1609 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1142 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1610 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1143 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1611 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1144 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1612 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1145 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1613 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1146 | else |
1614 | else |
1147 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1615 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1148 | break; |
1616 | break; |
1149 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1617 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1150 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1618 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1151 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1619 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1152 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1620 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1153 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1621 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1154 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1622 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1155 | else |
1623 | else |
1156 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1624 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1157 | break; |
1625 | break; |
1158 | } |
1626 | } |
1159 | break; |
1627 | break; |
1160 | case 2: |
1628 | case 2: |
1161 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1629 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1162 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1630 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1163 | switch (radeon_encoder->encoder_id) { |
1631 | switch (radeon_encoder->encoder_id) { |
1164 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1632 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1165 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1633 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1166 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1634 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1167 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1635 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1168 | dig = radeon_encoder->enc_priv; |
1636 | dig = radeon_encoder->enc_priv; |
1169 | switch (dig->dig_encoder) { |
1637 | switch (dig->dig_encoder) { |
1170 | case 0: |
1638 | case 0: |
1171 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1639 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1172 | break; |
1640 | break; |
1173 | case 1: |
1641 | case 1: |
1174 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1642 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1175 | break; |
1643 | break; |
1176 | case 2: |
1644 | case 2: |
1177 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; |
1645 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; |
1178 | break; |
1646 | break; |
1179 | case 3: |
1647 | case 3: |
1180 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; |
1648 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; |
1181 | break; |
1649 | break; |
1182 | case 4: |
1650 | case 4: |
1183 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1651 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1184 | break; |
1652 | break; |
1185 | case 5: |
1653 | case 5: |
1186 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1654 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1187 | break; |
1655 | break; |
1188 | } |
1656 | } |
1189 | break; |
1657 | break; |
1190 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1658 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1191 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1659 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1192 | break; |
1660 | break; |
1193 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1661 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1194 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1662 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1195 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1663 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1196 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1664 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1197 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1665 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1198 | else |
1666 | else |
1199 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1667 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1200 | break; |
1668 | break; |
1201 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1669 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1202 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1670 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1203 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1671 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1204 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1672 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1205 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1673 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1206 | else |
1674 | else |
1207 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1675 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1208 | break; |
1676 | break; |
1209 | } |
1677 | } |
1210 | break; |
1678 | break; |
1211 | } |
1679 | } |
1212 | break; |
1680 | break; |
1213 | default: |
1681 | default: |
1214 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1682 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1215 | break; |
1683 | return; |
1216 | } |
1684 | } |
1217 | 1685 | ||
1218 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1686 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
- | 1687 | ||
- | 1688 | /* update scratch regs with new routing */ |
|
- | 1689 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
|
1219 | } |
1690 | } |
1220 | 1691 | ||
1221 | static void |
1692 | static void |
1222 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1693 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1223 | struct drm_display_mode *mode) |
1694 | struct drm_display_mode *mode) |
1224 | { |
1695 | { |
1225 | struct drm_device *dev = encoder->dev; |
1696 | struct drm_device *dev = encoder->dev; |
1226 | struct radeon_device *rdev = dev->dev_private; |
1697 | struct radeon_device *rdev = dev->dev_private; |
1227 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1698 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1228 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1699 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1229 | 1700 | ||
1230 | /* Funky macbooks */ |
1701 | /* Funky macbooks */ |
1231 | if ((dev->pdev->device == 0x71C5) && |
1702 | if ((dev->pdev->device == 0x71C5) && |
1232 | (dev->pdev->subsystem_vendor == 0x106b) && |
1703 | (dev->pdev->subsystem_vendor == 0x106b) && |
1233 | (dev->pdev->subsystem_device == 0x0080)) { |
1704 | (dev->pdev->subsystem_device == 0x0080)) { |
1234 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1705 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1235 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1706 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1236 | 1707 | ||
1237 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1708 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1238 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1709 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1239 | 1710 | ||
1240 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1711 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1241 | } |
1712 | } |
1242 | } |
1713 | } |
1243 | 1714 | ||
1244 | /* set scaler clears this on some chips */ |
1715 | /* set scaler clears this on some chips */ |
1245 | /* XXX check DCE4 */ |
1716 | if (ASIC_IS_AVIVO(rdev) && |
1246 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { |
1717 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
- | 1718 | if (ASIC_IS_DCE4(rdev)) { |
|
- | 1719 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
|
- | 1720 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
|
- | 1721 | EVERGREEN_INTERLEAVE_EN); |
|
- | 1722 | else |
|
- | 1723 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
|
- | 1724 | } else { |
|
1247 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
1725 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1248 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
1726 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
1249 | AVIVO_D1MODE_INTERLEAVE_EN); |
1727 | AVIVO_D1MODE_INTERLEAVE_EN); |
- | 1728 | else |
|
- | 1729 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
|
- | 1730 | } |
|
1250 | } |
1731 | } |
1251 | } |
1732 | } |
1252 | 1733 | ||
1253 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1734 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1254 | { |
1735 | { |
1255 | struct drm_device *dev = encoder->dev; |
1736 | struct drm_device *dev = encoder->dev; |
1256 | struct radeon_device *rdev = dev->dev_private; |
1737 | struct radeon_device *rdev = dev->dev_private; |
1257 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1738 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1258 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1739 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1259 | struct drm_encoder *test_encoder; |
1740 | struct drm_encoder *test_encoder; |
1260 | struct radeon_encoder_atom_dig *dig; |
1741 | struct radeon_encoder_atom_dig *dig; |
1261 | uint32_t dig_enc_in_use = 0; |
1742 | uint32_t dig_enc_in_use = 0; |
- | 1743 | ||
1262 | 1744 | /* DCE4/5 */ |
|
1263 | if (ASIC_IS_DCE4(rdev)) { |
1745 | if (ASIC_IS_DCE4(rdev)) { |
- | 1746 | dig = radeon_encoder->enc_priv; |
|
1264 | struct radeon_connector_atom_dig *dig_connector = |
1747 | if (ASIC_IS_DCE41(rdev)) |
1265 | radeon_get_atom_connector_priv_from_encoder(encoder); |
1748 | return radeon_crtc->crtc_id; |
1266 | 1749 | else { |
|
1267 | switch (radeon_encoder->encoder_id) { |
1750 | switch (radeon_encoder->encoder_id) { |
1268 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1751 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1269 | if (dig_connector->linkb) |
1752 | if (dig->linkb) |
1270 | return 1; |
1753 | return 1; |
1271 | else |
1754 | else |
1272 | return 0; |
1755 | return 0; |
1273 | break; |
1756 | break; |
1274 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1757 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1275 | if (dig_connector->linkb) |
1758 | if (dig->linkb) |
1276 | return 3; |
1759 | return 3; |
1277 | else |
1760 | else |
1278 | return 2; |
1761 | return 2; |
1279 | break; |
1762 | break; |
1280 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1763 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1281 | if (dig_connector->linkb) |
1764 | if (dig->linkb) |
1282 | return 5; |
1765 | return 5; |
1283 | else |
1766 | else |
1284 | return 4; |
1767 | return 4; |
1285 | break; |
1768 | break; |
1286 | } |
1769 | } |
1287 | } |
1770 | } |
- | 1771 | } |
|
1288 | 1772 | ||
1289 | /* on DCE32 and encoder can driver any block so just crtc id */ |
1773 | /* on DCE32 and encoder can driver any block so just crtc id */ |
1290 | if (ASIC_IS_DCE32(rdev)) { |
1774 | if (ASIC_IS_DCE32(rdev)) { |
1291 | return radeon_crtc->crtc_id; |
1775 | return radeon_crtc->crtc_id; |
1292 | } |
1776 | } |
1293 | 1777 | ||
1294 | /* on DCE3 - LVTMA can only be driven by DIGB */ |
1778 | /* on DCE3 - LVTMA can only be driven by DIGB */ |
1295 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1779 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1296 | struct radeon_encoder *radeon_test_encoder; |
1780 | struct radeon_encoder *radeon_test_encoder; |
1297 | 1781 | ||
1298 | if (encoder == test_encoder) |
1782 | if (encoder == test_encoder) |
1299 | continue; |
1783 | continue; |
1300 | 1784 | ||
1301 | if (!radeon_encoder_is_digital(test_encoder)) |
1785 | if (!radeon_encoder_is_digital(test_encoder)) |
1302 | continue; |
1786 | continue; |
1303 | 1787 | ||
1304 | radeon_test_encoder = to_radeon_encoder(test_encoder); |
1788 | radeon_test_encoder = to_radeon_encoder(test_encoder); |
1305 | dig = radeon_test_encoder->enc_priv; |
1789 | dig = radeon_test_encoder->enc_priv; |
1306 | 1790 | ||
1307 | if (dig->dig_encoder >= 0) |
1791 | if (dig->dig_encoder >= 0) |
1308 | dig_enc_in_use |= (1 << dig->dig_encoder); |
1792 | dig_enc_in_use |= (1 << dig->dig_encoder); |
1309 | } |
1793 | } |
1310 | 1794 | ||
1311 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { |
1795 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { |
1312 | if (dig_enc_in_use & 0x2) |
1796 | if (dig_enc_in_use & 0x2) |
1313 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); |
1797 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); |
1314 | return 1; |
1798 | return 1; |
1315 | } |
1799 | } |
1316 | if (!(dig_enc_in_use & 1)) |
1800 | if (!(dig_enc_in_use & 1)) |
1317 | return 0; |
1801 | return 0; |
1318 | return 1; |
1802 | return 1; |
1319 | } |
1803 | } |
- | 1804 | ||
- | 1805 | /* This only needs to be called once at startup */ |
|
- | 1806 | void |
|
- | 1807 | radeon_atom_encoder_init(struct radeon_device *rdev) |
|
- | 1808 | { |
|
- | 1809 | struct drm_device *dev = rdev->ddev; |
|
- | 1810 | struct drm_encoder *encoder; |
|
- | 1811 | ||
- | 1812 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
|
- | 1813 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 1814 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
|
- | 1815 | ||
- | 1816 | switch (radeon_encoder->encoder_id) { |
|
- | 1817 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
|
- | 1818 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
|
- | 1819 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
|
- | 1820 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
|
- | 1821 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
|
- | 1822 | break; |
|
- | 1823 | default: |
|
- | 1824 | break; |
|
- | 1825 | } |
|
- | 1826 | ||
- | 1827 | if (ext_encoder && ASIC_IS_DCE41(rdev)) |
|
- | 1828 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
- | 1829 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); |
|
- | 1830 | } |
|
- | 1831 | } |
|
1320 | 1832 | ||
1321 | static void |
1833 | static void |
1322 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
1834 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
1323 | struct drm_display_mode *mode, |
1835 | struct drm_display_mode *mode, |
1324 | struct drm_display_mode *adjusted_mode) |
1836 | struct drm_display_mode *adjusted_mode) |
1325 | { |
1837 | { |
1326 | struct drm_device *dev = encoder->dev; |
1838 | struct drm_device *dev = encoder->dev; |
1327 | struct radeon_device *rdev = dev->dev_private; |
1839 | struct radeon_device *rdev = dev->dev_private; |
1328 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1840 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1329 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1841 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
1330 | - | ||
1331 | if (radeon_encoder->active_device & |
- | |
1332 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { |
- | |
1333 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
- | |
1334 | if (dig) |
- | |
1335 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
- | |
1336 | } |
1842 | |
1337 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
- | |
1338 | - | ||
1339 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
- | |
1340 | atombios_set_encoder_crtc_source(encoder); |
1843 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1341 | 1844 | ||
1342 | if (ASIC_IS_AVIVO(rdev)) { |
1845 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
1343 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1846 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1344 | atombios_yuv_setup(encoder, true); |
1847 | atombios_yuv_setup(encoder, true); |
1345 | else |
1848 | else |
1346 | atombios_yuv_setup(encoder, false); |
1849 | atombios_yuv_setup(encoder, false); |
1347 | } |
1850 | } |
1348 | 1851 | ||
1349 | switch (radeon_encoder->encoder_id) { |
1852 | switch (radeon_encoder->encoder_id) { |
1350 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1853 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1351 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1854 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1352 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1855 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1353 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1856 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1354 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
1857 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
1355 | break; |
1858 | break; |
1356 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1859 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1357 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1860 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1358 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1861 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1359 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1862 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1360 | if (ASIC_IS_DCE4(rdev)) { |
1863 | if (ASIC_IS_DCE4(rdev)) { |
1361 | /* disable the transmitter */ |
1864 | /* disable the transmitter */ |
1362 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1865 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1363 | /* setup and enable the encoder */ |
1866 | /* setup and enable the encoder */ |
1364 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); |
1867 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1365 | 1868 | ||
1366 | /* init and enable the transmitter */ |
- | |
1367 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
1869 | /* enable the transmitter */ |
1368 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1870 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1369 | } else { |
1871 | } else { |
1370 | /* disable the encoder and transmitter */ |
1872 | /* disable the encoder and transmitter */ |
1371 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1873 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1372 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); |
1874 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1373 | 1875 | ||
1374 | /* setup and enable the encoder and transmitter */ |
1876 | /* setup and enable the encoder and transmitter */ |
1375 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); |
- | |
1376 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
1877 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
1377 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1878 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1378 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1879 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1379 | } |
1880 | } |
1380 | break; |
1881 | break; |
1381 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1882 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1382 | atombios_ddia_setup(encoder, ATOM_ENABLE); |
- | |
1383 | break; |
- | |
1384 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1883 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1385 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1884 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1386 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); |
1885 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1387 | break; |
1886 | break; |
1388 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1887 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1389 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1888 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1390 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1889 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1391 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1890 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1392 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1891 | atombios_dac_setup(encoder, ATOM_ENABLE); |
- | 1892 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
|
1393 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1893 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1394 | atombios_tv_setup(encoder, ATOM_ENABLE); |
1894 | atombios_tv_setup(encoder, ATOM_ENABLE); |
- | 1895 | else |
|
- | 1896 | atombios_tv_setup(encoder, ATOM_DISABLE); |
|
- | 1897 | } |
|
1395 | break; |
1898 | break; |
1396 | } |
1899 | } |
- | 1900 | ||
- | 1901 | if (ext_encoder) { |
|
- | 1902 | if (ASIC_IS_DCE41(rdev)) |
|
- | 1903 | atombios_external_encoder_setup(encoder, ext_encoder, |
|
- | 1904 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
|
- | 1905 | else |
|
- | 1906 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
|
- | 1907 | } |
|
- | 1908 | ||
1397 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
1909 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
1398 | 1910 | ||
1399 | /* XXX */ |
1911 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
1400 | if (!ASIC_IS_DCE4(rdev)) |
1912 | r600_hdmi_enable(encoder); |
1401 | r600_hdmi_setmode(encoder, adjusted_mode); |
1913 | r600_hdmi_setmode(encoder, adjusted_mode); |
- | 1914 | } |
|
1402 | } |
1915 | } |
1403 | 1916 | ||
1404 | static bool |
1917 | static bool |
1405 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1918 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1406 | { |
1919 | { |
1407 | struct drm_device *dev = encoder->dev; |
1920 | struct drm_device *dev = encoder->dev; |
1408 | struct radeon_device *rdev = dev->dev_private; |
1921 | struct radeon_device *rdev = dev->dev_private; |
1409 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1922 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1410 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1923 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1411 | 1924 | ||
1412 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
1925 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
1413 | ATOM_DEVICE_CV_SUPPORT | |
1926 | ATOM_DEVICE_CV_SUPPORT | |
1414 | ATOM_DEVICE_CRT_SUPPORT)) { |
1927 | ATOM_DEVICE_CRT_SUPPORT)) { |
1415 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
1928 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
1416 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
1929 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
1417 | uint8_t frev, crev; |
1930 | uint8_t frev, crev; |
1418 | 1931 | ||
1419 | memset(&args, 0, sizeof(args)); |
1932 | memset(&args, 0, sizeof(args)); |
1420 | 1933 | ||
- | 1934 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
|
1421 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
1935 | return false; |
1422 | 1936 | ||
1423 | args.sDacload.ucMisc = 0; |
1937 | args.sDacload.ucMisc = 0; |
1424 | 1938 | ||
1425 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
1939 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
1426 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
1940 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
1427 | args.sDacload.ucDacType = ATOM_DAC_A; |
1941 | args.sDacload.ucDacType = ATOM_DAC_A; |
1428 | else |
1942 | else |
1429 | args.sDacload.ucDacType = ATOM_DAC_B; |
1943 | args.sDacload.ucDacType = ATOM_DAC_B; |
1430 | 1944 | ||
1431 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
1945 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
1432 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
1946 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
1433 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
1947 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
1434 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
1948 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
1435 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1949 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1436 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1950 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1437 | if (crev >= 3) |
1951 | if (crev >= 3) |
1438 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1952 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1439 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1953 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1440 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1954 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1441 | if (crev >= 3) |
1955 | if (crev >= 3) |
1442 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1956 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1443 | } |
1957 | } |
1444 | 1958 | ||
1445 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1959 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1446 | 1960 | ||
1447 | return true; |
1961 | return true; |
1448 | } else |
1962 | } else |
1449 | return false; |
1963 | return false; |
1450 | } |
1964 | } |
1451 | 1965 | ||
1452 | static enum drm_connector_status |
1966 | static enum drm_connector_status |
1453 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1967 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1454 | { |
1968 | { |
1455 | struct drm_device *dev = encoder->dev; |
1969 | struct drm_device *dev = encoder->dev; |
1456 | struct radeon_device *rdev = dev->dev_private; |
1970 | struct radeon_device *rdev = dev->dev_private; |
1457 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1971 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1458 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1972 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1459 | uint32_t bios_0_scratch; |
1973 | uint32_t bios_0_scratch; |
1460 | 1974 | ||
1461 | if (!atombios_dac_load_detect(encoder, connector)) { |
1975 | if (!atombios_dac_load_detect(encoder, connector)) { |
1462 | DRM_DEBUG("detect returned false \n"); |
1976 | DRM_DEBUG_KMS("detect returned false \n"); |
1463 | return connector_status_unknown; |
1977 | return connector_status_unknown; |
1464 | } |
1978 | } |
1465 | 1979 | ||
1466 | if (rdev->family >= CHIP_R600) |
1980 | if (rdev->family >= CHIP_R600) |
1467 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1981 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1468 | else |
1982 | else |
1469 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1983 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1470 | 1984 | ||
1471 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1985 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1472 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1986 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1473 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1987 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1474 | return connector_status_connected; |
1988 | return connector_status_connected; |
1475 | } |
1989 | } |
1476 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
1990 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
1477 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1991 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1478 | return connector_status_connected; |
1992 | return connector_status_connected; |
1479 | } |
1993 | } |
1480 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1994 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1481 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1995 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1482 | return connector_status_connected; |
1996 | return connector_status_connected; |
1483 | } |
1997 | } |
1484 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1998 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1485 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1999 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1486 | return connector_status_connected; /* CTV */ |
2000 | return connector_status_connected; /* CTV */ |
1487 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
2001 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
1488 | return connector_status_connected; /* STV */ |
2002 | return connector_status_connected; /* STV */ |
1489 | } |
2003 | } |
1490 | return connector_status_disconnected; |
2004 | return connector_status_disconnected; |
1491 | } |
2005 | } |
1492 | 2006 | ||
1493 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
2007 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
1494 | { |
2008 | { |
- | 2009 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 2010 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
|
- | 2011 | ||
- | 2012 | if ((radeon_encoder->active_device & |
|
- | 2013 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
|
- | 2014 | radeon_encoder_is_dp_bridge(encoder)) { |
|
- | 2015 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
|
- | 2016 | if (dig) |
|
- | 2017 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
|
- | 2018 | } |
|
- | 2019 | ||
1495 | radeon_atom_output_lock(encoder, true); |
2020 | radeon_atom_output_lock(encoder, true); |
1496 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2021 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
- | 2022 | ||
- | 2023 | if (connector) { |
|
- | 2024 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 2025 | ||
- | 2026 | /* select the clock/data port if it uses a router */ |
|
- | 2027 | if (radeon_connector->router.cd_valid) |
|
- | 2028 | radeon_router_select_cd_port(radeon_connector); |
|
- | 2029 | ||
- | 2030 | /* turn eDP panel on for mode set */ |
|
- | 2031 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
|
- | 2032 | atombios_set_edp_panel_power(connector, |
|
- | 2033 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
|
- | 2034 | } |
|
- | 2035 | ||
- | 2036 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
|
- | 2037 | atombios_set_encoder_crtc_source(encoder); |
|
1497 | } |
2038 | } |
1498 | 2039 | ||
1499 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
2040 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
1500 | { |
2041 | { |
1501 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
2042 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
1502 | radeon_atom_output_lock(encoder, false); |
2043 | radeon_atom_output_lock(encoder, false); |
1503 | } |
2044 | } |
1504 | 2045 | ||
1505 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
2046 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
1506 | { |
2047 | { |
- | 2048 | struct drm_device *dev = encoder->dev; |
|
- | 2049 | struct radeon_device *rdev = dev->dev_private; |
|
1507 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2050 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1508 | struct radeon_encoder_atom_dig *dig; |
2051 | struct radeon_encoder_atom_dig *dig; |
- | 2052 | ||
- | 2053 | /* check for pre-DCE3 cards with shared encoders; |
|
- | 2054 | * can't really use the links individually, so don't disable |
|
- | 2055 | * the encoder if it's in use by another connector |
|
- | 2056 | */ |
|
- | 2057 | if (!ASIC_IS_DCE3(rdev)) { |
|
- | 2058 | struct drm_encoder *other_encoder; |
|
- | 2059 | struct radeon_encoder *other_radeon_encoder; |
|
- | 2060 | ||
- | 2061 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
|
- | 2062 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
|
- | 2063 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && |
|
- | 2064 | drm_helper_encoder_in_use(other_encoder)) |
|
- | 2065 | goto disable_done; |
|
- | 2066 | } |
|
- | 2067 | } |
|
- | 2068 | ||
1509 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2069 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
- | 2070 | ||
- | 2071 | switch (radeon_encoder->encoder_id) { |
|
- | 2072 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
|
- | 2073 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
|
- | 2074 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
|
- | 2075 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
|
- | 2076 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
|
- | 2077 | break; |
|
- | 2078 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
|
- | 2079 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
|
- | 2080 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
|
- | 2081 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
|
- | 2082 | if (ASIC_IS_DCE4(rdev)) |
|
- | 2083 | /* disable the transmitter */ |
|
- | 2084 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
|
- | 2085 | else { |
|
- | 2086 | /* disable the encoder and transmitter */ |
|
- | 2087 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
|
- | 2088 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
|
- | 2089 | } |
|
- | 2090 | break; |
|
- | 2091 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
|
- | 2092 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
|
- | 2093 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
|
- | 2094 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
|
- | 2095 | break; |
|
- | 2096 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
|
- | 2097 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
|
- | 2098 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
|
- | 2099 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
|
- | 2100 | atombios_dac_setup(encoder, ATOM_DISABLE); |
|
- | 2101 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
|
- | 2102 | atombios_tv_setup(encoder, ATOM_DISABLE); |
|
- | 2103 | break; |
|
- | 2104 | } |
|
- | 2105 | ||
1510 | 2106 | disable_done: |
|
- | 2107 | if (radeon_encoder_is_digital(encoder)) { |
|
- | 2108 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
|
1511 | if (radeon_encoder_is_digital(encoder)) { |
2109 | r600_hdmi_disable(encoder); |
1512 | dig = radeon_encoder->enc_priv; |
2110 | dig = radeon_encoder->enc_priv; |
1513 | dig->dig_encoder = -1; |
2111 | dig->dig_encoder = -1; |
1514 | } |
2112 | } |
1515 | radeon_encoder->active_device = 0; |
2113 | radeon_encoder->active_device = 0; |
1516 | } |
2114 | } |
- | 2115 | ||
- | 2116 | /* these are handled by the primary encoders */ |
|
- | 2117 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) |
|
- | 2118 | { |
|
- | 2119 | ||
- | 2120 | } |
|
- | 2121 | ||
- | 2122 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) |
|
- | 2123 | { |
|
- | 2124 | ||
- | 2125 | } |
|
- | 2126 | ||
- | 2127 | static void |
|
- | 2128 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, |
|
- | 2129 | struct drm_display_mode *mode, |
|
- | 2130 | struct drm_display_mode *adjusted_mode) |
|
- | 2131 | { |
|
- | 2132 | ||
- | 2133 | } |
|
- | 2134 | ||
- | 2135 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) |
|
- | 2136 | { |
|
- | 2137 | ||
- | 2138 | } |
|
- | 2139 | ||
- | 2140 | static void |
|
- | 2141 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) |
|
- | 2142 | { |
|
- | 2143 | ||
- | 2144 | } |
|
- | 2145 | ||
- | 2146 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, |
|
- | 2147 | struct drm_display_mode *mode, |
|
- | 2148 | struct drm_display_mode *adjusted_mode) |
|
- | 2149 | { |
|
- | 2150 | return true; |
|
- | 2151 | } |
|
- | 2152 | ||
- | 2153 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { |
|
- | 2154 | .dpms = radeon_atom_ext_dpms, |
|
- | 2155 | .mode_fixup = radeon_atom_ext_mode_fixup, |
|
- | 2156 | .prepare = radeon_atom_ext_prepare, |
|
- | 2157 | .mode_set = radeon_atom_ext_mode_set, |
|
- | 2158 | .commit = radeon_atom_ext_commit, |
|
- | 2159 | .disable = radeon_atom_ext_disable, |
|
- | 2160 | /* no detect for TMDS/LVDS yet */ |
|
- | 2161 | }; |
|
1517 | 2162 | ||
1518 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
2163 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1519 | .dpms = radeon_atom_encoder_dpms, |
2164 | .dpms = radeon_atom_encoder_dpms, |
1520 | .mode_fixup = radeon_atom_mode_fixup, |
2165 | .mode_fixup = radeon_atom_mode_fixup, |
1521 | .prepare = radeon_atom_encoder_prepare, |
2166 | .prepare = radeon_atom_encoder_prepare, |
1522 | .mode_set = radeon_atom_encoder_mode_set, |
2167 | .mode_set = radeon_atom_encoder_mode_set, |
1523 | .commit = radeon_atom_encoder_commit, |
2168 | .commit = radeon_atom_encoder_commit, |
1524 | .disable = radeon_atom_encoder_disable, |
2169 | .disable = radeon_atom_encoder_disable, |
1525 | /* no detect for TMDS/LVDS yet */ |
2170 | /* no detect for TMDS/LVDS yet */ |
1526 | }; |
2171 | }; |
1527 | 2172 | ||
1528 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
2173 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
1529 | .dpms = radeon_atom_encoder_dpms, |
2174 | .dpms = radeon_atom_encoder_dpms, |
1530 | .mode_fixup = radeon_atom_mode_fixup, |
2175 | .mode_fixup = radeon_atom_mode_fixup, |
1531 | .prepare = radeon_atom_encoder_prepare, |
2176 | .prepare = radeon_atom_encoder_prepare, |
1532 | .mode_set = radeon_atom_encoder_mode_set, |
2177 | .mode_set = radeon_atom_encoder_mode_set, |
1533 | .commit = radeon_atom_encoder_commit, |
2178 | .commit = radeon_atom_encoder_commit, |
1534 | .detect = radeon_atom_dac_detect, |
2179 | .detect = radeon_atom_dac_detect, |
1535 | }; |
2180 | }; |
1536 | 2181 | ||
1537 | void radeon_enc_destroy(struct drm_encoder *encoder) |
2182 | void radeon_enc_destroy(struct drm_encoder *encoder) |
1538 | { |
2183 | { |
1539 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2184 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1540 | kfree(radeon_encoder->enc_priv); |
2185 | kfree(radeon_encoder->enc_priv); |
1541 | drm_encoder_cleanup(encoder); |
2186 | drm_encoder_cleanup(encoder); |
1542 | kfree(radeon_encoder); |
2187 | kfree(radeon_encoder); |
1543 | } |
2188 | } |
1544 | 2189 | ||
1545 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
2190 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
1546 | .destroy = radeon_enc_destroy, |
2191 | .destroy = radeon_enc_destroy, |
1547 | }; |
2192 | }; |
1548 | 2193 | ||
1549 | struct radeon_encoder_atom_dac * |
2194 | struct radeon_encoder_atom_dac * |
1550 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
2195 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
1551 | { |
2196 | { |
- | 2197 | struct drm_device *dev = radeon_encoder->base.dev; |
|
- | 2198 | struct radeon_device *rdev = dev->dev_private; |
|
1552 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
2199 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
1553 | 2200 | ||
1554 | if (!dac) |
2201 | if (!dac) |
1555 | return NULL; |
2202 | return NULL; |
1556 | 2203 | ||
1557 | dac->tv_std = TV_STD_NTSC; |
2204 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
1558 | return dac; |
2205 | return dac; |
1559 | } |
2206 | } |
1560 | 2207 | ||
1561 | struct radeon_encoder_atom_dig * |
2208 | struct radeon_encoder_atom_dig * |
1562 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
2209 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
1563 | { |
2210 | { |
- | 2211 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
|
1564 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
2212 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
1565 | 2213 | ||
1566 | if (!dig) |
2214 | if (!dig) |
1567 | return NULL; |
2215 | return NULL; |
1568 | 2216 | ||
1569 | /* coherent mode by default */ |
2217 | /* coherent mode by default */ |
1570 | dig->coherent_mode = true; |
2218 | dig->coherent_mode = true; |
1571 | dig->dig_encoder = -1; |
2219 | dig->dig_encoder = -1; |
- | 2220 | ||
- | 2221 | if (encoder_enum == 2) |
|
- | 2222 | dig->linkb = true; |
|
- | 2223 | else |
|
- | 2224 | dig->linkb = false; |
|
1572 | 2225 | ||
1573 | return dig; |
2226 | return dig; |
1574 | } |
2227 | } |
1575 | 2228 | ||
1576 | void |
2229 | void |
1577 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) |
2230 | radeon_add_atom_encoder(struct drm_device *dev, |
- | 2231 | uint32_t encoder_enum, |
|
- | 2232 | uint32_t supported_device, |
|
- | 2233 | u16 caps) |
|
1578 | { |
2234 | { |
1579 | struct radeon_device *rdev = dev->dev_private; |
2235 | struct radeon_device *rdev = dev->dev_private; |
1580 | struct drm_encoder *encoder; |
2236 | struct drm_encoder *encoder; |
1581 | struct radeon_encoder *radeon_encoder; |
2237 | struct radeon_encoder *radeon_encoder; |
1582 | 2238 | ||
1583 | /* see if we already added it */ |
2239 | /* see if we already added it */ |
1584 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2240 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1585 | radeon_encoder = to_radeon_encoder(encoder); |
2241 | radeon_encoder = to_radeon_encoder(encoder); |
1586 | if (radeon_encoder->encoder_id == encoder_id) { |
2242 | if (radeon_encoder->encoder_enum == encoder_enum) { |
1587 | radeon_encoder->devices |= supported_device; |
2243 | radeon_encoder->devices |= supported_device; |
1588 | return; |
2244 | return; |
1589 | } |
2245 | } |
1590 | 2246 | ||
1591 | } |
2247 | } |
1592 | 2248 | ||
1593 | /* add a new one */ |
2249 | /* add a new one */ |
1594 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
2250 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
1595 | if (!radeon_encoder) |
2251 | if (!radeon_encoder) |
1596 | return; |
2252 | return; |
1597 | 2253 | ||
1598 | encoder = &radeon_encoder->base; |
2254 | encoder = &radeon_encoder->base; |
1599 | switch (rdev->num_crtc) { |
2255 | switch (rdev->num_crtc) { |
1600 | case 1: |
2256 | case 1: |
1601 | encoder->possible_crtcs = 0x1; |
2257 | encoder->possible_crtcs = 0x1; |
1602 | break; |
2258 | break; |
1603 | case 2: |
2259 | case 2: |
1604 | default: |
2260 | default: |
1605 | encoder->possible_crtcs = 0x3; |
2261 | encoder->possible_crtcs = 0x3; |
1606 | break; |
2262 | break; |
1607 | case 6: |
2263 | case 6: |
1608 | encoder->possible_crtcs = 0x3f; |
2264 | encoder->possible_crtcs = 0x3f; |
1609 | break; |
2265 | break; |
1610 | } |
2266 | } |
1611 | 2267 | ||
1612 | radeon_encoder->enc_priv = NULL; |
2268 | radeon_encoder->enc_priv = NULL; |
1613 | 2269 | ||
- | 2270 | radeon_encoder->encoder_enum = encoder_enum; |
|
1614 | radeon_encoder->encoder_id = encoder_id; |
2271 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1615 | radeon_encoder->devices = supported_device; |
2272 | radeon_encoder->devices = supported_device; |
- | 2273 | radeon_encoder->rmx_type = RMX_OFF; |
|
- | 2274 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
|
- | 2275 | radeon_encoder->is_ext_encoder = false; |
|
1616 | radeon_encoder->rmx_type = RMX_OFF; |
2276 | radeon_encoder->caps = caps; |
1617 | 2277 | ||
1618 | switch (radeon_encoder->encoder_id) { |
2278 | switch (radeon_encoder->encoder_id) { |
1619 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2279 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1620 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2280 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1621 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2281 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1622 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2282 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1623 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2283 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1624 | radeon_encoder->rmx_type = RMX_FULL; |
2284 | radeon_encoder->rmx_type = RMX_FULL; |
1625 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2285 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
1626 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2286 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
1627 | } else { |
2287 | } else { |
1628 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2288 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1629 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2289 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
1630 | } |
2290 | } |
1631 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2291 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1632 | break; |
2292 | break; |
1633 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2293 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1634 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2294 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
- | 2295 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
|
1635 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2296 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1636 | break; |
2297 | break; |
1637 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2298 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1638 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2299 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1639 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2300 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1640 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
2301 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
1641 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2302 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
1642 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2303 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1643 | break; |
2304 | break; |
1644 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2305 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1645 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2306 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1646 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2307 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1647 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2308 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1648 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2309 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1649 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2310 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1650 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2311 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1651 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2312 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1652 | radeon_encoder->rmx_type = RMX_FULL; |
2313 | radeon_encoder->rmx_type = RMX_FULL; |
1653 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2314 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
1654 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2315 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
- | 2316 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
|
- | 2317 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
|
- | 2318 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
|
1655 | } else { |
2319 | } else { |
1656 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2320 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1657 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2321 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
1658 | } |
2322 | } |
1659 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2323 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1660 | break; |
2324 | break; |
- | 2325 | case ENCODER_OBJECT_ID_SI170B: |
|
- | 2326 | case ENCODER_OBJECT_ID_CH7303: |
|
- | 2327 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: |
|
- | 2328 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: |
|
- | 2329 | case ENCODER_OBJECT_ID_TITFP513: |
|
- | 2330 | case ENCODER_OBJECT_ID_VT1623: |
|
- | 2331 | case ENCODER_OBJECT_ID_HDMI_SI1930: |
|
- | 2332 | case ENCODER_OBJECT_ID_TRAVIS: |
|
- | 2333 | case ENCODER_OBJECT_ID_NUTMEG: |
|
- | 2334 | /* these are handled by the primary encoders */ |
|
- | 2335 | radeon_encoder->is_ext_encoder = true; |
|
- | 2336 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
|
- | 2337 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
|
- | 2338 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
|
- | 2339 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
|
- | 2340 | else |
|
- | 2341 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
|
- | 2342 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); |
|
- | 2343 | break; |
|
1661 | } |
2344 | } |
1662 | - | ||
1663 | r600_hdmi_init(encoder); |
- | |
1664 | }><>><>><>><>><>><>><>>><> |
2345 | }><>><>><>><>>=>>><> |