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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include "drmP.h" |
26 | #include "drmP.h" |
27 | #include "drm_crtc_helper.h" |
27 | #include "drm_crtc_helper.h" |
28 | #include "radeon_drm.h" |
28 | #include "radeon_drm.h" |
29 | #include "radeon.h" |
29 | #include "radeon.h" |
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | 31 | ||
32 | extern int atom_debug; |
32 | extern int atom_debug; |
33 | 33 | ||
34 | uint32_t |
34 | uint32_t |
35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
36 | { |
36 | { |
37 | struct radeon_device *rdev = dev->dev_private; |
37 | struct radeon_device *rdev = dev->dev_private; |
38 | uint32_t ret = 0; |
38 | uint32_t ret = 0; |
39 | 39 | ||
40 | switch (supported_device) { |
40 | switch (supported_device) { |
41 | case ATOM_DEVICE_CRT1_SUPPORT: |
41 | case ATOM_DEVICE_CRT1_SUPPORT: |
42 | case ATOM_DEVICE_TV1_SUPPORT: |
42 | case ATOM_DEVICE_TV1_SUPPORT: |
43 | case ATOM_DEVICE_TV2_SUPPORT: |
43 | case ATOM_DEVICE_TV2_SUPPORT: |
44 | case ATOM_DEVICE_CRT2_SUPPORT: |
44 | case ATOM_DEVICE_CRT2_SUPPORT: |
45 | case ATOM_DEVICE_CV_SUPPORT: |
45 | case ATOM_DEVICE_CV_SUPPORT: |
46 | switch (dac) { |
46 | switch (dac) { |
47 | case 1: /* dac a */ |
47 | case 1: /* dac a */ |
48 | if ((rdev->family == CHIP_RS300) || |
48 | if ((rdev->family == CHIP_RS300) || |
49 | (rdev->family == CHIP_RS400) || |
49 | (rdev->family == CHIP_RS400) || |
50 | (rdev->family == CHIP_RS480)) |
50 | (rdev->family == CHIP_RS480)) |
51 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
51 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
52 | else if (ASIC_IS_AVIVO(rdev)) |
52 | else if (ASIC_IS_AVIVO(rdev)) |
53 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; |
53 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; |
54 | else |
54 | else |
55 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; |
55 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; |
56 | break; |
56 | break; |
57 | case 2: /* dac b */ |
57 | case 2: /* dac b */ |
58 | if (ASIC_IS_AVIVO(rdev)) |
58 | if (ASIC_IS_AVIVO(rdev)) |
59 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; |
59 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; |
60 | else { |
60 | else { |
61 | /*if (rdev->family == CHIP_R200) |
61 | /*if (rdev->family == CHIP_R200) |
62 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
62 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
63 | else*/ |
63 | else*/ |
64 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
64 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
65 | } |
65 | } |
66 | break; |
66 | break; |
67 | case 3: /* external dac */ |
67 | case 3: /* external dac */ |
68 | if (ASIC_IS_AVIVO(rdev)) |
68 | if (ASIC_IS_AVIVO(rdev)) |
69 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
69 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
70 | else |
70 | else |
71 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
71 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
72 | break; |
72 | break; |
73 | } |
73 | } |
74 | break; |
74 | break; |
75 | case ATOM_DEVICE_LCD1_SUPPORT: |
75 | case ATOM_DEVICE_LCD1_SUPPORT: |
76 | if (ASIC_IS_AVIVO(rdev)) |
76 | if (ASIC_IS_AVIVO(rdev)) |
77 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
77 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
78 | else |
78 | else |
79 | ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; |
79 | ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; |
80 | break; |
80 | break; |
81 | case ATOM_DEVICE_DFP1_SUPPORT: |
81 | case ATOM_DEVICE_DFP1_SUPPORT: |
82 | if ((rdev->family == CHIP_RS300) || |
82 | if ((rdev->family == CHIP_RS300) || |
83 | (rdev->family == CHIP_RS400) || |
83 | (rdev->family == CHIP_RS400) || |
84 | (rdev->family == CHIP_RS480)) |
84 | (rdev->family == CHIP_RS480)) |
85 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
85 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
86 | else if (ASIC_IS_AVIVO(rdev)) |
86 | else if (ASIC_IS_AVIVO(rdev)) |
87 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; |
87 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; |
88 | else |
88 | else |
89 | ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; |
89 | ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; |
90 | break; |
90 | break; |
91 | case ATOM_DEVICE_LCD2_SUPPORT: |
91 | case ATOM_DEVICE_LCD2_SUPPORT: |
92 | case ATOM_DEVICE_DFP2_SUPPORT: |
92 | case ATOM_DEVICE_DFP2_SUPPORT: |
93 | if ((rdev->family == CHIP_RS600) || |
93 | if ((rdev->family == CHIP_RS600) || |
94 | (rdev->family == CHIP_RS690) || |
94 | (rdev->family == CHIP_RS690) || |
95 | (rdev->family == CHIP_RS740)) |
95 | (rdev->family == CHIP_RS740)) |
96 | ret = ENCODER_OBJECT_ID_INTERNAL_DDI; |
96 | ret = ENCODER_OBJECT_ID_INTERNAL_DDI; |
97 | else if (ASIC_IS_AVIVO(rdev)) |
97 | else if (ASIC_IS_AVIVO(rdev)) |
98 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
98 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
99 | else |
99 | else |
100 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
100 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
101 | break; |
101 | break; |
102 | case ATOM_DEVICE_DFP3_SUPPORT: |
102 | case ATOM_DEVICE_DFP3_SUPPORT: |
103 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
103 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
104 | break; |
104 | break; |
105 | } |
105 | } |
106 | 106 | ||
107 | return ret; |
107 | return ret; |
108 | } |
108 | } |
109 | 109 | ||
110 | void |
110 | void |
111 | radeon_link_encoder_connector(struct drm_device *dev) |
111 | radeon_link_encoder_connector(struct drm_device *dev) |
112 | { |
112 | { |
113 | struct drm_connector *connector; |
113 | struct drm_connector *connector; |
114 | struct radeon_connector *radeon_connector; |
114 | struct radeon_connector *radeon_connector; |
115 | struct drm_encoder *encoder; |
115 | struct drm_encoder *encoder; |
116 | struct radeon_encoder *radeon_encoder; |
116 | struct radeon_encoder *radeon_encoder; |
117 | 117 | ||
118 | /* walk the list and link encoders to connectors */ |
118 | /* walk the list and link encoders to connectors */ |
119 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
119 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
120 | radeon_connector = to_radeon_connector(connector); |
120 | radeon_connector = to_radeon_connector(connector); |
121 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
121 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
122 | radeon_encoder = to_radeon_encoder(encoder); |
122 | radeon_encoder = to_radeon_encoder(encoder); |
123 | if (radeon_encoder->devices & radeon_connector->devices) |
123 | if (radeon_encoder->devices & radeon_connector->devices) |
124 | drm_mode_connector_attach_encoder(connector, encoder); |
124 | drm_mode_connector_attach_encoder(connector, encoder); |
125 | } |
125 | } |
126 | } |
126 | } |
127 | } |
127 | } |
128 | 128 | ||
129 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
129 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
130 | { |
130 | { |
131 | struct drm_device *dev = encoder->dev; |
131 | struct drm_device *dev = encoder->dev; |
132 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
132 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
133 | struct drm_connector *connector; |
133 | struct drm_connector *connector; |
134 | 134 | ||
135 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
135 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
136 | if (connector->encoder == encoder) { |
136 | if (connector->encoder == encoder) { |
137 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
137 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
138 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
138 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
139 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", |
139 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", |
140 | radeon_encoder->active_device, radeon_encoder->devices, |
140 | radeon_encoder->active_device, radeon_encoder->devices, |
141 | radeon_connector->devices, encoder->encoder_type); |
141 | radeon_connector->devices, encoder->encoder_type); |
142 | } |
142 | } |
143 | } |
143 | } |
144 | } |
144 | } |
145 | 145 | ||
146 | static struct drm_connector * |
146 | static struct drm_connector * |
147 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
147 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
148 | { |
148 | { |
149 | struct drm_device *dev = encoder->dev; |
149 | struct drm_device *dev = encoder->dev; |
150 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
150 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
151 | struct drm_connector *connector; |
151 | struct drm_connector *connector; |
152 | struct radeon_connector *radeon_connector; |
152 | struct radeon_connector *radeon_connector; |
153 | 153 | ||
154 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
154 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
155 | radeon_connector = to_radeon_connector(connector); |
155 | radeon_connector = to_radeon_connector(connector); |
156 | if (radeon_encoder->devices & radeon_connector->devices) |
156 | if (radeon_encoder->devices & radeon_connector->devices) |
157 | return connector; |
157 | return connector; |
158 | } |
158 | } |
159 | return NULL; |
159 | return NULL; |
160 | } |
160 | } |
161 | 161 | ||
162 | /* used for both atom and legacy */ |
162 | /* used for both atom and legacy */ |
163 | void radeon_rmx_mode_fixup(struct drm_encoder *encoder, |
163 | void radeon_rmx_mode_fixup(struct drm_encoder *encoder, |
164 | struct drm_display_mode *mode, |
164 | struct drm_display_mode *mode, |
165 | struct drm_display_mode *adjusted_mode) |
165 | struct drm_display_mode *adjusted_mode) |
166 | { |
166 | { |
167 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
167 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
168 | struct drm_device *dev = encoder->dev; |
168 | struct drm_device *dev = encoder->dev; |
169 | struct radeon_device *rdev = dev->dev_private; |
169 | struct radeon_device *rdev = dev->dev_private; |
170 | struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; |
170 | struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; |
171 | 171 | ||
172 | if (mode->hdisplay < native_mode->panel_xres || |
172 | if (mode->hdisplay < native_mode->panel_xres || |
173 | mode->vdisplay < native_mode->panel_yres) { |
173 | mode->vdisplay < native_mode->panel_yres) { |
174 | if (ASIC_IS_AVIVO(rdev)) { |
174 | if (ASIC_IS_AVIVO(rdev)) { |
175 | adjusted_mode->hdisplay = native_mode->panel_xres; |
175 | adjusted_mode->hdisplay = native_mode->panel_xres; |
176 | adjusted_mode->vdisplay = native_mode->panel_yres; |
176 | adjusted_mode->vdisplay = native_mode->panel_yres; |
177 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
177 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
178 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; |
178 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; |
179 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; |
179 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; |
180 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; |
180 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; |
181 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; |
181 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; |
182 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; |
182 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; |
183 | /* update crtc values */ |
183 | /* update crtc values */ |
184 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
184 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
185 | /* adjust crtc values */ |
185 | /* adjust crtc values */ |
186 | adjusted_mode->crtc_hdisplay = native_mode->panel_xres; |
186 | adjusted_mode->crtc_hdisplay = native_mode->panel_xres; |
187 | adjusted_mode->crtc_vdisplay = native_mode->panel_yres; |
187 | adjusted_mode->crtc_vdisplay = native_mode->panel_yres; |
188 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; |
188 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; |
189 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; |
189 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; |
190 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; |
190 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; |
191 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; |
191 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; |
192 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; |
192 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; |
193 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; |
193 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; |
194 | } else { |
194 | } else { |
195 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
195 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
196 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; |
196 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; |
197 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; |
197 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; |
198 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; |
198 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; |
199 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; |
199 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; |
200 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; |
200 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; |
201 | /* update crtc values */ |
201 | /* update crtc values */ |
202 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
202 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
203 | /* adjust crtc values */ |
203 | /* adjust crtc values */ |
204 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; |
204 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; |
205 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; |
205 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; |
206 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; |
206 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; |
207 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; |
207 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; |
208 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; |
208 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; |
209 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; |
209 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; |
210 | } |
210 | } |
211 | adjusted_mode->flags = native_mode->flags; |
211 | adjusted_mode->flags = native_mode->flags; |
212 | adjusted_mode->clock = native_mode->dotclock; |
212 | adjusted_mode->clock = native_mode->dotclock; |
213 | } |
213 | } |
214 | } |
214 | } |
215 | 215 | ||
216 | 216 | ||
217 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
217 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
218 | struct drm_display_mode *mode, |
218 | struct drm_display_mode *mode, |
219 | struct drm_display_mode *adjusted_mode) |
219 | struct drm_display_mode *adjusted_mode) |
220 | { |
220 | { |
221 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
221 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
222 | 222 | ||
223 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
223 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
224 | 224 | ||
225 | if (radeon_encoder->rmx_type != RMX_OFF) |
225 | if (radeon_encoder->rmx_type != RMX_OFF) |
226 | radeon_rmx_mode_fixup(encoder, mode, adjusted_mode); |
226 | radeon_rmx_mode_fixup(encoder, mode, adjusted_mode); |
227 | 227 | ||
228 | /* hw bug */ |
228 | /* hw bug */ |
229 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
229 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
230 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
230 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
231 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
231 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
232 | 232 | ||
233 | return true; |
233 | return true; |
234 | } |
234 | } |
235 | 235 | ||
236 | static void |
236 | static void |
237 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
237 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
238 | { |
238 | { |
239 | struct drm_device *dev = encoder->dev; |
239 | struct drm_device *dev = encoder->dev; |
240 | struct radeon_device *rdev = dev->dev_private; |
240 | struct radeon_device *rdev = dev->dev_private; |
241 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
241 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
242 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
242 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
243 | int index = 0, num = 0; |
243 | int index = 0, num = 0; |
244 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
244 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
245 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
245 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
246 | 246 | ||
247 | if (dac_info->tv_std) |
247 | if (dac_info->tv_std) |
248 | tv_std = dac_info->tv_std; |
248 | tv_std = dac_info->tv_std; |
249 | 249 | ||
250 | memset(&args, 0, sizeof(args)); |
250 | memset(&args, 0, sizeof(args)); |
251 | 251 | ||
252 | switch (radeon_encoder->encoder_id) { |
252 | switch (radeon_encoder->encoder_id) { |
253 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
253 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
254 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
254 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
255 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
255 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
256 | num = 1; |
256 | num = 1; |
257 | break; |
257 | break; |
258 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
258 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
259 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
259 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
260 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
260 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
261 | num = 2; |
261 | num = 2; |
262 | break; |
262 | break; |
263 | } |
263 | } |
264 | 264 | ||
265 | args.ucAction = action; |
265 | args.ucAction = action; |
266 | 266 | ||
267 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
267 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
268 | args.ucDacStandard = ATOM_DAC1_PS2; |
268 | args.ucDacStandard = ATOM_DAC1_PS2; |
269 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
269 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
270 | args.ucDacStandard = ATOM_DAC1_CV; |
270 | args.ucDacStandard = ATOM_DAC1_CV; |
271 | else { |
271 | else { |
272 | switch (tv_std) { |
272 | switch (tv_std) { |
273 | case TV_STD_PAL: |
273 | case TV_STD_PAL: |
274 | case TV_STD_PAL_M: |
274 | case TV_STD_PAL_M: |
275 | case TV_STD_SCART_PAL: |
275 | case TV_STD_SCART_PAL: |
276 | case TV_STD_SECAM: |
276 | case TV_STD_SECAM: |
277 | case TV_STD_PAL_CN: |
277 | case TV_STD_PAL_CN: |
278 | args.ucDacStandard = ATOM_DAC1_PAL; |
278 | args.ucDacStandard = ATOM_DAC1_PAL; |
279 | break; |
279 | break; |
280 | case TV_STD_NTSC: |
280 | case TV_STD_NTSC: |
281 | case TV_STD_NTSC_J: |
281 | case TV_STD_NTSC_J: |
282 | case TV_STD_PAL_60: |
282 | case TV_STD_PAL_60: |
283 | default: |
283 | default: |
284 | args.ucDacStandard = ATOM_DAC1_NTSC; |
284 | args.ucDacStandard = ATOM_DAC1_NTSC; |
285 | break; |
285 | break; |
286 | } |
286 | } |
287 | } |
287 | } |
288 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
288 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
289 | 289 | ||
290 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
290 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
291 | 291 | ||
292 | } |
292 | } |
293 | 293 | ||
294 | static void |
294 | static void |
295 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
295 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
296 | { |
296 | { |
297 | struct drm_device *dev = encoder->dev; |
297 | struct drm_device *dev = encoder->dev; |
298 | struct radeon_device *rdev = dev->dev_private; |
298 | struct radeon_device *rdev = dev->dev_private; |
299 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
299 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
300 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
300 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
301 | int index = 0; |
301 | int index = 0; |
302 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
302 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
303 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
303 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
304 | 304 | ||
305 | if (dac_info->tv_std) |
305 | if (dac_info->tv_std) |
306 | tv_std = dac_info->tv_std; |
306 | tv_std = dac_info->tv_std; |
307 | 307 | ||
308 | memset(&args, 0, sizeof(args)); |
308 | memset(&args, 0, sizeof(args)); |
309 | 309 | ||
310 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
310 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
311 | 311 | ||
312 | args.sTVEncoder.ucAction = action; |
312 | args.sTVEncoder.ucAction = action; |
313 | 313 | ||
314 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
314 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
315 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
315 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
316 | else { |
316 | else { |
317 | switch (tv_std) { |
317 | switch (tv_std) { |
318 | case TV_STD_NTSC: |
318 | case TV_STD_NTSC: |
319 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
319 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
320 | break; |
320 | break; |
321 | case TV_STD_PAL: |
321 | case TV_STD_PAL: |
322 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
322 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
323 | break; |
323 | break; |
324 | case TV_STD_PAL_M: |
324 | case TV_STD_PAL_M: |
325 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
325 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
326 | break; |
326 | break; |
327 | case TV_STD_PAL_60: |
327 | case TV_STD_PAL_60: |
328 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
328 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
329 | break; |
329 | break; |
330 | case TV_STD_NTSC_J: |
330 | case TV_STD_NTSC_J: |
331 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
331 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
332 | break; |
332 | break; |
333 | case TV_STD_SCART_PAL: |
333 | case TV_STD_SCART_PAL: |
334 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
334 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
335 | break; |
335 | break; |
336 | case TV_STD_SECAM: |
336 | case TV_STD_SECAM: |
337 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
337 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
338 | break; |
338 | break; |
339 | case TV_STD_PAL_CN: |
339 | case TV_STD_PAL_CN: |
340 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
340 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
341 | break; |
341 | break; |
342 | default: |
342 | default: |
343 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
343 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
344 | break; |
344 | break; |
345 | } |
345 | } |
346 | } |
346 | } |
347 | 347 | ||
348 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
348 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
349 | 349 | ||
350 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
350 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
351 | 351 | ||
352 | } |
352 | } |
353 | 353 | ||
354 | void |
354 | void |
355 | atombios_external_tmds_setup(struct drm_encoder *encoder, int action) |
355 | atombios_external_tmds_setup(struct drm_encoder *encoder, int action) |
356 | { |
356 | { |
357 | struct drm_device *dev = encoder->dev; |
357 | struct drm_device *dev = encoder->dev; |
358 | struct radeon_device *rdev = dev->dev_private; |
358 | struct radeon_device *rdev = dev->dev_private; |
359 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
359 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
360 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; |
360 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; |
361 | int index = 0; |
361 | int index = 0; |
362 | 362 | ||
363 | memset(&args, 0, sizeof(args)); |
363 | memset(&args, 0, sizeof(args)); |
364 | 364 | ||
365 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
365 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
366 | 366 | ||
367 | args.sXTmdsEncoder.ucEnable = action; |
367 | args.sXTmdsEncoder.ucEnable = action; |
368 | 368 | ||
369 | if (radeon_encoder->pixel_clock > 165000) |
369 | if (radeon_encoder->pixel_clock > 165000) |
370 | args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; |
370 | args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; |
371 | 371 | ||
372 | /*if (pScrn->rgbBits == 8)*/ |
372 | /*if (pScrn->rgbBits == 8)*/ |
373 | args.sXTmdsEncoder.ucMisc |= (1 << 1); |
373 | args.sXTmdsEncoder.ucMisc |= (1 << 1); |
374 | 374 | ||
375 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
375 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
376 | 376 | ||
377 | } |
377 | } |
378 | 378 | ||
379 | static void |
379 | static void |
380 | atombios_ddia_setup(struct drm_encoder *encoder, int action) |
380 | atombios_ddia_setup(struct drm_encoder *encoder, int action) |
381 | { |
381 | { |
382 | struct drm_device *dev = encoder->dev; |
382 | struct drm_device *dev = encoder->dev; |
383 | struct radeon_device *rdev = dev->dev_private; |
383 | struct radeon_device *rdev = dev->dev_private; |
384 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
384 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
385 | DVO_ENCODER_CONTROL_PS_ALLOCATION args; |
385 | DVO_ENCODER_CONTROL_PS_ALLOCATION args; |
386 | int index = 0; |
386 | int index = 0; |
387 | 387 | ||
388 | memset(&args, 0, sizeof(args)); |
388 | memset(&args, 0, sizeof(args)); |
389 | 389 | ||
390 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
390 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
391 | 391 | ||
392 | args.sDVOEncoder.ucAction = action; |
392 | args.sDVOEncoder.ucAction = action; |
393 | args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
393 | args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
394 | 394 | ||
395 | if (radeon_encoder->pixel_clock > 165000) |
395 | if (radeon_encoder->pixel_clock > 165000) |
396 | args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; |
396 | args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; |
397 | 397 | ||
398 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
398 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
399 | 399 | ||
400 | } |
400 | } |
401 | 401 | ||
402 | union lvds_encoder_control { |
402 | union lvds_encoder_control { |
403 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
403 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
404 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
404 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
405 | }; |
405 | }; |
406 | 406 | ||
407 | static void |
407 | static void |
408 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
408 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
409 | { |
409 | { |
410 | struct drm_device *dev = encoder->dev; |
410 | struct drm_device *dev = encoder->dev; |
411 | struct radeon_device *rdev = dev->dev_private; |
411 | struct radeon_device *rdev = dev->dev_private; |
412 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
412 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
413 | union lvds_encoder_control args; |
413 | union lvds_encoder_control args; |
414 | int index = 0; |
414 | int index = 0; |
415 | uint8_t frev, crev; |
415 | uint8_t frev, crev; |
416 | struct radeon_encoder_atom_dig *dig; |
416 | struct radeon_encoder_atom_dig *dig; |
417 | struct drm_connector *connector; |
417 | struct drm_connector *connector; |
418 | struct radeon_connector *radeon_connector; |
418 | struct radeon_connector *radeon_connector; |
419 | struct radeon_connector_atom_dig *dig_connector; |
419 | struct radeon_connector_atom_dig *dig_connector; |
420 | 420 | ||
421 | connector = radeon_get_connector_for_encoder(encoder); |
421 | connector = radeon_get_connector_for_encoder(encoder); |
422 | if (!connector) |
422 | if (!connector) |
423 | return; |
423 | return; |
424 | 424 | ||
425 | radeon_connector = to_radeon_connector(connector); |
425 | radeon_connector = to_radeon_connector(connector); |
426 | 426 | ||
427 | if (!radeon_encoder->enc_priv) |
427 | if (!radeon_encoder->enc_priv) |
428 | return; |
428 | return; |
429 | 429 | ||
430 | dig = radeon_encoder->enc_priv; |
430 | dig = radeon_encoder->enc_priv; |
431 | 431 | ||
432 | if (!radeon_connector->con_priv) |
432 | if (!radeon_connector->con_priv) |
433 | return; |
433 | return; |
434 | 434 | ||
435 | dig_connector = radeon_connector->con_priv; |
435 | dig_connector = radeon_connector->con_priv; |
436 | 436 | ||
437 | memset(&args, 0, sizeof(args)); |
437 | memset(&args, 0, sizeof(args)); |
438 | 438 | ||
439 | switch (radeon_encoder->encoder_id) { |
439 | switch (radeon_encoder->encoder_id) { |
440 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
440 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
441 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
441 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
442 | break; |
442 | break; |
443 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
443 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
444 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
444 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
445 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
445 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
446 | break; |
446 | break; |
447 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
447 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
448 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
448 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
449 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
449 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
450 | else |
450 | else |
451 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
451 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
452 | break; |
452 | break; |
453 | } |
453 | } |
454 | 454 | ||
455 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
455 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
456 | 456 | ||
457 | switch (frev) { |
457 | switch (frev) { |
458 | case 1: |
458 | case 1: |
459 | case 2: |
459 | case 2: |
460 | switch (crev) { |
460 | switch (crev) { |
461 | case 1: |
461 | case 1: |
462 | args.v1.ucMisc = 0; |
462 | args.v1.ucMisc = 0; |
463 | args.v1.ucAction = action; |
463 | args.v1.ucAction = action; |
464 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
464 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
465 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
465 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
466 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
466 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
467 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
467 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
468 | if (dig->lvds_misc & (1 << 0)) |
468 | if (dig->lvds_misc & (1 << 0)) |
469 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
469 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
470 | if (dig->lvds_misc & (1 << 1)) |
470 | if (dig->lvds_misc & (1 << 1)) |
471 | args.v1.ucMisc |= (1 << 1); |
471 | args.v1.ucMisc |= (1 << 1); |
472 | } else { |
472 | } else { |
473 | if (dig_connector->linkb) |
473 | if (dig_connector->linkb) |
474 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
474 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
475 | if (radeon_encoder->pixel_clock > 165000) |
475 | if (radeon_encoder->pixel_clock > 165000) |
476 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
476 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
477 | /*if (pScrn->rgbBits == 8) */ |
477 | /*if (pScrn->rgbBits == 8) */ |
478 | args.v1.ucMisc |= (1 << 1); |
478 | args.v1.ucMisc |= (1 << 1); |
479 | } |
479 | } |
480 | break; |
480 | break; |
481 | case 2: |
481 | case 2: |
482 | case 3: |
482 | case 3: |
483 | args.v2.ucMisc = 0; |
483 | args.v2.ucMisc = 0; |
484 | args.v2.ucAction = action; |
484 | args.v2.ucAction = action; |
485 | if (crev == 3) { |
485 | if (crev == 3) { |
486 | if (dig->coherent_mode) |
486 | if (dig->coherent_mode) |
487 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
487 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
488 | } |
488 | } |
489 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
489 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
490 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
490 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
491 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
491 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
492 | args.v2.ucTruncate = 0; |
492 | args.v2.ucTruncate = 0; |
493 | args.v2.ucSpatial = 0; |
493 | args.v2.ucSpatial = 0; |
494 | args.v2.ucTemporal = 0; |
494 | args.v2.ucTemporal = 0; |
495 | args.v2.ucFRC = 0; |
495 | args.v2.ucFRC = 0; |
496 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
496 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
497 | if (dig->lvds_misc & (1 << 0)) |
497 | if (dig->lvds_misc & (1 << 0)) |
498 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
498 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
499 | if (dig->lvds_misc & (1 << 5)) { |
499 | if (dig->lvds_misc & (1 << 5)) { |
500 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
500 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
501 | if (dig->lvds_misc & (1 << 1)) |
501 | if (dig->lvds_misc & (1 << 1)) |
502 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
502 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
503 | } |
503 | } |
504 | if (dig->lvds_misc & (1 << 6)) { |
504 | if (dig->lvds_misc & (1 << 6)) { |
505 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
505 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
506 | if (dig->lvds_misc & (1 << 1)) |
506 | if (dig->lvds_misc & (1 << 1)) |
507 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
507 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
508 | if (((dig->lvds_misc >> 2) & 0x3) == 2) |
508 | if (((dig->lvds_misc >> 2) & 0x3) == 2) |
509 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
509 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
510 | } |
510 | } |
511 | } else { |
511 | } else { |
512 | if (dig_connector->linkb) |
512 | if (dig_connector->linkb) |
513 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
513 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
514 | if (radeon_encoder->pixel_clock > 165000) |
514 | if (radeon_encoder->pixel_clock > 165000) |
515 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
515 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
516 | } |
516 | } |
517 | break; |
517 | break; |
518 | default: |
518 | default: |
519 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
519 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
520 | break; |
520 | break; |
521 | } |
521 | } |
522 | break; |
522 | break; |
523 | default: |
523 | default: |
524 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
524 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
525 | break; |
525 | break; |
526 | } |
526 | } |
527 | 527 | ||
528 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
528 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
529 | 529 | ||
530 | } |
530 | } |
531 | 531 | ||
532 | int |
532 | int |
533 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
533 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
534 | { |
534 | { |
535 | struct drm_connector *connector; |
535 | struct drm_connector *connector; |
536 | struct radeon_connector *radeon_connector; |
536 | struct radeon_connector *radeon_connector; |
537 | 537 | ||
538 | connector = radeon_get_connector_for_encoder(encoder); |
538 | connector = radeon_get_connector_for_encoder(encoder); |
539 | if (!connector) |
539 | if (!connector) |
540 | return 0; |
540 | return 0; |
541 | 541 | ||
542 | radeon_connector = to_radeon_connector(connector); |
542 | radeon_connector = to_radeon_connector(connector); |
543 | 543 | ||
544 | switch (connector->connector_type) { |
544 | switch (connector->connector_type) { |
545 | case DRM_MODE_CONNECTOR_DVII: |
545 | case DRM_MODE_CONNECTOR_DVII: |
546 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
546 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
547 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
547 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
548 | return ATOM_ENCODER_MODE_HDMI; |
548 | return ATOM_ENCODER_MODE_HDMI; |
549 | else if (radeon_connector->use_digital) |
549 | else if (radeon_connector->use_digital) |
550 | return ATOM_ENCODER_MODE_DVI; |
550 | return ATOM_ENCODER_MODE_DVI; |
551 | else |
551 | else |
552 | return ATOM_ENCODER_MODE_CRT; |
552 | return ATOM_ENCODER_MODE_CRT; |
553 | break; |
553 | break; |
554 | case DRM_MODE_CONNECTOR_DVID: |
554 | case DRM_MODE_CONNECTOR_DVID: |
555 | case DRM_MODE_CONNECTOR_HDMIA: |
555 | case DRM_MODE_CONNECTOR_HDMIA: |
556 | default: |
556 | default: |
557 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
557 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
558 | return ATOM_ENCODER_MODE_HDMI; |
558 | return ATOM_ENCODER_MODE_HDMI; |
559 | else |
559 | else |
560 | return ATOM_ENCODER_MODE_DVI; |
560 | return ATOM_ENCODER_MODE_DVI; |
561 | break; |
561 | break; |
562 | case DRM_MODE_CONNECTOR_LVDS: |
562 | case DRM_MODE_CONNECTOR_LVDS: |
563 | return ATOM_ENCODER_MODE_LVDS; |
563 | return ATOM_ENCODER_MODE_LVDS; |
564 | break; |
564 | break; |
565 | case DRM_MODE_CONNECTOR_DisplayPort: |
565 | case DRM_MODE_CONNECTOR_DisplayPort: |
566 | /*if (radeon_output->MonType == MT_DP) |
566 | /*if (radeon_output->MonType == MT_DP) |
567 | return ATOM_ENCODER_MODE_DP; |
567 | return ATOM_ENCODER_MODE_DP; |
568 | else*/ |
568 | else*/ |
569 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
569 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
570 | return ATOM_ENCODER_MODE_HDMI; |
570 | return ATOM_ENCODER_MODE_HDMI; |
571 | else |
571 | else |
572 | return ATOM_ENCODER_MODE_DVI; |
572 | return ATOM_ENCODER_MODE_DVI; |
573 | break; |
573 | break; |
574 | case CONNECTOR_DVI_A: |
574 | case CONNECTOR_DVI_A: |
575 | case CONNECTOR_VGA: |
575 | case CONNECTOR_VGA: |
576 | return ATOM_ENCODER_MODE_CRT; |
576 | return ATOM_ENCODER_MODE_CRT; |
577 | break; |
577 | break; |
578 | case CONNECTOR_STV: |
578 | case CONNECTOR_STV: |
579 | case CONNECTOR_CTV: |
579 | case CONNECTOR_CTV: |
580 | case CONNECTOR_DIN: |
580 | case CONNECTOR_DIN: |
581 | /* fix me */ |
581 | /* fix me */ |
582 | return ATOM_ENCODER_MODE_TV; |
582 | return ATOM_ENCODER_MODE_TV; |
583 | /*return ATOM_ENCODER_MODE_CV;*/ |
583 | /*return ATOM_ENCODER_MODE_CV;*/ |
584 | break; |
584 | break; |
585 | } |
585 | } |
586 | } |
586 | } |
587 | 587 | ||
588 | static void |
588 | static void |
589 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) |
589 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) |
590 | { |
590 | { |
591 | struct drm_device *dev = encoder->dev; |
591 | struct drm_device *dev = encoder->dev; |
592 | struct radeon_device *rdev = dev->dev_private; |
592 | struct radeon_device *rdev = dev->dev_private; |
593 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
593 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
594 | DIG_ENCODER_CONTROL_PS_ALLOCATION args; |
594 | DIG_ENCODER_CONTROL_PS_ALLOCATION args; |
595 | int index = 0, num = 0; |
595 | int index = 0, num = 0; |
596 | uint8_t frev, crev; |
596 | uint8_t frev, crev; |
597 | struct radeon_encoder_atom_dig *dig; |
597 | struct radeon_encoder_atom_dig *dig; |
598 | struct drm_connector *connector; |
598 | struct drm_connector *connector; |
599 | struct radeon_connector *radeon_connector; |
599 | struct radeon_connector *radeon_connector; |
600 | struct radeon_connector_atom_dig *dig_connector; |
600 | struct radeon_connector_atom_dig *dig_connector; |
601 | 601 | ||
602 | connector = radeon_get_connector_for_encoder(encoder); |
602 | connector = radeon_get_connector_for_encoder(encoder); |
603 | if (!connector) |
603 | if (!connector) |
604 | return; |
604 | return; |
605 | 605 | ||
606 | radeon_connector = to_radeon_connector(connector); |
606 | radeon_connector = to_radeon_connector(connector); |
607 | 607 | ||
608 | if (!radeon_connector->con_priv) |
608 | if (!radeon_connector->con_priv) |
609 | return; |
609 | return; |
610 | 610 | ||
611 | dig_connector = radeon_connector->con_priv; |
611 | dig_connector = radeon_connector->con_priv; |
612 | 612 | ||
613 | if (!radeon_encoder->enc_priv) |
613 | if (!radeon_encoder->enc_priv) |
614 | return; |
614 | return; |
615 | 615 | ||
616 | dig = radeon_encoder->enc_priv; |
616 | dig = radeon_encoder->enc_priv; |
617 | 617 | ||
618 | memset(&args, 0, sizeof(args)); |
618 | memset(&args, 0, sizeof(args)); |
619 | 619 | ||
620 | if (ASIC_IS_DCE32(rdev)) { |
620 | if (ASIC_IS_DCE32(rdev)) { |
621 | if (dig->dig_block) |
621 | if (dig->dig_block) |
622 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
622 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
623 | else |
623 | else |
624 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
624 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
625 | num = dig->dig_block + 1; |
625 | num = dig->dig_block + 1; |
626 | } else { |
626 | } else { |
627 | switch (radeon_encoder->encoder_id) { |
627 | switch (radeon_encoder->encoder_id) { |
628 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
628 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
629 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
629 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
630 | num = 1; |
630 | num = 1; |
631 | break; |
631 | break; |
632 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
632 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
633 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
633 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
634 | num = 2; |
634 | num = 2; |
635 | break; |
635 | break; |
636 | } |
636 | } |
637 | } |
637 | } |
638 | 638 | ||
639 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
639 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
640 | 640 | ||
641 | args.ucAction = action; |
641 | args.ucAction = action; |
642 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
642 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
643 | 643 | ||
644 | if (ASIC_IS_DCE32(rdev)) { |
644 | if (ASIC_IS_DCE32(rdev)) { |
645 | switch (radeon_encoder->encoder_id) { |
645 | switch (radeon_encoder->encoder_id) { |
646 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
646 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
647 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
647 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
648 | break; |
648 | break; |
649 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
649 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
650 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
650 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
651 | break; |
651 | break; |
652 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
652 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
653 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
653 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
654 | break; |
654 | break; |
655 | } |
655 | } |
656 | } else { |
656 | } else { |
657 | switch (radeon_encoder->encoder_id) { |
657 | switch (radeon_encoder->encoder_id) { |
658 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
658 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
659 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; |
659 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; |
660 | break; |
660 | break; |
661 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
661 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
662 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; |
662 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; |
663 | break; |
663 | break; |
664 | } |
664 | } |
665 | } |
665 | } |
666 | 666 | ||
667 | if (radeon_encoder->pixel_clock > 165000) { |
667 | if (radeon_encoder->pixel_clock > 165000) { |
668 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B; |
668 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B; |
669 | args.ucLaneNum = 8; |
669 | args.ucLaneNum = 8; |
670 | } else { |
670 | } else { |
671 | if (dig_connector->linkb) |
671 | if (dig_connector->linkb) |
672 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
672 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
673 | else |
673 | else |
674 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
674 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
675 | args.ucLaneNum = 4; |
675 | args.ucLaneNum = 4; |
676 | } |
676 | } |
677 | 677 | ||
678 | args.ucEncoderMode = atombios_get_encoder_mode(encoder); |
678 | args.ucEncoderMode = atombios_get_encoder_mode(encoder); |
679 | 679 | ||
680 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
680 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
681 | 681 | ||
682 | } |
682 | } |
683 | 683 | ||
684 | union dig_transmitter_control { |
684 | union dig_transmitter_control { |
685 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
685 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
686 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
686 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
687 | }; |
687 | }; |
688 | 688 | ||
689 | static void |
689 | static void |
690 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action) |
690 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action) |
691 | { |
691 | { |
692 | struct drm_device *dev = encoder->dev; |
692 | struct drm_device *dev = encoder->dev; |
693 | struct radeon_device *rdev = dev->dev_private; |
693 | struct radeon_device *rdev = dev->dev_private; |
694 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
694 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
695 | union dig_transmitter_control args; |
695 | union dig_transmitter_control args; |
696 | int index = 0, num = 0; |
696 | int index = 0, num = 0; |
697 | uint8_t frev, crev; |
697 | uint8_t frev, crev; |
698 | struct radeon_encoder_atom_dig *dig; |
698 | struct radeon_encoder_atom_dig *dig; |
699 | struct drm_connector *connector; |
699 | struct drm_connector *connector; |
700 | struct radeon_connector *radeon_connector; |
700 | struct radeon_connector *radeon_connector; |
701 | struct radeon_connector_atom_dig *dig_connector; |
701 | struct radeon_connector_atom_dig *dig_connector; |
702 | 702 | ||
703 | connector = radeon_get_connector_for_encoder(encoder); |
703 | connector = radeon_get_connector_for_encoder(encoder); |
704 | if (!connector) |
704 | if (!connector) |
705 | return; |
705 | return; |
706 | 706 | ||
707 | radeon_connector = to_radeon_connector(connector); |
707 | radeon_connector = to_radeon_connector(connector); |
708 | 708 | ||
709 | if (!radeon_encoder->enc_priv) |
709 | if (!radeon_encoder->enc_priv) |
710 | return; |
710 | return; |
711 | 711 | ||
712 | dig = radeon_encoder->enc_priv; |
712 | dig = radeon_encoder->enc_priv; |
713 | 713 | ||
714 | if (!radeon_connector->con_priv) |
714 | if (!radeon_connector->con_priv) |
715 | return; |
715 | return; |
716 | 716 | ||
717 | dig_connector = radeon_connector->con_priv; |
717 | dig_connector = radeon_connector->con_priv; |
718 | 718 | ||
719 | memset(&args, 0, sizeof(args)); |
719 | memset(&args, 0, sizeof(args)); |
720 | 720 | ||
721 | if (ASIC_IS_DCE32(rdev)) |
721 | if (ASIC_IS_DCE32(rdev)) |
722 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
722 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
723 | else { |
723 | else { |
724 | switch (radeon_encoder->encoder_id) { |
724 | switch (radeon_encoder->encoder_id) { |
725 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
725 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
726 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); |
726 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); |
727 | break; |
727 | break; |
728 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
728 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
729 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); |
729 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); |
730 | break; |
730 | break; |
731 | } |
731 | } |
732 | } |
732 | } |
733 | 733 | ||
734 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
734 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
735 | 735 | ||
736 | args.v1.ucAction = action; |
736 | args.v1.ucAction = action; |
737 | 737 | ||
738 | if (ASIC_IS_DCE32(rdev)) { |
738 | if (ASIC_IS_DCE32(rdev)) { |
739 | if (radeon_encoder->pixel_clock > 165000) { |
739 | if (radeon_encoder->pixel_clock > 165000) { |
740 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100); |
740 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100); |
741 | args.v2.acConfig.fDualLinkConnector = 1; |
741 | args.v2.acConfig.fDualLinkConnector = 1; |
742 | } else { |
742 | } else { |
743 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100); |
743 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100); |
744 | } |
744 | } |
745 | if (dig->dig_block) |
745 | if (dig->dig_block) |
746 | args.v2.acConfig.ucEncoderSel = 1; |
746 | args.v2.acConfig.ucEncoderSel = 1; |
747 | 747 | ||
748 | switch (radeon_encoder->encoder_id) { |
748 | switch (radeon_encoder->encoder_id) { |
749 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
749 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
750 | args.v2.acConfig.ucTransmitterSel = 0; |
750 | args.v2.acConfig.ucTransmitterSel = 0; |
751 | num = 0; |
751 | num = 0; |
752 | break; |
752 | break; |
753 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
753 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
754 | args.v2.acConfig.ucTransmitterSel = 1; |
754 | args.v2.acConfig.ucTransmitterSel = 1; |
755 | num = 1; |
755 | num = 1; |
756 | break; |
756 | break; |
757 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
757 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
758 | args.v2.acConfig.ucTransmitterSel = 2; |
758 | args.v2.acConfig.ucTransmitterSel = 2; |
759 | num = 2; |
759 | num = 2; |
760 | break; |
760 | break; |
761 | } |
761 | } |
762 | 762 | ||
763 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
763 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
764 | if (dig->coherent_mode) |
764 | if (dig->coherent_mode) |
765 | args.v2.acConfig.fCoherentMode = 1; |
765 | args.v2.acConfig.fCoherentMode = 1; |
766 | } |
766 | } |
767 | } else { |
767 | } else { |
768 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
768 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
769 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10); |
769 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10); |
770 | 770 | ||
771 | switch (radeon_encoder->encoder_id) { |
771 | switch (radeon_encoder->encoder_id) { |
772 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
772 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
773 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
773 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
774 | if (rdev->flags & RADEON_IS_IGP) { |
774 | if (rdev->flags & RADEON_IS_IGP) { |
775 | if (radeon_encoder->pixel_clock > 165000) { |
775 | if (radeon_encoder->pixel_clock > 165000) { |
776 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
776 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
777 | ATOM_TRANSMITTER_CONFIG_LINKA_B); |
777 | ATOM_TRANSMITTER_CONFIG_LINKA_B); |
778 | if (dig_connector->igp_lane_info & 0x3) |
778 | if (dig_connector->igp_lane_info & 0x3) |
779 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
779 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
780 | else if (dig_connector->igp_lane_info & 0xc) |
780 | else if (dig_connector->igp_lane_info & 0xc) |
781 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
781 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
782 | } else { |
782 | } else { |
783 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
783 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
784 | if (dig_connector->igp_lane_info & 0x1) |
784 | if (dig_connector->igp_lane_info & 0x1) |
785 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
785 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
786 | else if (dig_connector->igp_lane_info & 0x2) |
786 | else if (dig_connector->igp_lane_info & 0x2) |
787 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
787 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
788 | else if (dig_connector->igp_lane_info & 0x4) |
788 | else if (dig_connector->igp_lane_info & 0x4) |
789 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
789 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
790 | else if (dig_connector->igp_lane_info & 0x8) |
790 | else if (dig_connector->igp_lane_info & 0x8) |
791 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
791 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
792 | } |
792 | } |
793 | } else { |
793 | } else { |
794 | if (radeon_encoder->pixel_clock > 165000) |
794 | if (radeon_encoder->pixel_clock > 165000) |
795 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
795 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
796 | ATOM_TRANSMITTER_CONFIG_LINKA_B | |
796 | ATOM_TRANSMITTER_CONFIG_LINKA_B | |
797 | ATOM_TRANSMITTER_CONFIG_LANE_0_7); |
797 | ATOM_TRANSMITTER_CONFIG_LANE_0_7); |
798 | else { |
798 | else { |
799 | if (dig_connector->linkb) |
799 | if (dig_connector->linkb) |
800 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
800 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
801 | else |
801 | else |
802 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
802 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
803 | } |
803 | } |
804 | } |
804 | } |
805 | break; |
805 | break; |
806 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
806 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
807 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
807 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
808 | if (radeon_encoder->pixel_clock > 165000) |
808 | if (radeon_encoder->pixel_clock > 165000) |
809 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
809 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
810 | ATOM_TRANSMITTER_CONFIG_LINKA_B | |
810 | ATOM_TRANSMITTER_CONFIG_LINKA_B | |
811 | ATOM_TRANSMITTER_CONFIG_LANE_0_7); |
811 | ATOM_TRANSMITTER_CONFIG_LANE_0_7); |
812 | else { |
812 | else { |
813 | if (dig_connector->linkb) |
813 | if (dig_connector->linkb) |
814 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
814 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
815 | else |
815 | else |
816 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
816 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
817 | } |
817 | } |
818 | break; |
818 | break; |
819 | } |
819 | } |
820 | 820 | ||
821 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
821 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
822 | if (dig->coherent_mode) |
822 | if (dig->coherent_mode) |
823 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
823 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
824 | } |
824 | } |
825 | } |
825 | } |
826 | 826 | ||
827 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
827 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
828 | 828 | ||
829 | } |
829 | } |
830 | 830 | ||
831 | static void |
831 | static void |
832 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
832 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
833 | { |
833 | { |
834 | struct drm_device *dev = encoder->dev; |
834 | struct drm_device *dev = encoder->dev; |
835 | struct radeon_device *rdev = dev->dev_private; |
835 | struct radeon_device *rdev = dev->dev_private; |
836 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
836 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
837 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
837 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
838 | ENABLE_YUV_PS_ALLOCATION args; |
838 | ENABLE_YUV_PS_ALLOCATION args; |
839 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
839 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
840 | uint32_t temp, reg; |
840 | uint32_t temp, reg; |
841 | 841 | ||
842 | memset(&args, 0, sizeof(args)); |
842 | memset(&args, 0, sizeof(args)); |
843 | 843 | ||
844 | if (rdev->family >= CHIP_R600) |
844 | if (rdev->family >= CHIP_R600) |
845 | reg = R600_BIOS_3_SCRATCH; |
845 | reg = R600_BIOS_3_SCRATCH; |
846 | else |
846 | else |
847 | reg = RADEON_BIOS_3_SCRATCH; |
847 | reg = RADEON_BIOS_3_SCRATCH; |
848 | 848 | ||
849 | /* XXX: fix up scratch reg handling */ |
849 | /* XXX: fix up scratch reg handling */ |
850 | temp = RREG32(reg); |
850 | temp = RREG32(reg); |
851 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
851 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
852 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
852 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
853 | (radeon_crtc->crtc_id << 18))); |
853 | (radeon_crtc->crtc_id << 18))); |
854 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
854 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
855 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
855 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
856 | else |
856 | else |
857 | WREG32(reg, 0); |
857 | WREG32(reg, 0); |
858 | 858 | ||
859 | if (enable) |
859 | if (enable) |
860 | args.ucEnable = ATOM_ENABLE; |
860 | args.ucEnable = ATOM_ENABLE; |
861 | args.ucCRTC = radeon_crtc->crtc_id; |
861 | args.ucCRTC = radeon_crtc->crtc_id; |
862 | 862 | ||
863 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
863 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
864 | 864 | ||
865 | WREG32(reg, temp); |
865 | WREG32(reg, temp); |
866 | } |
866 | } |
867 | 867 | ||
868 | static void |
868 | static void |
869 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
869 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
870 | { |
870 | { |
871 | struct drm_device *dev = encoder->dev; |
871 | struct drm_device *dev = encoder->dev; |
872 | struct radeon_device *rdev = dev->dev_private; |
872 | struct radeon_device *rdev = dev->dev_private; |
873 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
873 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
874 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
874 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
875 | int index = 0; |
875 | int index = 0; |
876 | bool is_dig = false; |
876 | bool is_dig = false; |
877 | int devices; |
877 | int devices; |
878 | 878 | ||
879 | memset(&args, 0, sizeof(args)); |
879 | memset(&args, 0, sizeof(args)); |
880 | 880 | ||
881 | /* on DPMS off we have no idea if active device is meaningful */ |
881 | /* on DPMS off we have no idea if active device is meaningful */ |
882 | if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) |
882 | if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) |
883 | devices = radeon_encoder->devices; |
883 | devices = radeon_encoder->devices; |
884 | else |
884 | else |
885 | devices = radeon_encoder->active_device; |
885 | devices = radeon_encoder->active_device; |
886 | 886 | ||
887 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
887 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
888 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
888 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
889 | radeon_encoder->active_device); |
889 | radeon_encoder->active_device); |
890 | switch (radeon_encoder->encoder_id) { |
890 | switch (radeon_encoder->encoder_id) { |
891 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
891 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
892 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
892 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
893 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
893 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
894 | break; |
894 | break; |
895 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
895 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
896 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
896 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
897 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
897 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
898 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
898 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
899 | is_dig = true; |
899 | is_dig = true; |
900 | break; |
900 | break; |
901 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
901 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
902 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
902 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
903 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
903 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
904 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
904 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
905 | break; |
905 | break; |
906 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
906 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
907 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
907 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
908 | break; |
908 | break; |
909 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
909 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
910 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
910 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
911 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
911 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
912 | else |
912 | else |
913 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
913 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
914 | break; |
914 | break; |
915 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
915 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
916 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
916 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
917 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
917 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
918 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
918 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
919 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
919 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
920 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
920 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
921 | else |
921 | else |
922 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
922 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
923 | break; |
923 | break; |
924 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
924 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
925 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
925 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
926 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
926 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
927 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
927 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
928 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
928 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
929 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
929 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
930 | else |
930 | else |
931 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
931 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
932 | break; |
932 | break; |
933 | } |
933 | } |
934 | 934 | ||
935 | if (is_dig) { |
935 | if (is_dig) { |
936 | switch (mode) { |
936 | switch (mode) { |
937 | case DRM_MODE_DPMS_ON: |
937 | case DRM_MODE_DPMS_ON: |
938 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
938 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
939 | break; |
939 | break; |
940 | case DRM_MODE_DPMS_STANDBY: |
940 | case DRM_MODE_DPMS_STANDBY: |
941 | case DRM_MODE_DPMS_SUSPEND: |
941 | case DRM_MODE_DPMS_SUSPEND: |
942 | case DRM_MODE_DPMS_OFF: |
942 | case DRM_MODE_DPMS_OFF: |
943 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
943 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
944 | break; |
944 | break; |
945 | } |
945 | } |
946 | } else { |
946 | } else { |
947 | switch (mode) { |
947 | switch (mode) { |
948 | case DRM_MODE_DPMS_ON: |
948 | case DRM_MODE_DPMS_ON: |
949 | args.ucAction = ATOM_ENABLE; |
949 | args.ucAction = ATOM_ENABLE; |
950 | break; |
950 | break; |
951 | case DRM_MODE_DPMS_STANDBY: |
951 | case DRM_MODE_DPMS_STANDBY: |
952 | case DRM_MODE_DPMS_SUSPEND: |
952 | case DRM_MODE_DPMS_SUSPEND: |
953 | case DRM_MODE_DPMS_OFF: |
953 | case DRM_MODE_DPMS_OFF: |
954 | args.ucAction = ATOM_DISABLE; |
954 | args.ucAction = ATOM_DISABLE; |
955 | break; |
955 | break; |
956 | } |
956 | } |
957 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
957 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
958 | } |
958 | } |
959 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
959 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
960 | } |
960 | } |
961 | 961 | ||
962 | union crtc_sourc_param { |
962 | union crtc_sourc_param { |
963 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
963 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
964 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
964 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
965 | }; |
965 | }; |
966 | 966 | ||
967 | static void |
967 | static void |
968 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
968 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
969 | { |
969 | { |
970 | struct drm_device *dev = encoder->dev; |
970 | struct drm_device *dev = encoder->dev; |
971 | struct radeon_device *rdev = dev->dev_private; |
971 | struct radeon_device *rdev = dev->dev_private; |
972 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
972 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
973 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
973 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
974 | union crtc_sourc_param args; |
974 | union crtc_sourc_param args; |
975 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
975 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
976 | uint8_t frev, crev; |
976 | uint8_t frev, crev; |
977 | 977 | ||
978 | memset(&args, 0, sizeof(args)); |
978 | memset(&args, 0, sizeof(args)); |
979 | 979 | ||
980 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
980 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
981 | 981 | ||
982 | switch (frev) { |
982 | switch (frev) { |
983 | case 1: |
983 | case 1: |
984 | switch (crev) { |
984 | switch (crev) { |
985 | case 1: |
985 | case 1: |
986 | default: |
986 | default: |
987 | if (ASIC_IS_AVIVO(rdev)) |
987 | if (ASIC_IS_AVIVO(rdev)) |
988 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
988 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
989 | else { |
989 | else { |
990 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
990 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
991 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
991 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
992 | } else { |
992 | } else { |
993 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
993 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
994 | } |
994 | } |
995 | } |
995 | } |
996 | switch (radeon_encoder->encoder_id) { |
996 | switch (radeon_encoder->encoder_id) { |
997 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
997 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
998 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
998 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
999 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
999 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
1000 | break; |
1000 | break; |
1001 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1001 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1002 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1002 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1003 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1003 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1004 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1004 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1005 | else |
1005 | else |
1006 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1006 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1007 | break; |
1007 | break; |
1008 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1008 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1009 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1009 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1010 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1010 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1011 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1011 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1012 | break; |
1012 | break; |
1013 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1013 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1014 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1014 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1015 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1015 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1016 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1016 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1017 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1017 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1018 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1018 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1019 | else |
1019 | else |
1020 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1020 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1021 | break; |
1021 | break; |
1022 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1022 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1023 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1023 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1024 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1024 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1025 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1025 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1026 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1026 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1027 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1027 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1028 | else |
1028 | else |
1029 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1029 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1030 | break; |
1030 | break; |
1031 | } |
1031 | } |
1032 | break; |
1032 | break; |
1033 | case 2: |
1033 | case 2: |
1034 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1034 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1035 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1035 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1036 | switch (radeon_encoder->encoder_id) { |
1036 | switch (radeon_encoder->encoder_id) { |
1037 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1037 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1038 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1038 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1039 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1039 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1040 | if (ASIC_IS_DCE32(rdev)) { |
1040 | if (ASIC_IS_DCE32(rdev)) { |
1041 | if (radeon_crtc->crtc_id) |
1041 | if (radeon_crtc->crtc_id) |
1042 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1042 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1043 | else |
1043 | else |
1044 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1044 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1045 | } else |
1045 | } else |
1046 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1046 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1047 | break; |
1047 | break; |
1048 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1048 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1049 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1049 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1050 | break; |
1050 | break; |
1051 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1051 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1052 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1052 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1053 | break; |
1053 | break; |
1054 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1054 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1055 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1055 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1056 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1056 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1057 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1057 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1058 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1058 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1059 | else |
1059 | else |
1060 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1060 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1061 | break; |
1061 | break; |
1062 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1062 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1063 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1063 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1064 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1064 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1065 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1065 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1066 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1066 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1067 | else |
1067 | else |
1068 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1068 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1069 | break; |
1069 | break; |
1070 | } |
1070 | } |
1071 | break; |
1071 | break; |
1072 | } |
1072 | } |
1073 | break; |
1073 | break; |
1074 | default: |
1074 | default: |
1075 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1075 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1076 | break; |
1076 | break; |
1077 | } |
1077 | } |
1078 | 1078 | ||
1079 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1079 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1080 | 1080 | ||
1081 | } |
1081 | } |
1082 | 1082 | ||
1083 | static void |
1083 | static void |
1084 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1084 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1085 | struct drm_display_mode *mode) |
1085 | struct drm_display_mode *mode) |
1086 | { |
1086 | { |
1087 | struct drm_device *dev = encoder->dev; |
1087 | struct drm_device *dev = encoder->dev; |
1088 | struct radeon_device *rdev = dev->dev_private; |
1088 | struct radeon_device *rdev = dev->dev_private; |
1089 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1089 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1090 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1090 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1091 | 1091 | ||
1092 | /* Funky macbooks */ |
1092 | /* Funky macbooks */ |
1093 | if ((dev->pdev->device == 0x71C5) && |
1093 | if ((dev->pdev->device == 0x71C5) && |
1094 | (dev->pdev->subsystem_vendor == 0x106b) && |
1094 | (dev->pdev->subsystem_vendor == 0x106b) && |
1095 | (dev->pdev->subsystem_device == 0x0080)) { |
1095 | (dev->pdev->subsystem_device == 0x0080)) { |
1096 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1096 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1097 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1097 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1098 | 1098 | ||
1099 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1099 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1100 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1100 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1101 | 1101 | ||
1102 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1102 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1103 | } |
1103 | } |
1104 | } |
1104 | } |
1105 | 1105 | ||
1106 | /* set scaler clears this on some chips */ |
1106 | /* set scaler clears this on some chips */ |
1107 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
1107 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
1108 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN); |
1108 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN); |
1109 | } |
1109 | } |
1110 | 1110 | ||
1111 | static void |
1111 | static void |
1112 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
1112 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
1113 | struct drm_display_mode *mode, |
1113 | struct drm_display_mode *mode, |
1114 | struct drm_display_mode *adjusted_mode) |
1114 | struct drm_display_mode *adjusted_mode) |
1115 | { |
1115 | { |
1116 | struct drm_device *dev = encoder->dev; |
1116 | struct drm_device *dev = encoder->dev; |
1117 | struct radeon_device *rdev = dev->dev_private; |
1117 | struct radeon_device *rdev = dev->dev_private; |
1118 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1118 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1119 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1119 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1120 | 1120 | ||
1121 | if (radeon_encoder->enc_priv) { |
1121 | if (radeon_encoder->enc_priv) { |
1122 | struct radeon_encoder_atom_dig *dig; |
1122 | struct radeon_encoder_atom_dig *dig; |
1123 | 1123 | ||
1124 | dig = radeon_encoder->enc_priv; |
1124 | dig = radeon_encoder->enc_priv; |
1125 | dig->dig_block = radeon_crtc->crtc_id; |
1125 | dig->dig_block = radeon_crtc->crtc_id; |
1126 | } |
1126 | } |
1127 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1127 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1128 | 1128 | ||
1129 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
1129 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
1130 | atombios_set_encoder_crtc_source(encoder); |
1130 | atombios_set_encoder_crtc_source(encoder); |
1131 | 1131 | ||
1132 | if (ASIC_IS_AVIVO(rdev)) { |
1132 | if (ASIC_IS_AVIVO(rdev)) { |
1133 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1133 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1134 | atombios_yuv_setup(encoder, true); |
1134 | atombios_yuv_setup(encoder, true); |
1135 | else |
1135 | else |
1136 | atombios_yuv_setup(encoder, false); |
1136 | atombios_yuv_setup(encoder, false); |
1137 | } |
1137 | } |
1138 | 1138 | ||
1139 | switch (radeon_encoder->encoder_id) { |
1139 | switch (radeon_encoder->encoder_id) { |
1140 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1140 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1141 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1141 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1142 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1142 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1143 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1143 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1144 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
1144 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
1145 | break; |
1145 | break; |
1146 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1146 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1147 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1147 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1148 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1148 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1149 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1149 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1150 | /* disable the encoder and transmitter */ |
1150 | /* disable the encoder and transmitter */ |
1151 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
1151 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
1152 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); |
1152 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); |
1153 | 1153 | ||
1154 | /* setup and enable the encoder and transmitter */ |
1154 | /* setup and enable the encoder and transmitter */ |
1155 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); |
1155 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); |
1156 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); |
1156 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); |
1157 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
1157 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
1158 | break; |
1158 | break; |
1159 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1159 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1160 | atombios_ddia_setup(encoder, ATOM_ENABLE); |
1160 | atombios_ddia_setup(encoder, ATOM_ENABLE); |
1161 | break; |
1161 | break; |
1162 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1162 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1163 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1163 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1164 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); |
1164 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); |
1165 | break; |
1165 | break; |
1166 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1166 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1167 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1167 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1168 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1168 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1169 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1169 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1170 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1170 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1171 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1171 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1172 | atombios_tv_setup(encoder, ATOM_ENABLE); |
1172 | atombios_tv_setup(encoder, ATOM_ENABLE); |
1173 | break; |
1173 | break; |
1174 | } |
1174 | } |
1175 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
1175 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
1176 | } |
1176 | } |
1177 | 1177 | ||
1178 | static bool |
1178 | static bool |
1179 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1179 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1180 | { |
1180 | { |
1181 | struct drm_device *dev = encoder->dev; |
1181 | struct drm_device *dev = encoder->dev; |
1182 | struct radeon_device *rdev = dev->dev_private; |
1182 | struct radeon_device *rdev = dev->dev_private; |
1183 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1183 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1184 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1184 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1185 | 1185 | ||
1186 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
1186 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
1187 | ATOM_DEVICE_CV_SUPPORT | |
1187 | ATOM_DEVICE_CV_SUPPORT | |
1188 | ATOM_DEVICE_CRT_SUPPORT)) { |
1188 | ATOM_DEVICE_CRT_SUPPORT)) { |
1189 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
1189 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
1190 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
1190 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
1191 | uint8_t frev, crev; |
1191 | uint8_t frev, crev; |
1192 | 1192 | ||
1193 | memset(&args, 0, sizeof(args)); |
1193 | memset(&args, 0, sizeof(args)); |
1194 | 1194 | ||
1195 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
1195 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
1196 | 1196 | ||
1197 | args.sDacload.ucMisc = 0; |
1197 | args.sDacload.ucMisc = 0; |
1198 | 1198 | ||
1199 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
1199 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
1200 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
1200 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
1201 | args.sDacload.ucDacType = ATOM_DAC_A; |
1201 | args.sDacload.ucDacType = ATOM_DAC_A; |
1202 | else |
1202 | else |
1203 | args.sDacload.ucDacType = ATOM_DAC_B; |
1203 | args.sDacload.ucDacType = ATOM_DAC_B; |
1204 | 1204 | ||
1205 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
1205 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
1206 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
1206 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
1207 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
1207 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
1208 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
1208 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
1209 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1209 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1210 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1210 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1211 | if (crev >= 3) |
1211 | if (crev >= 3) |
1212 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1212 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1213 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1213 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1214 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1214 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1215 | if (crev >= 3) |
1215 | if (crev >= 3) |
1216 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1216 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1217 | } |
1217 | } |
1218 | 1218 | ||
1219 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1219 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1220 | 1220 | ||
1221 | return true; |
1221 | return true; |
1222 | } else |
1222 | } else |
1223 | return false; |
1223 | return false; |
1224 | } |
1224 | } |
1225 | 1225 | ||
1226 | static enum drm_connector_status |
1226 | static enum drm_connector_status |
1227 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1227 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1228 | { |
1228 | { |
1229 | struct drm_device *dev = encoder->dev; |
1229 | struct drm_device *dev = encoder->dev; |
1230 | struct radeon_device *rdev = dev->dev_private; |
1230 | struct radeon_device *rdev = dev->dev_private; |
1231 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1231 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1232 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1232 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1233 | uint32_t bios_0_scratch; |
1233 | uint32_t bios_0_scratch; |
1234 | 1234 | ||
1235 | if (!atombios_dac_load_detect(encoder, connector)) { |
1235 | if (!atombios_dac_load_detect(encoder, connector)) { |
1236 | DRM_DEBUG("detect returned false \n"); |
1236 | DRM_DEBUG("detect returned false \n"); |
1237 | return connector_status_unknown; |
1237 | return connector_status_unknown; |
1238 | } |
1238 | } |
1239 | 1239 | ||
1240 | if (rdev->family >= CHIP_R600) |
1240 | if (rdev->family >= CHIP_R600) |
1241 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1241 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1242 | else |
1242 | else |
1243 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1243 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1244 | 1244 | ||
1245 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1245 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1246 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1246 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1247 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1247 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1248 | return connector_status_connected; |
1248 | return connector_status_connected; |
1249 | } |
1249 | } |
1250 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
1250 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
1251 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1251 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1252 | return connector_status_connected; |
1252 | return connector_status_connected; |
1253 | } |
1253 | } |
1254 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1254 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
1255 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1255 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1256 | return connector_status_connected; |
1256 | return connector_status_connected; |
1257 | } |
1257 | } |
1258 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1258 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1259 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1259 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1260 | return connector_status_connected; /* CTV */ |
1260 | return connector_status_connected; /* CTV */ |
1261 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
1261 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
1262 | return connector_status_connected; /* STV */ |
1262 | return connector_status_connected; /* STV */ |
1263 | } |
1263 | } |
1264 | return connector_status_disconnected; |
1264 | return connector_status_disconnected; |
1265 | } |
1265 | } |
1266 | 1266 | ||
1267 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
1267 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
1268 | { |
1268 | { |
1269 | radeon_atom_output_lock(encoder, true); |
1269 | radeon_atom_output_lock(encoder, true); |
1270 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
1270 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
1271 | 1271 | ||
1272 | radeon_encoder_set_active_device(encoder); |
1272 | radeon_encoder_set_active_device(encoder); |
1273 | } |
1273 | } |
1274 | 1274 | ||
1275 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
1275 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
1276 | { |
1276 | { |
1277 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
1277 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
1278 | radeon_atom_output_lock(encoder, false); |
1278 | radeon_atom_output_lock(encoder, false); |
1279 | } |
1279 | } |
1280 | 1280 | ||
1281 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
1281 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
1282 | { |
1282 | { |
1283 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1283 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1284 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
1284 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
1285 | radeon_encoder->active_device = 0; |
1285 | radeon_encoder->active_device = 0; |
1286 | } |
1286 | } |
1287 | 1287 | ||
1288 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1288 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1289 | .dpms = radeon_atom_encoder_dpms, |
1289 | .dpms = radeon_atom_encoder_dpms, |
1290 | .mode_fixup = radeon_atom_mode_fixup, |
1290 | .mode_fixup = radeon_atom_mode_fixup, |
1291 | .prepare = radeon_atom_encoder_prepare, |
1291 | .prepare = radeon_atom_encoder_prepare, |
1292 | .mode_set = radeon_atom_encoder_mode_set, |
1292 | .mode_set = radeon_atom_encoder_mode_set, |
1293 | .commit = radeon_atom_encoder_commit, |
1293 | .commit = radeon_atom_encoder_commit, |
1294 | .disable = radeon_atom_encoder_disable, |
1294 | .disable = radeon_atom_encoder_disable, |
1295 | /* no detect for TMDS/LVDS yet */ |
1295 | /* no detect for TMDS/LVDS yet */ |
1296 | }; |
1296 | }; |
1297 | 1297 | ||
1298 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
1298 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
1299 | .dpms = radeon_atom_encoder_dpms, |
1299 | .dpms = radeon_atom_encoder_dpms, |
1300 | .mode_fixup = radeon_atom_mode_fixup, |
1300 | .mode_fixup = radeon_atom_mode_fixup, |
1301 | .prepare = radeon_atom_encoder_prepare, |
1301 | .prepare = radeon_atom_encoder_prepare, |
1302 | .mode_set = radeon_atom_encoder_mode_set, |
1302 | .mode_set = radeon_atom_encoder_mode_set, |
1303 | .commit = radeon_atom_encoder_commit, |
1303 | .commit = radeon_atom_encoder_commit, |
1304 | .detect = radeon_atom_dac_detect, |
1304 | .detect = radeon_atom_dac_detect, |
1305 | }; |
1305 | }; |
1306 | 1306 | ||
1307 | void radeon_enc_destroy(struct drm_encoder *encoder) |
1307 | void radeon_enc_destroy(struct drm_encoder *encoder) |
1308 | { |
1308 | { |
1309 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1309 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1310 | kfree(radeon_encoder->enc_priv); |
1310 | kfree(radeon_encoder->enc_priv); |
1311 | drm_encoder_cleanup(encoder); |
1311 | drm_encoder_cleanup(encoder); |
1312 | kfree(radeon_encoder); |
1312 | kfree(radeon_encoder); |
1313 | } |
1313 | } |
1314 | 1314 | ||
1315 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
1315 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
1316 | .destroy = radeon_enc_destroy, |
1316 | .destroy = radeon_enc_destroy, |
1317 | }; |
1317 | }; |
1318 | 1318 | ||
1319 | struct radeon_encoder_atom_dac * |
1319 | struct radeon_encoder_atom_dac * |
1320 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
1320 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
1321 | { |
1321 | { |
1322 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
1322 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
1323 | 1323 | ||
1324 | if (!dac) |
1324 | if (!dac) |
1325 | return NULL; |
1325 | return NULL; |
1326 | 1326 | ||
1327 | dac->tv_std = TV_STD_NTSC; |
1327 | dac->tv_std = TV_STD_NTSC; |
1328 | return dac; |
1328 | return dac; |
1329 | } |
1329 | } |
1330 | 1330 | ||
1331 | struct radeon_encoder_atom_dig * |
1331 | struct radeon_encoder_atom_dig * |
1332 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
1332 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
1333 | { |
1333 | { |
1334 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
1334 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
1335 | 1335 | ||
1336 | if (!dig) |
1336 | if (!dig) |
1337 | return NULL; |
1337 | return NULL; |
1338 | 1338 | ||
1339 | /* coherent mode by default */ |
1339 | /* coherent mode by default */ |
1340 | dig->coherent_mode = true; |
1340 | dig->coherent_mode = true; |
1341 | 1341 | ||
1342 | return dig; |
1342 | return dig; |
1343 | } |
1343 | } |
1344 | 1344 | ||
1345 | void |
1345 | void |
1346 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) |
1346 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) |
1347 | { |
1347 | { |
- | 1348 | struct radeon_device *rdev = dev->dev_private; |
|
1348 | struct drm_encoder *encoder; |
1349 | struct drm_encoder *encoder; |
1349 | struct radeon_encoder *radeon_encoder; |
1350 | struct radeon_encoder *radeon_encoder; |
1350 | 1351 | ||
1351 | /* see if we already added it */ |
1352 | /* see if we already added it */ |
1352 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1353 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1353 | radeon_encoder = to_radeon_encoder(encoder); |
1354 | radeon_encoder = to_radeon_encoder(encoder); |
1354 | if (radeon_encoder->encoder_id == encoder_id) { |
1355 | if (radeon_encoder->encoder_id == encoder_id) { |
1355 | radeon_encoder->devices |= supported_device; |
1356 | radeon_encoder->devices |= supported_device; |
1356 | return; |
1357 | return; |
1357 | } |
1358 | } |
1358 | 1359 | ||
1359 | } |
1360 | } |
1360 | 1361 | ||
1361 | /* add a new one */ |
1362 | /* add a new one */ |
1362 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
1363 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
1363 | if (!radeon_encoder) |
1364 | if (!radeon_encoder) |
1364 | return; |
1365 | return; |
1365 | 1366 | ||
1366 | encoder = &radeon_encoder->base; |
1367 | encoder = &radeon_encoder->base; |
- | 1368 | if (rdev->flags & RADEON_SINGLE_CRTC) |
|
- | 1369 | encoder->possible_crtcs = 0x1; |
|
- | 1370 | else |
|
1367 | encoder->possible_crtcs = 0x3; |
1371 | encoder->possible_crtcs = 0x3; |
1368 | encoder->possible_clones = 0; |
1372 | encoder->possible_clones = 0; |
1369 | 1373 | ||
1370 | radeon_encoder->enc_priv = NULL; |
1374 | radeon_encoder->enc_priv = NULL; |
1371 | 1375 | ||
1372 | radeon_encoder->encoder_id = encoder_id; |
1376 | radeon_encoder->encoder_id = encoder_id; |
1373 | radeon_encoder->devices = supported_device; |
1377 | radeon_encoder->devices = supported_device; |
1374 | radeon_encoder->rmx_type = RMX_OFF; |
1378 | radeon_encoder->rmx_type = RMX_OFF; |
1375 | 1379 | ||
1376 | switch (radeon_encoder->encoder_id) { |
1380 | switch (radeon_encoder->encoder_id) { |
1377 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1381 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1378 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1382 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1379 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1383 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1380 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1384 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1381 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1385 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1382 | radeon_encoder->rmx_type = RMX_FULL; |
1386 | radeon_encoder->rmx_type = RMX_FULL; |
1383 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
1387 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
1384 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
1388 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
1385 | } else { |
1389 | } else { |
1386 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1390 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1387 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
1391 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
1388 | } |
1392 | } |
1389 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1393 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1390 | break; |
1394 | break; |
1391 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1395 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1392 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
1396 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
1393 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1397 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1394 | break; |
1398 | break; |
1395 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1399 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1396 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1400 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1397 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1401 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1398 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
1402 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
1399 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
1403 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
1400 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1404 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1401 | break; |
1405 | break; |
1402 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1406 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1403 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1407 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1404 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1408 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1405 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1409 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1406 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1410 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1407 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1411 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1408 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1412 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1409 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1413 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1410 | radeon_encoder->rmx_type = RMX_FULL; |
1414 | radeon_encoder->rmx_type = RMX_FULL; |
1411 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
1415 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
1412 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
1416 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
1413 | } else { |
1417 | } else { |
1414 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1418 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1415 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
1419 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
1416 | } |
1420 | } |
1417 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1421 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1418 | break; |
1422 | break; |
1419 | } |
1423 | } |
1420 | }><>><>><>><>><>><>><>><>><>><>><>><>><>>>> |
1424 | }><>><>><>><>><>><>><>><>><>><>><>><>><>>>> |