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1 | /* |
1 | /* |
2 | * Copyright 2015 Red Hat Inc. |
2 | * Copyright 2015 Red Hat Inc. |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
12 | * all copies or substantial portions of the Software. |
13 | * |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
21 | * |
22 | * Authors: Dave Airlie |
22 | * Authors: Dave Airlie |
23 | */ |
23 | */ |
24 | #include |
24 | #include |
25 | #include |
25 | #include |
26 | #include "radeon.h" |
26 | #include "radeon.h" |
27 | #include "nid.h" |
27 | #include "nid.h" |
28 | 28 | ||
29 | #define AUX_RX_ERROR_FLAGS (AUX_SW_RX_OVERFLOW | \ |
29 | #define AUX_RX_ERROR_FLAGS (AUX_SW_RX_OVERFLOW | \ |
30 | AUX_SW_RX_HPD_DISCON | \ |
30 | AUX_SW_RX_HPD_DISCON | \ |
31 | AUX_SW_RX_PARTIAL_BYTE | \ |
31 | AUX_SW_RX_PARTIAL_BYTE | \ |
32 | AUX_SW_NON_AUX_MODE | \ |
32 | AUX_SW_NON_AUX_MODE | \ |
33 | AUX_SW_RX_SYNC_INVALID_L | \ |
33 | AUX_SW_RX_SYNC_INVALID_L | \ |
34 | AUX_SW_RX_SYNC_INVALID_H | \ |
34 | AUX_SW_RX_SYNC_INVALID_H | \ |
35 | AUX_SW_RX_INVALID_START | \ |
35 | AUX_SW_RX_INVALID_START | \ |
36 | AUX_SW_RX_RECV_NO_DET | \ |
36 | AUX_SW_RX_RECV_NO_DET | \ |
37 | AUX_SW_RX_RECV_INVALID_H | \ |
37 | AUX_SW_RX_RECV_INVALID_H | \ |
38 | AUX_SW_RX_RECV_INVALID_V) |
38 | AUX_SW_RX_RECV_INVALID_V) |
39 | 39 | ||
40 | #define AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f) |
40 | #define AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f) |
41 | 41 | ||
42 | #define BARE_ADDRESS_SIZE 3 |
42 | #define BARE_ADDRESS_SIZE 3 |
43 | 43 | ||
44 | static const u32 aux_offset[] = |
44 | static const u32 aux_offset[] = |
45 | { |
45 | { |
46 | 0x6200 - 0x6200, |
46 | 0x6200 - 0x6200, |
47 | 0x6250 - 0x6200, |
47 | 0x6250 - 0x6200, |
48 | 0x62a0 - 0x6200, |
48 | 0x62a0 - 0x6200, |
49 | 0x6300 - 0x6200, |
49 | 0x6300 - 0x6200, |
50 | 0x6350 - 0x6200, |
50 | 0x6350 - 0x6200, |
51 | 0x63a0 - 0x6200, |
51 | 0x63a0 - 0x6200, |
52 | }; |
52 | }; |
53 | 53 | ||
54 | ssize_t |
54 | ssize_t |
55 | radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
55 | radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
56 | { |
56 | { |
57 | struct radeon_i2c_chan *chan = |
57 | struct radeon_i2c_chan *chan = |
58 | container_of(aux, struct radeon_i2c_chan, aux); |
58 | container_of(aux, struct radeon_i2c_chan, aux); |
59 | struct drm_device *dev = chan->dev; |
59 | struct drm_device *dev = chan->dev; |
60 | struct radeon_device *rdev = dev->dev_private; |
60 | struct radeon_device *rdev = dev->dev_private; |
61 | int ret = 0, i; |
61 | int ret = 0, i; |
62 | uint32_t tmp, ack = 0; |
62 | uint32_t tmp, ack = 0; |
63 | int instance = chan->rec.i2c_id & 0xf; |
63 | int instance = chan->rec.i2c_id & 0xf; |
64 | u8 byte; |
64 | u8 byte; |
65 | u8 *buf = msg->buffer; |
65 | u8 *buf = msg->buffer; |
66 | int retry_count = 0; |
66 | int retry_count = 0; |
67 | int bytes; |
67 | int bytes; |
68 | int msize; |
68 | int msize; |
69 | bool is_write = false; |
69 | bool is_write = false; |
70 | 70 | ||
71 | if (WARN_ON(msg->size > 16)) |
71 | if (WARN_ON(msg->size > 16)) |
72 | return -E2BIG; |
72 | return -E2BIG; |
73 | 73 | ||
74 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
74 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
75 | case DP_AUX_NATIVE_WRITE: |
75 | case DP_AUX_NATIVE_WRITE: |
76 | case DP_AUX_I2C_WRITE: |
76 | case DP_AUX_I2C_WRITE: |
77 | is_write = true; |
77 | is_write = true; |
78 | break; |
78 | break; |
79 | case DP_AUX_NATIVE_READ: |
79 | case DP_AUX_NATIVE_READ: |
80 | case DP_AUX_I2C_READ: |
80 | case DP_AUX_I2C_READ: |
81 | break; |
81 | break; |
82 | default: |
82 | default: |
83 | return -EINVAL; |
83 | return -EINVAL; |
84 | } |
84 | } |
85 | 85 | ||
86 | /* work out two sizes required */ |
86 | /* work out two sizes required */ |
87 | msize = 0; |
87 | msize = 0; |
88 | bytes = BARE_ADDRESS_SIZE; |
88 | bytes = BARE_ADDRESS_SIZE; |
89 | if (msg->size) { |
89 | if (msg->size) { |
90 | msize = msg->size - 1; |
90 | msize = msg->size - 1; |
91 | bytes++; |
91 | bytes++; |
92 | if (is_write) |
92 | if (is_write) |
93 | bytes += msg->size; |
93 | bytes += msg->size; |
94 | } |
94 | } |
95 | 95 | ||
96 | mutex_lock(&chan->mutex); |
96 | mutex_lock(&chan->mutex); |
97 | 97 | ||
98 | /* switch the pad to aux mode */ |
98 | /* switch the pad to aux mode */ |
99 | tmp = RREG32(chan->rec.mask_clk_reg); |
99 | tmp = RREG32(chan->rec.mask_clk_reg); |
100 | tmp |= (1 << 16); |
100 | tmp |= (1 << 16); |
101 | WREG32(chan->rec.mask_clk_reg, tmp); |
101 | WREG32(chan->rec.mask_clk_reg, tmp); |
102 | 102 | ||
103 | /* setup AUX control register with correct HPD pin */ |
103 | /* setup AUX control register with correct HPD pin */ |
104 | tmp = RREG32(AUX_CONTROL + aux_offset[instance]); |
104 | tmp = RREG32(AUX_CONTROL + aux_offset[instance]); |
105 | 105 | ||
106 | tmp &= AUX_HPD_SEL(0x7); |
106 | tmp &= AUX_HPD_SEL(0x7); |
107 | tmp |= AUX_HPD_SEL(chan->rec.hpd); |
107 | tmp |= AUX_HPD_SEL(chan->rec.hpd); |
108 | tmp |= AUX_EN | AUX_LS_READ_EN; |
108 | tmp |= AUX_EN | AUX_LS_READ_EN | AUX_HPD_DISCON(0x1); |
109 | 109 | ||
110 | WREG32(AUX_CONTROL + aux_offset[instance], tmp); |
110 | WREG32(AUX_CONTROL + aux_offset[instance], tmp); |
111 | 111 | ||
112 | /* atombios appears to write this twice lets copy it */ |
112 | /* atombios appears to write this twice lets copy it */ |
113 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
113 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
114 | AUX_SW_WR_BYTES(bytes)); |
114 | AUX_SW_WR_BYTES(bytes)); |
115 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
115 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
116 | AUX_SW_WR_BYTES(bytes)); |
116 | AUX_SW_WR_BYTES(bytes)); |
117 | 117 | ||
118 | /* write the data header into the registers */ |
118 | /* write the data header into the registers */ |
119 | /* request, address, msg size */ |
119 | /* request, address, msg size */ |
120 | byte = (msg->request << 4) | ((msg->address >> 16) & 0xf); |
120 | byte = (msg->request << 4) | ((msg->address >> 16) & 0xf); |
121 | WREG32(AUX_SW_DATA + aux_offset[instance], |
121 | WREG32(AUX_SW_DATA + aux_offset[instance], |
122 | AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE); |
122 | AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE); |
123 | 123 | ||
124 | byte = (msg->address >> 8) & 0xff; |
124 | byte = (msg->address >> 8) & 0xff; |
125 | WREG32(AUX_SW_DATA + aux_offset[instance], |
125 | WREG32(AUX_SW_DATA + aux_offset[instance], |
126 | AUX_SW_DATA_MASK(byte)); |
126 | AUX_SW_DATA_MASK(byte)); |
127 | 127 | ||
128 | byte = msg->address & 0xff; |
128 | byte = msg->address & 0xff; |
129 | WREG32(AUX_SW_DATA + aux_offset[instance], |
129 | WREG32(AUX_SW_DATA + aux_offset[instance], |
130 | AUX_SW_DATA_MASK(byte)); |
130 | AUX_SW_DATA_MASK(byte)); |
131 | 131 | ||
132 | byte = msize; |
132 | byte = msize; |
133 | WREG32(AUX_SW_DATA + aux_offset[instance], |
133 | WREG32(AUX_SW_DATA + aux_offset[instance], |
134 | AUX_SW_DATA_MASK(byte)); |
134 | AUX_SW_DATA_MASK(byte)); |
135 | 135 | ||
136 | /* if we are writing - write the msg buffer */ |
136 | /* if we are writing - write the msg buffer */ |
137 | if (is_write) { |
137 | if (is_write) { |
138 | for (i = 0; i < msg->size; i++) { |
138 | for (i = 0; i < msg->size; i++) { |
139 | WREG32(AUX_SW_DATA + aux_offset[instance], |
139 | WREG32(AUX_SW_DATA + aux_offset[instance], |
140 | AUX_SW_DATA_MASK(buf[i])); |
140 | AUX_SW_DATA_MASK(buf[i])); |
141 | } |
141 | } |
142 | } |
142 | } |
143 | 143 | ||
144 | /* clear the ACK */ |
144 | /* clear the ACK */ |
145 | WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
145 | WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
146 | 146 | ||
147 | /* write the size and GO bits */ |
147 | /* write the size and GO bits */ |
148 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
148 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
149 | AUX_SW_WR_BYTES(bytes) | AUX_SW_GO); |
149 | AUX_SW_WR_BYTES(bytes) | AUX_SW_GO); |
150 | 150 | ||
151 | /* poll the status registers - TODO irq support */ |
151 | /* poll the status registers - TODO irq support */ |
152 | do { |
152 | do { |
153 | tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); |
153 | tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); |
154 | if (tmp & AUX_SW_DONE) { |
154 | if (tmp & AUX_SW_DONE) { |
155 | break; |
155 | break; |
156 | } |
156 | } |
157 | usleep_range(100, 200); |
157 | usleep_range(100, 200); |
158 | } while (retry_count++ < 1000); |
158 | } while (retry_count++ < 1000); |
159 | 159 | ||
160 | if (retry_count >= 1000) { |
160 | if (retry_count >= 1000) { |
161 | DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp); |
161 | DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp); |
162 | ret = -EIO; |
162 | ret = -EIO; |
163 | goto done; |
163 | goto done; |
164 | } |
164 | } |
165 | 165 | ||
166 | if (tmp & AUX_SW_RX_TIMEOUT) { |
166 | if (tmp & AUX_SW_RX_TIMEOUT) { |
167 | DRM_DEBUG_KMS("dp_aux_ch timed out\n"); |
167 | DRM_DEBUG_KMS("dp_aux_ch timed out\n"); |
168 | ret = -ETIMEDOUT; |
168 | ret = -ETIMEDOUT; |
169 | goto done; |
169 | goto done; |
170 | } |
170 | } |
171 | if (tmp & AUX_RX_ERROR_FLAGS) { |
171 | if (tmp & AUX_RX_ERROR_FLAGS) { |
172 | DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp); |
172 | DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp); |
173 | ret = -EIO; |
173 | ret = -EIO; |
174 | goto done; |
174 | goto done; |
175 | } |
175 | } |
176 | 176 | ||
177 | bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp); |
177 | bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp); |
178 | if (bytes) { |
178 | if (bytes) { |
179 | WREG32(AUX_SW_DATA + aux_offset[instance], |
179 | WREG32(AUX_SW_DATA + aux_offset[instance], |
180 | AUX_SW_DATA_RW | AUX_SW_AUTOINCREMENT_DISABLE); |
180 | AUX_SW_DATA_RW | AUX_SW_AUTOINCREMENT_DISABLE); |
181 | 181 | ||
182 | tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
182 | tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
183 | ack = (tmp >> 8) & 0xff; |
183 | ack = (tmp >> 8) & 0xff; |
184 | 184 | ||
185 | for (i = 0; i < bytes - 1; i++) { |
185 | for (i = 0; i < bytes - 1; i++) { |
186 | tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
186 | tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
187 | if (buf) |
187 | if (buf) |
188 | buf[i] = (tmp >> 8) & 0xff; |
188 | buf[i] = (tmp >> 8) & 0xff; |
189 | } |
189 | } |
190 | if (buf) |
190 | if (buf) |
191 | ret = bytes - 1; |
191 | ret = bytes - 1; |
192 | } |
192 | } |
193 | 193 | ||
194 | WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
194 | WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
195 | 195 | ||
196 | if (is_write) |
196 | if (is_write) |
197 | ret = msg->size; |
197 | ret = msg->size; |
198 | done: |
198 | done: |
199 | mutex_unlock(&chan->mutex); |
199 | mutex_unlock(&chan->mutex); |
200 | 200 | ||
201 | if (ret >= 0) |
201 | if (ret >= 0) |
202 | msg->reply = ack >> 4; |
202 | msg->reply = ack >> 4; |
203 | return ret; |
203 | return ret; |
204 | }>>>><>><> |
204 | }>>>><>><> |