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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include "drmP.h" |
26 | #include "drmP.h" |
27 | #include "radeon_drm.h" |
27 | #include "radeon_drm.h" |
28 | #include "radeon.h" |
28 | #include "radeon.h" |
29 | 29 | ||
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | //#include |
31 | #include |
32 | 32 | ||
33 | #include "drm_crtc_helper.h" |
33 | #include "drm_crtc_helper.h" |
34 | #include "drm_edid.h" |
34 | #include "drm_edid.h" |
35 | 35 | ||
36 | static int radeon_ddc_dump(struct drm_connector *connector); |
36 | static int radeon_ddc_dump(struct drm_connector *connector); |
37 | 37 | ||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
39 | { |
39 | { |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
41 | struct drm_device *dev = crtc->dev; |
41 | struct drm_device *dev = crtc->dev; |
42 | struct radeon_device *rdev = dev->dev_private; |
42 | struct radeon_device *rdev = dev->dev_private; |
43 | int i; |
43 | int i; |
44 | 44 | ||
45 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); |
45 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
47 | 47 | ||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
51 | 51 | ||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
55 | 55 | ||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
59 | 59 | ||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
61 | for (i = 0; i < 256; i++) { |
61 | for (i = 0; i < 256; i++) { |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, |
63 | (radeon_crtc->lut_r[i] << 20) | |
63 | (radeon_crtc->lut_r[i] << 20) | |
64 | (radeon_crtc->lut_g[i] << 10) | |
64 | (radeon_crtc->lut_g[i] << 10) | |
65 | (radeon_crtc->lut_b[i] << 0)); |
65 | (radeon_crtc->lut_b[i] << 0)); |
66 | } |
66 | } |
67 | 67 | ||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
69 | } |
69 | } |
70 | 70 | ||
71 | static void evergreen_crtc_load_lut(struct drm_crtc *crtc) |
71 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
72 | { |
72 | { |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
74 | struct drm_device *dev = crtc->dev; |
74 | struct drm_device *dev = crtc->dev; |
75 | struct radeon_device *rdev = dev->dev_private; |
75 | struct radeon_device *rdev = dev->dev_private; |
76 | int i; |
76 | int i; |
77 | 77 | ||
78 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); |
78 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
80 | 80 | ||
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
84 | 84 | ||
85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
88 | 88 | ||
89 | WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id); |
89 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007); |
90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
91 | 91 | ||
92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0); |
92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
93 | for (i = 0; i < 256; i++) { |
93 | for (i = 0; i < 256; i++) { |
94 | WREG32(EVERGREEN_DC_LUT_30_COLOR, |
94 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
95 | (radeon_crtc->lut_r[i] << 20) | |
95 | (radeon_crtc->lut_r[i] << 20) | |
96 | (radeon_crtc->lut_g[i] << 10) | |
96 | (radeon_crtc->lut_g[i] << 10) | |
97 | (radeon_crtc->lut_b[i] << 0)); |
97 | (radeon_crtc->lut_b[i] << 0)); |
98 | } |
98 | } |
99 | } |
99 | } |
- | 100 | ||
- | 101 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
|
- | 102 | { |
|
- | 103 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
|
- | 104 | struct drm_device *dev = crtc->dev; |
|
- | 105 | struct radeon_device *rdev = dev->dev_private; |
|
- | 106 | int i; |
|
- | 107 | ||
- | 108 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
|
- | 109 | ||
- | 110 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
|
- | 111 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
|
- | 112 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
|
- | 113 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
|
- | 114 | NI_GRPH_PRESCALE_BYPASS); |
|
- | 115 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
|
- | 116 | NI_OVL_PRESCALE_BYPASS); |
|
- | 117 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
|
- | 118 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
|
- | 119 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
|
- | 120 | ||
- | 121 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
|
- | 122 | ||
- | 123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
|
- | 124 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
|
- | 125 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
|
- | 126 | ||
- | 127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
|
- | 128 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
|
- | 129 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
|
- | 130 | ||
- | 131 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
|
- | 132 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
|
- | 133 | ||
- | 134 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
|
- | 135 | for (i = 0; i < 256; i++) { |
|
- | 136 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
|
- | 137 | (radeon_crtc->lut_r[i] << 20) | |
|
- | 138 | (radeon_crtc->lut_g[i] << 10) | |
|
- | 139 | (radeon_crtc->lut_b[i] << 0)); |
|
- | 140 | } |
|
- | 141 | ||
- | 142 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
|
- | 143 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
|
- | 144 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
|
- | 145 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
|
- | 146 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
|
- | 147 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
|
- | 148 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
|
- | 149 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
|
- | 150 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
|
- | 151 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
|
- | 152 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
|
- | 153 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
|
- | 154 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | |
|
- | 155 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
|
- | 156 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
|
- | 157 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
|
- | 158 | ||
- | 159 | } |
|
100 | 160 | ||
101 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
161 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
102 | { |
162 | { |
103 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
163 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
104 | struct drm_device *dev = crtc->dev; |
164 | struct drm_device *dev = crtc->dev; |
105 | struct radeon_device *rdev = dev->dev_private; |
165 | struct radeon_device *rdev = dev->dev_private; |
106 | int i; |
166 | int i; |
107 | uint32_t dac2_cntl; |
167 | uint32_t dac2_cntl; |
108 | 168 | ||
109 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
169 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
110 | if (radeon_crtc->crtc_id == 0) |
170 | if (radeon_crtc->crtc_id == 0) |
111 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
171 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
112 | else |
172 | else |
113 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
173 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
114 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
174 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
115 | 175 | ||
116 | WREG8(RADEON_PALETTE_INDEX, 0); |
176 | WREG8(RADEON_PALETTE_INDEX, 0); |
117 | for (i = 0; i < 256; i++) { |
177 | for (i = 0; i < 256; i++) { |
118 | WREG32(RADEON_PALETTE_30_DATA, |
178 | WREG32(RADEON_PALETTE_30_DATA, |
119 | (radeon_crtc->lut_r[i] << 20) | |
179 | (radeon_crtc->lut_r[i] << 20) | |
120 | (radeon_crtc->lut_g[i] << 10) | |
180 | (radeon_crtc->lut_g[i] << 10) | |
121 | (radeon_crtc->lut_b[i] << 0)); |
181 | (radeon_crtc->lut_b[i] << 0)); |
122 | } |
182 | } |
123 | } |
183 | } |
124 | 184 | ||
125 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
185 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
126 | { |
186 | { |
127 | struct drm_device *dev = crtc->dev; |
187 | struct drm_device *dev = crtc->dev; |
128 | struct radeon_device *rdev = dev->dev_private; |
188 | struct radeon_device *rdev = dev->dev_private; |
129 | 189 | ||
130 | if (!crtc->enabled) |
190 | if (!crtc->enabled) |
131 | return; |
191 | return; |
132 | 192 | ||
133 | if (ASIC_IS_DCE4(rdev)) |
193 | if (ASIC_IS_DCE5(rdev)) |
- | 194 | dce5_crtc_load_lut(crtc); |
|
- | 195 | else if (ASIC_IS_DCE4(rdev)) |
|
134 | evergreen_crtc_load_lut(crtc); |
196 | dce4_crtc_load_lut(crtc); |
135 | else if (ASIC_IS_AVIVO(rdev)) |
197 | else if (ASIC_IS_AVIVO(rdev)) |
136 | avivo_crtc_load_lut(crtc); |
198 | avivo_crtc_load_lut(crtc); |
137 | else |
199 | else |
138 | legacy_crtc_load_lut(crtc); |
200 | legacy_crtc_load_lut(crtc); |
139 | } |
201 | } |
140 | 202 | ||
141 | /** Sets the color ramps on behalf of fbcon */ |
203 | /** Sets the color ramps on behalf of fbcon */ |
142 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
204 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
143 | u16 blue, int regno) |
205 | u16 blue, int regno) |
144 | { |
206 | { |
145 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
207 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
146 | 208 | ||
147 | radeon_crtc->lut_r[regno] = red >> 6; |
209 | radeon_crtc->lut_r[regno] = red >> 6; |
148 | radeon_crtc->lut_g[regno] = green >> 6; |
210 | radeon_crtc->lut_g[regno] = green >> 6; |
149 | radeon_crtc->lut_b[regno] = blue >> 6; |
211 | radeon_crtc->lut_b[regno] = blue >> 6; |
150 | } |
212 | } |
151 | 213 | ||
152 | /** Gets the color ramps on behalf of fbcon */ |
214 | /** Gets the color ramps on behalf of fbcon */ |
153 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
215 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
154 | u16 *blue, int regno) |
216 | u16 *blue, int regno) |
155 | { |
217 | { |
156 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
218 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
157 | 219 | ||
158 | *red = radeon_crtc->lut_r[regno] << 6; |
220 | *red = radeon_crtc->lut_r[regno] << 6; |
159 | *green = radeon_crtc->lut_g[regno] << 6; |
221 | *green = radeon_crtc->lut_g[regno] << 6; |
160 | *blue = radeon_crtc->lut_b[regno] << 6; |
222 | *blue = radeon_crtc->lut_b[regno] << 6; |
161 | } |
223 | } |
162 | 224 | ||
163 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
225 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
164 | u16 *blue, uint32_t size) |
226 | u16 *blue, uint32_t start, uint32_t size) |
165 | { |
227 | { |
166 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
228 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
167 | int i; |
- | |
168 | - | ||
169 | if (size != 256) { |
229 | int end = (start + size > 256) ? 256 : start + size, i; |
170 | return; |
- | |
171 | } |
- | |
172 | 230 | ||
173 | /* userspace palettes are always correct as is */ |
231 | /* userspace palettes are always correct as is */ |
174 | for (i = 0; i < 256; i++) { |
232 | for (i = start; i < end; i++) { |
175 | radeon_crtc->lut_r[i] = red[i] >> 6; |
233 | radeon_crtc->lut_r[i] = red[i] >> 6; |
176 | radeon_crtc->lut_g[i] = green[i] >> 6; |
234 | radeon_crtc->lut_g[i] = green[i] >> 6; |
177 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
235 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
178 | } |
236 | } |
179 | radeon_crtc_load_lut(crtc); |
237 | radeon_crtc_load_lut(crtc); |
180 | } |
238 | } |
181 | 239 | ||
182 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
240 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
183 | { |
241 | { |
184 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
242 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
185 | 243 | ||
186 | drm_crtc_cleanup(crtc); |
244 | drm_crtc_cleanup(crtc); |
187 | kfree(radeon_crtc); |
245 | kfree(radeon_crtc); |
188 | } |
246 | } |
189 | 247 | ||
190 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
248 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
191 | .cursor_set = NULL, |
249 | .cursor_set = NULL, |
192 | .cursor_move = NULL, |
250 | .cursor_move = NULL, |
193 | .gamma_set = radeon_crtc_gamma_set, |
251 | .gamma_set = radeon_crtc_gamma_set, |
194 | .set_config = drm_crtc_helper_set_config, |
252 | .set_config = drm_crtc_helper_set_config, |
195 | .destroy = radeon_crtc_destroy, |
253 | .destroy = radeon_crtc_destroy, |
- | 254 | .page_flip = NULL, |
|
196 | }; |
255 | }; |
197 | 256 | ||
198 | static void radeon_crtc_init(struct drm_device *dev, int index) |
257 | static void radeon_crtc_init(struct drm_device *dev, int index) |
199 | { |
258 | { |
200 | struct radeon_device *rdev = dev->dev_private; |
259 | struct radeon_device *rdev = dev->dev_private; |
201 | struct radeon_crtc *radeon_crtc; |
260 | struct radeon_crtc *radeon_crtc; |
202 | int i; |
261 | int i; |
203 | 262 | ||
204 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
263 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
205 | if (radeon_crtc == NULL) |
264 | if (radeon_crtc == NULL) |
206 | return; |
265 | return; |
207 | 266 | ||
208 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
267 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
209 | 268 | ||
210 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
269 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
211 | radeon_crtc->crtc_id = index; |
270 | radeon_crtc->crtc_id = index; |
212 | rdev->mode_info.crtcs[index] = radeon_crtc; |
271 | rdev->mode_info.crtcs[index] = radeon_crtc; |
213 | 272 | ||
214 | #if 0 |
273 | #if 0 |
215 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
274 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
216 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
275 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
217 | radeon_crtc->mode_set.num_connectors = 0; |
276 | radeon_crtc->mode_set.num_connectors = 0; |
218 | #endif |
277 | #endif |
219 | 278 | ||
220 | for (i = 0; i < 256; i++) { |
279 | for (i = 0; i < 256; i++) { |
221 | radeon_crtc->lut_r[i] = i << 2; |
280 | radeon_crtc->lut_r[i] = i << 2; |
222 | radeon_crtc->lut_g[i] = i << 2; |
281 | radeon_crtc->lut_g[i] = i << 2; |
223 | radeon_crtc->lut_b[i] = i << 2; |
282 | radeon_crtc->lut_b[i] = i << 2; |
224 | } |
283 | } |
225 | 284 | ||
226 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
285 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
227 | radeon_atombios_init_crtc(dev, radeon_crtc); |
286 | radeon_atombios_init_crtc(dev, radeon_crtc); |
228 | else |
287 | else |
229 | radeon_legacy_init_crtc(dev, radeon_crtc); |
288 | radeon_legacy_init_crtc(dev, radeon_crtc); |
230 | } |
289 | } |
231 | 290 | ||
232 | static const char *encoder_names[34] = { |
291 | static const char *encoder_names[36] = { |
233 | "NONE", |
292 | "NONE", |
234 | "INTERNAL_LVDS", |
293 | "INTERNAL_LVDS", |
235 | "INTERNAL_TMDS1", |
294 | "INTERNAL_TMDS1", |
236 | "INTERNAL_TMDS2", |
295 | "INTERNAL_TMDS2", |
237 | "INTERNAL_DAC1", |
296 | "INTERNAL_DAC1", |
238 | "INTERNAL_DAC2", |
297 | "INTERNAL_DAC2", |
239 | "INTERNAL_SDVOA", |
298 | "INTERNAL_SDVOA", |
240 | "INTERNAL_SDVOB", |
299 | "INTERNAL_SDVOB", |
241 | "SI170B", |
300 | "SI170B", |
242 | "CH7303", |
301 | "CH7303", |
243 | "CH7301", |
302 | "CH7301", |
244 | "INTERNAL_DVO1", |
303 | "INTERNAL_DVO1", |
245 | "EXTERNAL_SDVOA", |
304 | "EXTERNAL_SDVOA", |
246 | "EXTERNAL_SDVOB", |
305 | "EXTERNAL_SDVOB", |
247 | "TITFP513", |
306 | "TITFP513", |
248 | "INTERNAL_LVTM1", |
307 | "INTERNAL_LVTM1", |
249 | "VT1623", |
308 | "VT1623", |
250 | "HDMI_SI1930", |
309 | "HDMI_SI1930", |
251 | "HDMI_INTERNAL", |
310 | "HDMI_INTERNAL", |
252 | "INTERNAL_KLDSCP_TMDS1", |
311 | "INTERNAL_KLDSCP_TMDS1", |
253 | "INTERNAL_KLDSCP_DVO1", |
312 | "INTERNAL_KLDSCP_DVO1", |
254 | "INTERNAL_KLDSCP_DAC1", |
313 | "INTERNAL_KLDSCP_DAC1", |
255 | "INTERNAL_KLDSCP_DAC2", |
314 | "INTERNAL_KLDSCP_DAC2", |
256 | "SI178", |
315 | "SI178", |
257 | "MVPU_FPGA", |
316 | "MVPU_FPGA", |
258 | "INTERNAL_DDI", |
317 | "INTERNAL_DDI", |
259 | "VT1625", |
318 | "VT1625", |
260 | "HDMI_SI1932", |
319 | "HDMI_SI1932", |
261 | "DP_AN9801", |
320 | "DP_AN9801", |
262 | "DP_DP501", |
321 | "DP_DP501", |
263 | "INTERNAL_UNIPHY", |
322 | "INTERNAL_UNIPHY", |
264 | "INTERNAL_KLDSCP_LVTMA", |
323 | "INTERNAL_KLDSCP_LVTMA", |
265 | "INTERNAL_UNIPHY1", |
324 | "INTERNAL_UNIPHY1", |
266 | "INTERNAL_UNIPHY2", |
325 | "INTERNAL_UNIPHY2", |
- | 326 | "NUTMEG", |
|
- | 327 | "TRAVIS", |
|
267 | }; |
328 | }; |
268 | 329 | ||
269 | static const char *connector_names[15] = { |
330 | static const char *connector_names[15] = { |
270 | "Unknown", |
331 | "Unknown", |
271 | "VGA", |
332 | "VGA", |
272 | "DVI-I", |
333 | "DVI-I", |
273 | "DVI-D", |
334 | "DVI-D", |
274 | "DVI-A", |
335 | "DVI-A", |
275 | "Composite", |
336 | "Composite", |
276 | "S-video", |
337 | "S-video", |
277 | "LVDS", |
338 | "LVDS", |
278 | "Component", |
339 | "Component", |
279 | "DIN", |
340 | "DIN", |
280 | "DisplayPort", |
341 | "DisplayPort", |
281 | "HDMI-A", |
342 | "HDMI-A", |
282 | "HDMI-B", |
343 | "HDMI-B", |
283 | "TV", |
344 | "TV", |
284 | "eDP", |
345 | "eDP", |
285 | }; |
346 | }; |
286 | 347 | ||
287 | static const char *hpd_names[7] = { |
- | |
288 | "NONE", |
348 | static const char *hpd_names[6] = { |
289 | "HPD1", |
349 | "HPD1", |
290 | "HPD2", |
350 | "HPD2", |
291 | "HPD3", |
351 | "HPD3", |
292 | "HPD4", |
352 | "HPD4", |
293 | "HPD5", |
353 | "HPD5", |
294 | "HPD6", |
354 | "HPD6", |
295 | }; |
355 | }; |
296 | 356 | ||
297 | static void radeon_print_display_setup(struct drm_device *dev) |
357 | static void radeon_print_display_setup(struct drm_device *dev) |
298 | { |
358 | { |
299 | struct drm_connector *connector; |
359 | struct drm_connector *connector; |
300 | struct radeon_connector *radeon_connector; |
360 | struct radeon_connector *radeon_connector; |
301 | struct drm_encoder *encoder; |
361 | struct drm_encoder *encoder; |
302 | struct radeon_encoder *radeon_encoder; |
362 | struct radeon_encoder *radeon_encoder; |
303 | uint32_t devices; |
363 | uint32_t devices; |
304 | int i = 0; |
364 | int i = 0; |
305 | 365 | ||
306 | DRM_INFO("Radeon Display Connectors\n"); |
366 | DRM_INFO("Radeon Display Connectors\n"); |
307 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
367 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
308 | radeon_connector = to_radeon_connector(connector); |
368 | radeon_connector = to_radeon_connector(connector); |
309 | DRM_INFO("Connector %d:\n", i); |
369 | DRM_INFO("Connector %d:\n", i); |
310 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
370 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
311 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
371 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
312 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
372 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
313 | if (radeon_connector->ddc_bus) { |
373 | if (radeon_connector->ddc_bus) { |
314 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
374 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
315 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
375 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
316 | radeon_connector->ddc_bus->rec.mask_data_reg, |
376 | radeon_connector->ddc_bus->rec.mask_data_reg, |
317 | radeon_connector->ddc_bus->rec.a_clk_reg, |
377 | radeon_connector->ddc_bus->rec.a_clk_reg, |
318 | radeon_connector->ddc_bus->rec.a_data_reg, |
378 | radeon_connector->ddc_bus->rec.a_data_reg, |
319 | radeon_connector->ddc_bus->rec.en_clk_reg, |
379 | radeon_connector->ddc_bus->rec.en_clk_reg, |
320 | radeon_connector->ddc_bus->rec.en_data_reg, |
380 | radeon_connector->ddc_bus->rec.en_data_reg, |
321 | radeon_connector->ddc_bus->rec.y_clk_reg, |
381 | radeon_connector->ddc_bus->rec.y_clk_reg, |
322 | radeon_connector->ddc_bus->rec.y_data_reg); |
382 | radeon_connector->ddc_bus->rec.y_data_reg); |
- | 383 | if (radeon_connector->router.ddc_valid) |
|
- | 384 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
|
- | 385 | radeon_connector->router.ddc_mux_control_pin, |
|
- | 386 | radeon_connector->router.ddc_mux_state); |
|
- | 387 | if (radeon_connector->router.cd_valid) |
|
- | 388 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
|
- | 389 | radeon_connector->router.cd_mux_control_pin, |
|
- | 390 | radeon_connector->router.cd_mux_state); |
|
323 | } else { |
391 | } else { |
324 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
392 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
325 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
393 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
326 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
394 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
327 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
395 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
328 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
396 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
329 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
397 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
330 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
398 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
331 | } |
399 | } |
332 | DRM_INFO(" Encoders:\n"); |
400 | DRM_INFO(" Encoders:\n"); |
333 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
401 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
334 | radeon_encoder = to_radeon_encoder(encoder); |
402 | radeon_encoder = to_radeon_encoder(encoder); |
335 | devices = radeon_encoder->devices & radeon_connector->devices; |
403 | devices = radeon_encoder->devices & radeon_connector->devices; |
336 | if (devices) { |
404 | if (devices) { |
337 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
405 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
338 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
406 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
339 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
407 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
340 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
408 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
341 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
409 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
342 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
410 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
343 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
411 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
344 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
412 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
345 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
413 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
346 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
414 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
347 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
415 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
348 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
416 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
349 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
417 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
350 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
418 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
351 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
419 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
352 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
420 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
- | 421 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
|
- | 422 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
|
353 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
423 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
354 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
424 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
355 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
425 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
356 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
426 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
357 | } |
427 | } |
358 | } |
428 | } |
359 | i++; |
429 | i++; |
360 | } |
430 | } |
361 | } |
431 | } |
362 | 432 | ||
363 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
433 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
364 | { |
434 | { |
365 | struct radeon_device *rdev = dev->dev_private; |
435 | struct radeon_device *rdev = dev->dev_private; |
366 | struct drm_connector *drm_connector; |
436 | struct drm_connector *drm_connector; |
367 | bool ret = false; |
437 | bool ret = false; |
368 | 438 | ||
369 | if (rdev->bios) { |
439 | if (rdev->bios) { |
370 | if (rdev->is_atom_bios) { |
440 | if (rdev->is_atom_bios) { |
371 | if (rdev->family >= CHIP_R600) |
- | |
372 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
- | |
373 | else |
- | |
374 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
441 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
- | 442 | if (ret == false) |
|
- | 443 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
|
375 | } else { |
444 | } else { |
376 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
445 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
377 | if (ret == false) |
446 | if (ret == false) |
378 | ret = radeon_get_legacy_connector_info_from_table(dev); |
447 | ret = radeon_get_legacy_connector_info_from_table(dev); |
379 | } |
448 | } |
380 | } else { |
449 | } else { |
381 | if (!ASIC_IS_AVIVO(rdev)) |
450 | if (!ASIC_IS_AVIVO(rdev)) |
382 | ret = radeon_get_legacy_connector_info_from_table(dev); |
451 | ret = radeon_get_legacy_connector_info_from_table(dev); |
383 | } |
452 | } |
384 | if (ret) { |
453 | if (ret) { |
385 | radeon_setup_encoder_clones(dev); |
454 | radeon_setup_encoder_clones(dev); |
386 | radeon_print_display_setup(dev); |
455 | radeon_print_display_setup(dev); |
- | 456 | ||
387 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
457 | // list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
388 | radeon_ddc_dump(drm_connector); |
458 | // radeon_ddc_dump(drm_connector); |
389 | } |
459 | } |
390 | 460 | ||
391 | return ret; |
461 | return ret; |
392 | } |
462 | } |
393 | 463 | ||
394 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
464 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
395 | { |
465 | { |
396 | struct drm_device *dev = radeon_connector->base.dev; |
466 | struct drm_device *dev = radeon_connector->base.dev; |
397 | struct radeon_device *rdev = dev->dev_private; |
467 | struct radeon_device *rdev = dev->dev_private; |
398 | int ret = 0; |
468 | int ret = 0; |
- | 469 | ||
- | 470 | /* on hw with routers, select right port */ |
|
- | 471 | if (radeon_connector->router.ddc_valid) |
|
- | 472 | radeon_router_select_ddc_port(radeon_connector); |
|
399 | 473 | ||
400 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
474 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
401 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { |
475 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { |
402 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
476 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
403 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
477 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
404 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
478 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
405 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
479 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
406 | } |
480 | } |
407 | if (!radeon_connector->ddc_bus) |
481 | if (!radeon_connector->ddc_bus) |
408 | return -1; |
482 | return -1; |
409 | if (!radeon_connector->edid) { |
483 | if (!radeon_connector->edid) { |
410 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
484 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
411 | } |
485 | } |
- | 486 | ||
- | 487 | if (!radeon_connector->edid) { |
|
- | 488 | if (rdev->is_atom_bios) { |
|
- | 489 | /* some laptops provide a hardcoded edid in rom for LCDs */ |
|
- | 490 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || |
|
- | 491 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) |
|
- | 492 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
|
- | 493 | } else |
|
412 | /* some servers provide a hardcoded edid in rom for KVMs */ |
494 | /* some servers provide a hardcoded edid in rom for KVMs */ |
413 | if (!radeon_connector->edid) |
- | |
414 | radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev); |
495 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
- | 496 | } |
|
415 | if (radeon_connector->edid) { |
497 | if (radeon_connector->edid) { |
416 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
498 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
417 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
499 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
418 | return ret; |
500 | return ret; |
419 | } |
501 | } |
420 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
502 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
421 | return 0; |
503 | return 0; |
422 | } |
504 | } |
423 | 505 | ||
424 | static int radeon_ddc_dump(struct drm_connector *connector) |
506 | static int radeon_ddc_dump(struct drm_connector *connector) |
425 | { |
507 | { |
426 | struct edid *edid; |
508 | struct edid *edid; |
427 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
509 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
428 | int ret = 0; |
510 | int ret = 0; |
- | 511 | ||
- | 512 | /* on hw with routers, select right port */ |
|
- | 513 | if (radeon_connector->router.ddc_valid) |
|
- | 514 | radeon_router_select_ddc_port(radeon_connector); |
|
429 | 515 | ||
430 | if (!radeon_connector->ddc_bus) |
516 | if (!radeon_connector->ddc_bus) |
431 | return -1; |
517 | return -1; |
432 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
518 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
433 | if (edid) { |
519 | if (edid) { |
434 | kfree(edid); |
520 | kfree(edid); |
435 | } |
521 | } |
436 | return ret; |
522 | return ret; |
437 | } |
523 | } |
- | 524 | ||
- | 525 | /* avivo */ |
|
- | 526 | static void avivo_get_fb_div(struct radeon_pll *pll, |
|
- | 527 | u32 target_clock, |
|
- | 528 | u32 post_div, |
|
- | 529 | u32 ref_div, |
|
- | 530 | u32 *fb_div, |
|
- | 531 | u32 *frac_fb_div) |
|
- | 532 | { |
|
- | 533 | u32 tmp = post_div * ref_div; |
|
- | 534 | ||
- | 535 | tmp *= target_clock; |
|
- | 536 | *fb_div = tmp / pll->reference_freq; |
|
- | 537 | *frac_fb_div = tmp % pll->reference_freq; |
|
- | 538 | ||
- | 539 | if (*fb_div > pll->max_feedback_div) |
|
- | 540 | *fb_div = pll->max_feedback_div; |
|
- | 541 | else if (*fb_div < pll->min_feedback_div) |
|
- | 542 | *fb_div = pll->min_feedback_div; |
|
- | 543 | } |
|
- | 544 | ||
- | 545 | static u32 avivo_get_post_div(struct radeon_pll *pll, |
|
- | 546 | u32 target_clock) |
|
- | 547 | { |
|
- | 548 | u32 vco, post_div, tmp; |
|
- | 549 | ||
- | 550 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
|
- | 551 | return pll->post_div; |
|
- | 552 | ||
- | 553 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
|
- | 554 | if (pll->flags & RADEON_PLL_IS_LCD) |
|
- | 555 | vco = pll->lcd_pll_out_min; |
|
- | 556 | else |
|
- | 557 | vco = pll->pll_out_min; |
|
- | 558 | } else { |
|
- | 559 | if (pll->flags & RADEON_PLL_IS_LCD) |
|
- | 560 | vco = pll->lcd_pll_out_max; |
|
- | 561 | else |
|
- | 562 | vco = pll->pll_out_max; |
|
- | 563 | } |
|
- | 564 | ||
- | 565 | post_div = vco / target_clock; |
|
- | 566 | tmp = vco % target_clock; |
|
- | 567 | ||
- | 568 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
|
- | 569 | if (tmp) |
|
- | 570 | post_div++; |
|
- | 571 | } else { |
|
- | 572 | if (!tmp) |
|
- | 573 | post_div--; |
|
- | 574 | } |
|
- | 575 | ||
- | 576 | if (post_div > pll->max_post_div) |
|
- | 577 | post_div = pll->max_post_div; |
|
- | 578 | else if (post_div < pll->min_post_div) |
|
- | 579 | post_div = pll->min_post_div; |
|
- | 580 | ||
- | 581 | return post_div; |
|
- | 582 | } |
|
- | 583 | ||
- | 584 | #define MAX_TOLERANCE 10 |
|
- | 585 | ||
- | 586 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
|
- | 587 | u32 freq, |
|
- | 588 | u32 *dot_clock_p, |
|
- | 589 | u32 *fb_div_p, |
|
- | 590 | u32 *frac_fb_div_p, |
|
- | 591 | u32 *ref_div_p, |
|
- | 592 | u32 *post_div_p) |
|
- | 593 | { |
|
- | 594 | u32 target_clock = freq / 10; |
|
- | 595 | u32 post_div = avivo_get_post_div(pll, target_clock); |
|
- | 596 | u32 ref_div = pll->min_ref_div; |
|
- | 597 | u32 fb_div = 0, frac_fb_div = 0, tmp; |
|
- | 598 | ||
- | 599 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
|
- | 600 | ref_div = pll->reference_div; |
|
- | 601 | ||
- | 602 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
|
- | 603 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); |
|
- | 604 | frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; |
|
- | 605 | if (frac_fb_div >= 5) { |
|
- | 606 | frac_fb_div -= 5; |
|
- | 607 | frac_fb_div = frac_fb_div / 10; |
|
- | 608 | frac_fb_div++; |
|
- | 609 | } |
|
- | 610 | if (frac_fb_div >= 10) { |
|
- | 611 | fb_div++; |
|
- | 612 | frac_fb_div = 0; |
|
- | 613 | } |
|
- | 614 | } else { |
|
- | 615 | while (ref_div <= pll->max_ref_div) { |
|
- | 616 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, |
|
- | 617 | &fb_div, &frac_fb_div); |
|
- | 618 | if (frac_fb_div >= (pll->reference_freq / 2)) |
|
- | 619 | fb_div++; |
|
- | 620 | frac_fb_div = 0; |
|
- | 621 | tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); |
|
- | 622 | tmp = (tmp * 10000) / target_clock; |
|
- | 623 | ||
- | 624 | if (tmp > (10000 + MAX_TOLERANCE)) |
|
- | 625 | ref_div++; |
|
- | 626 | else if (tmp >= (10000 - MAX_TOLERANCE)) |
|
- | 627 | break; |
|
- | 628 | else |
|
- | 629 | ref_div++; |
|
- | 630 | } |
|
- | 631 | } |
|
- | 632 | ||
- | 633 | *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / |
|
- | 634 | (ref_div * post_div * 10); |
|
- | 635 | *fb_div_p = fb_div; |
|
- | 636 | *frac_fb_div_p = frac_fb_div; |
|
- | 637 | *ref_div_p = ref_div; |
|
- | 638 | *post_div_p = post_div; |
|
- | 639 | DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
|
- | 640 | *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); |
|
- | 641 | } |
|
- | 642 | ||
438 | 643 | /* pre-avivo */ |
|
439 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
644 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
440 | { |
645 | { |
441 | uint64_t mod; |
646 | uint64_t mod; |
442 | 647 | ||
443 | n += d / 2; |
648 | n += d / 2; |
444 | 649 | ||
445 | mod = do_div(n, d); |
650 | mod = do_div(n, d); |
446 | return n; |
651 | return n; |
447 | } |
652 | } |
448 | 653 | ||
449 | static void radeon_compute_pll_legacy(struct radeon_pll *pll, |
654 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
450 | uint64_t freq, |
655 | uint64_t freq, |
451 | uint32_t *dot_clock_p, |
656 | uint32_t *dot_clock_p, |
452 | uint32_t *fb_div_p, |
657 | uint32_t *fb_div_p, |
453 | uint32_t *frac_fb_div_p, |
658 | uint32_t *frac_fb_div_p, |
454 | uint32_t *ref_div_p, |
659 | uint32_t *ref_div_p, |
455 | uint32_t *post_div_p) |
660 | uint32_t *post_div_p) |
456 | { |
661 | { |
457 | uint32_t min_ref_div = pll->min_ref_div; |
662 | uint32_t min_ref_div = pll->min_ref_div; |
458 | uint32_t max_ref_div = pll->max_ref_div; |
663 | uint32_t max_ref_div = pll->max_ref_div; |
459 | uint32_t min_post_div = pll->min_post_div; |
664 | uint32_t min_post_div = pll->min_post_div; |
460 | uint32_t max_post_div = pll->max_post_div; |
665 | uint32_t max_post_div = pll->max_post_div; |
461 | uint32_t min_fractional_feed_div = 0; |
666 | uint32_t min_fractional_feed_div = 0; |
462 | uint32_t max_fractional_feed_div = 0; |
667 | uint32_t max_fractional_feed_div = 0; |
463 | uint32_t best_vco = pll->best_vco; |
668 | uint32_t best_vco = pll->best_vco; |
464 | uint32_t best_post_div = 1; |
669 | uint32_t best_post_div = 1; |
465 | uint32_t best_ref_div = 1; |
670 | uint32_t best_ref_div = 1; |
466 | uint32_t best_feedback_div = 1; |
671 | uint32_t best_feedback_div = 1; |
467 | uint32_t best_frac_feedback_div = 0; |
672 | uint32_t best_frac_feedback_div = 0; |
468 | uint32_t best_freq = -1; |
673 | uint32_t best_freq = -1; |
469 | uint32_t best_error = 0xffffffff; |
674 | uint32_t best_error = 0xffffffff; |
470 | uint32_t best_vco_diff = 1; |
675 | uint32_t best_vco_diff = 1; |
471 | uint32_t post_div; |
676 | uint32_t post_div; |
- | 677 | u32 pll_out_min, pll_out_max; |
|
472 | 678 | ||
473 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
679 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
- | 680 | freq = freq * 1000; |
|
- | 681 | ||
- | 682 | if (pll->flags & RADEON_PLL_IS_LCD) { |
|
- | 683 | pll_out_min = pll->lcd_pll_out_min; |
|
- | 684 | pll_out_max = pll->lcd_pll_out_max; |
|
- | 685 | } else { |
|
- | 686 | pll_out_min = pll->pll_out_min; |
|
- | 687 | pll_out_max = pll->pll_out_max; |
|
- | 688 | } |
|
- | 689 | ||
- | 690 | if (pll_out_min > 64800) |
|
474 | freq = freq * 1000; |
691 | pll_out_min = 64800; |
475 | 692 | ||
476 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
693 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
477 | min_ref_div = max_ref_div = pll->reference_div; |
694 | min_ref_div = max_ref_div = pll->reference_div; |
478 | else { |
695 | else { |
479 | while (min_ref_div < max_ref_div-1) { |
696 | while (min_ref_div < max_ref_div-1) { |
480 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
697 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
481 | uint32_t pll_in = pll->reference_freq / mid; |
698 | uint32_t pll_in = pll->reference_freq / mid; |
482 | if (pll_in < pll->pll_in_min) |
699 | if (pll_in < pll->pll_in_min) |
483 | max_ref_div = mid; |
700 | max_ref_div = mid; |
484 | else if (pll_in > pll->pll_in_max) |
701 | else if (pll_in > pll->pll_in_max) |
485 | min_ref_div = mid; |
702 | min_ref_div = mid; |
486 | else |
703 | else |
487 | break; |
704 | break; |
488 | } |
705 | } |
489 | } |
706 | } |
490 | 707 | ||
491 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
708 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
492 | min_post_div = max_post_div = pll->post_div; |
709 | min_post_div = max_post_div = pll->post_div; |
493 | 710 | ||
494 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
711 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
495 | min_fractional_feed_div = pll->min_frac_feedback_div; |
712 | min_fractional_feed_div = pll->min_frac_feedback_div; |
496 | max_fractional_feed_div = pll->max_frac_feedback_div; |
713 | max_fractional_feed_div = pll->max_frac_feedback_div; |
497 | } |
714 | } |
498 | 715 | ||
499 | for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { |
716 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
500 | uint32_t ref_div; |
717 | uint32_t ref_div; |
501 | 718 | ||
502 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
719 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
503 | continue; |
720 | continue; |
504 | 721 | ||
505 | /* legacy radeons only have a few post_divs */ |
722 | /* legacy radeons only have a few post_divs */ |
506 | if (pll->flags & RADEON_PLL_LEGACY) { |
723 | if (pll->flags & RADEON_PLL_LEGACY) { |
507 | if ((post_div == 5) || |
724 | if ((post_div == 5) || |
508 | (post_div == 7) || |
725 | (post_div == 7) || |
509 | (post_div == 9) || |
726 | (post_div == 9) || |
510 | (post_div == 10) || |
727 | (post_div == 10) || |
511 | (post_div == 11) || |
728 | (post_div == 11) || |
512 | (post_div == 13) || |
729 | (post_div == 13) || |
513 | (post_div == 14) || |
730 | (post_div == 14) || |
514 | (post_div == 15)) |
731 | (post_div == 15)) |
515 | continue; |
732 | continue; |
516 | } |
733 | } |
517 | 734 | ||
518 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
735 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
519 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
736 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
520 | uint32_t pll_in = pll->reference_freq / ref_div; |
737 | uint32_t pll_in = pll->reference_freq / ref_div; |
521 | uint32_t min_feed_div = pll->min_feedback_div; |
738 | uint32_t min_feed_div = pll->min_feedback_div; |
522 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
739 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
523 | 740 | ||
524 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
741 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
525 | continue; |
742 | continue; |
526 | 743 | ||
527 | while (min_feed_div < max_feed_div) { |
744 | while (min_feed_div < max_feed_div) { |
528 | uint32_t vco; |
745 | uint32_t vco; |
529 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
746 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
530 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
747 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
531 | uint32_t frac_feedback_div; |
748 | uint32_t frac_feedback_div; |
532 | uint64_t tmp; |
749 | uint64_t tmp; |
533 | 750 | ||
534 | feedback_div = (min_feed_div + max_feed_div) / 2; |
751 | feedback_div = (min_feed_div + max_feed_div) / 2; |
535 | 752 | ||
536 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
753 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
537 | vco = radeon_div(tmp, ref_div); |
754 | vco = radeon_div(tmp, ref_div); |
538 | 755 | ||
539 | if (vco < pll->pll_out_min) { |
756 | if (vco < pll_out_min) { |
540 | min_feed_div = feedback_div + 1; |
757 | min_feed_div = feedback_div + 1; |
541 | continue; |
758 | continue; |
542 | } else if (vco > pll->pll_out_max) { |
759 | } else if (vco > pll_out_max) { |
543 | max_feed_div = feedback_div; |
760 | max_feed_div = feedback_div; |
544 | continue; |
761 | continue; |
545 | } |
762 | } |
546 | 763 | ||
547 | while (min_frac_feed_div < max_frac_feed_div) { |
764 | while (min_frac_feed_div < max_frac_feed_div) { |
548 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
765 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
549 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
766 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
550 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
767 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
551 | current_freq = radeon_div(tmp, ref_div * post_div); |
768 | current_freq = radeon_div(tmp, ref_div * post_div); |
552 | 769 | ||
553 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
770 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
- | 771 | if (freq < current_freq) |
|
- | 772 | error = 0xffffffff; |
|
- | 773 | else |
|
554 | error = freq - current_freq; |
774 | error = freq - current_freq; |
555 | error = error < 0 ? 0xffffffff : error; |
- | |
556 | } else |
775 | } else |
557 | error = abs(current_freq - freq); |
776 | error = abs(current_freq - freq); |
558 | vco_diff = abs(vco - best_vco); |
777 | vco_diff = abs(vco - best_vco); |
559 | 778 | ||
560 | if ((best_vco == 0 && error < best_error) || |
779 | if ((best_vco == 0 && error < best_error) || |
561 | (best_vco != 0 && |
780 | (best_vco != 0 && |
562 | (error < best_error - 100 || |
781 | ((best_error > 100 && error < best_error - 100) || |
563 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
782 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
564 | best_post_div = post_div; |
783 | best_post_div = post_div; |
565 | best_ref_div = ref_div; |
784 | best_ref_div = ref_div; |
566 | best_feedback_div = feedback_div; |
785 | best_feedback_div = feedback_div; |
567 | best_frac_feedback_div = frac_feedback_div; |
786 | best_frac_feedback_div = frac_feedback_div; |
568 | best_freq = current_freq; |
787 | best_freq = current_freq; |
569 | best_error = error; |
788 | best_error = error; |
570 | best_vco_diff = vco_diff; |
789 | best_vco_diff = vco_diff; |
571 | } else if (current_freq == freq) { |
790 | } else if (current_freq == freq) { |
572 | if (best_freq == -1) { |
791 | if (best_freq == -1) { |
573 | best_post_div = post_div; |
792 | best_post_div = post_div; |
574 | best_ref_div = ref_div; |
793 | best_ref_div = ref_div; |
575 | best_feedback_div = feedback_div; |
794 | best_feedback_div = feedback_div; |
576 | best_frac_feedback_div = frac_feedback_div; |
795 | best_frac_feedback_div = frac_feedback_div; |
577 | best_freq = current_freq; |
796 | best_freq = current_freq; |
578 | best_error = error; |
797 | best_error = error; |
579 | best_vco_diff = vco_diff; |
798 | best_vco_diff = vco_diff; |
580 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
799 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
581 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
800 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
582 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
801 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
583 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
802 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
584 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
803 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
585 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
804 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
586 | best_post_div = post_div; |
805 | best_post_div = post_div; |
587 | best_ref_div = ref_div; |
806 | best_ref_div = ref_div; |
588 | best_feedback_div = feedback_div; |
807 | best_feedback_div = feedback_div; |
589 | best_frac_feedback_div = frac_feedback_div; |
808 | best_frac_feedback_div = frac_feedback_div; |
590 | best_freq = current_freq; |
809 | best_freq = current_freq; |
591 | best_error = error; |
810 | best_error = error; |
592 | best_vco_diff = vco_diff; |
811 | best_vco_diff = vco_diff; |
593 | } |
812 | } |
594 | } |
813 | } |
595 | if (current_freq < freq) |
814 | if (current_freq < freq) |
596 | min_frac_feed_div = frac_feedback_div + 1; |
815 | min_frac_feed_div = frac_feedback_div + 1; |
597 | else |
816 | else |
598 | max_frac_feed_div = frac_feedback_div; |
817 | max_frac_feed_div = frac_feedback_div; |
599 | } |
818 | } |
600 | if (current_freq < freq) |
819 | if (current_freq < freq) |
601 | min_feed_div = feedback_div + 1; |
820 | min_feed_div = feedback_div + 1; |
602 | else |
821 | else |
603 | max_feed_div = feedback_div; |
822 | max_feed_div = feedback_div; |
604 | } |
823 | } |
605 | } |
824 | } |
606 | } |
825 | } |
607 | 826 | ||
608 | *dot_clock_p = best_freq / 10000; |
827 | *dot_clock_p = best_freq / 10000; |
609 | *fb_div_p = best_feedback_div; |
828 | *fb_div_p = best_feedback_div; |
610 | *frac_fb_div_p = best_frac_feedback_div; |
829 | *frac_fb_div_p = best_frac_feedback_div; |
611 | *ref_div_p = best_ref_div; |
830 | *ref_div_p = best_ref_div; |
612 | *post_div_p = best_post_div; |
831 | *post_div_p = best_post_div; |
613 | } |
- | |
614 | - | ||
615 | static bool |
- | |
616 | calc_fb_div(struct radeon_pll *pll, |
832 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
617 | uint32_t freq, |
833 | (long long)freq, |
618 | uint32_t post_div, |
- | |
619 | uint32_t ref_div, |
- | |
620 | uint32_t *fb_div, |
- | |
621 | uint32_t *fb_div_frac) |
- | |
622 | { |
- | |
623 | fixed20_12 feedback_divider, a, b; |
- | |
624 | u32 vco_freq; |
- | |
625 | - | ||
626 | vco_freq = freq * post_div; |
- | |
627 | /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */ |
- | |
628 | a.full = rfixed_const(pll->reference_freq); |
- | |
629 | feedback_divider.full = rfixed_const(vco_freq); |
- | |
630 | feedback_divider.full = rfixed_div(feedback_divider, a); |
- | |
631 | a.full = rfixed_const(ref_div); |
- | |
632 | feedback_divider.full = rfixed_mul(feedback_divider, a); |
- | |
633 | - | ||
634 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
- | |
635 | /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */ |
- | |
636 | a.full = rfixed_const(10); |
- | |
637 | feedback_divider.full = rfixed_mul(feedback_divider, a); |
- | |
638 | feedback_divider.full += rfixed_const_half(0); |
- | |
639 | feedback_divider.full = rfixed_floor(feedback_divider); |
- | |
640 | feedback_divider.full = rfixed_div(feedback_divider, a); |
- | |
641 | - | ||
642 | /* *fb_div = floor(feedback_divider); */ |
- | |
643 | a.full = rfixed_floor(feedback_divider); |
- | |
644 | *fb_div = rfixed_trunc(a); |
- | |
645 | /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */ |
834 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
646 | a.full = rfixed_const(10); |
835 | best_ref_div, best_post_div); |
647 | b.full = rfixed_mul(feedback_divider, a); |
- | |
648 | - | ||
649 | feedback_divider.full = rfixed_floor(feedback_divider); |
- | |
650 | feedback_divider.full = rfixed_mul(feedback_divider, a); |
- | |
651 | feedback_divider.full = b.full - feedback_divider.full; |
- | |
652 | *fb_div_frac = rfixed_trunc(feedback_divider); |
- | |
653 | } else { |
- | |
654 | /* *fb_div = floor(feedback_divider + 0.5); */ |
- | |
655 | feedback_divider.full += rfixed_const_half(0); |
- | |
656 | feedback_divider.full = rfixed_floor(feedback_divider); |
- | |
657 | - | ||
658 | *fb_div = rfixed_trunc(feedback_divider); |
- | |
659 | *fb_div_frac = 0; |
- | |
660 | } |
- | |
661 | - | ||
662 | if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div)) |
- | |
663 | return false; |
- | |
664 | else |
- | |
665 | return true; |
- | |
666 | } |
- | |
667 | - | ||
668 | static bool |
- | |
669 | calc_fb_ref_div(struct radeon_pll *pll, |
- | |
670 | uint32_t freq, |
- | |
671 | uint32_t post_div, |
- | |
672 | uint32_t *fb_div, |
- | |
673 | uint32_t *fb_div_frac, |
- | |
674 | uint32_t *ref_div) |
- | |
675 | { |
- | |
676 | fixed20_12 ffreq, max_error, error, pll_out, a; |
- | |
677 | u32 vco; |
- | |
678 | - | ||
679 | ffreq.full = rfixed_const(freq); |
- | |
680 | /* max_error = ffreq * 0.0025; */ |
- | |
681 | a.full = rfixed_const(400); |
- | |
682 | max_error.full = rfixed_div(ffreq, a); |
- | |
683 | - | ||
684 | for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { |
- | |
685 | if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) { |
- | |
686 | vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac)); |
- | |
687 | vco = vco / ((*ref_div) * 10); |
- | |
688 | - | ||
689 | if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max)) |
- | |
690 | continue; |
- | |
691 | - | ||
692 | /* pll_out = vco / post_div; */ |
- | |
693 | a.full = rfixed_const(post_div); |
- | |
694 | pll_out.full = rfixed_const(vco); |
- | |
695 | pll_out.full = rfixed_div(pll_out, a); |
- | |
696 | - | ||
697 | if (pll_out.full >= ffreq.full) { |
- | |
698 | error.full = pll_out.full - ffreq.full; |
- | |
699 | if (error.full <= max_error.full) |
- | |
700 | return true; |
- | |
701 | } |
- | |
702 | } |
- | |
703 | } |
- | |
704 | return false; |
- | |
705 | } |
- | |
706 | - | ||
707 | static void radeon_compute_pll_new(struct radeon_pll *pll, |
- | |
708 | uint64_t freq, |
- | |
709 | uint32_t *dot_clock_p, |
- | |
710 | uint32_t *fb_div_p, |
- | |
711 | uint32_t *frac_fb_div_p, |
- | |
712 | uint32_t *ref_div_p, |
- | |
713 | uint32_t *post_div_p) |
- | |
714 | { |
- | |
715 | u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; |
- | |
716 | u32 best_freq = 0, vco_frequency; |
- | |
717 | - | ||
718 | /* freq = freq / 10; */ |
- | |
719 | do_div(freq, 10); |
- | |
720 | - | ||
721 | if (pll->flags & RADEON_PLL_USE_POST_DIV) { |
- | |
722 | post_div = pll->post_div; |
- | |
723 | if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) |
- | |
724 | goto done; |
- | |
725 | - | ||
726 | vco_frequency = freq * post_div; |
- | |
727 | if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) |
- | |
728 | goto done; |
- | |
729 | - | ||
730 | if (pll->flags & RADEON_PLL_USE_REF_DIV) { |
- | |
731 | ref_div = pll->reference_div; |
- | |
732 | if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) |
- | |
733 | goto done; |
- | |
734 | if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) |
- | |
735 | goto done; |
- | |
736 | } |
- | |
737 | } else { |
- | |
738 | for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { |
- | |
739 | if (pll->flags & RADEON_PLL_LEGACY) { |
- | |
740 | if ((post_div == 5) || |
- | |
741 | (post_div == 7) || |
- | |
742 | (post_div == 9) || |
- | |
743 | (post_div == 10) || |
- | |
744 | (post_div == 11)) |
- | |
745 | continue; |
- | |
746 | } |
- | |
747 | - | ||
748 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
- | |
749 | continue; |
- | |
750 | - | ||
751 | vco_frequency = freq * post_div; |
- | |
752 | if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) |
- | |
753 | continue; |
- | |
754 | if (pll->flags & RADEON_PLL_USE_REF_DIV) { |
- | |
755 | ref_div = pll->reference_div; |
- | |
756 | if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) |
- | |
757 | goto done; |
- | |
758 | if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) |
- | |
759 | break; |
- | |
760 | } else { |
- | |
761 | if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div)) |
- | |
762 | break; |
- | |
763 | } |
- | |
764 | } |
- | |
765 | } |
- | |
766 | - | ||
767 | best_freq = pll->reference_freq * 10 * fb_div; |
- | |
768 | best_freq += pll->reference_freq * fb_div_frac; |
- | |
769 | best_freq = best_freq / (ref_div * post_div); |
- | |
770 | - | ||
771 | done: |
- | |
772 | if (best_freq == 0) |
- | |
773 | DRM_ERROR("Couldn't find valid PLL dividers\n"); |
- | |
774 | - | ||
775 | *dot_clock_p = best_freq / 10; |
- | |
776 | *fb_div_p = fb_div; |
- | |
777 | *frac_fb_div_p = fb_div_frac; |
- | |
778 | *ref_div_p = ref_div; |
- | |
779 | *post_div_p = post_div; |
- | |
780 | - | ||
781 | DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); |
- | |
782 | } |
- | |
783 | - | ||
784 | void radeon_compute_pll(struct radeon_pll *pll, |
- | |
785 | uint64_t freq, |
- | |
786 | uint32_t *dot_clock_p, |
- | |
787 | uint32_t *fb_div_p, |
- | |
788 | uint32_t *frac_fb_div_p, |
- | |
789 | uint32_t *ref_div_p, |
- | |
790 | uint32_t *post_div_p) |
- | |
791 | { |
- | |
792 | switch (pll->algo) { |
- | |
793 | case PLL_ALGO_NEW: |
- | |
794 | radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p, |
- | |
795 | frac_fb_div_p, ref_div_p, post_div_p); |
- | |
796 | break; |
- | |
797 | case PLL_ALGO_LEGACY: |
- | |
798 | default: |
- | |
799 | radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p, |
- | |
800 | frac_fb_div_p, ref_div_p, post_div_p); |
- | |
801 | break; |
- | |
802 | } |
836 | |
803 | } |
837 | } |
804 | 838 | ||
805 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
839 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
806 | { |
840 | { |
807 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
841 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
808 | struct drm_device *dev = fb->dev; |
- | |
809 | - | ||
810 | if (fb->fbdev) |
- | |
811 | radeonfb_remove(dev, fb); |
- | |
812 | - | ||
813 | 842 | ||
814 | drm_framebuffer_cleanup(fb); |
843 | drm_framebuffer_cleanup(fb); |
815 | kfree(radeon_fb); |
844 | kfree(radeon_fb); |
816 | } |
845 | } |
817 | 846 | ||
818 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
847 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
819 | struct drm_file *file_priv, |
848 | struct drm_file *file_priv, |
820 | unsigned int *handle) |
849 | unsigned int *handle) |
821 | { |
850 | { |
822 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
851 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
823 | 852 | ||
824 | return NULL; |
853 | return NULL; |
825 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
854 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
826 | } |
855 | } |
827 | 856 | ||
828 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
857 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
829 | .destroy = radeon_user_framebuffer_destroy, |
858 | .destroy = radeon_user_framebuffer_destroy, |
830 | .create_handle = radeon_user_framebuffer_create_handle, |
859 | .create_handle = radeon_user_framebuffer_create_handle, |
831 | }; |
860 | }; |
832 | 861 | ||
833 | struct drm_framebuffer * |
862 | void |
- | 863 | radeon_framebuffer_init(struct drm_device *dev, |
|
834 | radeon_framebuffer_create(struct drm_device *dev, |
864 | struct radeon_framebuffer *rfb, |
835 | struct drm_mode_fb_cmd *mode_cmd, |
865 | struct drm_mode_fb_cmd *mode_cmd, |
836 | struct drm_gem_object *obj) |
866 | struct drm_gem_object *obj) |
837 | { |
867 | { |
838 | struct radeon_framebuffer *radeon_fb; |
- | |
839 | - | ||
840 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); |
- | |
841 | if (radeon_fb == NULL) { |
- | |
842 | return NULL; |
868 | rfb->obj = obj; |
843 | } |
- | |
844 | drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); |
869 | drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
845 | drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); |
870 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
846 | radeon_fb->obj = obj; |
- | |
847 | return &radeon_fb->base; |
- | |
848 | } |
871 | } |
849 | 872 | ||
850 | static struct drm_framebuffer * |
873 | static struct drm_framebuffer * |
851 | radeon_user_framebuffer_create(struct drm_device *dev, |
874 | radeon_user_framebuffer_create(struct drm_device *dev, |
852 | struct drm_file *file_priv, |
875 | struct drm_file *file_priv, |
853 | struct drm_mode_fb_cmd *mode_cmd) |
876 | struct drm_mode_fb_cmd *mode_cmd) |
854 | { |
877 | { |
855 | struct drm_gem_object *obj; |
878 | struct drm_gem_object *obj; |
856 | 879 | ||
857 | return NULL; |
880 | return NULL; |
858 | 881 | ||
859 | // obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); |
882 | // obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); |
860 | // |
883 | // |
861 | // return radeon_framebuffer_create(dev, mode_cmd, obj); |
884 | // return radeon_framebuffer_create(dev, mode_cmd, obj); |
862 | } |
885 | } |
- | 886 | ||
863 | 887 | ||
864 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
888 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
865 | // .fb_create = radeon_user_framebuffer_create, |
889 | // .fb_create = radeon_user_framebuffer_create, |
866 | .fb_changed = radeonfb_probe, |
890 | // .output_poll_changed = radeon_output_poll_changed |
867 | }; |
891 | }; |
868 | 892 | ||
869 | struct drm_prop_enum_list { |
893 | struct drm_prop_enum_list { |
870 | int type; |
894 | int type; |
871 | char *name; |
895 | char *name; |
872 | }; |
896 | }; |
873 | 897 | ||
874 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
898 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
875 | { { 0, "driver" }, |
899 | { { 0, "driver" }, |
876 | { 1, "bios" }, |
900 | { 1, "bios" }, |
877 | }; |
901 | }; |
878 | 902 | ||
879 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
903 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
880 | { { TV_STD_NTSC, "ntsc" }, |
904 | { { TV_STD_NTSC, "ntsc" }, |
881 | { TV_STD_PAL, "pal" }, |
905 | { TV_STD_PAL, "pal" }, |
882 | { TV_STD_PAL_M, "pal-m" }, |
906 | { TV_STD_PAL_M, "pal-m" }, |
883 | { TV_STD_PAL_60, "pal-60" }, |
907 | { TV_STD_PAL_60, "pal-60" }, |
884 | { TV_STD_NTSC_J, "ntsc-j" }, |
908 | { TV_STD_NTSC_J, "ntsc-j" }, |
885 | { TV_STD_SCART_PAL, "scart-pal" }, |
909 | { TV_STD_SCART_PAL, "scart-pal" }, |
886 | { TV_STD_PAL_CN, "pal-cn" }, |
910 | { TV_STD_PAL_CN, "pal-cn" }, |
887 | { TV_STD_SECAM, "secam" }, |
911 | { TV_STD_SECAM, "secam" }, |
888 | }; |
912 | }; |
- | 913 | ||
- | 914 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
|
- | 915 | { { UNDERSCAN_OFF, "off" }, |
|
- | 916 | { UNDERSCAN_ON, "on" }, |
|
- | 917 | { UNDERSCAN_AUTO, "auto" }, |
|
- | 918 | }; |
|
889 | 919 | ||
890 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
920 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
891 | { |
921 | { |
892 | int i, sz; |
922 | int i, sz; |
893 | 923 | ||
894 | if (rdev->is_atom_bios) { |
924 | if (rdev->is_atom_bios) { |
895 | rdev->mode_info.coherent_mode_property = |
925 | rdev->mode_info.coherent_mode_property = |
896 | drm_property_create(rdev->ddev, |
926 | drm_property_create(rdev->ddev, |
897 | DRM_MODE_PROP_RANGE, |
927 | DRM_MODE_PROP_RANGE, |
898 | "coherent", 2); |
928 | "coherent", 2); |
899 | if (!rdev->mode_info.coherent_mode_property) |
929 | if (!rdev->mode_info.coherent_mode_property) |
900 | return -ENOMEM; |
930 | return -ENOMEM; |
901 | 931 | ||
902 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
932 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
903 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
933 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
904 | } |
934 | } |
905 | 935 | ||
906 | if (!ASIC_IS_AVIVO(rdev)) { |
936 | if (!ASIC_IS_AVIVO(rdev)) { |
907 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
937 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
908 | rdev->mode_info.tmds_pll_property = |
938 | rdev->mode_info.tmds_pll_property = |
909 | drm_property_create(rdev->ddev, |
939 | drm_property_create(rdev->ddev, |
910 | DRM_MODE_PROP_ENUM, |
940 | DRM_MODE_PROP_ENUM, |
911 | "tmds_pll", sz); |
941 | "tmds_pll", sz); |
912 | for (i = 0; i < sz; i++) { |
942 | for (i = 0; i < sz; i++) { |
913 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, |
943 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, |
914 | i, |
944 | i, |
915 | radeon_tmds_pll_enum_list[i].type, |
945 | radeon_tmds_pll_enum_list[i].type, |
916 | radeon_tmds_pll_enum_list[i].name); |
946 | radeon_tmds_pll_enum_list[i].name); |
917 | } |
947 | } |
918 | } |
948 | } |
919 | 949 | ||
920 | rdev->mode_info.load_detect_property = |
950 | rdev->mode_info.load_detect_property = |
921 | drm_property_create(rdev->ddev, |
951 | drm_property_create(rdev->ddev, |
922 | DRM_MODE_PROP_RANGE, |
952 | DRM_MODE_PROP_RANGE, |
923 | "load detection", 2); |
953 | "load detection", 2); |
924 | if (!rdev->mode_info.load_detect_property) |
954 | if (!rdev->mode_info.load_detect_property) |
925 | return -ENOMEM; |
955 | return -ENOMEM; |
926 | rdev->mode_info.load_detect_property->values[0] = 0; |
956 | rdev->mode_info.load_detect_property->values[0] = 0; |
927 | rdev->mode_info.load_detect_property->values[1] = 1; |
957 | rdev->mode_info.load_detect_property->values[1] = 1; |
928 | 958 | ||
929 | drm_mode_create_scaling_mode_property(rdev->ddev); |
959 | drm_mode_create_scaling_mode_property(rdev->ddev); |
930 | 960 | ||
931 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
961 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
932 | rdev->mode_info.tv_std_property = |
962 | rdev->mode_info.tv_std_property = |
933 | drm_property_create(rdev->ddev, |
963 | drm_property_create(rdev->ddev, |
934 | DRM_MODE_PROP_ENUM, |
964 | DRM_MODE_PROP_ENUM, |
935 | "tv standard", sz); |
965 | "tv standard", sz); |
936 | for (i = 0; i < sz; i++) { |
966 | for (i = 0; i < sz; i++) { |
937 | drm_property_add_enum(rdev->mode_info.tv_std_property, |
967 | drm_property_add_enum(rdev->mode_info.tv_std_property, |
938 | i, |
968 | i, |
939 | radeon_tv_std_enum_list[i].type, |
969 | radeon_tv_std_enum_list[i].type, |
940 | radeon_tv_std_enum_list[i].name); |
970 | radeon_tv_std_enum_list[i].name); |
941 | } |
971 | } |
- | 972 | ||
- | 973 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
|
- | 974 | rdev->mode_info.underscan_property = |
|
- | 975 | drm_property_create(rdev->ddev, |
|
- | 976 | DRM_MODE_PROP_ENUM, |
|
- | 977 | "underscan", sz); |
|
- | 978 | for (i = 0; i < sz; i++) { |
|
- | 979 | drm_property_add_enum(rdev->mode_info.underscan_property, |
|
- | 980 | i, |
|
- | 981 | radeon_underscan_enum_list[i].type, |
|
- | 982 | radeon_underscan_enum_list[i].name); |
|
- | 983 | } |
|
- | 984 | ||
- | 985 | rdev->mode_info.underscan_hborder_property = |
|
- | 986 | drm_property_create(rdev->ddev, |
|
- | 987 | DRM_MODE_PROP_RANGE, |
|
- | 988 | "underscan hborder", 2); |
|
- | 989 | if (!rdev->mode_info.underscan_hborder_property) |
|
- | 990 | return -ENOMEM; |
|
- | 991 | rdev->mode_info.underscan_hborder_property->values[0] = 0; |
|
- | 992 | rdev->mode_info.underscan_hborder_property->values[1] = 128; |
|
- | 993 | ||
- | 994 | rdev->mode_info.underscan_vborder_property = |
|
- | 995 | drm_property_create(rdev->ddev, |
|
- | 996 | DRM_MODE_PROP_RANGE, |
|
- | 997 | "underscan vborder", 2); |
|
- | 998 | if (!rdev->mode_info.underscan_vborder_property) |
|
- | 999 | return -ENOMEM; |
|
- | 1000 | rdev->mode_info.underscan_vborder_property->values[0] = 0; |
|
- | 1001 | rdev->mode_info.underscan_vborder_property->values[1] = 128; |
|
942 | 1002 | ||
943 | return 0; |
1003 | return 0; |
944 | } |
1004 | } |
- | 1005 | ||
- | 1006 | void radeon_update_display_priority(struct radeon_device *rdev) |
|
- | 1007 | { |
|
- | 1008 | /* adjustment options for the display watermarks */ |
|
- | 1009 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
|
- | 1010 | /* set display priority to high for r3xx, rv515 chips |
|
- | 1011 | * this avoids flickering due to underflow to the |
|
- | 1012 | * display controllers during heavy acceleration. |
|
- | 1013 | * Don't force high on rs4xx igp chips as it seems to |
|
- | 1014 | * affect the sound card. See kernel bug 15982. |
|
- | 1015 | */ |
|
- | 1016 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
|
- | 1017 | !(rdev->flags & RADEON_IS_IGP)) |
|
- | 1018 | rdev->disp_priority = 2; |
|
- | 1019 | else |
|
- | 1020 | rdev->disp_priority = 0; |
|
- | 1021 | } else |
|
- | 1022 | rdev->disp_priority = radeon_disp_priority; |
|
- | 1023 | ||
- | 1024 | } |
|
945 | 1025 | ||
946 | int radeon_modeset_init(struct radeon_device *rdev) |
1026 | int radeon_modeset_init(struct radeon_device *rdev) |
947 | { |
1027 | { |
948 | int i; |
1028 | int i; |
949 | int ret; |
1029 | int ret; |
- | 1030 | ||
- | 1031 | ENTER(); |
|
950 | 1032 | ||
951 | drm_mode_config_init(rdev->ddev); |
1033 | drm_mode_config_init(rdev->ddev); |
952 | rdev->mode_info.mode_config_initialized = true; |
1034 | rdev->mode_info.mode_config_initialized = true; |
953 | 1035 | ||
954 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
1036 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
955 | 1037 | ||
- | 1038 | if (ASIC_IS_DCE5(rdev)) { |
|
- | 1039 | rdev->ddev->mode_config.max_width = 16384; |
|
- | 1040 | rdev->ddev->mode_config.max_height = 16384; |
|
956 | if (ASIC_IS_AVIVO(rdev)) { |
1041 | } else if (ASIC_IS_AVIVO(rdev)) { |
957 | rdev->ddev->mode_config.max_width = 8192; |
1042 | rdev->ddev->mode_config.max_width = 8192; |
958 | rdev->ddev->mode_config.max_height = 8192; |
1043 | rdev->ddev->mode_config.max_height = 8192; |
959 | } else { |
1044 | } else { |
960 | rdev->ddev->mode_config.max_width = 4096; |
1045 | rdev->ddev->mode_config.max_width = 4096; |
961 | rdev->ddev->mode_config.max_height = 4096; |
1046 | rdev->ddev->mode_config.max_height = 4096; |
962 | } |
1047 | } |
963 | 1048 | ||
964 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1049 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
965 | 1050 | ||
966 | ret = radeon_modeset_create_props(rdev); |
1051 | ret = radeon_modeset_create_props(rdev); |
967 | if (ret) { |
1052 | if (ret) { |
968 | return ret; |
1053 | return ret; |
969 | } |
1054 | } |
- | 1055 | ||
- | 1056 | /* init i2c buses */ |
|
- | 1057 | radeon_i2c_init(rdev); |
|
970 | 1058 | ||
971 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1059 | /* check combios for a valid hardcoded EDID - Sun servers */ |
972 | if (!rdev->is_atom_bios) { |
1060 | if (!rdev->is_atom_bios) { |
973 | /* check for hardcoded EDID in BIOS */ |
1061 | /* check for hardcoded EDID in BIOS */ |
974 | radeon_combios_check_hardcoded_edid(rdev); |
1062 | radeon_combios_check_hardcoded_edid(rdev); |
975 | } |
1063 | } |
976 | - | ||
977 | if (rdev->flags & RADEON_SINGLE_CRTC) |
- | |
978 | rdev->num_crtc = 1; |
- | |
979 | else { |
- | |
980 | if (ASIC_IS_DCE4(rdev)) |
- | |
981 | rdev->num_crtc = 6; |
- | |
982 | else |
- | |
983 | rdev->num_crtc = 2; |
- | |
984 | } |
- | |
985 | 1064 | ||
986 | /* allocate crtcs */ |
1065 | /* allocate crtcs */ |
987 | for (i = 0; i < rdev->num_crtc; i++) { |
1066 | for (i = 0; i < rdev->num_crtc; i++) { |
988 | radeon_crtc_init(rdev->ddev, i); |
1067 | radeon_crtc_init(rdev->ddev, i); |
989 | } |
1068 | } |
990 | 1069 | ||
991 | /* okay we should have all the bios connectors */ |
1070 | /* okay we should have all the bios connectors */ |
992 | ret = radeon_setup_enc_conn(rdev->ddev); |
1071 | ret = radeon_setup_enc_conn(rdev->ddev); |
993 | if (!ret) { |
1072 | if (!ret) { |
994 | return ret; |
1073 | return ret; |
995 | } |
1074 | } |
- | 1075 | ||
- | 1076 | /* init dig PHYs */ |
|
- | 1077 | if (rdev->is_atom_bios) |
|
- | 1078 | radeon_atom_encoder_init(rdev); |
|
- | 1079 | ||
996 | /* initialize hpd */ |
1080 | /* initialize hpd */ |
- | 1081 | // radeon_hpd_init(rdev); |
|
- | 1082 | ||
- | 1083 | /* Initialize power management */ |
|
- | 1084 | // radeon_pm_init(rdev); |
|
- | 1085 | ||
997 | radeon_hpd_init(rdev); |
1086 | radeon_fbdev_init(rdev); |
998 | drm_helper_initial_config(rdev->ddev); |
1087 | // drm_kms_helper_poll_init(rdev->ddev); |
- | 1088 | ||
- | 1089 | LEAVE(); |
|
- | 1090 | ||
999 | return 0; |
1091 | return 0; |
1000 | } |
1092 | } |
1001 | 1093 | ||
1002 | void radeon_modeset_fini(struct radeon_device *rdev) |
1094 | void radeon_modeset_fini(struct radeon_device *rdev) |
1003 | { |
1095 | { |
1004 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1096 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1005 | 1097 | ||
1006 | if (rdev->mode_info.mode_config_initialized) { |
1098 | if (rdev->mode_info.mode_config_initialized) { |
- | 1099 | // drm_kms_helper_poll_fini(rdev->ddev); |
|
1007 | radeon_hpd_fini(rdev); |
1100 | // radeon_hpd_fini(rdev); |
1008 | drm_mode_config_cleanup(rdev->ddev); |
1101 | drm_mode_config_cleanup(rdev->ddev); |
1009 | rdev->mode_info.mode_config_initialized = false; |
1102 | rdev->mode_info.mode_config_initialized = false; |
1010 | } |
1103 | } |
- | 1104 | /* free i2c buses */ |
|
- | 1105 | radeon_i2c_fini(rdev); |
|
- | 1106 | } |
|
- | 1107 | ||
- | 1108 | static bool is_hdtv_mode(struct drm_display_mode *mode) |
|
- | 1109 | { |
|
- | 1110 | /* try and guess if this is a tv or a monitor */ |
|
- | 1111 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
|
- | 1112 | (mode->vdisplay == 576) || /* 576p */ |
|
- | 1113 | (mode->vdisplay == 720) || /* 720p */ |
|
- | 1114 | (mode->vdisplay == 1080)) /* 1080p */ |
|
- | 1115 | return true; |
|
- | 1116 | else |
|
- | 1117 | return false; |
|
1011 | } |
1118 | } |
1012 | 1119 | ||
1013 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1120 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1014 | struct drm_display_mode *mode, |
1121 | struct drm_display_mode *mode, |
1015 | struct drm_display_mode *adjusted_mode) |
1122 | struct drm_display_mode *adjusted_mode) |
1016 | { |
1123 | { |
1017 | struct drm_device *dev = crtc->dev; |
1124 | struct drm_device *dev = crtc->dev; |
- | 1125 | struct radeon_device *rdev = dev->dev_private; |
|
1018 | struct drm_encoder *encoder; |
1126 | struct drm_encoder *encoder; |
1019 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1127 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1020 | struct radeon_encoder *radeon_encoder; |
1128 | struct radeon_encoder *radeon_encoder; |
- | 1129 | struct drm_connector *connector; |
|
- | 1130 | struct radeon_connector *radeon_connector; |
|
1021 | bool first = true; |
1131 | bool first = true; |
- | 1132 | u32 src_v = 1, dst_v = 1; |
|
- | 1133 | u32 src_h = 1, dst_h = 1; |
|
- | 1134 | ||
- | 1135 | radeon_crtc->h_border = 0; |
|
- | 1136 | radeon_crtc->v_border = 0; |
|
1022 | 1137 | ||
1023 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
- | |
1024 | radeon_encoder = to_radeon_encoder(encoder); |
1138 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1025 | if (encoder->crtc != crtc) |
1139 | if (encoder->crtc != crtc) |
- | 1140 | continue; |
|
- | 1141 | radeon_encoder = to_radeon_encoder(encoder); |
|
- | 1142 | connector = radeon_get_connector_for_encoder(encoder); |
|
- | 1143 | radeon_connector = to_radeon_connector(connector); |
|
1026 | continue; |
1144 | |
1027 | if (first) { |
1145 | if (first) { |
1028 | /* set scaling */ |
1146 | /* set scaling */ |
1029 | if (radeon_encoder->rmx_type == RMX_OFF) |
1147 | if (radeon_encoder->rmx_type == RMX_OFF) |
1030 | radeon_crtc->rmx_type = RMX_OFF; |
1148 | radeon_crtc->rmx_type = RMX_OFF; |
1031 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
1149 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
1032 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
1150 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
1033 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1151 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1034 | else |
1152 | else |
1035 | radeon_crtc->rmx_type = RMX_OFF; |
1153 | radeon_crtc->rmx_type = RMX_OFF; |
1036 | /* copy native mode */ |
1154 | /* copy native mode */ |
1037 | memcpy(&radeon_crtc->native_mode, |
1155 | memcpy(&radeon_crtc->native_mode, |
1038 | &radeon_encoder->native_mode, |
1156 | &radeon_encoder->native_mode, |
1039 | sizeof(struct drm_display_mode)); |
1157 | sizeof(struct drm_display_mode)); |
- | 1158 | src_v = crtc->mode.vdisplay; |
|
- | 1159 | dst_v = radeon_crtc->native_mode.vdisplay; |
|
- | 1160 | src_h = crtc->mode.hdisplay; |
|
- | 1161 | dst_h = radeon_crtc->native_mode.hdisplay; |
|
- | 1162 | ||
- | 1163 | /* fix up for overscan on hdmi */ |
|
- | 1164 | if (ASIC_IS_AVIVO(rdev) && |
|
- | 1165 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
|
- | 1166 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
|
- | 1167 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
|
- | 1168 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
|
- | 1169 | is_hdtv_mode(mode)))) { |
|
- | 1170 | if (radeon_encoder->underscan_hborder != 0) |
|
- | 1171 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
|
- | 1172 | else |
|
- | 1173 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
|
- | 1174 | if (radeon_encoder->underscan_vborder != 0) |
|
- | 1175 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
|
- | 1176 | else |
|
- | 1177 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
|
- | 1178 | radeon_crtc->rmx_type = RMX_FULL; |
|
- | 1179 | src_v = crtc->mode.vdisplay; |
|
- | 1180 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
|
- | 1181 | src_h = crtc->mode.hdisplay; |
|
- | 1182 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
|
- | 1183 | } |
|
1040 | first = false; |
1184 | first = false; |
1041 | } else { |
1185 | } else { |
1042 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
1186 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
1043 | /* WARNING: Right now this can't happen but |
1187 | /* WARNING: Right now this can't happen but |
1044 | * in the future we need to check that scaling |
1188 | * in the future we need to check that scaling |
1045 | * are consistent accross different encoder |
1189 | * are consistent across different encoder |
1046 | * (ie all encoder can work with the same |
1190 | * (ie all encoder can work with the same |
1047 | * scaling). |
1191 | * scaling). |
1048 | */ |
1192 | */ |
1049 | DRM_ERROR("Scaling not consistent accross encoder.\n"); |
1193 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
1050 | return false; |
1194 | return false; |
1051 | } |
1195 | } |
1052 | } |
1196 | } |
1053 | } |
1197 | } |
1054 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1198 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1055 | fixed20_12 a, b; |
1199 | fixed20_12 a, b; |
1056 | a.full = rfixed_const(crtc->mode.vdisplay); |
1200 | a.full = dfixed_const(src_v); |
1057 | b.full = rfixed_const(radeon_crtc->native_mode.hdisplay); |
1201 | b.full = dfixed_const(dst_v); |
1058 | radeon_crtc->vsc.full = rfixed_div(a, b); |
1202 | radeon_crtc->vsc.full = dfixed_div(a, b); |
1059 | a.full = rfixed_const(crtc->mode.hdisplay); |
1203 | a.full = dfixed_const(src_h); |
1060 | b.full = rfixed_const(radeon_crtc->native_mode.vdisplay); |
1204 | b.full = dfixed_const(dst_h); |
1061 | radeon_crtc->hsc.full = rfixed_div(a, b); |
1205 | radeon_crtc->hsc.full = dfixed_div(a, b); |
1062 | } else { |
1206 | } else { |
1063 | radeon_crtc->vsc.full = rfixed_const(1); |
1207 | radeon_crtc->vsc.full = dfixed_const(1); |
1064 | radeon_crtc->hsc.full = rfixed_const(1); |
1208 | radeon_crtc->hsc.full = dfixed_const(1); |
1065 | } |
1209 | } |
1066 | return true; |
1210 | return true; |
1067 | }>>>>>>>>>>=>>>>>>>>>>>>>>>>>>=>=>>>><>><>><>>>><>><>><>><>><>><>>><>><>><>>><>><>><>> |
1211 | } |
- | 1212 | ||
- | 1213 | /* |
|
- | 1214 | * Retrieve current video scanout position of crtc on a given gpu. |
|
- | 1215 | * |
|
- | 1216 | * \param dev Device to query. |
|
- | 1217 | * \param crtc Crtc to query. |
|
- | 1218 | * \param *vpos Location where vertical scanout position should be stored. |
|
- | 1219 | * \param *hpos Location where horizontal scanout position should go. |
|
- | 1220 | * |
|
- | 1221 | * Returns vpos as a positive number while in active scanout area. |
|
- | 1222 | * Returns vpos as a negative number inside vblank, counting the number |
|
- | 1223 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
|
- | 1224 | * until start of active scanout / end of vblank." |
|
- | 1225 | * |
|
- | 1226 | * \return Flags, or'ed together as follows: |
|
- | 1227 | * |
|
- | 1228 | * DRM_SCANOUTPOS_VALID = Query successful. |
|
- | 1229 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
|
- | 1230 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
|
- | 1231 | * this flag means that returned position may be offset by a constant but |
|
- | 1232 | * unknown small number of scanlines wrt. real scanout position. |
|
- | 1233 | * |
|
- | 1234 | */ |
|
- | 1235 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) |
|
- | 1236 | { |
|
- | 1237 | u32 stat_crtc = 0, vbl = 0, position = 0; |
|
- | 1238 | int vbl_start, vbl_end, vtotal, ret = 0; |
|
- | 1239 | bool in_vbl = true; |
|
- | 1240 | ||
- | 1241 | struct radeon_device *rdev = dev->dev_private; |
|
- | 1242 | ||
- | 1243 | if (ASIC_IS_DCE4(rdev)) { |
|
- | 1244 | if (crtc == 0) { |
|
- | 1245 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
|
- | 1246 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
|
- | 1247 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
|
- | 1248 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
|
- | 1249 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1250 | } |
|
- | 1251 | if (crtc == 1) { |
|
- | 1252 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
|
- | 1253 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
|
- | 1254 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
|
- | 1255 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
|
- | 1256 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1257 | } |
|
- | 1258 | if (crtc == 2) { |
|
- | 1259 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
|
- | 1260 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
|
- | 1261 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
|
- | 1262 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
|
- | 1263 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1264 | } |
|
- | 1265 | if (crtc == 3) { |
|
- | 1266 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
|
- | 1267 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
|
- | 1268 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
|
- | 1269 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
|
- | 1270 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1271 | } |
|
- | 1272 | if (crtc == 4) { |
|
- | 1273 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
|
- | 1274 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
|
- | 1275 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
|
- | 1276 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
|
- | 1277 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1278 | } |
|
- | 1279 | if (crtc == 5) { |
|
- | 1280 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
|
- | 1281 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
|
- | 1282 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
|
- | 1283 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
|
- | 1284 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1285 | } |
|
- | 1286 | } else if (ASIC_IS_AVIVO(rdev)) { |
|
- | 1287 | if (crtc == 0) { |
|
- | 1288 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
|
- | 1289 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
|
- | 1290 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1291 | } |
|
- | 1292 | if (crtc == 1) { |
|
- | 1293 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
|
- | 1294 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
|
- | 1295 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1296 | } |
|
- | 1297 | } else { |
|
- | 1298 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
|
- | 1299 | if (crtc == 0) { |
|
- | 1300 | /* Assume vbl_end == 0, get vbl_start from |
|
- | 1301 | * upper 16 bits. |
|
- | 1302 | */ |
|
- | 1303 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
|
- | 1304 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
|
- | 1305 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
|
- | 1306 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
|
- | 1307 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
|
- | 1308 | if (!(stat_crtc & 1)) |
|
- | 1309 | in_vbl = false; |
|
- | 1310 | ||
- | 1311 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1312 | } |
|
- | 1313 | if (crtc == 1) { |
|
- | 1314 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
|
- | 1315 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
|
- | 1316 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
|
- | 1317 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
|
- | 1318 | if (!(stat_crtc & 1)) |
|
- | 1319 | in_vbl = false; |
|
- | 1320 | ||
- | 1321 | ret |= DRM_SCANOUTPOS_VALID; |
|
- | 1322 | } |
|
- | 1323 | } |
|
- | 1324 | ||
- | 1325 | /* Decode into vertical and horizontal scanout position. */ |
|
- | 1326 | *vpos = position & 0x1fff; |
|
- | 1327 | *hpos = (position >> 16) & 0x1fff; |
|
- | 1328 | ||
- | 1329 | /* Valid vblank area boundaries from gpu retrieved? */ |
|
- | 1330 | if (vbl > 0) { |
|
- | 1331 | /* Yes: Decode. */ |
|
- | 1332 | ret |= DRM_SCANOUTPOS_ACCURATE; |
|
- | 1333 | vbl_start = vbl & 0x1fff; |
|
- | 1334 | vbl_end = (vbl >> 16) & 0x1fff; |
|
- | 1335 | } |
|
- | 1336 | else { |
|
- | 1337 | /* No: Fake something reasonable which gives at least ok results. */ |
|
- | 1338 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
|
- | 1339 | vbl_end = 0; |
|
- | 1340 | } |
|
- | 1341 | ||
- | 1342 | /* Test scanout position against vblank region. */ |
|
- | 1343 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
|
- | 1344 | in_vbl = false; |
|
- | 1345 | ||
- | 1346 | /* Check if inside vblank area and apply corrective offsets: |
|
- | 1347 | * vpos will then be >=0 in video scanout area, but negative |
|
- | 1348 | * within vblank area, counting down the number of lines until |
|
- | 1349 | * start of scanout. |
|
- | 1350 | */ |
|
- | 1351 | ||
- | 1352 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
|
- | 1353 | if (in_vbl && (*vpos >= vbl_start)) { |
|
- | 1354 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
|
- | 1355 | *vpos = *vpos - vtotal; |
|
- | 1356 | } |
|
- | 1357 | ||
- | 1358 | /* Correct for shifted end of vbl at vbl_end. */ |
|
- | 1359 | *vpos = *vpos - vbl_end; |
|
- | 1360 | ||
- | 1361 | /* In vblank? */ |
|
- | 1362 | if (in_vbl) |
|
- | 1363 | ret |= DRM_SCANOUTPOS_INVBL; |
|
- | 1364 | ||
- | 1365 | return ret; |
|
- | 1366 | }>>>>>>>>>>>>>>>>>>>>>=>>>=>>>><>><>><>>>><>><>><>><>><>><>>><>><>><>>><>><>><>>><>><>><>> |