WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_device.c

 int radeon_audio = 1;
 int radeon_hw_i2c = 0;
 int radeon_pcie_gen2 = 0;
 int radeon_disp_priority = 0;
 int radeon_lockup_timeout = 10000;
+int radeon_fastfb = 0;
 int irq_override = 0;
 	"CAYMAN",
 	"ARUBA",
 	"TAHITI",
 	"PITCAIRN",
 	"VERDE",
+	"OLAND",
+	"HAINAN",
 	"LAST",
 };
+/**
+ * radeon_program_register_sequence - program an array of registers.
+ *
+ * @rdev: radeon_device pointer
+ * @registers: pointer to the register array
+ * @array_size: size of the register array
+ *
+ * Programs an array or registers with and and or masks.
+ * This is a helper for setting golden registers.
+ */
+void radeon_program_register_sequence(struct radeon_device *rdev,
+				      const u32 *registers,
+				      const u32 array_size)
+{
+	u32 tmp, reg, and_mask, or_mask;
+	int i;
+	if (array_size % 3)
+		return;
+	for (i = 0; i < array_size; i +=3) {
+		reg = registers[i + 0];
+		and_mask = registers[i + 1];
+		or_mask = registers[i + 2];
+		if (and_mask == 0xffffffff) {
+			tmp = or_mask;
+		} else {
+			tmp = RREG32(reg);
+			tmp &= ~and_mask;
+			tmp |= or_mask;
+		}
+		WREG32(reg, tmp);
+	}
+}
 /**
  * radeon_surface_init - Clear GPU surface registers.
+ *
  * @rdev: radeon_device pointer
+ *
+ *
  * Disables Writeback (all asics).  Used for suspend.
  */
 void radeon_wb_disable(struct radeon_device *rdev)
+{
-	int r;
-	if (rdev->wb.wb_obj) {
-		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
-		if (unlikely(r != 0))
-			return;
-		radeon_bo_kunmap(rdev->wb.wb_obj);
-		radeon_bo_unpin(rdev->wb.wb_obj);
-		radeon_bo_unreserve(rdev->wb.wb_obj);
-	}
 	rdev->wb.enabled = false;
+}
 /**
 				     RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
 		if (r) {
 			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 			return r;
+		}
-	}
 	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 	if (unlikely(r != 0)) {
 		radeon_wb_fini(rdev);
 		return r;
+	}
 	if (r) {
 		dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 		radeon_wb_fini(rdev);
 		return r;
+	}
+	}
 	/* clear wb memory */
 	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 	/* disable event_write fences */
 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
+{
 	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 	mc->vram_start = base;
-	if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
+	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
 		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 		mc->real_vram_size = mc->aper_size;
 		mc->mc_vram_size = mc->aper_size;
+	}
  */
 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
+{
 	u64 size_af, size_bf;
-	size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
+	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 	size_bf = mc->vram_start & ~mc->gtt_base_align;
 	if (size_bf > size_af) {
 		if (mc->gtt_size > size_bf) {
 			dev_warn(rdev->dev, "limiting GTT\n");
  */
 bool radeon_card_posted(struct radeon_device *rdev)
+{
 	uint32_t reg;
+	if (ASIC_IS_NODCE(rdev))
+		goto check_memsize;
 	/* first check CRTCs */
-	if (ASIC_IS_DCE41(rdev)) {
+	if (ASIC_IS_DCE4(rdev)) {
 		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
-			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
-		if (reg & EVERGREEN_CRTC_MASTER_EN)
-			return true;
+			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
-	} else if (ASIC_IS_DCE4(rdev)) {
+			if (rdev->num_crtc >= 4) {
-		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
-			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
+				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
-			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+			}
-			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
+			if (rdev->num_crtc >= 6) {
-			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 		if (reg & EVERGREEN_CRTC_MASTER_EN)
 			return true;
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 		if (reg & RADEON_CRTC_EN) {
 			return true;
+		}
+	}
 check_memsize:
 	/* then check MEM_SIZE, in case the crtcs are off */
 	if (rdev->family >= CHIP_R600)
 		reg = RREG32(R600_CONFIG_MEMSIZE);
 	else
 	atom_card_info->mc_write = cail_mc_write;
 	atom_card_info->pll_read = cail_pll_read;
 	atom_card_info->pll_write = cail_pll_write;
+	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
+	if (!rdev->mode_info.atom_context) {
+		radeon_atombios_fini(rdev);
+		return -ENOMEM;
+	}
 	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 	mutex_init(&rdev->mode_info.atom_context->mutex);
     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
     return 0;
  */
 void radeon_atombios_fini(struct radeon_device *rdev)
+{
 	if (rdev->mode_info.atom_context) {
 		kfree(rdev->mode_info.atom_context->scratch);
-	kfree(rdev->mode_info.atom_context);
+	}
+	kfree(rdev->mode_info.atom_context);
+	rdev->mode_info.atom_context = NULL;
 	kfree(rdev->mode_info.atom_card_info);
+	rdev->mode_info.atom_card_info = NULL;
+}
 /* COMBIOS */
 /*
 	mutex_init(&rdev->dc_hw_i2c_mutex);
 	atomic_set(&rdev->ih.lock, 0);
 	mutex_init(&rdev->gem.mutex);
 	mutex_init(&rdev->pm.mutex);
 	mutex_init(&rdev->gpu_clock_mutex);
-	init_rwsem(&rdev->pm.mclk_lock);
+//   init_rwsem(&rdev->pm.mclk_lock);
-	init_rwsem(&rdev->exclusive_lock);
+//   init_rwsem(&rdev->exclusive_lock);
 	init_waitqueue_head(&rdev->irq.vblank_queue);
 	r = radeon_gem_init(rdev);
 	if (r)
 		return r;
 	/* initialize vm here */
 	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 		radeon_agp_disable(rdev);
+    }
+	/* Set the internal MC address mask
+	 * This is the max address of the GPU's
+	 * internal address space.
+	 */
+	if (rdev->family >= CHIP_CAYMAN)
+		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
+	else if (rdev->family >= CHIP_CEDAR)
+		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
+	else
 		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits
         dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
         radeon_resume(rdev);
+    }
-    radeon_restore_bios_scratch_regs(rdev);
-    drm_helper_resume_force_mode(rdev->ddev);
+    radeon_restore_bios_scratch_regs(rdev);
     if (!r) {
         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
+{
     struct radeon_device *rdev;
     int r;
     ENTER();
     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
     if (rdev == NULL) {
 int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
     static struct drm_device *dev;
     int ret;
-    ENTER();
     dev = kzalloc(sizeof(*dev), 0);
     if (!dev)
         return -ENOMEM;
         init_display_kms(dev->dev_private, &usermode);
     else
         init_display(dev->dev_private, &usermode);
     LEAVE();
     return 0;
                        inp, io->inp_size);
             check_input(sizeof(videomode_t));
             if( radeon_modeset )
                 retval = set_user_mode((videomode_t*)inp);
             break;
+/*
         case SRV_GET_CAPS:
             retval = get_driver_caps((hwcaps_t*)inp);
             break;
             break;
         case SRV_BLIT_BITMAP:
             srv_blit_bitmap( inp[0], inp[1], inp[2],
                         inp[3], inp[4], inp[5], inp[6]);
 */
     };
     if( cmdline && *cmdline )
         parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
     if(!dbg_open(log))
     {
-        strcpy(log, "/TMP1/1/atikms.log");
+        strcpy(log, "/TMP1/1/ati.log");
         if(!dbg_open(log))
+        {
             printf("Can't open %s\nExit\n", log);
             return 0;
         };
+    }
+    dbgprintf("Radeon v3.10 preview-1 cmdline %s\n", cmdline);
-    dbgprintf("Radeon RC13 cmdline %s\n", cmdline);
+    cpu_detect();
     };
     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
+                                device.pci_dev.device);
-                                device.pci_dev.device);
+    drm_global_init();
     err = drm_get_dev(&device.pci_dev, ent);
             ret = 1;
+    }
     return ret;
+}
-unsigned int hweight32(unsigned int w)
-{
-    unsigned int res = w - ((w >> 1) & 0x55555555);
-    res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
-    res = (res + (res >> 4)) & 0x0F0F0F0F;
-    res = res + (res >> 8);
-    return (res + (res >> 16)) & 0x000000FF;
-}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_device.c – Rev 3192 → 3764