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Line 37... | Line 37... | ||
37 | #include "display.h" |
37 | #include "display.h" |
Line 38... | Line 38... | ||
38 | 38 | ||
Line -... | Line 39... | ||
- | 39 | #include |
|
- | 40 | ||
39 | #include |
41 | |
40 | 42 | int radeon_no_wb; |
|
41 | 43 | int radeon_modeset = -1; |
|
- | 44 | int radeon_dynclks = -1; |
|
42 | int radeon_dynclks = -1; |
45 | int radeon_r4xx_atom = 0; |
43 | int radeon_r4xx_atom = 0; |
46 | int radeon_agpmode = 0; |
- | 47 | int radeon_vram_limit = 0; |
|
44 | int radeon_agpmode = -1; |
48 | int radeon_gart_size = 512; /* default gart size */ |
45 | int radeon_gart_size = 512; /* default gart size */ |
- | |
46 | int radeon_benchmarking = 0; |
49 | int radeon_benchmarking = 0; |
47 | int radeon_connector_table = 0; |
50 | int radeon_testing = 0; |
48 | int radeon_tv = 0; |
51 | int radeon_connector_table = 0; |
49 | int radeon_modeset = 1; |
52 | int radeon_tv = 1; |
- | 53 | int radeon_new_pll = -1; |
|
Line 50... | Line 54... | ||
50 | int radeon_new_pll = 1; |
54 | int radeon_dynpm = -1; |
Line 51... | Line 55... | ||
51 | int radeon_vram_limit = 0; |
55 | int radeon_audio = 1; |
52 | int radeon_audio = 0; |
56 | |
Line 133... | Line 137... | ||
133 | return; |
137 | return; |
134 | } |
138 | } |
135 | } |
139 | } |
136 | } |
140 | } |
Line 137... | Line 141... | ||
137 | 141 | ||
- | 142 | /** |
|
- | 143 | * radeon_vram_location - try to find VRAM location |
|
- | 144 | * @rdev: radeon device structure holding all necessary informations |
|
- | 145 | * @mc: memory controller structure holding memory informations |
|
- | 146 | * @base: base address at which to put VRAM |
|
- | 147 | * |
|
- | 148 | * Function will place try to place VRAM at base address provided |
|
- | 149 | * as parameter (which is so far either PCI aperture address or |
|
- | 150 | * for IGP TOM base address). |
|
- | 151 | * |
|
- | 152 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
|
- | 153 | * address space then we limit the VRAM size to the aperture. |
|
- | 154 | * |
|
- | 155 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
|
- | 156 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
|
- | 157 | * size and print a warning. |
|
- | 158 | * |
|
- | 159 | * This function will never fails, worst case are limiting VRAM. |
|
- | 160 | * |
|
138 | /* |
161 | * Note: GTT start, end, size should be initialized before calling this |
- | 162 | * function on AGP platform. |
|
- | 163 | * |
|
- | 164 | * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, |
|
- | 165 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
|
- | 166 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
|
- | 167 | * not IGP. |
|
- | 168 | * |
|
- | 169 | * Note: we use mc_vram_size as on some board we need to program the mc to |
|
- | 170 | * cover the whole aperture even if VRAM size is inferior to aperture size |
|
- | 171 | * Novell bug 204882 + along with lots of ubuntu ones |
|
- | 172 | * |
|
- | 173 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
|
- | 174 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
|
- | 175 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
|
- | 176 | * ones) |
|
- | 177 | * |
|
- | 178 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
|
- | 179 | * explicitly check for that thought. |
|
- | 180 | * |
|
139 | * MC common functions |
181 | * FIXME: when reducing VRAM size align new size on power of 2. |
140 | */ |
182 | */ |
141 | int radeon_mc_setup(struct radeon_device *rdev) |
183 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
142 | { |
184 | { |
- | 185 | mc->vram_start = base; |
|
- | 186 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
|
- | 187 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
|
- | 188 | mc->real_vram_size = mc->aper_size; |
|
- | 189 | mc->mc_vram_size = mc->aper_size; |
|
- | 190 | } |
|
- | 191 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
|
- | 192 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { |
|
- | 193 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
|
- | 194 | mc->real_vram_size = mc->aper_size; |
|
- | 195 | mc->mc_vram_size = mc->aper_size; |
|
- | 196 | } |
|
- | 197 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
|
- | 198 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
|
- | 199 | mc->mc_vram_size >> 20, mc->vram_start, |
|
- | 200 | mc->vram_end, mc->real_vram_size >> 20); |
|
143 | uint32_t tmp; |
201 | } |
- | 202 | ||
- | 203 | /** |
|
- | 204 | * radeon_gtt_location - try to find GTT location |
|
144 | 205 | * @rdev: radeon device structure holding all necessary informations |
|
- | 206 | * @mc: memory controller structure holding memory informations |
|
145 | /* Some chips have an "issue" with the memory controller, the |
207 | * |
- | 208 | * Function will place try to place GTT before or after VRAM. |
|
146 | * location must be aligned to the size. We just align it down, |
209 | * |
147 | * too bad if we walk over the top of system memory, we don't |
210 | * If GTT size is bigger than space left then we ajust GTT size. |
- | 211 | * Thus function will never fails. |
|
148 | * use DMA without a remapped anyway. |
212 | * |
149 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
213 | * FIXME: when reducing GTT size align new size on power of 2. |
150 | */ |
214 | */ |
151 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
- | |
152 | */ |
215 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
153 | /* |
- | |
154 | * Note: from R6xx the address space is 40bits but here we only |
- | |
155 | * use 32bits (still have to see a card which would exhaust 4G |
216 | { |
156 | * address space). |
217 | u64 size_af, size_bf; |
157 | */ |
- | |
158 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
- | |
159 | /* vram location was already setup try to put gtt after |
- | |
160 | * if it fits */ |
- | |
161 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
- | |
162 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
218 | |
163 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
- | |
164 | rdev->mc.gtt_location = tmp; |
- | |
165 | } else { |
- | |
166 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
- | |
167 | printk(KERN_ERR "[drm] GTT too big to fit " |
- | |
168 | "before or after vram location.\n"); |
- | |
169 | return -EINVAL; |
- | |
170 | } |
219 | size_af = 0xFFFFFFFF - mc->vram_end; |
171 | rdev->mc.gtt_location = 0; |
- | |
172 | } |
- | |
173 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
- | |
174 | /* gtt location was already setup try to put vram before |
220 | size_bf = mc->vram_start; |
175 | * if it fits */ |
- | |
176 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
- | |
177 | rdev->mc.vram_location = 0; |
- | |
178 | } else { |
- | |
179 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
221 | if (size_bf > size_af) { |
180 | tmp += (rdev->mc.mc_vram_size - 1); |
222 | if (mc->gtt_size > size_bf) { |
181 | tmp &= ~(rdev->mc.mc_vram_size - 1); |
- | |
182 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { |
- | |
183 | rdev->mc.vram_location = tmp; |
- | |
184 | } else { |
- | |
185 | printk(KERN_ERR "[drm] vram too big to fit " |
- | |
186 | "before or after GTT location.\n"); |
223 | dev_warn(rdev->dev, "limiting GTT\n"); |
187 | return -EINVAL; |
- | |
188 | } |
224 | mc->gtt_size = size_bf; |
- | 225 | } |
|
189 | } |
226 | mc->gtt_start = mc->vram_start - mc->gtt_size; |
190 | } else { |
227 | } else { |
191 | rdev->mc.vram_location = 0; |
228 | if (mc->gtt_size > size_af) { |
192 | tmp = rdev->mc.mc_vram_size; |
- | |
193 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
229 | dev_warn(rdev->dev, "limiting GTT\n"); |
194 | rdev->mc.gtt_location = tmp; |
230 | mc->gtt_size = size_af; |
195 | } |
- | |
196 | rdev->mc.vram_start = rdev->mc.vram_location; |
- | |
197 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
231 | } |
- | 232 | mc->gtt_start = mc->vram_end + 1; |
|
198 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
233 | } |
199 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
- | |
200 | DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); |
- | |
201 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
- | |
202 | (unsigned)rdev->mc.vram_location, |
- | |
203 | (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); |
- | |
204 | DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); |
234 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
205 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
- | |
206 | (unsigned)rdev->mc.gtt_location, |
235 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", |
207 | (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); |
- | |
208 | return 0; |
236 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
Line 209... | Line -... | ||
209 | } |
- | |
210 | 237 | } |
|
211 | 238 | ||
212 | /* |
239 | /* |
213 | * GPU helpers function. |
240 | * GPU helpers function. |
214 | */ |
241 | */ |
215 | bool radeon_card_posted(struct radeon_device *rdev) |
242 | bool radeon_card_posted(struct radeon_device *rdev) |
Line 216... | Line 243... | ||
216 | { |
243 | { |
217 | uint32_t reg; |
244 | uint32_t reg; |
- | 245 | ||
- | 246 | /* first check CRTCs */ |
|
- | 247 | if (ASIC_IS_DCE4(rdev)) { |
|
- | 248 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
|
- | 249 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
|
- | 250 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
|
- | 251 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
|
- | 252 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
|
- | 253 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
|
218 | 254 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
|
219 | /* first check CRTCs */ |
255 | return true; |
220 | if (ASIC_IS_AVIVO(rdev)) { |
256 | } else if (ASIC_IS_AVIVO(rdev)) { |
221 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
257 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
222 | RREG32(AVIVO_D2CRTC_CONTROL); |
258 | RREG32(AVIVO_D2CRTC_CONTROL); |
Line 262... | Line 298... | ||
262 | } |
298 | } |
263 | } |
299 | } |
Line 264... | Line 300... | ||
264 | 300 | ||
265 | int radeon_dummy_page_init(struct radeon_device *rdev) |
301 | int radeon_dummy_page_init(struct radeon_device *rdev) |
- | 302 | { |
|
- | 303 | if (rdev->dummy_page.page) |
|
266 | { |
304 | return 0; |
267 | rdev->dummy_page.page = AllocPage(); |
305 | rdev->dummy_page.page = AllocPage(); |
268 | if (rdev->dummy_page.page == NULL) |
306 | if (rdev->dummy_page.page == NULL) |
269 | return -ENOMEM; |
307 | return -ENOMEM; |
270 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
308 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
Line 340... | Line 378... | ||
340 | } |
378 | } |
341 | if (rdev->family == CHIP_RS600) { |
379 | if (rdev->family == CHIP_RS600) { |
342 | rdev->mc_rreg = &rs600_mc_rreg; |
380 | rdev->mc_rreg = &rs600_mc_rreg; |
343 | rdev->mc_wreg = &rs600_mc_wreg; |
381 | rdev->mc_wreg = &rs600_mc_wreg; |
344 | } |
382 | } |
345 | if (rdev->family >= CHIP_R600) { |
383 | if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { |
346 | rdev->pciep_rreg = &r600_pciep_rreg; |
384 | rdev->pciep_rreg = &r600_pciep_rreg; |
347 | rdev->pciep_wreg = &r600_pciep_wreg; |
385 | rdev->pciep_wreg = &r600_pciep_wreg; |
348 | } |
386 | } |
349 | } |
387 | } |
Line 359... | Line 397... | ||
359 | case CHIP_R100: |
397 | case CHIP_R100: |
360 | case CHIP_RV100: |
398 | case CHIP_RV100: |
361 | case CHIP_RS100: |
399 | case CHIP_RS100: |
362 | case CHIP_RV200: |
400 | case CHIP_RV200: |
363 | case CHIP_RS200: |
401 | case CHIP_RS200: |
- | 402 | rdev->asic = &r100_asic; |
|
- | 403 | break; |
|
364 | case CHIP_R200: |
404 | case CHIP_R200: |
365 | case CHIP_RV250: |
405 | case CHIP_RV250: |
366 | case CHIP_RS300: |
406 | case CHIP_RS300: |
367 | case CHIP_RV280: |
407 | case CHIP_RV280: |
368 | rdev->asic = &r100_asic; |
408 | rdev->asic = &r200_asic; |
369 | break; |
409 | break; |
370 | case CHIP_R300: |
410 | case CHIP_R300: |
371 | case CHIP_R350: |
411 | case CHIP_R350: |
372 | case CHIP_RV350: |
412 | case CHIP_RV350: |
373 | case CHIP_RV380: |
413 | case CHIP_RV380: |
- | 414 | if (rdev->flags & RADEON_IS_PCIE) |
|
- | 415 | rdev->asic = &r300_asic_pcie; |
|
- | 416 | else |
|
374 | rdev->asic = &r300_asic; |
417 | rdev->asic = &r300_asic; |
375 | if (rdev->flags & RADEON_IS_PCIE) { |
- | |
376 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
- | |
377 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
- | |
378 | } |
- | |
379 | break; |
418 | break; |
380 | case CHIP_R420: |
419 | case CHIP_R420: |
381 | case CHIP_R423: |
420 | case CHIP_R423: |
382 | case CHIP_RV410: |
421 | case CHIP_RV410: |
383 | rdev->asic = &r420_asic; |
422 | rdev->asic = &r420_asic; |
Line 417... | Line 456... | ||
417 | case CHIP_RV730: |
456 | case CHIP_RV730: |
418 | case CHIP_RV710: |
457 | case CHIP_RV710: |
419 | case CHIP_RV740: |
458 | case CHIP_RV740: |
420 | rdev->asic = &rv770_asic; |
459 | rdev->asic = &rv770_asic; |
421 | break; |
460 | break; |
- | 461 | case CHIP_CEDAR: |
|
- | 462 | case CHIP_REDWOOD: |
|
- | 463 | case CHIP_JUNIPER: |
|
- | 464 | case CHIP_CYPRESS: |
|
- | 465 | case CHIP_HEMLOCK: |
|
- | 466 | rdev->asic = &evergreen_asic; |
|
- | 467 | break; |
|
422 | default: |
468 | default: |
423 | /* FIXME: not supported yet */ |
469 | /* FIXME: not supported yet */ |
424 | return -EINVAL; |
470 | return -EINVAL; |
425 | } |
471 | } |
Line 712... | Line 758... | ||
712 | } |
758 | } |
713 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
759 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
714 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
760 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
Line 715... | Line 761... | ||
715 | 761 | ||
- | 762 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
|
- | 763 | /* this will fail for cards that aren't VGA class devices, just |
|
716 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
764 | * ignore it */ |
717 | // r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
765 | // r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
718 | // if (r) { |
766 | // if (r) { |
719 | // return -EINVAL; |
767 | // return -EINVAL; |
Line 984... | Line 1032... | ||
984 | { |
1032 | { |
985 | printf("Can't open %s\nExit\n", log); |
1033 | printf("Can't open %s\nExit\n", log); |
986 | return 0; |
1034 | return 0; |
987 | }; |
1035 | }; |
988 | } |
1036 | } |
989 | dbgprintf("Radeon RC9 cmdline %s\n", cmdline); |
1037 | dbgprintf("Radeon RC10 cmdline %s\n", cmdline); |
Line 990... | Line 1038... | ||
990 | 1038 | ||
Line 991... | Line 1039... | ||
991 | enum_pci_devices(); |
1039 | enum_pci_devices(); |
Line 1006... | Line 1054... | ||
1006 | rdev = rdisplay->ddev->dev_private; |
1054 | rdev = rdisplay->ddev->dev_private; |
Line 1007... | Line 1055... | ||
1007 | 1055 | ||
1008 | if( (rdev->asic == &r600_asic) || |
1056 | if( (rdev->asic == &r600_asic) || |
1009 | (rdev->asic == &rv770_asic)) |
1057 | (rdev->asic == &rv770_asic)) |
1010 | r600_2D_test(rdev); |
1058 | r600_2D_test(rdev); |
1011 | else |
1059 | else if (rdev->asic != &evergreen_asic) |
Line 1012... | Line 1060... | ||
1012 | r100_2D_test(rdev); |
1060 | r100_2D_test(rdev); |
Line 1013... | Line 1061... | ||
1013 | 1061 | ||
1014 | err = RegService("DISPLAY", display_handler); |
1062 | err = RegService("DISPLAY", display_handler); |
Line 1015... | Line 1063... | ||
1015 | 1063 | ||
1016 | if( err != 0) |
1064 | if( err != 0) |
- | 1065 | dbgprintf("Set DISPLAY handler\n"); |
|
- | 1066 | ||
- | 1067 | return err; |
|
- | 1068 | }; |
|
- | 1069 | ||
- | 1070 | void drm_vblank_post_modeset(struct drm_device *dev, int crtc) |
|
- | 1071 | {}; |