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Rev 1313 | Rev 1321 | ||
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Line 75... | Line 75... | ||
75 | 75 | ||
76 | /* FIXME: check this out */ |
76 | /* FIXME: check this out */ |
77 | if (rdev->family < CHIP_R600) { |
77 | if (rdev->family < CHIP_R600) { |
Line 78... | Line 78... | ||
78 | int i; |
78 | int i; |
79 | 79 | ||
80 | for (i = 0; i < 8; i++) { |
80 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
- | 81 | if (rdev->surface_regs[i].bo) |
|
81 | WREG32(RADEON_SURFACE0_INFO + |
82 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
82 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
83 | else |
83 | 0); |
84 | radeon_clear_surface_reg(rdev, i); |
84 | } |
85 | } |
85 | /* enable surfaces */ |
86 | /* enable surfaces */ |
86 | WREG32(RADEON_SURFACE_CNTL, 0); |
87 | WREG32(RADEON_SURFACE_CNTL, 0); |
Line 239... | Line 240... | ||
239 | 240 | ||
Line 240... | Line 241... | ||
240 | return false; |
241 | return false; |
Line -... | Line 242... | ||
- | 242 | ||
- | 243 | } |
|
- | 244 | ||
- | 245 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
|
- | 246 | { |
|
- | 247 | if (radeon_card_posted(rdev)) |
|
- | 248 | return true; |
|
- | 249 | ||
- | 250 | if (rdev->bios) { |
|
- | 251 | DRM_INFO("GPU not posted. posting now...\n"); |
|
- | 252 | if (rdev->is_atom_bios) |
|
- | 253 | atom_asic_init(rdev->mode_info.atom_context); |
|
- | 254 | else |
|
- | 255 | radeon_combios_asic_init(rdev->ddev); |
|
- | 256 | return true; |
|
- | 257 | } else { |
|
- | 258 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
|
- | 259 | return false; |
|
241 | 260 | } |
|
242 | } |
261 | } |
243 | 262 | ||
244 | int radeon_dummy_page_init(struct radeon_device *rdev) |
263 | int radeon_dummy_page_init(struct radeon_device *rdev) |
245 | { |
264 | { |
Line 491... | Line 510... | ||
491 | atom_card_info->pll_read = cail_pll_read; |
510 | atom_card_info->pll_read = cail_pll_read; |
492 | atom_card_info->pll_write = cail_pll_write; |
511 | atom_card_info->pll_write = cail_pll_write; |
Line 493... | Line 512... | ||
493 | 512 | ||
494 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
513 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
- | 514 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
|
495 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
515 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
496 | return 0; |
516 | return 0; |
Line 497... | Line 517... | ||
497 | } |
517 | } |
498 | 518 | ||
- | 519 | void radeon_atombios_fini(struct radeon_device *rdev) |
|
- | 520 | { |
|
499 | void radeon_atombios_fini(struct radeon_device *rdev) |
521 | if (rdev->mode_info.atom_context) { |
- | 522 | kfree(rdev->mode_info.atom_context->scratch); |
|
500 | { |
523 | kfree(rdev->mode_info.atom_context); |
501 | kfree(rdev->mode_info.atom_context); |
524 | } |
Line 502... | Line 525... | ||
502 | kfree(rdev->mode_info.atom_card_info); |
525 | kfree(rdev->mode_info.atom_card_info); |
503 | } |
526 | } |
Line 579... | Line 602... | ||
579 | r = radeon_asic_init(rdev); |
602 | r = radeon_asic_init(rdev); |
580 | if (r) { |
603 | if (r) { |
581 | return r; |
604 | return r; |
582 | } |
605 | } |
Line 583... | Line 606... | ||
583 | 606 | ||
584 | if (radeon_agpmode == -1) { |
607 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
585 | radeon_agp_disable(rdev); |
608 | radeon_agp_disable(rdev); |
Line 586... | Line 609... | ||
586 | } |
609 | } |
587 | 610 | ||
Line 893... | Line 916... | ||
893 | { |
916 | { |
894 | printf("Can't open %s\nExit\n", log); |
917 | printf("Can't open %s\nExit\n", log); |
895 | return 0; |
918 | return 0; |
896 | }; |
919 | }; |
897 | } |
920 | } |
898 | dbgprintf("Radeon RC08 cmdline %s\n", cmdline); |
921 | dbgprintf("Radeon RC09 cmdline %s\n", cmdline); |
Line 899... | Line 922... | ||
899 | 922 | ||
Line 900... | Line 923... | ||
900 | enum_pci_devices(); |
923 | enum_pci_devices(); |