WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_device.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
//#include 
 
#include 
//#include 
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
 
#include 
 
 
int radeon_dynclks = -1;
int radeon_r4xx_atom = 0;
 
int radeon_agpmode   = -1;
int radeon_gart_size = 512; /* default gart size */
int radeon_benchmarking = 0;
int radeon_connector_table = 0;
 
 
/*
 * Clear GPU surface registers.
 */
static void radeon_surface_init(struct radeon_device *rdev)
{
    dbgprintf("%s\n",__FUNCTION__);
 
    /* FIXME: check this out */
    if (rdev->family < CHIP_R600) {
        int i;
 
        for (i = 0; i < 8; i++) {
            WREG32(RADEON_SURFACE0_INFO +
                   i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
                   0);
        }
    }
}
 
/*
 * GPU scratch registers helpers function.
 */
static void radeon_scratch_init(struct radeon_device *rdev)
{
    int i;
 
    /* FIXME: check this out */
    if (rdev->family < CHIP_R300) {
        rdev->scratch.num_reg = 5;
    } else {
        rdev->scratch.num_reg = 7;
    }
    for (i = 0; i < rdev->scratch.num_reg; i++) {
        rdev->scratch.free[i] = true;
        rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
    }
}
 
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.free[i]) {
			rdev->scratch.free[i] = false;
			*reg = rdev->scratch.reg[i];
			return 0;
		}
	}
	return -EINVAL;
}
 
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.reg[i] == reg) {
			rdev->scratch.free[i] = true;
			return;
		}
	}
}
 
/*
 * MC common functions
 */
int radeon_mc_setup(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	/* Some chips have an "issue" with the memory controller, the
	 * location must be aligned to the size. We just align it down,
	 * too bad if we walk over the top of system memory, we don't
	 * use DMA without a remapped anyway.
	 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
	 */
	/* FGLRX seems to setup like this, VRAM a 0, then GART.
	 */
/*
	 * Note: from R6xx the address space is 40bits but here we only
	 * use 32bits (still have to see a card which would exhaust 4G
	 * address space).
	 */
	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
		/* vram location was already setup try to put gtt after
		 * if it fits */
		tmp = rdev->mc.vram_location + rdev->mc.vram_size;
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
			rdev->mc.gtt_location = tmp;
		} else {
			if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
				printk(KERN_ERR "[drm] GTT too big to fit "
				       "before or after vram location.\n");
				return -EINVAL;
			}
			rdev->mc.gtt_location = 0;
		}
	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
		/* gtt location was already setup try to put vram before
		 * if it fits */
		if (rdev->mc.vram_size < rdev->mc.gtt_location) {
			rdev->mc.vram_location = 0;
		} else {
			tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
			tmp += (rdev->mc.vram_size - 1);
			tmp &= ~(rdev->mc.vram_size - 1);
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
				rdev->mc.vram_location = tmp;
			} else {
				printk(KERN_ERR "[drm] vram too big to fit "
				       "before or after GTT location.\n");
				return -EINVAL;
			}
		}
	} else {
		rdev->mc.vram_location = 0;
		rdev->mc.gtt_location = rdev->mc.vram_size;
	}
	DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
		 rdev->mc.vram_location,
		 rdev->mc.vram_location + rdev->mc.vram_size - 1);
	DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
		 rdev->mc.gtt_location,
		 rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
	return 0;
}
 
 
/*
 * GPU helpers function.
 */
static bool radeon_card_posted(struct radeon_device *rdev)
{
	uint32_t reg;
 
    dbgprintf("%s\n",__FUNCTION__);
 
	/* first check CRTCs */
	if (ASIC_IS_AVIVO(rdev)) {
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
		      RREG32(AVIVO_D2CRTC_CONTROL);
		if (reg & AVIVO_CRTC_EN) {
			return true;
		}
	} else {
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
		      RREG32(RADEON_CRTC2_GEN_CNTL);
		if (reg & RADEON_CRTC_EN) {
			return true;
		}
	}
 
	/* then check MEM_SIZE, in case the crtcs are off */
	if (rdev->family >= CHIP_R600)
		reg = RREG32(R600_CONFIG_MEMSIZE);
	else
		reg = RREG32(RADEON_CONFIG_MEMSIZE);
 
	if (reg)
		return true;
 
	return false;
 
}
 
 
/*
 * Registers accessors functions.
 */
uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
{
    DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
    BUG_ON(1);
    return 0;
}
 
void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
    DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
          reg, v);
    BUG_ON(1);
}
 
void radeon_register_accessor_init(struct radeon_device *rdev)
{
 
    dbgprintf("%s\n",__FUNCTION__);
 
    rdev->mm_rreg = &r100_mm_rreg;
    rdev->mm_wreg = &r100_mm_wreg;
    rdev->mc_rreg = &radeon_invalid_rreg;
    rdev->mc_wreg = &radeon_invalid_wreg;
    rdev->pll_rreg = &radeon_invalid_rreg;
    rdev->pll_wreg = &radeon_invalid_wreg;
    rdev->pcie_rreg = &radeon_invalid_rreg;
    rdev->pcie_wreg = &radeon_invalid_wreg;
    rdev->pciep_rreg = &radeon_invalid_rreg;
    rdev->pciep_wreg = &radeon_invalid_wreg;
 
    /* Don't change order as we are overridding accessor. */
    if (rdev->family < CHIP_RV515) {
//        rdev->pcie_rreg = &rv370_pcie_rreg;
//        rdev->pcie_wreg = &rv370_pcie_wreg;
    }
    if (rdev->family >= CHIP_RV515) {
        rdev->pcie_rreg = &rv515_pcie_rreg;
        rdev->pcie_wreg = &rv515_pcie_wreg;
    }
    /* FIXME: not sure here */
    if (rdev->family <= CHIP_R580) {
        rdev->pll_rreg = &r100_pll_rreg;
        rdev->pll_wreg = &r100_pll_wreg;
    }
    if (rdev->family >= CHIP_RV515) {
        rdev->mc_rreg = &rv515_mc_rreg;
        rdev->mc_wreg = &rv515_mc_wreg;
    }
    if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
//        rdev->mc_rreg = &rs400_mc_rreg;
//        rdev->mc_wreg = &rs400_mc_wreg;
    }
    if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
//        rdev->mc_rreg = &rs690_mc_rreg;
//        rdev->mc_wreg = &rs690_mc_wreg;
    }
    if (rdev->family == CHIP_RS600) {
//        rdev->mc_rreg = &rs600_mc_rreg;
//        rdev->mc_wreg = &rs600_mc_wreg;
    }
    if (rdev->family >= CHIP_R600) {
//        rdev->pciep_rreg = &r600_pciep_rreg;
//        rdev->pciep_wreg = &r600_pciep_wreg;
    }
}
 
 
 
/*
 * ASIC
 */
int radeon_asic_init(struct radeon_device *rdev)
{
 
    dbgprintf("%s\n",__FUNCTION__);
 
    radeon_register_accessor_init(rdev);
	switch (rdev->family) {
	case CHIP_R100:
	case CHIP_RV100:
	case CHIP_RS100:
	case CHIP_RV200:
	case CHIP_RS200:
	case CHIP_R200:
	case CHIP_RV250:
	case CHIP_RS300:
	case CHIP_RV280:
//       rdev->asic = &r100_asic;
		break;
	case CHIP_R300:
	case CHIP_R350:
	case CHIP_RV350:
	case CHIP_RV380:
//       rdev->asic = &r300_asic;
		break;
	case CHIP_R420:
	case CHIP_R423:
	case CHIP_RV410:
//       rdev->asic = &r420_asic;
		break;
	case CHIP_RS400:
	case CHIP_RS480:
//       rdev->asic = &rs400_asic;
		break;
	case CHIP_RS600:
//       rdev->asic = &rs600_asic;
		break;
	case CHIP_RS690:
	case CHIP_RS740:
//       rdev->asic = &rs690_asic;
		break;
	case CHIP_RV515:
//       rdev->asic = &rv515_asic;
		break;
	case CHIP_R520:
	case CHIP_RV530:
	case CHIP_RV560:
	case CHIP_RV570:
	case CHIP_R580:
        rdev->asic = &r520_asic;
		break;
	case CHIP_R600:
	case CHIP_RV610:
	case CHIP_RV630:
	case CHIP_RV620:
	case CHIP_RV635:
	case CHIP_RV670:
	case CHIP_RS780:
	case CHIP_RV770:
	case CHIP_RV730:
	case CHIP_RV710:
	default:
		/* FIXME: not supported yet */
		return -EINVAL;
	}
	return 0;
}
 
 
/*
 * Wrapper around modesetting bits.
 */
int radeon_clocks_init(struct radeon_device *rdev)
{
	int r;
 
    dbgprintf("%s\n",__FUNCTION__);
 
    radeon_get_clock_info(rdev->ddev);
    r = radeon_static_clocks_init(rdev->ddev);
	if (r) {
		return r;
	}
	DRM_INFO("Clocks initialized !\n");
	return 0;
}
 
void radeon_clocks_fini(struct radeon_device *rdev)
{
}
 
/* ATOM accessor methods */
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->pll_rreg(rdev, reg);
    return r;
}
 
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->pll_wreg(rdev, reg, val);
}
 
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->mc_rreg(rdev, reg);
    return r;
}
 
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->mc_wreg(rdev, reg, val);
}
 
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    WREG32(reg*4, val);
}
 
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = RREG32(reg*4);
    return r;
}
 
static struct card_info atom_card_info = {
    .dev = NULL,
    .reg_read = cail_reg_read,
    .reg_write = cail_reg_write,
    .mc_read = cail_mc_read,
    .mc_write = cail_mc_write,
    .pll_read = cail_pll_read,
    .pll_write = cail_pll_write,
};
 
int radeon_atombios_init(struct radeon_device *rdev)
{
    dbgprintf("%s\n",__FUNCTION__);
 
    atom_card_info.dev = rdev->ddev;
    rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
    return 0;
}
 
void radeon_atombios_fini(struct radeon_device *rdev)
{
	kfree(rdev->mode_info.atom_context);
}
 
int radeon_combios_init(struct radeon_device *rdev)
{
//	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
	return 0;
}
 
void radeon_combios_fini(struct radeon_device *rdev)
{
}
 
int radeon_modeset_init(struct radeon_device *rdev);
void radeon_modeset_fini(struct radeon_device *rdev);
 
/*
 * Radeon device.
 */
int radeon_device_init(struct radeon_device *rdev,
               struct drm_device *ddev,
               struct pci_dev *pdev,
               uint32_t flags)
{
    int r, ret = -1;
 
    dbgprintf("%s\n",__FUNCTION__);
 
    DRM_INFO("radeon: Initializing kernel modesetting.\n");
    rdev->shutdown = false;
    rdev->ddev = ddev;
    rdev->pdev = pdev;
    rdev->flags = flags;
    rdev->family = flags & RADEON_FAMILY_MASK;
    rdev->is_atom_bios = false;
    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
    rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
    rdev->gpu_lockup = false;
    /* mutex initialization are all done here so we
     * can recall function without having locking issues */
 //   mutex_init(&rdev->cs_mutex);
 //   mutex_init(&rdev->ib_pool.mutex);
 //   mutex_init(&rdev->cp.mutex);
 //   rwlock_init(&rdev->fence_drv.lock);
 
 
    if (radeon_agpmode == -1) {
        rdev->flags &= ~RADEON_IS_AGP;
        if (rdev->family > CHIP_RV515 ||
            rdev->family == CHIP_RV380 ||
            rdev->family == CHIP_RV410 ||
            rdev->family == CHIP_R423) {
            DRM_INFO("Forcing AGP to PCIE mode\n");
            rdev->flags |= RADEON_IS_PCIE;
        } else {
            DRM_INFO("Forcing AGP to PCI mode\n");
            rdev->flags |= RADEON_IS_PCI;
        }
    }
 
    /* Set asic functions */
    r = radeon_asic_init(rdev);
    if (r) {
        return r;
    }
 
 
    r = rdev->asic->init(rdev);
 
    if (r) {
        return r;
    }
 
    /* Report DMA addressing limitation */
    r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
    if (r) {
        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
    }
 
    /* Registers mapping */
    /* TODO: block userspace mapping of io register */
    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 
    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 
    rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
                                   PG_SW+PG_NOCACHE);
 
    if (rdev->rmmio == NULL) {
        return -ENOMEM;
    }
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 
    /* Setup errata flags */
    radeon_errata(rdev);
    /* Initialize scratch registers */
    radeon_scratch_init(rdev);
	/* Initialize surface registers */
    radeon_surface_init(rdev);
 
    /* TODO: disable VGA need to use VGA request */
    /* BIOS*/
    if (!radeon_get_bios(rdev)) {
        if (ASIC_IS_AVIVO(rdev))
            return -EINVAL;
    }
    if (rdev->is_atom_bios) {
        r = radeon_atombios_init(rdev);
        if (r) {
            return r;
        }
    } else {
        r = radeon_combios_init(rdev);
        if (r) {
            return r;
        }
    }
    /* Reset gpu before posting otherwise ATOM will enter infinite loop */
    if (radeon_gpu_reset(rdev)) {
        /* FIXME: what do we want to do here ? */
    }
    /* check if cards are posted or not */
    if (!radeon_card_posted(rdev) && rdev->bios) {
        DRM_INFO("GPU not posted. posting now...\n");
        if (rdev->is_atom_bios) {
            atom_asic_init(rdev->mode_info.atom_context);
        } else {
    //        radeon_combios_asic_init(rdev->ddev);
        }
    }
 
    /* Get vram informations */
    radeon_vram_info(rdev);
    /* Device is severly broken if aper size > vram size.
     * for RN50/M6/M7 - Novell bug 204882 ?
     */
    if (rdev->mc.vram_size < rdev->mc.aper_size) {
        rdev->mc.aper_size = rdev->mc.vram_size;
    }
    /* Add an MTRR for the VRAM */
//    rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
//                      MTRR_TYPE_WRCOMB, 1);
    DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
         rdev->mc.vram_size >> 20,
         (unsigned)rdev->mc.aper_size >> 20);
    DRM_INFO("RAM width %dbits %cDR\n",
         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 
    /* Initialize clocks */
    r = radeon_clocks_init(rdev);
    if (r) {
        return r;
    }
 
    /* Initialize memory controller (also test AGP) */
    r = radeon_mc_init(rdev);
    if (r) {
        return r;
    };
 
 
    /* Fence driver */
//    r = radeon_fence_driver_init(rdev);
//    if (r) {
//        return r;
//    }
//    r = radeon_irq_kms_init(rdev);
//    if (r) {
//        return r;
//    }
    /* Memory manager */
    r = radeon_object_init(rdev);
    if (r) {
        return r;
    }
    /* Initialize GART (initialize after TTM so we can allocate
     * memory through TTM but finalize after TTM) */
    r = radeon_gart_enable(rdev);
//    if (!r) {
//        r = radeon_gem_init(rdev);
//    }
 
    /* 1M ring buffer */
    if (!r) {
        r = radeon_cp_init(rdev, 1024 * 1024);
    }
//    if (!r) {
//        r = radeon_wb_init(rdev);
//        if (r) {
//            DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
//            return r;
//        }
//    }
 
#if 0
    if (!r) {
        r = radeon_ib_pool_init(rdev);
        if (r) {
            DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
            return r;
        }
    }
 
 
    if (!r) {
        r = radeon_ib_test(rdev);
        if (r) {
            DRM_ERROR("radeon: failled testing IB (%d).\n", r);
            return r;
        }
    }
#endif
 
    ret = r;
    r = radeon_modeset_init(rdev);
    if (r) {
        return r;
    }
//    if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
//        rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
//    }
    if (!ret) {
        DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
    }
//    if (radeon_benchmarking) {
//        radeon_benchmark(rdev);
//    }
 
 
 
    return -1;
}
 
static struct pci_device_id pciidlist[] = {
    radeon_PCI_IDS
};
 
 
u32_t __stdcall drvEntry(int action)
{
    struct pci_device_id  *ent;
 
    dev_t   device;
    int     err;
    u32_t   retval = 0;
 
    if(action != 1)
        return 0;
 
    if(!dbg_open("/hd0/2/atikms.log"))
    {
        printf("Can't open /hd0/2/atikms.log\nExit\n");
        return 0;
    }
 
    enum_pci_devices();
 
    ent = find_pci_device(&device, pciidlist);
 
    if( unlikely(ent == NULL) )
    {
        dbgprintf("device not found\n");
        return 0;
    };
 
    dbgprintf("device %x:%x\n", device.pci_dev.vendor,
                                device.pci_dev.device);
 
    err = drm_get_dev(&device.pci_dev, ent);
 
    return retval;
};
 
/*
static struct drm_driver kms_driver = {
    .driver_features =
        DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
        DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM,
    .dev_priv_size = 0,
    .load = radeon_driver_load_kms,
    .firstopen = radeon_driver_firstopen_kms,
    .open = radeon_driver_open_kms,
    .preclose = radeon_driver_preclose_kms,
    .postclose = radeon_driver_postclose_kms,
    .lastclose = radeon_driver_lastclose_kms,
    .unload = radeon_driver_unload_kms,
    .suspend = radeon_suspend_kms,
    .resume = radeon_resume_kms,
    .get_vblank_counter = radeon_get_vblank_counter_kms,
    .enable_vblank = radeon_enable_vblank_kms,
    .disable_vblank = radeon_disable_vblank_kms,
    .master_create = radeon_master_create_kms,
    .master_destroy = radeon_master_destroy_kms,
#if defined(CONFIG_DEBUG_FS)
    .debugfs_init = radeon_debugfs_init,
    .debugfs_cleanup = radeon_debugfs_cleanup,
#endif
    .irq_preinstall = radeon_driver_irq_preinstall_kms,
    .irq_postinstall = radeon_driver_irq_postinstall_kms,
    .irq_uninstall = radeon_driver_irq_uninstall_kms,
    .irq_handler = radeon_driver_irq_handler_kms,
    .reclaim_buffers = drm_core_reclaim_buffers,
    .get_map_ofs = drm_core_get_map_ofs,
    .get_reg_ofs = drm_core_get_reg_ofs,
    .ioctls = radeon_ioctls_kms,
    .gem_init_object = radeon_gem_object_init,
    .gem_free_object = radeon_gem_object_free,
    .dma_ioctl = radeon_dma_ioctl_kms,
    .fops = {
         .owner = THIS_MODULE,
         .open = drm_open,
         .release = drm_release,
         .ioctl = drm_ioctl,
         .mmap = radeon_mmap,
         .poll = drm_poll,
         .fasync = drm_fasync,
#ifdef CONFIG_COMPAT
         .compat_ioctl = NULL,
#endif
    },
 
    .pci_driver = {
         .name = DRIVER_NAME,
         .id_table = pciidlist,
         .probe = radeon_pci_probe,
         .remove = radeon_pci_remove,
         .suspend = radeon_pci_suspend,
         .resume = radeon_pci_resume,
    },
 
    .name = DRIVER_NAME,
    .desc = DRIVER_DESC,
    .date = DRIVER_DATE,
    .major = KMS_DRIVER_MAJOR,
    .minor = KMS_DRIVER_MINOR,
    .patchlevel = KMS_DRIVER_PATCHLEVEL,
};
*/
 
 
/*
 * Driver load/unload
 */
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
    struct radeon_device *rdev;
    int r;
 
    dbgprintf("%s\n",__FUNCTION__);
 
    rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
    if (rdev == NULL) {
        return -ENOMEM;
    };
 
    dev->dev_private = (void *)rdev;
 
    /* update BUS flag */
//    if (drm_device_is_agp(dev)) {
        flags |= RADEON_IS_AGP;
//    } else if (drm_device_is_pcie(dev)) {
//        flags |= RADEON_IS_PCIE;
//    } else {
//        flags |= RADEON_IS_PCI;
//    }
 
    r = radeon_device_init(rdev, dev, dev->pdev, flags);
    if (r) {
        dbgprintf("Failed to initialize Radeon, disabling IOCTL\n");
//        radeon_device_fini(rdev);
        return r;
    }
    return 0;
}
 
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
    struct drm_device *dev;
    int ret;
 
    dbgprintf("%s\n",__FUNCTION__);
 
    dev = malloc(sizeof(*dev));
    if (!dev)
        return -ENOMEM;
 
 //   ret = pci_enable_device(pdev);
 //   if (ret)
 //       goto err_g1;
 
 //   pci_set_master(pdev);
 
 //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
 //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
 //       goto err_g2;
 //   }
 
    dev->pdev = pdev;
    dev->pci_device = pdev->device;
    dev->pci_vendor = pdev->vendor;
 
 //   if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 //       pci_set_drvdata(pdev, dev);
 //       ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
 //       if (ret)
 //           goto err_g2;
 //   }
 
 //   if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
 //       goto err_g3;
 
 //   if (dev->driver->load) {
 //       ret = dev->driver->load(dev, ent->driver_data);
 //       if (ret)
 //           goto err_g4;
 //   }
 
      ret = radeon_driver_load_kms(dev, ent->driver_data );
      if (ret)
        goto err_g4;
 
 //   list_add_tail(&dev->driver_item, &driver->device_list);
 
 //   DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
 //        driver->name, driver->major, driver->minor, driver->patchlevel,
 //        driver->date, pci_name(pdev), dev->primary->index);
 
    return 0;
 
err_g4:
//    drm_put_minor(&dev->primary);
//err_g3:
//    if (drm_core_check_feature(dev, DRIVER_MODESET))
//        drm_put_minor(&dev->control);
//err_g2:
//    pci_disable_device(pdev);
//err_g1:
    free(dev);
 
    return ret;
}
 
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_start(dev->pdev, resource);
}
 
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_len(dev->pdev, resource);
}
 
 
uint32_t __div64_32(uint64_t *n, uint32_t base)
{
        uint64_t rem = *n;
        uint64_t b = base;
        uint64_t res, d = 1;
        uint32_t high = rem >> 32;
 
        /* Reduce the thing a bit first */
        res = 0;
        if (high >= base) {
                high /= base;
                res = (uint64_t) high << 32;
                rem -= (uint64_t) (high*base) << 32;
        }
 
        while ((int64_t)b > 0 && b < rem) {
                b = b+b;
                d = d+d;
        }
 
        do {
                if (rem >= b) {
                        rem -= b;
                        res += d;
                }
                b >>= 1;
                d >>= 1;
        } while (d);
 
        *n = res;
        return rem;
}

Rev 1123	Rev 1125
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	//#include	28	//#include
29		29
30	#include	30	#include
31	//#include	31	//#include
32	#include "radeon_drm.h"	32	#include "radeon_drm.h"
33	#include "radeon_reg.h"	33	#include "radeon_reg.h"
34	#include "radeon.h"	34	#include "radeon.h"
35	#include "radeon_asic.h"	35	#include "radeon_asic.h"
36	#include "atom.h"	36	#include "atom.h"
37		37
38	#include	38	#include
39		-
40	int radeon_modeset = -1;	39
41	int radeon_dynclks = -1;	40	int radeon_dynclks = -1;
42	int radeon_r4xx_atom = 0;	41	int radeon_r4xx_atom = 0;
43	int radeon_agpmode = 0;	-
44	int radeon_vram_limit = 0;	42	int radeon_agpmode = -1;
45	int radeon_gart_size = 512; /* default gart size */	43	int radeon_gart_size = 512; /* default gart size */
46	int radeon_benchmarking = 0;	44	int radeon_benchmarking = 0;
47	int radeon_connector_table = 0;	45	int radeon_connector_table = 0;
48		46
49		47
50	/*	48	/*
51	* Clear GPU surface registers.	49	* Clear GPU surface registers.
52	*/	50	*/
53	static void radeon_surface_init(struct radeon_device *rdev)	51	static void radeon_surface_init(struct radeon_device *rdev)
54	{	52	{
55	dbgprintf("%s\n",__FUNCTION__);	53	dbgprintf("%s\n",__FUNCTION__);
56		54
57	/* FIXME: check this out */	55	/* FIXME: check this out */
58	if (rdev->family < CHIP_R600) {	56	if (rdev->family < CHIP_R600) {
59	int i;	57	int i;
60		58
61	for (i = 0; i < 8; i++) {	59	for (i = 0; i < 8; i++) {
62	WREG32(RADEON_SURFACE0_INFO +	60	WREG32(RADEON_SURFACE0_INFO +
63	i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),	61	i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
64	0);	62	0);
65	}	63	}
66	}	64	}
67	}	65	}
68		66
69	/*	67	/*
70	* GPU scratch registers helpers function.	68	* GPU scratch registers helpers function.
71	*/	69	*/
72	static void radeon_scratch_init(struct radeon_device *rdev)	70	static void radeon_scratch_init(struct radeon_device *rdev)
73	{	71	{
74	int i;	72	int i;
75		73
76	/* FIXME: check this out */	74	/* FIXME: check this out */
77	if (rdev->family < CHIP_R300) {	75	if (rdev->family < CHIP_R300) {
78	rdev->scratch.num_reg = 5;	76	rdev->scratch.num_reg = 5;
79	} else {	77	} else {
80	rdev->scratch.num_reg = 7;	78	rdev->scratch.num_reg = 7;
81	}	79	}
82	for (i = 0; i < rdev->scratch.num_reg; i++) {	80	for (i = 0; i < rdev->scratch.num_reg; i++) {
83	rdev->scratch.free[i] = true;	81	rdev->scratch.free[i] = true;
84	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);	82	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
85	}	83	}
86	}	84	}
87		85
88	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)	86	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
89	{	87	{
90	int i;	88	int i;
91		89
92	for (i = 0; i < rdev->scratch.num_reg; i++) {	90	for (i = 0; i < rdev->scratch.num_reg; i++) {
93	if (rdev->scratch.free[i]) {	91	if (rdev->scratch.free[i]) {
94	rdev->scratch.free[i] = false;	92	rdev->scratch.free[i] = false;
95	*reg = rdev->scratch.reg[i];	93	*reg = rdev->scratch.reg[i];
96	return 0;	94	return 0;
97	}	95	}
98	}	96	}
99	return -EINVAL;	97	return -EINVAL;
100	}	98	}
101		99
102	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)	100	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
103	{	101	{
104	int i;	102	int i;
105		103
106	for (i = 0; i < rdev->scratch.num_reg; i++) {	104	for (i = 0; i < rdev->scratch.num_reg; i++) {
107	if (rdev->scratch.reg[i] == reg) {	105	if (rdev->scratch.reg[i] == reg) {
108	rdev->scratch.free[i] = true;	106	rdev->scratch.free[i] = true;
109	return;	107	return;
110	}	108	}
111	}	109	}
112	}	110	}
113		111
114	/*	112	/*
115	* MC common functions	113	* MC common functions
116	*/	114	*/
117	int radeon_mc_setup(struct radeon_device *rdev)	115	int radeon_mc_setup(struct radeon_device *rdev)
118	{	116	{
119	uint32_t tmp;	117	uint32_t tmp;
120		118
121	/* Some chips have an "issue" with the memory controller, the	119	/* Some chips have an "issue" with the memory controller, the
122	* location must be aligned to the size. We just align it down,	120	* location must be aligned to the size. We just align it down,
123	* too bad if we walk over the top of system memory, we don't	121	* too bad if we walk over the top of system memory, we don't
124	* use DMA without a remapped anyway.	122	* use DMA without a remapped anyway.
125	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP	123	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
126	*/	124	*/
127	/* FGLRX seems to setup like this, VRAM a 0, then GART.	125	/* FGLRX seems to setup like this, VRAM a 0, then GART.
128	*/	126	*/
129	/*	127	/*
130	* Note: from R6xx the address space is 40bits but here we only	128	* Note: from R6xx the address space is 40bits but here we only
131	* use 32bits (still have to see a card which would exhaust 4G	129	* use 32bits (still have to see a card which would exhaust 4G
132	* address space).	130	* address space).
133	*/	131	*/
134	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {	132	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
135	/* vram location was already setup try to put gtt after	133	/* vram location was already setup try to put gtt after
136	* if it fits */	134	* if it fits */
137	tmp = rdev->mc.vram_location + rdev->mc.vram_size;	135	tmp = rdev->mc.vram_location + rdev->mc.vram_size;
138	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);	136	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
139	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {	137	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
140	rdev->mc.gtt_location = tmp;	138	rdev->mc.gtt_location = tmp;
141	} else {	139	} else {
142	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {	140	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
143	printk(KERN_ERR "[drm] GTT too big to fit "	141	printk(KERN_ERR "[drm] GTT too big to fit "
144	"before or after vram location.\n");	142	"before or after vram location.\n");
145	return -EINVAL;	143	return -EINVAL;
146	}	144	}
147	rdev->mc.gtt_location = 0;	145	rdev->mc.gtt_location = 0;
148	}	146	}
149	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {	147	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
150	/* gtt location was already setup try to put vram before	148	/* gtt location was already setup try to put vram before
151	* if it fits */	149	* if it fits */
152	if (rdev->mc.vram_size < rdev->mc.gtt_location) {	150	if (rdev->mc.vram_size < rdev->mc.gtt_location) {
153	rdev->mc.vram_location = 0;	151	rdev->mc.vram_location = 0;
154	} else {	152	} else {
155	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;	153	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
156	tmp += (rdev->mc.vram_size - 1);	154	tmp += (rdev->mc.vram_size - 1);
157	tmp &= ~(rdev->mc.vram_size - 1);	155	tmp &= ~(rdev->mc.vram_size - 1);
158	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {	156	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
159	rdev->mc.vram_location = tmp;	157	rdev->mc.vram_location = tmp;
160	} else {	158	} else {
161	printk(KERN_ERR "[drm] vram too big to fit "	159	printk(KERN_ERR "[drm] vram too big to fit "
162	"before or after GTT location.\n");	160	"before or after GTT location.\n");
163	return -EINVAL;	161	return -EINVAL;
164	}	162	}
165	}	163	}
166	} else {	164	} else {
167	rdev->mc.vram_location = 0;	165	rdev->mc.vram_location = 0;
168	rdev->mc.gtt_location = rdev->mc.vram_size;	166	rdev->mc.gtt_location = rdev->mc.vram_size;
169	}	167	}
170	DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);	168	DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
171	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",	169	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
172	rdev->mc.vram_location,	170	rdev->mc.vram_location,
173	rdev->mc.vram_location + rdev->mc.vram_size - 1);	171	rdev->mc.vram_location + rdev->mc.vram_size - 1);
174	DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);	172	DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
175	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",	173	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
176	rdev->mc.gtt_location,	174	rdev->mc.gtt_location,
177	rdev->mc.gtt_location + rdev->mc.gtt_size - 1);	175	rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
178	return 0;	176	return 0;
179	}	177	}
180		178
181		179
182	/*	180	/*
183	* GPU helpers function.	181	* GPU helpers function.
184	*/	182	*/
185	static bool radeon_card_posted(struct radeon_device *rdev)	183	static bool radeon_card_posted(struct radeon_device *rdev)
186	{	184	{
187	uint32_t reg;	185	uint32_t reg;
188		186
189	dbgprintf("%s\n",__FUNCTION__);	187	dbgprintf("%s\n",__FUNCTION__);
190		188
191	/* first check CRTCs */	189	/* first check CRTCs */
192	if (ASIC_IS_AVIVO(rdev)) {	190	if (ASIC_IS_AVIVO(rdev)) {
193	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|	191	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
194	RREG32(AVIVO_D2CRTC_CONTROL);	192	RREG32(AVIVO_D2CRTC_CONTROL);
195	if (reg & AVIVO_CRTC_EN) {	193	if (reg & AVIVO_CRTC_EN) {
196	return true;	194	return true;
197	}	195	}
198	} else {	196	} else {
199	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|	197	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
200	RREG32(RADEON_CRTC2_GEN_CNTL);	198	RREG32(RADEON_CRTC2_GEN_CNTL);
201	if (reg & RADEON_CRTC_EN) {	199	if (reg & RADEON_CRTC_EN) {
202	return true;	200	return true;
203	}	201	}
204	}	202	}
205		203
206	/* then check MEM_SIZE, in case the crtcs are off */	204	/* then check MEM_SIZE, in case the crtcs are off */
207	if (rdev->family >= CHIP_R600)	205	if (rdev->family >= CHIP_R600)
208	reg = RREG32(R600_CONFIG_MEMSIZE);	206	reg = RREG32(R600_CONFIG_MEMSIZE);
209	else	207	else
210	reg = RREG32(RADEON_CONFIG_MEMSIZE);	208	reg = RREG32(RADEON_CONFIG_MEMSIZE);
211		209
212	if (reg)	210	if (reg)
213	return true;	211	return true;
214		212
215	return false;	213	return false;
216		214
217	}	215	}
218		216
219		217
220	/*	218	/*
221	* Registers accessors functions.	219	* Registers accessors functions.
222	*/	220	*/
223	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)	221	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
224	{	222	{
225	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);	223	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
226	BUG_ON(1);	224	BUG_ON(1);
227	return 0;	225	return 0;
228	}	226	}
229		227
230	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)	228	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
231	{	229	{
232	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",	230	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
233	reg, v);	231	reg, v);
234	BUG_ON(1);	232	BUG_ON(1);
235	}	233	}
236		234
237	void radeon_register_accessor_init(struct radeon_device *rdev)	235	void radeon_register_accessor_init(struct radeon_device *rdev)
238	{	236	{
239		237
240	dbgprintf("%s\n",__FUNCTION__);	238	dbgprintf("%s\n",__FUNCTION__);
241		239
242	rdev->mm_rreg = &r100_mm_rreg;	240	rdev->mm_rreg = &r100_mm_rreg;
243	rdev->mm_wreg = &r100_mm_wreg;	241	rdev->mm_wreg = &r100_mm_wreg;
244	rdev->mc_rreg = &radeon_invalid_rreg;	242	rdev->mc_rreg = &radeon_invalid_rreg;
245	rdev->mc_wreg = &radeon_invalid_wreg;	243	rdev->mc_wreg = &radeon_invalid_wreg;
246	rdev->pll_rreg = &radeon_invalid_rreg;	244	rdev->pll_rreg = &radeon_invalid_rreg;
247	rdev->pll_wreg = &radeon_invalid_wreg;	245	rdev->pll_wreg = &radeon_invalid_wreg;
248	rdev->pcie_rreg = &radeon_invalid_rreg;	246	rdev->pcie_rreg = &radeon_invalid_rreg;
249	rdev->pcie_wreg = &radeon_invalid_wreg;	247	rdev->pcie_wreg = &radeon_invalid_wreg;
250	rdev->pciep_rreg = &radeon_invalid_rreg;	248	rdev->pciep_rreg = &radeon_invalid_rreg;
251	rdev->pciep_wreg = &radeon_invalid_wreg;	249	rdev->pciep_wreg = &radeon_invalid_wreg;
252		250
253	/* Don't change order as we are overridding accessor. */	251	/* Don't change order as we are overridding accessor. */
254	if (rdev->family < CHIP_RV515) {	252	if (rdev->family < CHIP_RV515) {
255	// rdev->pcie_rreg = &rv370_pcie_rreg;	253	// rdev->pcie_rreg = &rv370_pcie_rreg;
256	// rdev->pcie_wreg = &rv370_pcie_wreg;	254	// rdev->pcie_wreg = &rv370_pcie_wreg;
257	}	255	}
258	if (rdev->family >= CHIP_RV515) {	256	if (rdev->family >= CHIP_RV515) {
259	rdev->pcie_rreg = &rv515_pcie_rreg;	257	rdev->pcie_rreg = &rv515_pcie_rreg;
260	rdev->pcie_wreg = &rv515_pcie_wreg;	258	rdev->pcie_wreg = &rv515_pcie_wreg;
261	}	259	}
262	/* FIXME: not sure here */	260	/* FIXME: not sure here */
263	if (rdev->family <= CHIP_R580) {	261	if (rdev->family <= CHIP_R580) {
264	rdev->pll_rreg = &r100_pll_rreg;	262	rdev->pll_rreg = &r100_pll_rreg;
265	rdev->pll_wreg = &r100_pll_wreg;	263	rdev->pll_wreg = &r100_pll_wreg;
266	}	264	}
267	if (rdev->family >= CHIP_RV515) {	265	if (rdev->family >= CHIP_RV515) {
268	rdev->mc_rreg = &rv515_mc_rreg;	266	rdev->mc_rreg = &rv515_mc_rreg;
269	rdev->mc_wreg = &rv515_mc_wreg;	267	rdev->mc_wreg = &rv515_mc_wreg;
270	}	268	}
271	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {	269	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
272	// rdev->mc_rreg = &rs400_mc_rreg;	270	// rdev->mc_rreg = &rs400_mc_rreg;
273	// rdev->mc_wreg = &rs400_mc_wreg;	271	// rdev->mc_wreg = &rs400_mc_wreg;
274	}	272	}
275	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {	273	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
276	// rdev->mc_rreg = &rs690_mc_rreg;	274	// rdev->mc_rreg = &rs690_mc_rreg;
277	// rdev->mc_wreg = &rs690_mc_wreg;	275	// rdev->mc_wreg = &rs690_mc_wreg;
278	}	276	}
279	if (rdev->family == CHIP_RS600) {	277	if (rdev->family == CHIP_RS600) {
280	// rdev->mc_rreg = &rs600_mc_rreg;	278	// rdev->mc_rreg = &rs600_mc_rreg;
281	// rdev->mc_wreg = &rs600_mc_wreg;	279	// rdev->mc_wreg = &rs600_mc_wreg;
282	}	280	}
283	if (rdev->family >= CHIP_R600) {	281	if (rdev->family >= CHIP_R600) {
284	// rdev->pciep_rreg = &r600_pciep_rreg;	282	// rdev->pciep_rreg = &r600_pciep_rreg;
285	// rdev->pciep_wreg = &r600_pciep_wreg;	283	// rdev->pciep_wreg = &r600_pciep_wreg;
286	}	284	}
287	}	285	}
288		286
289		287
290		288
291	/*	289	/*
292	* ASIC	290	* ASIC
293	*/	291	*/
294	int radeon_asic_init(struct radeon_device *rdev)	292	int radeon_asic_init(struct radeon_device *rdev)
295	{	293	{
296		294
297	dbgprintf("%s\n",__FUNCTION__);	295	dbgprintf("%s\n",__FUNCTION__);
298		296
299	radeon_register_accessor_init(rdev);	297	radeon_register_accessor_init(rdev);
300	switch (rdev->family) {	298	switch (rdev->family) {
301	case CHIP_R100:	299	case CHIP_R100:
302	case CHIP_RV100:	300	case CHIP_RV100:
303	case CHIP_RS100:	301	case CHIP_RS100:
304	case CHIP_RV200:	302	case CHIP_RV200:
305	case CHIP_RS200:	303	case CHIP_RS200:
306	case CHIP_R200:	304	case CHIP_R200:
307	case CHIP_RV250:	305	case CHIP_RV250:
308	case CHIP_RS300:	306	case CHIP_RS300:
309	case CHIP_RV280:	307	case CHIP_RV280:
310	// rdev->asic = &r100_asic;	308	// rdev->asic = &r100_asic;
311	break;	309	break;
312	case CHIP_R300:	310	case CHIP_R300:
313	case CHIP_R350:	311	case CHIP_R350:
314	case CHIP_RV350:	312	case CHIP_RV350:
315	case CHIP_RV380:	313	case CHIP_RV380:
316	// rdev->asic = &r300_asic;	314	// rdev->asic = &r300_asic;
317	break;	315	break;
318	case CHIP_R420:	316	case CHIP_R420:
319	case CHIP_R423:	317	case CHIP_R423:
320	case CHIP_RV410:	318	case CHIP_RV410:
321	// rdev->asic = &r420_asic;	319	// rdev->asic = &r420_asic;
322	break;	320	break;
323	case CHIP_RS400:	321	case CHIP_RS400:
324	case CHIP_RS480:	322	case CHIP_RS480:
325	// rdev->asic = &rs400_asic;	323	// rdev->asic = &rs400_asic;
326	break;	324	break;
327	case CHIP_RS600:	325	case CHIP_RS600:
328	// rdev->asic = &rs600_asic;	326	// rdev->asic = &rs600_asic;
329	break;	327	break;
330	case CHIP_RS690:	328	case CHIP_RS690:
331	case CHIP_RS740:	329	case CHIP_RS740:
332	// rdev->asic = &rs690_asic;	330	// rdev->asic = &rs690_asic;
333	break;	331	break;
334	case CHIP_RV515:	332	case CHIP_RV515:
335	// rdev->asic = &rv515_asic;	333	// rdev->asic = &rv515_asic;
336	break;	334	break;
337	case CHIP_R520:	335	case CHIP_R520:
338	case CHIP_RV530:	336	case CHIP_RV530:
339	case CHIP_RV560:	337	case CHIP_RV560:
340	case CHIP_RV570:	338	case CHIP_RV570:
341	case CHIP_R580:	339	case CHIP_R580:
342	rdev->asic = &r520_asic;	340	rdev->asic = &r520_asic;
343	break;	341	break;
344	case CHIP_R600:	342	case CHIP_R600:
345	case CHIP_RV610:	343	case CHIP_RV610:
346	case CHIP_RV630:	344	case CHIP_RV630:
347	case CHIP_RV620:	345	case CHIP_RV620:
348	case CHIP_RV635:	346	case CHIP_RV635:
349	case CHIP_RV670:	347	case CHIP_RV670:
350	case CHIP_RS780:	348	case CHIP_RS780:
351	case CHIP_RV770:	349	case CHIP_RV770:
352	case CHIP_RV730:	350	case CHIP_RV730:
353	case CHIP_RV710:	351	case CHIP_RV710:
354	default:	352	default:
355	/* FIXME: not supported yet */	353	/* FIXME: not supported yet */
356	return -EINVAL;	354	return -EINVAL;
357	}	355	}
358	return 0;	356	return 0;
359	}	357	}
360		358
361		359
362	/*	360	/*
363	* Wrapper around modesetting bits.	361	* Wrapper around modesetting bits.
364	*/	362	*/
365	int radeon_clocks_init(struct radeon_device *rdev)	363	int radeon_clocks_init(struct radeon_device *rdev)
366	{	364	{
367	int r;	365	int r;
368		366
369	dbgprintf("%s\n",__FUNCTION__);	367	dbgprintf("%s\n",__FUNCTION__);
370		368
371	radeon_get_clock_info(rdev->ddev);	369	radeon_get_clock_info(rdev->ddev);
372	r = radeon_static_clocks_init(rdev->ddev);	370	r = radeon_static_clocks_init(rdev->ddev);
373	if (r) {	371	if (r) {
374	return r;	372	return r;
375	}	373	}
376	DRM_INFO("Clocks initialized !\n");	374	DRM_INFO("Clocks initialized !\n");
377	return 0;	375	return 0;
378	}	376	}
379		377
380	void radeon_clocks_fini(struct radeon_device *rdev)	378	void radeon_clocks_fini(struct radeon_device *rdev)
381	{	379	{
382	}	380	}
383		381
384	/* ATOM accessor methods */	382	/* ATOM accessor methods */
385	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)	383	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
386	{	384	{
387	struct radeon_device *rdev = info->dev->dev_private;	385	struct radeon_device *rdev = info->dev->dev_private;
388	uint32_t r;	386	uint32_t r;
389		387
390	r = rdev->pll_rreg(rdev, reg);	388	r = rdev->pll_rreg(rdev, reg);
391	return r;	389	return r;
392	}	390	}
393		391
394	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)	392	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
395	{	393	{
396	struct radeon_device *rdev = info->dev->dev_private;	394	struct radeon_device *rdev = info->dev->dev_private;
397		395
398	rdev->pll_wreg(rdev, reg, val);	396	rdev->pll_wreg(rdev, reg, val);
399	}	397	}
400		398
401	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)	399	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
402	{	400	{
403	struct radeon_device *rdev = info->dev->dev_private;	401	struct radeon_device *rdev = info->dev->dev_private;
404	uint32_t r;	402	uint32_t r;
405		403
406	r = rdev->mc_rreg(rdev, reg);	404	r = rdev->mc_rreg(rdev, reg);
407	return r;	405	return r;
408	}	406	}
409		407
410	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)	408	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
411	{	409	{
412	struct radeon_device *rdev = info->dev->dev_private;	410	struct radeon_device *rdev = info->dev->dev_private;
413		411
414	rdev->mc_wreg(rdev, reg, val);	412	rdev->mc_wreg(rdev, reg, val);
415	}	413	}
416		414
417	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)	415	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
418	{	416	{
419	struct radeon_device *rdev = info->dev->dev_private;	417	struct radeon_device *rdev = info->dev->dev_private;
420		418
421	WREG32(reg*4, val);	419	WREG32(reg*4, val);
422	}	420	}
423		421
424	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)	422	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
425	{	423	{
426	struct radeon_device *rdev = info->dev->dev_private;	424	struct radeon_device *rdev = info->dev->dev_private;
427	uint32_t r;	425	uint32_t r;
428		426
429	r = RREG32(reg*4);	427	r = RREG32(reg*4);
430	return r;	428	return r;
431	}	429	}
432		430
433	static struct card_info atom_card_info = {	431	static struct card_info atom_card_info = {
434	.dev = NULL,	432	.dev = NULL,
435	.reg_read = cail_reg_read,	433	.reg_read = cail_reg_read,
436	.reg_write = cail_reg_write,	434	.reg_write = cail_reg_write,
437	.mc_read = cail_mc_read,	435	.mc_read = cail_mc_read,
438	.mc_write = cail_mc_write,	436	.mc_write = cail_mc_write,
439	.pll_read = cail_pll_read,	437	.pll_read = cail_pll_read,
440	.pll_write = cail_pll_write,	438	.pll_write = cail_pll_write,
441	};	439	};
442		440
443	int radeon_atombios_init(struct radeon_device *rdev)	441	int radeon_atombios_init(struct radeon_device *rdev)
444	{	442	{
445	dbgprintf("%s\n",__FUNCTION__);	443	dbgprintf("%s\n",__FUNCTION__);
446		444
447	atom_card_info.dev = rdev->ddev;	445	atom_card_info.dev = rdev->ddev;
448	rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);	446	rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
449	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);	447	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
450	return 0;	448	return 0;
451	}	449	}
452		450
453	void radeon_atombios_fini(struct radeon_device *rdev)	451	void radeon_atombios_fini(struct radeon_device *rdev)
454	{	452	{
455	kfree(rdev->mode_info.atom_context);	453	kfree(rdev->mode_info.atom_context);
456	}	454	}
457		455
458	int radeon_combios_init(struct radeon_device *rdev)	456	int radeon_combios_init(struct radeon_device *rdev)
459	{	457	{
460	// radeon_combios_initialize_bios_scratch_regs(rdev->ddev);	458	// radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
461	return 0;	459	return 0;
462	}	460	}
463		461
464	void radeon_combios_fini(struct radeon_device *rdev)	462	void radeon_combios_fini(struct radeon_device *rdev)
465	{	463	{
466	}	464	}
467		465
468	int radeon_modeset_init(struct radeon_device *rdev);	466	int radeon_modeset_init(struct radeon_device *rdev);
469	void radeon_modeset_fini(struct radeon_device *rdev);	467	void radeon_modeset_fini(struct radeon_device *rdev);
470		468
471	/*	469	/*
472	* Radeon device.	470	* Radeon device.
473	*/	471	*/
474	int radeon_device_init(struct radeon_device *rdev,	472	int radeon_device_init(struct radeon_device *rdev,
475	struct drm_device *ddev,	473	struct drm_device *ddev,
476	struct pci_dev *pdev,	474	struct pci_dev *pdev,
477	uint32_t flags)	475	uint32_t flags)
478	{	476	{
479	int r, ret = -1;	477	int r, ret = -1;
480		478
481	dbgprintf("%s\n",__FUNCTION__);	479	dbgprintf("%s\n",__FUNCTION__);
482		480
483	DRM_INFO("radeon: Initializing kernel modesetting.\n");	481	DRM_INFO("radeon: Initializing kernel modesetting.\n");
484	rdev->shutdown = false;	482	rdev->shutdown = false;
485	rdev->ddev = ddev;	483	rdev->ddev = ddev;
486	rdev->pdev = pdev;	484	rdev->pdev = pdev;
487	rdev->flags = flags;	485	rdev->flags = flags;
488	rdev->family = flags & RADEON_FAMILY_MASK;	486	rdev->family = flags & RADEON_FAMILY_MASK;
489	rdev->is_atom_bios = false;	487	rdev->is_atom_bios = false;
490	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;	488	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
491	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;	489	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
492	rdev->gpu_lockup = false;	490	rdev->gpu_lockup = false;
493	/* mutex initialization are all done here so we	491	/* mutex initialization are all done here so we
494	* can recall function without having locking issues */	492	* can recall function without having locking issues */
495	// mutex_init(&rdev->cs_mutex);	493	// mutex_init(&rdev->cs_mutex);
496	// mutex_init(&rdev->ib_pool.mutex);	494	// mutex_init(&rdev->ib_pool.mutex);
497	// mutex_init(&rdev->cp.mutex);	495	// mutex_init(&rdev->cp.mutex);
498	// rwlock_init(&rdev->fence_drv.lock);	496	// rwlock_init(&rdev->fence_drv.lock);
499		497
500		498

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(root)/drivers/video/drm/radeon/radeon_device.c @ 2175 – Rev 1123 → 1125