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Rev 1430 | Rev 1963 | ||
---|---|---|---|
Line 37... | Line 37... | ||
37 | #include |
37 | #include |
38 | #endif /* CONFIG_PPC_PMAC */ |
38 | #endif /* CONFIG_PPC_PMAC */ |
Line 39... | Line 39... | ||
39 | 39 | ||
40 | /* from radeon_encoder.c */ |
40 | /* from radeon_encoder.c */ |
41 | extern uint32_t |
41 | extern uint32_t |
42 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, |
42 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
43 | uint8_t dac); |
43 | uint8_t dac); |
Line 44... | Line 44... | ||
44 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
44 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
45 | 45 | ||
Line 53... | Line 53... | ||
53 | uint16_t connector_object_id, |
53 | uint16_t connector_object_id, |
54 | struct radeon_hpd *hpd); |
54 | struct radeon_hpd *hpd); |
Line 55... | Line 55... | ||
55 | 55 | ||
56 | /* from radeon_legacy_encoder.c */ |
56 | /* from radeon_legacy_encoder.c */ |
57 | extern void |
57 | extern void |
58 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, |
58 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
Line 59... | Line 59... | ||
59 | uint32_t supported_device); |
59 | uint32_t supported_device); |
Line 60... | Line 60... | ||
60 | 60 | ||
Line 446... | Line 446... | ||
446 | 446 | ||
Line 447... | Line 447... | ||
447 | } |
447 | } |
448 | 448 | ||
449 | bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
449 | bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
450 | { |
450 | { |
- | 451 | int edid_info, size; |
|
451 | int edid_info; |
452 | struct edid *edid; |
452 | struct edid *edid; |
453 | unsigned char *raw; |
453 | edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
454 | edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
Line -... | Line 455... | ||
- | 455 | if (!edid_info) |
|
454 | if (!edid_info) |
456 | return false; |
455 | return false; |
457 | |
456 | 458 | raw = rdev->bios + edid_info; |
|
457 | edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1), |
459 | size = EDID_LENGTH * (raw[0x7e] + 1); |
Line 458... | Line 460... | ||
458 | GFP_KERNEL); |
460 | edid = kmalloc(size, GFP_KERNEL); |
459 | if (edid == NULL) |
- | |
Line 460... | Line 461... | ||
460 | return false; |
461 | if (edid == NULL) |
461 | 462 | return false; |
|
462 | memcpy((unsigned char *)edid, |
463 | |
463 | (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH); |
464 | memcpy((unsigned char *)edid, raw, size); |
Line 464... | Line 465... | ||
464 | 465 | ||
- | 466 | if (!drm_edid_is_valid(edid)) { |
|
465 | if (!drm_edid_is_valid(edid)) { |
467 | kfree(edid); |
466 | kfree(edid); |
468 | return false; |
Line -... | Line 469... | ||
- | 469 | } |
|
467 | return false; |
470 | |
468 | } |
471 | rdev->mode_info.bios_hardcoded_edid = edid; |
469 | 472 | rdev->mode_info.bios_hardcoded_edid_size = size; |
|
- | 473 | return true; |
|
- | 474 | } |
|
470 | rdev->mode_info.bios_hardcoded_edid = edid; |
475 | |
- | 476 | /* this is used for atom LCDs as well */ |
|
- | 477 | struct edid * |
|
- | 478 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) |
|
- | 479 | { |
|
471 | return true; |
480 | struct edid *edid; |
- | 481 | ||
- | 482 | if (rdev->mode_info.bios_hardcoded_edid) { |
|
- | 483 | edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); |
|
472 | } |
484 | if (edid) { |
473 | 485 | memcpy((unsigned char *)edid, |
|
Line 474... | Line 486... | ||
474 | struct edid * |
486 | (unsigned char *)rdev->mode_info.bios_hardcoded_edid, |
- | 487 | rdev->mode_info.bios_hardcoded_edid_size); |
|
- | 488 | return edid; |
|
475 | radeon_combios_get_hardcoded_edid(struct radeon_device *rdev) |
489 | } |
476 | { |
490 | } |
477 | if (rdev->mode_info.bios_hardcoded_edid) |
491 | return NULL; |
- | 492 | } |
|
- | 493 | ||
- | 494 | static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
|
- | 495 | enum radeon_combios_ddc ddc, |
|
- | 496 | u32 clk_mask, |
|
- | 497 | u32 data_mask) |
|
- | 498 | { |
|
- | 499 | struct radeon_i2c_bus_rec i2c; |
|
- | 500 | int ddc_line = 0; |
|
- | 501 | ||
- | 502 | /* ddc id = mask reg |
|
- | 503 | * DDC_NONE_DETECTED = none |
|
- | 504 | * DDC_DVI = RADEON_GPIO_DVI_DDC |
|
- | 505 | * DDC_VGA = RADEON_GPIO_VGA_DDC |
|
- | 506 | * DDC_LCD = RADEON_GPIOPAD_MASK |
|
- | 507 | * DDC_GPIO = RADEON_MDGPIO_MASK |
|
- | 508 | * r1xx |
|
- | 509 | * DDC_MONID = RADEON_GPIO_MONID |
|
- | 510 | * DDC_CRT2 = RADEON_GPIO_CRT2_DDC |
|
- | 511 | * r200 |
|
- | 512 | * DDC_MONID = RADEON_GPIO_MONID |
|
- | 513 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
|
- | 514 | * r300/r350 |
|
- | 515 | * DDC_MONID = RADEON_GPIO_DVI_DDC |
|
- | 516 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
|
- | 517 | * rv2xx/rv3xx |
|
- | 518 | * DDC_MONID = RADEON_GPIO_MONID |
|
- | 519 | * DDC_CRT2 = RADEON_GPIO_MONID |
|
- | 520 | * rs3xx/rs4xx |
|
- | 521 | * DDC_MONID = RADEON_GPIOPAD_MASK |
|
- | 522 | * DDC_CRT2 = RADEON_GPIO_MONID |
|
- | 523 | */ |
|
- | 524 | switch (ddc) { |
|
- | 525 | case DDC_NONE_DETECTED: |
|
- | 526 | default: |
|
- | 527 | ddc_line = 0; |
|
- | 528 | break; |
|
- | 529 | case DDC_DVI: |
|
- | 530 | ddc_line = RADEON_GPIO_DVI_DDC; |
|
- | 531 | break; |
|
- | 532 | case DDC_VGA: |
|
- | 533 | ddc_line = RADEON_GPIO_VGA_DDC; |
|
- | 534 | break; |
|
- | 535 | case DDC_LCD: |
|
- | 536 | ddc_line = RADEON_GPIOPAD_MASK; |
|
- | 537 | break; |
|
- | 538 | case DDC_GPIO: |
|
- | 539 | ddc_line = RADEON_MDGPIO_MASK; |
|
- | 540 | break; |
|
- | 541 | case DDC_MONID: |
|
- | 542 | if (rdev->family == CHIP_RS300 || |
|
- | 543 | rdev->family == CHIP_RS400 || |
|
- | 544 | rdev->family == CHIP_RS480) |
|
- | 545 | ddc_line = RADEON_GPIOPAD_MASK; |
|
- | 546 | else if (rdev->family == CHIP_R300 || |
|
- | 547 | rdev->family == CHIP_R350) { |
|
- | 548 | ddc_line = RADEON_GPIO_DVI_DDC; |
|
- | 549 | ddc = DDC_DVI; |
|
- | 550 | } else |
|
- | 551 | ddc_line = RADEON_GPIO_MONID; |
|
- | 552 | break; |
|
- | 553 | case DDC_CRT2: |
|
- | 554 | if (rdev->family == CHIP_R200 || |
|
- | 555 | rdev->family == CHIP_R300 || |
|
- | 556 | rdev->family == CHIP_R350) { |
|
- | 557 | ddc_line = RADEON_GPIO_DVI_DDC; |
|
- | 558 | ddc = DDC_DVI; |
|
- | 559 | } else if (rdev->family == CHIP_RS300 || |
|
- | 560 | rdev->family == CHIP_RS400 || |
|
- | 561 | rdev->family == CHIP_RS480) |
|
Line 478... | Line 562... | ||
478 | return rdev->mode_info.bios_hardcoded_edid; |
562 | ddc_line = RADEON_GPIO_MONID; |
479 | return NULL; |
563 | else if (rdev->family >= CHIP_RV350) { |
480 | } |
564 | ddc_line = RADEON_GPIO_MONID; |
481 | 565 | ddc = DDC_MONID; |
|
Line 501... | Line 585... | ||
501 | i2c.en_clk_reg = RADEON_MDGPIO_EN; |
585 | i2c.en_clk_reg = RADEON_MDGPIO_EN; |
502 | i2c.en_data_reg = RADEON_MDGPIO_EN; |
586 | i2c.en_data_reg = RADEON_MDGPIO_EN; |
503 | i2c.y_clk_reg = RADEON_MDGPIO_Y; |
587 | i2c.y_clk_reg = RADEON_MDGPIO_Y; |
504 | i2c.y_data_reg = RADEON_MDGPIO_Y; |
588 | i2c.y_data_reg = RADEON_MDGPIO_Y; |
505 | } else { |
589 | } else { |
506 | i2c.mask_clk_mask = RADEON_GPIO_EN_1; |
- | |
507 | i2c.mask_data_mask = RADEON_GPIO_EN_0; |
- | |
508 | i2c.a_clk_mask = RADEON_GPIO_A_1; |
- | |
509 | i2c.a_data_mask = RADEON_GPIO_A_0; |
- | |
510 | i2c.en_clk_mask = RADEON_GPIO_EN_1; |
- | |
511 | i2c.en_data_mask = RADEON_GPIO_EN_0; |
- | |
512 | i2c.y_clk_mask = RADEON_GPIO_Y_1; |
- | |
513 | i2c.y_data_mask = RADEON_GPIO_Y_0; |
- | |
514 | - | ||
515 | i2c.mask_clk_reg = ddc_line; |
590 | i2c.mask_clk_reg = ddc_line; |
516 | i2c.mask_data_reg = ddc_line; |
591 | i2c.mask_data_reg = ddc_line; |
517 | i2c.a_clk_reg = ddc_line; |
592 | i2c.a_clk_reg = ddc_line; |
518 | i2c.a_data_reg = ddc_line; |
593 | i2c.a_data_reg = ddc_line; |
519 | i2c.en_clk_reg = ddc_line; |
594 | i2c.en_clk_reg = ddc_line; |
520 | i2c.en_data_reg = ddc_line; |
595 | i2c.en_data_reg = ddc_line; |
521 | i2c.y_clk_reg = ddc_line; |
596 | i2c.y_clk_reg = ddc_line; |
522 | i2c.y_data_reg = ddc_line; |
597 | i2c.y_data_reg = ddc_line; |
523 | } |
598 | } |
Line -... | Line 599... | ||
- | 599 | ||
- | 600 | if (clk_mask && data_mask) { |
|
- | 601 | /* system specific masks */ |
|
- | 602 | i2c.mask_clk_mask = clk_mask; |
|
- | 603 | i2c.mask_data_mask = data_mask; |
|
- | 604 | i2c.a_clk_mask = clk_mask; |
|
- | 605 | i2c.a_data_mask = data_mask; |
|
- | 606 | i2c.en_clk_mask = clk_mask; |
|
- | 607 | i2c.en_data_mask = data_mask; |
|
- | 608 | i2c.y_clk_mask = clk_mask; |
|
- | 609 | i2c.y_data_mask = data_mask; |
|
- | 610 | } else if ((ddc_line == RADEON_GPIOPAD_MASK) || |
|
- | 611 | (ddc_line == RADEON_MDGPIO_MASK)) { |
|
- | 612 | /* default gpiopad masks */ |
|
- | 613 | i2c.mask_clk_mask = (0x20 << 8); |
|
- | 614 | i2c.mask_data_mask = 0x80; |
|
- | 615 | i2c.a_clk_mask = (0x20 << 8); |
|
- | 616 | i2c.a_data_mask = 0x80; |
|
- | 617 | i2c.en_clk_mask = (0x20 << 8); |
|
- | 618 | i2c.en_data_mask = 0x80; |
|
- | 619 | i2c.y_clk_mask = (0x20 << 8); |
|
- | 620 | i2c.y_data_mask = 0x80; |
|
- | 621 | } else { |
|
- | 622 | /* default masks for ddc pads */ |
|
- | 623 | i2c.mask_clk_mask = RADEON_GPIO_EN_1; |
|
- | 624 | i2c.mask_data_mask = RADEON_GPIO_EN_0; |
|
- | 625 | i2c.a_clk_mask = RADEON_GPIO_A_1; |
|
- | 626 | i2c.a_data_mask = RADEON_GPIO_A_0; |
|
- | 627 | i2c.en_clk_mask = RADEON_GPIO_EN_1; |
|
- | 628 | i2c.en_data_mask = RADEON_GPIO_EN_0; |
|
- | 629 | i2c.y_clk_mask = RADEON_GPIO_Y_1; |
|
- | 630 | i2c.y_data_mask = RADEON_GPIO_Y_0; |
|
- | 631 | } |
|
524 | 632 | ||
525 | switch (rdev->family) { |
633 | switch (rdev->family) { |
526 | case CHIP_R100: |
634 | case CHIP_R100: |
527 | case CHIP_RV100: |
635 | case CHIP_RV100: |
528 | case CHIP_RS100: |
636 | case CHIP_RS100: |
529 | case CHIP_RV200: |
637 | case CHIP_RV200: |
530 | case CHIP_RS200: |
638 | case CHIP_RS200: |
531 | case CHIP_RS300: |
639 | case CHIP_RS300: |
532 | switch (ddc_line) { |
640 | switch (ddc_line) { |
533 | case RADEON_GPIO_DVI_DDC: |
- | |
534 | /* in theory this should be hw capable, |
- | |
535 | * but it doesn't seem to work |
- | |
536 | */ |
641 | case RADEON_GPIO_DVI_DDC: |
537 | i2c.hw_capable = false; |
642 | i2c.hw_capable = true; |
538 | break; |
643 | break; |
539 | default: |
644 | default: |
540 | i2c.hw_capable = false; |
645 | i2c.hw_capable = false; |
541 | break; |
646 | break; |
Line 600... | Line 705... | ||
600 | default: |
705 | default: |
601 | i2c.hw_capable = false; |
706 | i2c.hw_capable = false; |
602 | break; |
707 | break; |
603 | } |
708 | } |
604 | i2c.mm_i2c = false; |
709 | i2c.mm_i2c = false; |
- | 710 | ||
605 | i2c.i2c_id = 0; |
711 | i2c.i2c_id = ddc; |
606 | i2c.hpd_id = 0; |
712 | i2c.hpd = RADEON_HPD_NONE; |
Line 607... | Line 713... | ||
607 | 713 | ||
608 | if (ddc_line) |
714 | if (ddc_line) |
609 | i2c.valid = true; |
715 | i2c.valid = true; |
610 | else |
716 | else |
Line 611... | Line 717... | ||
611 | i2c.valid = false; |
717 | i2c.valid = false; |
612 | 718 | ||
Line -... | Line 719... | ||
- | 719 | return i2c; |
|
- | 720 | } |
|
- | 721 | ||
- | 722 | void radeon_combios_i2c_init(struct radeon_device *rdev) |
|
- | 723 | { |
|
- | 724 | struct drm_device *dev = rdev->ddev; |
|
- | 725 | struct radeon_i2c_bus_rec i2c; |
|
- | 726 | ||
- | 727 | /* actual hw pads |
|
- | 728 | * r1xx/rs2xx/rs3xx |
|
- | 729 | * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm |
|
- | 730 | * r200 |
|
- | 731 | * 0x60, 0x64, 0x68, mm |
|
- | 732 | * r300/r350 |
|
- | 733 | * 0x60, 0x64, mm |
|
- | 734 | * rv2xx/rv3xx/rs4xx |
|
- | 735 | * 0x60, 0x64, 0x68, gpiopads, mm |
|
- | 736 | */ |
|
- | 737 | ||
- | 738 | /* 0x60 */ |
|
- | 739 | i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
|
- | 740 | rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); |
|
- | 741 | /* 0x64 */ |
|
- | 742 | i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
|
- | 743 | rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); |
|
- | 744 | ||
- | 745 | /* mm i2c */ |
|
- | 746 | i2c.valid = true; |
|
- | 747 | i2c.hw_capable = true; |
|
- | 748 | i2c.mm_i2c = true; |
|
- | 749 | i2c.i2c_id = 0xa0; |
|
- | 750 | rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); |
|
- | 751 | ||
- | 752 | if (rdev->family == CHIP_R300 || |
|
- | 753 | rdev->family == CHIP_R350) { |
|
- | 754 | /* only 2 sw i2c pads */ |
|
- | 755 | } else if (rdev->family == CHIP_RS300 || |
|
- | 756 | rdev->family == CHIP_RS400 || |
|
- | 757 | rdev->family == CHIP_RS480) { |
|
- | 758 | u16 offset; |
|
- | 759 | u8 id, blocks, clk, data; |
|
- | 760 | int i; |
|
- | 761 | ||
- | 762 | /* 0x68 */ |
|
- | 763 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
|
- | 764 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
|
- | 765 | ||
- | 766 | offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
|
- | 767 | if (offset) { |
|
- | 768 | blocks = RBIOS8(offset + 2); |
|
- | 769 | for (i = 0; i < blocks; i++) { |
|
- | 770 | id = RBIOS8(offset + 3 + (i * 5) + 0); |
|
- | 771 | if (id == 136) { |
|
- | 772 | clk = RBIOS8(offset + 3 + (i * 5) + 3); |
|
- | 773 | data = RBIOS8(offset + 3 + (i * 5) + 4); |
|
- | 774 | /* gpiopad */ |
|
- | 775 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, |
|
- | 776 | (1 << clk), (1 << data)); |
|
- | 777 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); |
|
- | 778 | break; |
|
- | 779 | } |
|
- | 780 | } |
|
- | 781 | } |
|
- | 782 | } else if (rdev->family >= CHIP_R200) { |
|
- | 783 | /* 0x68 */ |
|
- | 784 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
|
- | 785 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
|
- | 786 | } else { |
|
- | 787 | /* 0x68 */ |
|
- | 788 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
|
- | 789 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
|
- | 790 | /* 0x6c */ |
|
- | 791 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
|
- | 792 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); |
|
613 | return i2c; |
793 | } |
614 | } |
794 | } |
615 | 795 | ||
616 | bool radeon_combios_get_clock_info(struct drm_device *dev) |
796 | bool radeon_combios_get_clock_info(struct drm_device *dev) |
617 | { |
797 | { |
Line 631... | Line 811... | ||
631 | /* pixel clocks */ |
811 | /* pixel clocks */ |
632 | p1pll->reference_freq = RBIOS16(pll_info + 0xe); |
812 | p1pll->reference_freq = RBIOS16(pll_info + 0xe); |
633 | p1pll->reference_div = RBIOS16(pll_info + 0x10); |
813 | p1pll->reference_div = RBIOS16(pll_info + 0x10); |
634 | p1pll->pll_out_min = RBIOS32(pll_info + 0x12); |
814 | p1pll->pll_out_min = RBIOS32(pll_info + 0x12); |
635 | p1pll->pll_out_max = RBIOS32(pll_info + 0x16); |
815 | p1pll->pll_out_max = RBIOS32(pll_info + 0x16); |
- | 816 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
|
- | 817 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
|
Line 636... | Line 818... | ||
636 | 818 | ||
637 | if (rev > 9) { |
819 | if (rev > 9) { |
638 | p1pll->pll_in_min = RBIOS32(pll_info + 0x36); |
820 | p1pll->pll_in_min = RBIOS32(pll_info + 0x36); |
639 | p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); |
821 | p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); |
Line 682... | Line 864... | ||
682 | mclk = 200 * 100; |
864 | mclk = 200 * 100; |
Line 683... | Line 865... | ||
683 | 865 | ||
684 | rdev->clock.default_sclk = sclk; |
866 | rdev->clock.default_sclk = sclk; |
Line -... | Line 867... | ||
- | 867 | rdev->clock.default_mclk = mclk; |
|
- | 868 | ||
- | 869 | if (RBIOS32(pll_info + 0x16)) |
|
- | 870 | rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); |
|
- | 871 | else |
|
685 | rdev->clock.default_mclk = mclk; |
872 | rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ |
686 | 873 | ||
687 | return true; |
874 | return true; |
688 | } |
875 | } |
Line 689... | Line 876... | ||
689 | return false; |
876 | return false; |
690 | } |
877 | } |
691 | 878 | ||
692 | bool radeon_combios_sideport_present(struct radeon_device *rdev) |
879 | bool radeon_combios_sideport_present(struct radeon_device *rdev) |
Line -... | Line 880... | ||
- | 880 | { |
|
- | 881 | struct drm_device *dev = rdev->ddev; |
|
- | 882 | u16 igp_info; |
|
- | 883 | ||
693 | { |
884 | /* sideport is AMD only */ |
Line 694... | Line 885... | ||
694 | struct drm_device *dev = rdev->ddev; |
885 | if (rdev->family == CHIP_RS400) |
695 | u16 igp_info; |
886 | return false; |
696 | 887 | ||
Line 759... | Line 950... | ||
759 | } else { |
950 | } else { |
760 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
951 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
761 | dac = RBIOS8(dac_info + 0x3) & 0xf; |
952 | dac = RBIOS8(dac_info + 0x3) & 0xf; |
762 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
953 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
763 | } |
954 | } |
- | 955 | /* if the values are all zeros, use the table */ |
|
- | 956 | if (p_dac->ps2_pdac_adj) |
|
764 | found = 1; |
957 | found = 1; |
765 | } |
958 | } |
Line 766... | Line 959... | ||
766 | 959 | ||
767 | if (!found) /* fallback to defaults */ |
960 | if (!found) /* fallback to defaults */ |
Line 781... | Line 974... | ||
781 | if (tv_info) { |
974 | if (tv_info) { |
782 | if (RBIOS8(tv_info + 6) == 'T') { |
975 | if (RBIOS8(tv_info + 6) == 'T') { |
783 | switch (RBIOS8(tv_info + 7) & 0xf) { |
976 | switch (RBIOS8(tv_info + 7) & 0xf) { |
784 | case 1: |
977 | case 1: |
785 | tv_std = TV_STD_NTSC; |
978 | tv_std = TV_STD_NTSC; |
786 | DRM_INFO("Default TV standard: NTSC\n"); |
979 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
787 | break; |
980 | break; |
788 | case 2: |
981 | case 2: |
789 | tv_std = TV_STD_PAL; |
982 | tv_std = TV_STD_PAL; |
790 | DRM_INFO("Default TV standard: PAL\n"); |
983 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
791 | break; |
984 | break; |
792 | case 3: |
985 | case 3: |
793 | tv_std = TV_STD_PAL_M; |
986 | tv_std = TV_STD_PAL_M; |
794 | DRM_INFO("Default TV standard: PAL-M\n"); |
987 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
795 | break; |
988 | break; |
796 | case 4: |
989 | case 4: |
797 | tv_std = TV_STD_PAL_60; |
990 | tv_std = TV_STD_PAL_60; |
798 | DRM_INFO("Default TV standard: PAL-60\n"); |
991 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
799 | break; |
992 | break; |
800 | case 5: |
993 | case 5: |
801 | tv_std = TV_STD_NTSC_J; |
994 | tv_std = TV_STD_NTSC_J; |
802 | DRM_INFO("Default TV standard: NTSC-J\n"); |
995 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
803 | break; |
996 | break; |
804 | case 6: |
997 | case 6: |
805 | tv_std = TV_STD_SCART_PAL; |
998 | tv_std = TV_STD_SCART_PAL; |
806 | DRM_INFO("Default TV standard: SCART-PAL\n"); |
999 | DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); |
807 | break; |
1000 | break; |
808 | default: |
1001 | default: |
809 | tv_std = TV_STD_NTSC; |
1002 | tv_std = TV_STD_NTSC; |
810 | DRM_INFO |
1003 | DRM_DEBUG_KMS |
811 | ("Unknown TV standard; defaulting to NTSC\n"); |
1004 | ("Unknown TV standard; defaulting to NTSC\n"); |
812 | break; |
1005 | break; |
813 | } |
1006 | } |
Line 814... | Line 1007... | ||
814 | 1007 | ||
815 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { |
1008 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { |
816 | case 0: |
1009 | case 0: |
817 | DRM_INFO("29.498928713 MHz TV ref clk\n"); |
1010 | DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); |
818 | break; |
1011 | break; |
819 | case 1: |
1012 | case 1: |
820 | DRM_INFO("28.636360000 MHz TV ref clk\n"); |
1013 | DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); |
821 | break; |
1014 | break; |
822 | case 2: |
1015 | case 2: |
823 | DRM_INFO("14.318180000 MHz TV ref clk\n"); |
1016 | DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); |
824 | break; |
1017 | break; |
825 | case 3: |
1018 | case 3: |
826 | DRM_INFO("27.000000000 MHz TV ref clk\n"); |
1019 | DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); |
827 | break; |
1020 | break; |
828 | default: |
1021 | default: |
829 | break; |
1022 | break; |
830 | } |
1023 | } |
Line 894... | Line 1087... | ||
894 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1087 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
Line 895... | Line 1088... | ||
895 | 1088 | ||
896 | bg = RBIOS8(dac_info + 0x10) & 0xf; |
1089 | bg = RBIOS8(dac_info + 0x10) & 0xf; |
897 | dac = RBIOS8(dac_info + 0x11) & 0xf; |
1090 | dac = RBIOS8(dac_info + 0x11) & 0xf; |
- | 1091 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
|
- | 1092 | /* if the values are all zeros, use the table */ |
|
898 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1093 | if (tv_dac->ps2_tvdac_adj) |
899 | found = 1; |
1094 | found = 1; |
900 | } else if (rev > 1) { |
1095 | } else if (rev > 1) { |
901 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
1096 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
902 | dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; |
1097 | dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; |
Line 907... | Line 1102... | ||
907 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1102 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
Line 908... | Line 1103... | ||
908 | 1103 | ||
909 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
1104 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
910 | dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; |
1105 | dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; |
- | 1106 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
|
- | 1107 | /* if the values are all zeros, use the table */ |
|
911 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1108 | if (tv_dac->ps2_tvdac_adj) |
912 | found = 1; |
1109 | found = 1; |
913 | } |
1110 | } |
914 | tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
1111 | tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
915 | } |
1112 | } |
Line 924... | Line 1121... | ||
924 | dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; |
1121 | dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; |
925 | tv_dac->ps2_tvdac_adj = |
1122 | tv_dac->ps2_tvdac_adj = |
926 | (bg << 16) | (dac << 20); |
1123 | (bg << 16) | (dac << 20); |
927 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1124 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
928 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1125 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
- | 1126 | /* if the values are all zeros, use the table */ |
|
- | 1127 | if (tv_dac->ps2_tvdac_adj) |
|
929 | found = 1; |
1128 | found = 1; |
930 | } else { |
1129 | } else { |
931 | bg = RBIOS8(dac_info + 0x4) & 0xf; |
1130 | bg = RBIOS8(dac_info + 0x4) & 0xf; |
932 | dac = RBIOS8(dac_info + 0x5) & 0xf; |
1131 | dac = RBIOS8(dac_info + 0x5) & 0xf; |
933 | tv_dac->ps2_tvdac_adj = |
1132 | tv_dac->ps2_tvdac_adj = |
934 | (bg << 16) | (dac << 20); |
1133 | (bg << 16) | (dac << 20); |
935 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1134 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
936 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1135 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
- | 1136 | /* if the values are all zeros, use the table */ |
|
- | 1137 | if (tv_dac->ps2_tvdac_adj) |
|
937 | found = 1; |
1138 | found = 1; |
938 | } |
1139 | } |
939 | } else { |
1140 | } else { |
940 | DRM_INFO("No TV DAC info found in BIOS\n"); |
1141 | DRM_INFO("No TV DAC info found in BIOS\n"); |
941 | } |
1142 | } |
Line 1102... | Line 1303... | ||
1102 | tmp = RBIOS16(lcd_info + 64 + i * 2); |
1303 | tmp = RBIOS16(lcd_info + 64 + i * 2); |
1103 | if (tmp == 0) |
1304 | if (tmp == 0) |
1104 | break; |
1305 | break; |
Line 1105... | Line 1306... | ||
1105 | 1306 | ||
1106 | if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && |
1307 | if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && |
1107 | (RBIOS16(tmp + 2) == |
1308 | (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { |
1108 | lvds->native_mode.vdisplay)) { |
1309 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1109 | lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8; |
1310 | (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; |
- | 1311 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
|
1110 | lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8; |
1312 | (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; |
1111 | lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) + |
1313 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
1112 | RBIOS16(tmp + 21)) * 8; |
1314 | (RBIOS8(tmp + 23) * 8); |
1113 | 1315 | ||
1114 | lvds->native_mode.vtotal = RBIOS16(tmp + 24); |
1316 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
1115 | lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff; |
1317 | (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); |
1116 | lvds->native_mode.vsync_end = |
1318 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
- | 1319 | ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); |
|
1117 | ((RBIOS16(tmp + 28) & 0xf800) >> 11) + |
1320 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
Line 1118... | Line 1321... | ||
1118 | (RBIOS16(tmp + 28) & 0x7ff); |
1321 | ((RBIOS16(tmp + 28) & 0xf800) >> 11); |
1119 | 1322 | ||
1120 | lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; |
1323 | lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; |
1121 | lvds->native_mode.flags = 0; |
1324 | lvds->native_mode.flags = 0; |
Line 1182... | Line 1385... | ||
1182 | 1385 | ||
Line 1183... | Line 1386... | ||
1183 | tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
1386 | tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
1184 | 1387 | ||
1185 | if (tmds_info) { |
1388 | if (tmds_info) { |
1186 | ver = RBIOS8(tmds_info); |
1389 | ver = RBIOS8(tmds_info); |
1187 | DRM_INFO("DFP table revision: %d\n", ver); |
1390 | DRM_DEBUG_KMS("DFP table revision: %d\n", ver); |
1188 | if (ver == 3) { |
1391 | if (ver == 3) { |
1189 | n = RBIOS8(tmds_info + 5) + 1; |
1392 | n = RBIOS8(tmds_info + 5) + 1; |
1190 | if (n > 4) |
1393 | if (n > 4) |
1191 | n = 4; |
1394 | n = 4; |
1192 | for (i = 0; i < n; i++) { |
1395 | for (i = 0; i < n; i++) { |
1193 | tmds->tmds_pll[i].value = |
1396 | tmds->tmds_pll[i].value = |
1194 | RBIOS32(tmds_info + i * 10 + 0x08); |
1397 | RBIOS32(tmds_info + i * 10 + 0x08); |
1195 | tmds->tmds_pll[i].freq = |
1398 | tmds->tmds_pll[i].freq = |
1196 | RBIOS16(tmds_info + i * 10 + 0x10); |
1399 | RBIOS16(tmds_info + i * 10 + 0x10); |
1197 | DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", |
1400 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1198 | tmds->tmds_pll[i].freq, |
1401 | tmds->tmds_pll[i].freq, |
1199 | tmds->tmds_pll[i].value); |
1402 | tmds->tmds_pll[i].value); |
1200 | } |
1403 | } |
Line 1210... | Line 1413... | ||
1210 | RBIOS16(tmds_info + stride + 0x10); |
1413 | RBIOS16(tmds_info + stride + 0x10); |
1211 | if (i == 0) |
1414 | if (i == 0) |
1212 | stride += 10; |
1415 | stride += 10; |
1213 | else |
1416 | else |
1214 | stride += 6; |
1417 | stride += 6; |
1215 | DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", |
1418 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1216 | tmds->tmds_pll[i].freq, |
1419 | tmds->tmds_pll[i].freq, |
1217 | tmds->tmds_pll[i].value); |
1420 | tmds->tmds_pll[i].value); |
1218 | } |
1421 | } |
1219 | } |
1422 | } |
1220 | } else { |
1423 | } else { |
Line 1230... | Line 1433... | ||
1230 | struct drm_device *dev = encoder->base.dev; |
1433 | struct drm_device *dev = encoder->base.dev; |
1231 | struct radeon_device *rdev = dev->dev_private; |
1434 | struct radeon_device *rdev = dev->dev_private; |
1232 | struct radeon_i2c_bus_rec i2c_bus; |
1435 | struct radeon_i2c_bus_rec i2c_bus; |
Line 1233... | Line 1436... | ||
1233 | 1436 | ||
1234 | /* default for macs */ |
1437 | /* default for macs */ |
1235 | i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
1438 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
Line 1236... | Line 1439... | ||
1236 | tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
1439 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1237 | 1440 | ||
1238 | /* XXX some macs have duallink chips */ |
1441 | /* XXX some macs have duallink chips */ |
1239 | switch (rdev->mode_info.connector_table) { |
1442 | switch (rdev->mode_info.connector_table) { |
Line 1252... | Line 1455... | ||
1252 | struct radeon_encoder_ext_tmds *tmds) |
1455 | struct radeon_encoder_ext_tmds *tmds) |
1253 | { |
1456 | { |
1254 | struct drm_device *dev = encoder->base.dev; |
1457 | struct drm_device *dev = encoder->base.dev; |
1255 | struct radeon_device *rdev = dev->dev_private; |
1458 | struct radeon_device *rdev = dev->dev_private; |
1256 | uint16_t offset; |
1459 | uint16_t offset; |
1257 | uint8_t ver, id, blocks, clk, data; |
- | |
1258 | int i; |
1460 | uint8_t ver; |
1259 | enum radeon_combios_ddc gpio; |
1461 | enum radeon_combios_ddc gpio; |
1260 | struct radeon_i2c_bus_rec i2c_bus; |
1462 | struct radeon_i2c_bus_rec i2c_bus; |
Line 1261... | Line 1463... | ||
1261 | 1463 | ||
1262 | tmds->i2c_bus = NULL; |
1464 | tmds->i2c_bus = NULL; |
1263 | if (rdev->flags & RADEON_IS_IGP) { |
1465 | if (rdev->flags & RADEON_IS_IGP) { |
1264 | offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
- | |
1265 | if (offset) { |
- | |
1266 | ver = RBIOS8(offset); |
- | |
1267 | DRM_INFO("GPIO Table revision: %d\n", ver); |
- | |
1268 | blocks = RBIOS8(offset + 2); |
- | |
1269 | for (i = 0; i < blocks; i++) { |
- | |
1270 | id = RBIOS8(offset + 3 + (i * 5) + 0); |
- | |
1271 | if (id == 136) { |
- | |
1272 | clk = RBIOS8(offset + 3 + (i * 5) + 3); |
- | |
1273 | data = RBIOS8(offset + 3 + (i * 5) + 4); |
- | |
1274 | i2c_bus.valid = true; |
- | |
1275 | i2c_bus.mask_clk_mask = (1 << clk); |
- | |
1276 | i2c_bus.mask_data_mask = (1 << data); |
- | |
1277 | i2c_bus.a_clk_mask = (1 << clk); |
- | |
1278 | i2c_bus.a_data_mask = (1 << data); |
- | |
1279 | i2c_bus.en_clk_mask = (1 << clk); |
- | |
1280 | i2c_bus.en_data_mask = (1 << data); |
- | |
1281 | i2c_bus.y_clk_mask = (1 << clk); |
- | |
1282 | i2c_bus.y_data_mask = (1 << data); |
- | |
1283 | i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK; |
- | |
1284 | i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK; |
- | |
1285 | i2c_bus.a_clk_reg = RADEON_GPIOPAD_A; |
- | |
1286 | i2c_bus.a_data_reg = RADEON_GPIOPAD_A; |
- | |
1287 | i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN; |
- | |
1288 | i2c_bus.en_data_reg = RADEON_GPIOPAD_EN; |
- | |
1289 | i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y; |
- | |
1290 | i2c_bus.y_data_reg = RADEON_GPIOPAD_Y; |
1466 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1291 | tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
1467 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1292 | tmds->dvo_chip = DVO_SIL164; |
1468 | tmds->dvo_chip = DVO_SIL164; |
1293 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
- | |
1294 | break; |
- | |
1295 | } |
- | |
1296 | } |
- | |
1297 | } |
1469 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
1298 | } else { |
1470 | } else { |
1299 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
1471 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
1300 | if (offset) { |
1472 | if (offset) { |
1301 | ver = RBIOS8(offset); |
1473 | ver = RBIOS8(offset); |
1302 | DRM_INFO("External TMDS Table revision: %d\n", ver); |
1474 | DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); |
1303 | tmds->slave_addr = RBIOS8(offset + 4 + 2); |
1475 | tmds->slave_addr = RBIOS8(offset + 4 + 2); |
1304 | tmds->slave_addr >>= 1; /* 7 bit addressing */ |
1476 | tmds->slave_addr >>= 1; /* 7 bit addressing */ |
1305 | gpio = RBIOS8(offset + 4 + 3); |
1477 | gpio = RBIOS8(offset + 4 + 3); |
1306 | switch (gpio) { |
- | |
1307 | case DDC_MONID: |
- | |
1308 | i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
- | |
1309 | tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
- | |
1310 | break; |
- | |
1311 | case DDC_DVI: |
- | |
1312 | i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
- | |
1313 | tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
- | |
1314 | break; |
- | |
1315 | case DDC_VGA: |
- | |
1316 | i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
- | |
1317 | tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
- | |
1318 | break; |
- | |
1319 | case DDC_CRT2: |
- | |
1320 | /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ |
- | |
1321 | if (rdev->family >= CHIP_R300) |
- | |
1322 | i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
- | |
1323 | else |
- | |
1324 | i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
- | |
1325 | tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
- | |
1326 | break; |
1478 | if (gpio == DDC_LCD) { |
1327 | case DDC_LCD: /* MM i2c */ |
1479 | /* MM i2c */ |
1328 | i2c_bus.valid = true; |
1480 | i2c_bus.valid = true; |
1329 | i2c_bus.hw_capable = true; |
1481 | i2c_bus.hw_capable = true; |
1330 | i2c_bus.mm_i2c = true; |
1482 | i2c_bus.mm_i2c = true; |
1331 | tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
1483 | i2c_bus.i2c_id = 0xa0; |
1332 | break; |
- | |
1333 | default: |
1484 | } else |
1334 | DRM_ERROR("Unsupported gpio %d\n", gpio); |
1485 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
1335 | break; |
- | |
1336 | } |
1486 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1337 | } |
1487 | } |
Line 1338... | Line 1488... | ||
1338 | } |
1488 | } |
1339 | 1489 | ||
Line 1396... | Line 1546... | ||
1396 | rdev->mode_info.connector_table = CT_MINI_EXTERNAL; |
1546 | rdev->mode_info.connector_table = CT_MINI_EXTERNAL; |
1397 | } else if (of_machine_is_compatible("PowerMac12,1")) { |
1547 | } else if (of_machine_is_compatible("PowerMac12,1")) { |
1398 | /* PowerMac8,1 ? */ |
1548 | /* PowerMac8,1 ? */ |
1399 | /* imac g5 isight */ |
1549 | /* imac g5 isight */ |
1400 | rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; |
1550 | rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; |
- | 1551 | } else if ((rdev->pdev->device == 0x4a48) && |
|
- | 1552 | (rdev->pdev->subsystem_vendor == 0x1002) && |
|
- | 1553 | (rdev->pdev->subsystem_device == 0x4a48)) { |
|
- | 1554 | /* Mac X800 */ |
|
- | 1555 | rdev->mode_info.connector_table = CT_MAC_X800; |
|
- | 1556 | } else if (of_machine_is_compatible("PowerMac7,2") || |
|
- | 1557 | of_machine_is_compatible("PowerMac7,3")) { |
|
- | 1558 | /* Mac G5 9600 */ |
|
- | 1559 | rdev->mode_info.connector_table = CT_MAC_G5_9600; |
|
1401 | } else |
1560 | } else |
1402 | #endif /* CONFIG_PPC_PMAC */ |
1561 | #endif /* CONFIG_PPC_PMAC */ |
- | 1562 | #ifdef CONFIG_PPC64 |
|
- | 1563 | if (ASIC_IS_RN50(rdev)) |
|
- | 1564 | rdev->mode_info.connector_table = CT_RN50_POWER; |
|
- | 1565 | else |
|
- | 1566 | #endif |
|
1403 | rdev->mode_info.connector_table = CT_GENERIC; |
1567 | rdev->mode_info.connector_table = CT_GENERIC; |
1404 | } |
1568 | } |
Line 1405... | Line 1569... | ||
1405 | 1569 | ||
1406 | switch (rdev->mode_info.connector_table) { |
1570 | switch (rdev->mode_info.connector_table) { |
1407 | case CT_GENERIC: |
1571 | case CT_GENERIC: |
1408 | DRM_INFO("Connector Table: %d (generic)\n", |
1572 | DRM_INFO("Connector Table: %d (generic)\n", |
1409 | rdev->mode_info.connector_table); |
1573 | rdev->mode_info.connector_table); |
1410 | /* these are the most common settings */ |
1574 | /* these are the most common settings */ |
1411 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
1575 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
1412 | /* VGA - primary dac */ |
1576 | /* VGA - primary dac */ |
1413 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1577 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1414 | hpd.hpd = RADEON_HPD_NONE; |
1578 | hpd.hpd = RADEON_HPD_NONE; |
1415 | radeon_add_legacy_encoder(dev, |
1579 | radeon_add_legacy_encoder(dev, |
1416 | radeon_get_encoder_id(dev, |
1580 | radeon_get_encoder_enum(dev, |
1417 | ATOM_DEVICE_CRT1_SUPPORT, |
1581 | ATOM_DEVICE_CRT1_SUPPORT, |
1418 | 1), |
1582 | 1), |
1419 | ATOM_DEVICE_CRT1_SUPPORT); |
1583 | ATOM_DEVICE_CRT1_SUPPORT); |
1420 | radeon_add_legacy_connector(dev, 0, |
1584 | radeon_add_legacy_connector(dev, 0, |
Line 1423... | Line 1587... | ||
1423 | &ddc_i2c, |
1587 | &ddc_i2c, |
1424 | CONNECTOR_OBJECT_ID_VGA, |
1588 | CONNECTOR_OBJECT_ID_VGA, |
1425 | &hpd); |
1589 | &hpd); |
1426 | } else if (rdev->flags & RADEON_IS_MOBILITY) { |
1590 | } else if (rdev->flags & RADEON_IS_MOBILITY) { |
1427 | /* LVDS */ |
1591 | /* LVDS */ |
1428 | ddc_i2c = combios_setup_i2c_bus(rdev, 0); |
1592 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
1429 | hpd.hpd = RADEON_HPD_NONE; |
1593 | hpd.hpd = RADEON_HPD_NONE; |
1430 | radeon_add_legacy_encoder(dev, |
1594 | radeon_add_legacy_encoder(dev, |
1431 | radeon_get_encoder_id(dev, |
1595 | radeon_get_encoder_enum(dev, |
1432 | ATOM_DEVICE_LCD1_SUPPORT, |
1596 | ATOM_DEVICE_LCD1_SUPPORT, |
1433 | 0), |
1597 | 0), |
1434 | ATOM_DEVICE_LCD1_SUPPORT); |
1598 | ATOM_DEVICE_LCD1_SUPPORT); |
1435 | radeon_add_legacy_connector(dev, 0, |
1599 | radeon_add_legacy_connector(dev, 0, |
1436 | ATOM_DEVICE_LCD1_SUPPORT, |
1600 | ATOM_DEVICE_LCD1_SUPPORT, |
Line 1438... | Line 1602... | ||
1438 | &ddc_i2c, |
1602 | &ddc_i2c, |
1439 | CONNECTOR_OBJECT_ID_LVDS, |
1603 | CONNECTOR_OBJECT_ID_LVDS, |
1440 | &hpd); |
1604 | &hpd); |
Line 1441... | Line 1605... | ||
1441 | 1605 | ||
1442 | /* VGA - primary dac */ |
1606 | /* VGA - primary dac */ |
1443 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1607 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1444 | hpd.hpd = RADEON_HPD_NONE; |
1608 | hpd.hpd = RADEON_HPD_NONE; |
1445 | radeon_add_legacy_encoder(dev, |
1609 | radeon_add_legacy_encoder(dev, |
1446 | radeon_get_encoder_id(dev, |
1610 | radeon_get_encoder_enum(dev, |
1447 | ATOM_DEVICE_CRT1_SUPPORT, |
1611 | ATOM_DEVICE_CRT1_SUPPORT, |
1448 | 1), |
1612 | 1), |
1449 | ATOM_DEVICE_CRT1_SUPPORT); |
1613 | ATOM_DEVICE_CRT1_SUPPORT); |
1450 | radeon_add_legacy_connector(dev, 1, |
1614 | radeon_add_legacy_connector(dev, 1, |
Line 1453... | Line 1617... | ||
1453 | &ddc_i2c, |
1617 | &ddc_i2c, |
1454 | CONNECTOR_OBJECT_ID_VGA, |
1618 | CONNECTOR_OBJECT_ID_VGA, |
1455 | &hpd); |
1619 | &hpd); |
1456 | } else { |
1620 | } else { |
1457 | /* DVI-I - tv dac, int tmds */ |
1621 | /* DVI-I - tv dac, int tmds */ |
1458 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
1622 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1459 | hpd.hpd = RADEON_HPD_1; |
1623 | hpd.hpd = RADEON_HPD_1; |
1460 | radeon_add_legacy_encoder(dev, |
1624 | radeon_add_legacy_encoder(dev, |
1461 | radeon_get_encoder_id(dev, |
1625 | radeon_get_encoder_enum(dev, |
1462 | ATOM_DEVICE_DFP1_SUPPORT, |
1626 | ATOM_DEVICE_DFP1_SUPPORT, |
1463 | 0), |
1627 | 0), |
1464 | ATOM_DEVICE_DFP1_SUPPORT); |
1628 | ATOM_DEVICE_DFP1_SUPPORT); |
1465 | radeon_add_legacy_encoder(dev, |
1629 | radeon_add_legacy_encoder(dev, |
1466 | radeon_get_encoder_id(dev, |
1630 | radeon_get_encoder_enum(dev, |
1467 | ATOM_DEVICE_CRT2_SUPPORT, |
1631 | ATOM_DEVICE_CRT2_SUPPORT, |
1468 | 2), |
1632 | 2), |
1469 | ATOM_DEVICE_CRT2_SUPPORT); |
1633 | ATOM_DEVICE_CRT2_SUPPORT); |
1470 | radeon_add_legacy_connector(dev, 0, |
1634 | radeon_add_legacy_connector(dev, 0, |
1471 | ATOM_DEVICE_DFP1_SUPPORT | |
1635 | ATOM_DEVICE_DFP1_SUPPORT | |
Line 1474... | Line 1638... | ||
1474 | &ddc_i2c, |
1638 | &ddc_i2c, |
1475 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1639 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1476 | &hpd); |
1640 | &hpd); |
Line 1477... | Line 1641... | ||
1477 | 1641 | ||
1478 | /* VGA - primary dac */ |
1642 | /* VGA - primary dac */ |
1479 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1643 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1480 | hpd.hpd = RADEON_HPD_NONE; |
1644 | hpd.hpd = RADEON_HPD_NONE; |
1481 | radeon_add_legacy_encoder(dev, |
1645 | radeon_add_legacy_encoder(dev, |
1482 | radeon_get_encoder_id(dev, |
1646 | radeon_get_encoder_enum(dev, |
1483 | ATOM_DEVICE_CRT1_SUPPORT, |
1647 | ATOM_DEVICE_CRT1_SUPPORT, |
1484 | 1), |
1648 | 1), |
1485 | ATOM_DEVICE_CRT1_SUPPORT); |
1649 | ATOM_DEVICE_CRT1_SUPPORT); |
1486 | radeon_add_legacy_connector(dev, 1, |
1650 | radeon_add_legacy_connector(dev, 1, |
Line 1494... | Line 1658... | ||
1494 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
1658 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
1495 | /* TV - tv dac */ |
1659 | /* TV - tv dac */ |
1496 | ddc_i2c.valid = false; |
1660 | ddc_i2c.valid = false; |
1497 | hpd.hpd = RADEON_HPD_NONE; |
1661 | hpd.hpd = RADEON_HPD_NONE; |
1498 | radeon_add_legacy_encoder(dev, |
1662 | radeon_add_legacy_encoder(dev, |
1499 | radeon_get_encoder_id(dev, |
1663 | radeon_get_encoder_enum(dev, |
1500 | ATOM_DEVICE_TV1_SUPPORT, |
1664 | ATOM_DEVICE_TV1_SUPPORT, |
1501 | 2), |
1665 | 2), |
1502 | ATOM_DEVICE_TV1_SUPPORT); |
1666 | ATOM_DEVICE_TV1_SUPPORT); |
1503 | radeon_add_legacy_connector(dev, 2, |
1667 | radeon_add_legacy_connector(dev, 2, |
1504 | ATOM_DEVICE_TV1_SUPPORT, |
1668 | ATOM_DEVICE_TV1_SUPPORT, |
Line 1510... | Line 1674... | ||
1510 | break; |
1674 | break; |
1511 | case CT_IBOOK: |
1675 | case CT_IBOOK: |
1512 | DRM_INFO("Connector Table: %d (ibook)\n", |
1676 | DRM_INFO("Connector Table: %d (ibook)\n", |
1513 | rdev->mode_info.connector_table); |
1677 | rdev->mode_info.connector_table); |
1514 | /* LVDS */ |
1678 | /* LVDS */ |
1515 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
1679 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1516 | hpd.hpd = RADEON_HPD_NONE; |
1680 | hpd.hpd = RADEON_HPD_NONE; |
1517 | radeon_add_legacy_encoder(dev, |
1681 | radeon_add_legacy_encoder(dev, |
1518 | radeon_get_encoder_id(dev, |
1682 | radeon_get_encoder_enum(dev, |
1519 | ATOM_DEVICE_LCD1_SUPPORT, |
1683 | ATOM_DEVICE_LCD1_SUPPORT, |
1520 | 0), |
1684 | 0), |
1521 | ATOM_DEVICE_LCD1_SUPPORT); |
1685 | ATOM_DEVICE_LCD1_SUPPORT); |
1522 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1686 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1523 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1687 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1524 | CONNECTOR_OBJECT_ID_LVDS, |
1688 | CONNECTOR_OBJECT_ID_LVDS, |
1525 | &hpd); |
1689 | &hpd); |
1526 | /* VGA - TV DAC */ |
1690 | /* VGA - TV DAC */ |
1527 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1691 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1528 | hpd.hpd = RADEON_HPD_NONE; |
1692 | hpd.hpd = RADEON_HPD_NONE; |
1529 | radeon_add_legacy_encoder(dev, |
1693 | radeon_add_legacy_encoder(dev, |
1530 | radeon_get_encoder_id(dev, |
1694 | radeon_get_encoder_enum(dev, |
1531 | ATOM_DEVICE_CRT2_SUPPORT, |
1695 | ATOM_DEVICE_CRT2_SUPPORT, |
1532 | 2), |
1696 | 2), |
1533 | ATOM_DEVICE_CRT2_SUPPORT); |
1697 | ATOM_DEVICE_CRT2_SUPPORT); |
1534 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1698 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1535 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1699 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Line 1537... | Line 1701... | ||
1537 | &hpd); |
1701 | &hpd); |
1538 | /* TV - TV DAC */ |
1702 | /* TV - TV DAC */ |
1539 | ddc_i2c.valid = false; |
1703 | ddc_i2c.valid = false; |
1540 | hpd.hpd = RADEON_HPD_NONE; |
1704 | hpd.hpd = RADEON_HPD_NONE; |
1541 | radeon_add_legacy_encoder(dev, |
1705 | radeon_add_legacy_encoder(dev, |
1542 | radeon_get_encoder_id(dev, |
1706 | radeon_get_encoder_enum(dev, |
1543 | ATOM_DEVICE_TV1_SUPPORT, |
1707 | ATOM_DEVICE_TV1_SUPPORT, |
1544 | 2), |
1708 | 2), |
1545 | ATOM_DEVICE_TV1_SUPPORT); |
1709 | ATOM_DEVICE_TV1_SUPPORT); |
1546 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1710 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1547 | DRM_MODE_CONNECTOR_SVIDEO, |
1711 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1551... | Line 1715... | ||
1551 | break; |
1715 | break; |
1552 | case CT_POWERBOOK_EXTERNAL: |
1716 | case CT_POWERBOOK_EXTERNAL: |
1553 | DRM_INFO("Connector Table: %d (powerbook external tmds)\n", |
1717 | DRM_INFO("Connector Table: %d (powerbook external tmds)\n", |
1554 | rdev->mode_info.connector_table); |
1718 | rdev->mode_info.connector_table); |
1555 | /* LVDS */ |
1719 | /* LVDS */ |
1556 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
1720 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1557 | hpd.hpd = RADEON_HPD_NONE; |
1721 | hpd.hpd = RADEON_HPD_NONE; |
1558 | radeon_add_legacy_encoder(dev, |
1722 | radeon_add_legacy_encoder(dev, |
1559 | radeon_get_encoder_id(dev, |
1723 | radeon_get_encoder_enum(dev, |
1560 | ATOM_DEVICE_LCD1_SUPPORT, |
1724 | ATOM_DEVICE_LCD1_SUPPORT, |
1561 | 0), |
1725 | 0), |
1562 | ATOM_DEVICE_LCD1_SUPPORT); |
1726 | ATOM_DEVICE_LCD1_SUPPORT); |
1563 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1727 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1564 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1728 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1565 | CONNECTOR_OBJECT_ID_LVDS, |
1729 | CONNECTOR_OBJECT_ID_LVDS, |
1566 | &hpd); |
1730 | &hpd); |
1567 | /* DVI-I - primary dac, ext tmds */ |
1731 | /* DVI-I - primary dac, ext tmds */ |
1568 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1732 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1569 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1733 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1570 | radeon_add_legacy_encoder(dev, |
1734 | radeon_add_legacy_encoder(dev, |
1571 | radeon_get_encoder_id(dev, |
1735 | radeon_get_encoder_enum(dev, |
1572 | ATOM_DEVICE_DFP2_SUPPORT, |
1736 | ATOM_DEVICE_DFP2_SUPPORT, |
1573 | 0), |
1737 | 0), |
1574 | ATOM_DEVICE_DFP2_SUPPORT); |
1738 | ATOM_DEVICE_DFP2_SUPPORT); |
1575 | radeon_add_legacy_encoder(dev, |
1739 | radeon_add_legacy_encoder(dev, |
1576 | radeon_get_encoder_id(dev, |
1740 | radeon_get_encoder_enum(dev, |
1577 | ATOM_DEVICE_CRT1_SUPPORT, |
1741 | ATOM_DEVICE_CRT1_SUPPORT, |
1578 | 1), |
1742 | 1), |
1579 | ATOM_DEVICE_CRT1_SUPPORT); |
1743 | ATOM_DEVICE_CRT1_SUPPORT); |
1580 | /* XXX some are SL */ |
1744 | /* XXX some are SL */ |
1581 | radeon_add_legacy_connector(dev, 1, |
1745 | radeon_add_legacy_connector(dev, 1, |
Line 1586... | Line 1750... | ||
1586 | &hpd); |
1750 | &hpd); |
1587 | /* TV - TV DAC */ |
1751 | /* TV - TV DAC */ |
1588 | ddc_i2c.valid = false; |
1752 | ddc_i2c.valid = false; |
1589 | hpd.hpd = RADEON_HPD_NONE; |
1753 | hpd.hpd = RADEON_HPD_NONE; |
1590 | radeon_add_legacy_encoder(dev, |
1754 | radeon_add_legacy_encoder(dev, |
1591 | radeon_get_encoder_id(dev, |
1755 | radeon_get_encoder_enum(dev, |
1592 | ATOM_DEVICE_TV1_SUPPORT, |
1756 | ATOM_DEVICE_TV1_SUPPORT, |
1593 | 2), |
1757 | 2), |
1594 | ATOM_DEVICE_TV1_SUPPORT); |
1758 | ATOM_DEVICE_TV1_SUPPORT); |
1595 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1759 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1596 | DRM_MODE_CONNECTOR_SVIDEO, |
1760 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1600... | Line 1764... | ||
1600 | break; |
1764 | break; |
1601 | case CT_POWERBOOK_INTERNAL: |
1765 | case CT_POWERBOOK_INTERNAL: |
1602 | DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", |
1766 | DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", |
1603 | rdev->mode_info.connector_table); |
1767 | rdev->mode_info.connector_table); |
1604 | /* LVDS */ |
1768 | /* LVDS */ |
1605 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
1769 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1606 | hpd.hpd = RADEON_HPD_NONE; |
1770 | hpd.hpd = RADEON_HPD_NONE; |
1607 | radeon_add_legacy_encoder(dev, |
1771 | radeon_add_legacy_encoder(dev, |
1608 | radeon_get_encoder_id(dev, |
1772 | radeon_get_encoder_enum(dev, |
1609 | ATOM_DEVICE_LCD1_SUPPORT, |
1773 | ATOM_DEVICE_LCD1_SUPPORT, |
1610 | 0), |
1774 | 0), |
1611 | ATOM_DEVICE_LCD1_SUPPORT); |
1775 | ATOM_DEVICE_LCD1_SUPPORT); |
1612 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1776 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1613 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1777 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1614 | CONNECTOR_OBJECT_ID_LVDS, |
1778 | CONNECTOR_OBJECT_ID_LVDS, |
1615 | &hpd); |
1779 | &hpd); |
1616 | /* DVI-I - primary dac, int tmds */ |
1780 | /* DVI-I - primary dac, int tmds */ |
1617 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1781 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1618 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1782 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1619 | radeon_add_legacy_encoder(dev, |
1783 | radeon_add_legacy_encoder(dev, |
1620 | radeon_get_encoder_id(dev, |
1784 | radeon_get_encoder_enum(dev, |
1621 | ATOM_DEVICE_DFP1_SUPPORT, |
1785 | ATOM_DEVICE_DFP1_SUPPORT, |
1622 | 0), |
1786 | 0), |
1623 | ATOM_DEVICE_DFP1_SUPPORT); |
1787 | ATOM_DEVICE_DFP1_SUPPORT); |
1624 | radeon_add_legacy_encoder(dev, |
1788 | radeon_add_legacy_encoder(dev, |
1625 | radeon_get_encoder_id(dev, |
1789 | radeon_get_encoder_enum(dev, |
1626 | ATOM_DEVICE_CRT1_SUPPORT, |
1790 | ATOM_DEVICE_CRT1_SUPPORT, |
1627 | 1), |
1791 | 1), |
1628 | ATOM_DEVICE_CRT1_SUPPORT); |
1792 | ATOM_DEVICE_CRT1_SUPPORT); |
1629 | radeon_add_legacy_connector(dev, 1, |
1793 | radeon_add_legacy_connector(dev, 1, |
1630 | ATOM_DEVICE_DFP1_SUPPORT | |
1794 | ATOM_DEVICE_DFP1_SUPPORT | |
Line 1634... | Line 1798... | ||
1634 | &hpd); |
1798 | &hpd); |
1635 | /* TV - TV DAC */ |
1799 | /* TV - TV DAC */ |
1636 | ddc_i2c.valid = false; |
1800 | ddc_i2c.valid = false; |
1637 | hpd.hpd = RADEON_HPD_NONE; |
1801 | hpd.hpd = RADEON_HPD_NONE; |
1638 | radeon_add_legacy_encoder(dev, |
1802 | radeon_add_legacy_encoder(dev, |
1639 | radeon_get_encoder_id(dev, |
1803 | radeon_get_encoder_enum(dev, |
1640 | ATOM_DEVICE_TV1_SUPPORT, |
1804 | ATOM_DEVICE_TV1_SUPPORT, |
1641 | 2), |
1805 | 2), |
1642 | ATOM_DEVICE_TV1_SUPPORT); |
1806 | ATOM_DEVICE_TV1_SUPPORT); |
1643 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1807 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1644 | DRM_MODE_CONNECTOR_SVIDEO, |
1808 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1648... | Line 1812... | ||
1648 | break; |
1812 | break; |
1649 | case CT_POWERBOOK_VGA: |
1813 | case CT_POWERBOOK_VGA: |
1650 | DRM_INFO("Connector Table: %d (powerbook vga)\n", |
1814 | DRM_INFO("Connector Table: %d (powerbook vga)\n", |
1651 | rdev->mode_info.connector_table); |
1815 | rdev->mode_info.connector_table); |
1652 | /* LVDS */ |
1816 | /* LVDS */ |
1653 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
1817 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1654 | hpd.hpd = RADEON_HPD_NONE; |
1818 | hpd.hpd = RADEON_HPD_NONE; |
1655 | radeon_add_legacy_encoder(dev, |
1819 | radeon_add_legacy_encoder(dev, |
1656 | radeon_get_encoder_id(dev, |
1820 | radeon_get_encoder_enum(dev, |
1657 | ATOM_DEVICE_LCD1_SUPPORT, |
1821 | ATOM_DEVICE_LCD1_SUPPORT, |
1658 | 0), |
1822 | 0), |
1659 | ATOM_DEVICE_LCD1_SUPPORT); |
1823 | ATOM_DEVICE_LCD1_SUPPORT); |
1660 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1824 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1661 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1825 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1662 | CONNECTOR_OBJECT_ID_LVDS, |
1826 | CONNECTOR_OBJECT_ID_LVDS, |
1663 | &hpd); |
1827 | &hpd); |
1664 | /* VGA - primary dac */ |
1828 | /* VGA - primary dac */ |
1665 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1829 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1666 | hpd.hpd = RADEON_HPD_NONE; |
1830 | hpd.hpd = RADEON_HPD_NONE; |
1667 | radeon_add_legacy_encoder(dev, |
1831 | radeon_add_legacy_encoder(dev, |
1668 | radeon_get_encoder_id(dev, |
1832 | radeon_get_encoder_enum(dev, |
1669 | ATOM_DEVICE_CRT1_SUPPORT, |
1833 | ATOM_DEVICE_CRT1_SUPPORT, |
1670 | 1), |
1834 | 1), |
1671 | ATOM_DEVICE_CRT1_SUPPORT); |
1835 | ATOM_DEVICE_CRT1_SUPPORT); |
1672 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
1836 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
1673 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1837 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Line 1675... | Line 1839... | ||
1675 | &hpd); |
1839 | &hpd); |
1676 | /* TV - TV DAC */ |
1840 | /* TV - TV DAC */ |
1677 | ddc_i2c.valid = false; |
1841 | ddc_i2c.valid = false; |
1678 | hpd.hpd = RADEON_HPD_NONE; |
1842 | hpd.hpd = RADEON_HPD_NONE; |
1679 | radeon_add_legacy_encoder(dev, |
1843 | radeon_add_legacy_encoder(dev, |
1680 | radeon_get_encoder_id(dev, |
1844 | radeon_get_encoder_enum(dev, |
1681 | ATOM_DEVICE_TV1_SUPPORT, |
1845 | ATOM_DEVICE_TV1_SUPPORT, |
1682 | 2), |
1846 | 2), |
1683 | ATOM_DEVICE_TV1_SUPPORT); |
1847 | ATOM_DEVICE_TV1_SUPPORT); |
1684 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1848 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1685 | DRM_MODE_CONNECTOR_SVIDEO, |
1849 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1689... | Line 1853... | ||
1689 | break; |
1853 | break; |
1690 | case CT_MINI_EXTERNAL: |
1854 | case CT_MINI_EXTERNAL: |
1691 | DRM_INFO("Connector Table: %d (mini external tmds)\n", |
1855 | DRM_INFO("Connector Table: %d (mini external tmds)\n", |
1692 | rdev->mode_info.connector_table); |
1856 | rdev->mode_info.connector_table); |
1693 | /* DVI-I - tv dac, ext tmds */ |
1857 | /* DVI-I - tv dac, ext tmds */ |
1694 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
1858 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1695 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1859 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1696 | radeon_add_legacy_encoder(dev, |
1860 | radeon_add_legacy_encoder(dev, |
1697 | radeon_get_encoder_id(dev, |
1861 | radeon_get_encoder_enum(dev, |
1698 | ATOM_DEVICE_DFP2_SUPPORT, |
1862 | ATOM_DEVICE_DFP2_SUPPORT, |
1699 | 0), |
1863 | 0), |
1700 | ATOM_DEVICE_DFP2_SUPPORT); |
1864 | ATOM_DEVICE_DFP2_SUPPORT); |
1701 | radeon_add_legacy_encoder(dev, |
1865 | radeon_add_legacy_encoder(dev, |
1702 | radeon_get_encoder_id(dev, |
1866 | radeon_get_encoder_enum(dev, |
1703 | ATOM_DEVICE_CRT2_SUPPORT, |
1867 | ATOM_DEVICE_CRT2_SUPPORT, |
1704 | 2), |
1868 | 2), |
1705 | ATOM_DEVICE_CRT2_SUPPORT); |
1869 | ATOM_DEVICE_CRT2_SUPPORT); |
1706 | /* XXX are any DL? */ |
1870 | /* XXX are any DL? */ |
1707 | radeon_add_legacy_connector(dev, 0, |
1871 | radeon_add_legacy_connector(dev, 0, |
Line 1712... | Line 1876... | ||
1712 | &hpd); |
1876 | &hpd); |
1713 | /* TV - TV DAC */ |
1877 | /* TV - TV DAC */ |
1714 | ddc_i2c.valid = false; |
1878 | ddc_i2c.valid = false; |
1715 | hpd.hpd = RADEON_HPD_NONE; |
1879 | hpd.hpd = RADEON_HPD_NONE; |
1716 | radeon_add_legacy_encoder(dev, |
1880 | radeon_add_legacy_encoder(dev, |
1717 | radeon_get_encoder_id(dev, |
1881 | radeon_get_encoder_enum(dev, |
1718 | ATOM_DEVICE_TV1_SUPPORT, |
1882 | ATOM_DEVICE_TV1_SUPPORT, |
1719 | 2), |
1883 | 2), |
1720 | ATOM_DEVICE_TV1_SUPPORT); |
1884 | ATOM_DEVICE_TV1_SUPPORT); |
1721 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1885 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1722 | DRM_MODE_CONNECTOR_SVIDEO, |
1886 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1726... | Line 1890... | ||
1726 | break; |
1890 | break; |
1727 | case CT_MINI_INTERNAL: |
1891 | case CT_MINI_INTERNAL: |
1728 | DRM_INFO("Connector Table: %d (mini internal tmds)\n", |
1892 | DRM_INFO("Connector Table: %d (mini internal tmds)\n", |
1729 | rdev->mode_info.connector_table); |
1893 | rdev->mode_info.connector_table); |
1730 | /* DVI-I - tv dac, int tmds */ |
1894 | /* DVI-I - tv dac, int tmds */ |
1731 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
1895 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1732 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1896 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1733 | radeon_add_legacy_encoder(dev, |
1897 | radeon_add_legacy_encoder(dev, |
1734 | radeon_get_encoder_id(dev, |
1898 | radeon_get_encoder_enum(dev, |
1735 | ATOM_DEVICE_DFP1_SUPPORT, |
1899 | ATOM_DEVICE_DFP1_SUPPORT, |
1736 | 0), |
1900 | 0), |
1737 | ATOM_DEVICE_DFP1_SUPPORT); |
1901 | ATOM_DEVICE_DFP1_SUPPORT); |
1738 | radeon_add_legacy_encoder(dev, |
1902 | radeon_add_legacy_encoder(dev, |
1739 | radeon_get_encoder_id(dev, |
1903 | radeon_get_encoder_enum(dev, |
1740 | ATOM_DEVICE_CRT2_SUPPORT, |
1904 | ATOM_DEVICE_CRT2_SUPPORT, |
1741 | 2), |
1905 | 2), |
1742 | ATOM_DEVICE_CRT2_SUPPORT); |
1906 | ATOM_DEVICE_CRT2_SUPPORT); |
1743 | radeon_add_legacy_connector(dev, 0, |
1907 | radeon_add_legacy_connector(dev, 0, |
1744 | ATOM_DEVICE_DFP1_SUPPORT | |
1908 | ATOM_DEVICE_DFP1_SUPPORT | |
Line 1748... | Line 1912... | ||
1748 | &hpd); |
1912 | &hpd); |
1749 | /* TV - TV DAC */ |
1913 | /* TV - TV DAC */ |
1750 | ddc_i2c.valid = false; |
1914 | ddc_i2c.valid = false; |
1751 | hpd.hpd = RADEON_HPD_NONE; |
1915 | hpd.hpd = RADEON_HPD_NONE; |
1752 | radeon_add_legacy_encoder(dev, |
1916 | radeon_add_legacy_encoder(dev, |
1753 | radeon_get_encoder_id(dev, |
1917 | radeon_get_encoder_enum(dev, |
1754 | ATOM_DEVICE_TV1_SUPPORT, |
1918 | ATOM_DEVICE_TV1_SUPPORT, |
1755 | 2), |
1919 | 2), |
1756 | ATOM_DEVICE_TV1_SUPPORT); |
1920 | ATOM_DEVICE_TV1_SUPPORT); |
1757 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1921 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1758 | DRM_MODE_CONNECTOR_SVIDEO, |
1922 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1762... | Line 1926... | ||
1762 | break; |
1926 | break; |
1763 | case CT_IMAC_G5_ISIGHT: |
1927 | case CT_IMAC_G5_ISIGHT: |
1764 | DRM_INFO("Connector Table: %d (imac g5 isight)\n", |
1928 | DRM_INFO("Connector Table: %d (imac g5 isight)\n", |
1765 | rdev->mode_info.connector_table); |
1929 | rdev->mode_info.connector_table); |
1766 | /* DVI-D - int tmds */ |
1930 | /* DVI-D - int tmds */ |
1767 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
1931 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1768 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1932 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1769 | radeon_add_legacy_encoder(dev, |
1933 | radeon_add_legacy_encoder(dev, |
1770 | radeon_get_encoder_id(dev, |
1934 | radeon_get_encoder_enum(dev, |
1771 | ATOM_DEVICE_DFP1_SUPPORT, |
1935 | ATOM_DEVICE_DFP1_SUPPORT, |
1772 | 0), |
1936 | 0), |
1773 | ATOM_DEVICE_DFP1_SUPPORT); |
1937 | ATOM_DEVICE_DFP1_SUPPORT); |
1774 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, |
1938 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, |
1775 | DRM_MODE_CONNECTOR_DVID, &ddc_i2c, |
1939 | DRM_MODE_CONNECTOR_DVID, &ddc_i2c, |
1776 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
1940 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
1777 | &hpd); |
1941 | &hpd); |
1778 | /* VGA - tv dac */ |
1942 | /* VGA - tv dac */ |
1779 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
1943 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1780 | hpd.hpd = RADEON_HPD_NONE; |
1944 | hpd.hpd = RADEON_HPD_NONE; |
1781 | radeon_add_legacy_encoder(dev, |
1945 | radeon_add_legacy_encoder(dev, |
1782 | radeon_get_encoder_id(dev, |
1946 | radeon_get_encoder_enum(dev, |
1783 | ATOM_DEVICE_CRT2_SUPPORT, |
1947 | ATOM_DEVICE_CRT2_SUPPORT, |
1784 | 2), |
1948 | 2), |
1785 | ATOM_DEVICE_CRT2_SUPPORT); |
1949 | ATOM_DEVICE_CRT2_SUPPORT); |
1786 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1950 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1787 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1951 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Line 1789... | Line 1953... | ||
1789 | &hpd); |
1953 | &hpd); |
1790 | /* TV - TV DAC */ |
1954 | /* TV - TV DAC */ |
1791 | ddc_i2c.valid = false; |
1955 | ddc_i2c.valid = false; |
1792 | hpd.hpd = RADEON_HPD_NONE; |
1956 | hpd.hpd = RADEON_HPD_NONE; |
1793 | radeon_add_legacy_encoder(dev, |
1957 | radeon_add_legacy_encoder(dev, |
1794 | radeon_get_encoder_id(dev, |
1958 | radeon_get_encoder_enum(dev, |
1795 | ATOM_DEVICE_TV1_SUPPORT, |
1959 | ATOM_DEVICE_TV1_SUPPORT, |
1796 | 2), |
1960 | 2), |
1797 | ATOM_DEVICE_TV1_SUPPORT); |
1961 | ATOM_DEVICE_TV1_SUPPORT); |
1798 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1962 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1799 | DRM_MODE_CONNECTOR_SVIDEO, |
1963 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1803... | Line 1967... | ||
1803 | break; |
1967 | break; |
1804 | case CT_EMAC: |
1968 | case CT_EMAC: |
1805 | DRM_INFO("Connector Table: %d (emac)\n", |
1969 | DRM_INFO("Connector Table: %d (emac)\n", |
1806 | rdev->mode_info.connector_table); |
1970 | rdev->mode_info.connector_table); |
1807 | /* VGA - primary dac */ |
1971 | /* VGA - primary dac */ |
1808 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
1972 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1809 | hpd.hpd = RADEON_HPD_NONE; |
1973 | hpd.hpd = RADEON_HPD_NONE; |
1810 | radeon_add_legacy_encoder(dev, |
1974 | radeon_add_legacy_encoder(dev, |
1811 | radeon_get_encoder_id(dev, |
1975 | radeon_get_encoder_enum(dev, |
1812 | ATOM_DEVICE_CRT1_SUPPORT, |
1976 | ATOM_DEVICE_CRT1_SUPPORT, |
1813 | 1), |
1977 | 1), |
1814 | ATOM_DEVICE_CRT1_SUPPORT); |
1978 | ATOM_DEVICE_CRT1_SUPPORT); |
1815 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
1979 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
1816 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1980 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1817 | CONNECTOR_OBJECT_ID_VGA, |
1981 | CONNECTOR_OBJECT_ID_VGA, |
1818 | &hpd); |
1982 | &hpd); |
1819 | /* VGA - tv dac */ |
1983 | /* VGA - tv dac */ |
- | 1984 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
|
- | 1985 | hpd.hpd = RADEON_HPD_NONE; |
|
- | 1986 | radeon_add_legacy_encoder(dev, |
|
- | 1987 | radeon_get_encoder_enum(dev, |
|
- | 1988 | ATOM_DEVICE_CRT2_SUPPORT, |
|
- | 1989 | 2), |
|
- | 1990 | ATOM_DEVICE_CRT2_SUPPORT); |
|
- | 1991 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
|
- | 1992 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
|
- | 1993 | CONNECTOR_OBJECT_ID_VGA, |
|
- | 1994 | &hpd); |
|
- | 1995 | /* TV - TV DAC */ |
|
- | 1996 | ddc_i2c.valid = false; |
|
- | 1997 | hpd.hpd = RADEON_HPD_NONE; |
|
- | 1998 | radeon_add_legacy_encoder(dev, |
|
- | 1999 | radeon_get_encoder_enum(dev, |
|
- | 2000 | ATOM_DEVICE_TV1_SUPPORT, |
|
- | 2001 | 2), |
|
- | 2002 | ATOM_DEVICE_TV1_SUPPORT); |
|
- | 2003 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
|
- | 2004 | DRM_MODE_CONNECTOR_SVIDEO, |
|
- | 2005 | &ddc_i2c, |
|
- | 2006 | CONNECTOR_OBJECT_ID_SVIDEO, |
|
- | 2007 | &hpd); |
|
- | 2008 | break; |
|
- | 2009 | case CT_RN50_POWER: |
|
- | 2010 | DRM_INFO("Connector Table: %d (rn50-power)\n", |
|
- | 2011 | rdev->mode_info.connector_table); |
|
- | 2012 | /* VGA - primary dac */ |
|
- | 2013 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
|
- | 2014 | hpd.hpd = RADEON_HPD_NONE; |
|
- | 2015 | radeon_add_legacy_encoder(dev, |
|
- | 2016 | radeon_get_encoder_enum(dev, |
|
- | 2017 | ATOM_DEVICE_CRT1_SUPPORT, |
|
- | 2018 | 1), |
|
- | 2019 | ATOM_DEVICE_CRT1_SUPPORT); |
|
- | 2020 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
|
- | 2021 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
|
- | 2022 | CONNECTOR_OBJECT_ID_VGA, |
|
- | 2023 | &hpd); |
|
1820 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
2024 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1821 | hpd.hpd = RADEON_HPD_NONE; |
2025 | hpd.hpd = RADEON_HPD_NONE; |
1822 | radeon_add_legacy_encoder(dev, |
2026 | radeon_add_legacy_encoder(dev, |
1823 | radeon_get_encoder_id(dev, |
2027 | radeon_get_encoder_enum(dev, |
1824 | ATOM_DEVICE_CRT2_SUPPORT, |
2028 | ATOM_DEVICE_CRT2_SUPPORT, |
1825 | 2), |
2029 | 2), |
1826 | ATOM_DEVICE_CRT2_SUPPORT); |
2030 | ATOM_DEVICE_CRT2_SUPPORT); |
1827 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
2031 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1828 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
2032 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1829 | CONNECTOR_OBJECT_ID_VGA, |
2033 | CONNECTOR_OBJECT_ID_VGA, |
1830 | &hpd); |
2034 | &hpd); |
- | 2035 | break; |
|
- | 2036 | case CT_MAC_X800: |
|
- | 2037 | DRM_INFO("Connector Table: %d (mac x800)\n", |
|
- | 2038 | rdev->mode_info.connector_table); |
|
- | 2039 | /* DVI - primary dac, internal tmds */ |
|
- | 2040 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
|
- | 2041 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
|
- | 2042 | radeon_add_legacy_encoder(dev, |
|
- | 2043 | radeon_get_encoder_enum(dev, |
|
- | 2044 | ATOM_DEVICE_DFP1_SUPPORT, |
|
- | 2045 | 0), |
|
- | 2046 | ATOM_DEVICE_DFP1_SUPPORT); |
|
- | 2047 | radeon_add_legacy_encoder(dev, |
|
- | 2048 | radeon_get_encoder_enum(dev, |
|
- | 2049 | ATOM_DEVICE_CRT1_SUPPORT, |
|
- | 2050 | 1), |
|
- | 2051 | ATOM_DEVICE_CRT1_SUPPORT); |
|
- | 2052 | radeon_add_legacy_connector(dev, 0, |
|
- | 2053 | ATOM_DEVICE_DFP1_SUPPORT | |
|
- | 2054 | ATOM_DEVICE_CRT1_SUPPORT, |
|
- | 2055 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
|
- | 2056 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
|
- | 2057 | &hpd); |
|
- | 2058 | /* DVI - tv dac, dvo */ |
|
- | 2059 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
|
- | 2060 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
|
- | 2061 | radeon_add_legacy_encoder(dev, |
|
- | 2062 | radeon_get_encoder_enum(dev, |
|
- | 2063 | ATOM_DEVICE_DFP2_SUPPORT, |
|
- | 2064 | 0), |
|
- | 2065 | ATOM_DEVICE_DFP2_SUPPORT); |
|
- | 2066 | radeon_add_legacy_encoder(dev, |
|
- | 2067 | radeon_get_encoder_enum(dev, |
|
- | 2068 | ATOM_DEVICE_CRT2_SUPPORT, |
|
- | 2069 | 2), |
|
- | 2070 | ATOM_DEVICE_CRT2_SUPPORT); |
|
- | 2071 | radeon_add_legacy_connector(dev, 1, |
|
- | 2072 | ATOM_DEVICE_DFP2_SUPPORT | |
|
- | 2073 | ATOM_DEVICE_CRT2_SUPPORT, |
|
- | 2074 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
|
- | 2075 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
|
- | 2076 | &hpd); |
|
- | 2077 | break; |
|
- | 2078 | case CT_MAC_G5_9600: |
|
- | 2079 | DRM_INFO("Connector Table: %d (mac g5 9600)\n", |
|
- | 2080 | rdev->mode_info.connector_table); |
|
- | 2081 | /* DVI - tv dac, dvo */ |
|
- | 2082 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
|
- | 2083 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
|
- | 2084 | radeon_add_legacy_encoder(dev, |
|
- | 2085 | radeon_get_encoder_enum(dev, |
|
- | 2086 | ATOM_DEVICE_DFP2_SUPPORT, |
|
- | 2087 | 0), |
|
- | 2088 | ATOM_DEVICE_DFP2_SUPPORT); |
|
- | 2089 | radeon_add_legacy_encoder(dev, |
|
- | 2090 | radeon_get_encoder_enum(dev, |
|
- | 2091 | ATOM_DEVICE_CRT2_SUPPORT, |
|
- | 2092 | 2), |
|
- | 2093 | ATOM_DEVICE_CRT2_SUPPORT); |
|
- | 2094 | radeon_add_legacy_connector(dev, 0, |
|
- | 2095 | ATOM_DEVICE_DFP2_SUPPORT | |
|
- | 2096 | ATOM_DEVICE_CRT2_SUPPORT, |
|
- | 2097 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
|
- | 2098 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
|
- | 2099 | &hpd); |
|
- | 2100 | /* ADC - primary dac, internal tmds */ |
|
- | 2101 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
|
- | 2102 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
|
- | 2103 | radeon_add_legacy_encoder(dev, |
|
- | 2104 | radeon_get_encoder_enum(dev, |
|
- | 2105 | ATOM_DEVICE_DFP1_SUPPORT, |
|
- | 2106 | 0), |
|
- | 2107 | ATOM_DEVICE_DFP1_SUPPORT); |
|
- | 2108 | radeon_add_legacy_encoder(dev, |
|
- | 2109 | radeon_get_encoder_enum(dev, |
|
- | 2110 | ATOM_DEVICE_CRT1_SUPPORT, |
|
- | 2111 | 1), |
|
- | 2112 | ATOM_DEVICE_CRT1_SUPPORT); |
|
- | 2113 | radeon_add_legacy_connector(dev, 1, |
|
- | 2114 | ATOM_DEVICE_DFP1_SUPPORT | |
|
- | 2115 | ATOM_DEVICE_CRT1_SUPPORT, |
|
- | 2116 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
|
- | 2117 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
|
- | 2118 | &hpd); |
|
1831 | /* TV - TV DAC */ |
2119 | /* TV - TV DAC */ |
1832 | ddc_i2c.valid = false; |
2120 | ddc_i2c.valid = false; |
1833 | hpd.hpd = RADEON_HPD_NONE; |
2121 | hpd.hpd = RADEON_HPD_NONE; |
1834 | radeon_add_legacy_encoder(dev, |
2122 | radeon_add_legacy_encoder(dev, |
1835 | radeon_get_encoder_id(dev, |
2123 | radeon_get_encoder_enum(dev, |
1836 | ATOM_DEVICE_TV1_SUPPORT, |
2124 | ATOM_DEVICE_TV1_SUPPORT, |
1837 | 2), |
2125 | 2), |
1838 | ATOM_DEVICE_TV1_SUPPORT); |
2126 | ATOM_DEVICE_TV1_SUPPORT); |
1839 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
2127 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1840 | DRM_MODE_CONNECTOR_SVIDEO, |
2128 | DRM_MODE_CONNECTOR_SVIDEO, |
Line 1858... | Line 2146... | ||
1858 | enum radeon_combios_connector |
2146 | enum radeon_combios_connector |
1859 | *legacy_connector, |
2147 | *legacy_connector, |
1860 | struct radeon_i2c_bus_rec *ddc_i2c, |
2148 | struct radeon_i2c_bus_rec *ddc_i2c, |
1861 | struct radeon_hpd *hpd) |
2149 | struct radeon_hpd *hpd) |
1862 | { |
2150 | { |
1863 | struct radeon_device *rdev = dev->dev_private; |
- | |
1864 | - | ||
1865 | /* XPRESS DDC quirks */ |
- | |
1866 | if ((rdev->family == CHIP_RS400 || |
- | |
1867 | rdev->family == CHIP_RS480) && |
- | |
1868 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
- | |
1869 | *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
- | |
1870 | else if ((rdev->family == CHIP_RS400 || |
- | |
1871 | rdev->family == CHIP_RS480) && |
- | |
1872 | ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) { |
- | |
1873 | *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK); |
- | |
1874 | ddc_i2c->mask_clk_mask = (0x20 << 8); |
- | |
1875 | ddc_i2c->mask_data_mask = 0x80; |
- | |
1876 | ddc_i2c->a_clk_mask = (0x20 << 8); |
- | |
1877 | ddc_i2c->a_data_mask = 0x80; |
- | |
1878 | ddc_i2c->en_clk_mask = (0x20 << 8); |
- | |
1879 | ddc_i2c->en_data_mask = 0x80; |
- | |
1880 | ddc_i2c->y_clk_mask = (0x20 << 8); |
- | |
1881 | ddc_i2c->y_data_mask = 0x80; |
- | |
1882 | } |
- | |
1883 | - | ||
1884 | /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ |
- | |
1885 | if ((rdev->family >= CHIP_R300) && |
- | |
1886 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
- | |
1887 | *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
- | |
Line 1888... | Line 2151... | ||
1888 | 2151 | ||
1889 | /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
2152 | /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
1890 | one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ |
2153 | one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ |
1891 | if (dev->pdev->device == 0x515e && |
2154 | if (dev->pdev->device == 0x515e && |
1892 | dev->pdev->subsystem_vendor == 0x1014) { |
2155 | dev->pdev->subsystem_vendor == 0x1014) { |
1893 | if (*legacy_connector == CONNECTOR_CRT_LEGACY && |
2156 | if (*legacy_connector == CONNECTOR_CRT_LEGACY && |
1894 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
2157 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
1895 | return false; |
2158 | return false; |
Line 1896... | Line -... | ||
1896 | } |
- | |
1897 | - | ||
1898 | /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ |
- | |
1899 | if (dev->pdev->device == 0x5159 && |
- | |
1900 | dev->pdev->subsystem_vendor == 0x1002 && |
- | |
1901 | dev->pdev->subsystem_device == 0x013a) { |
- | |
1902 | if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) |
- | |
1903 | *legacy_connector = CONNECTOR_CRT_LEGACY; |
- | |
1904 | - | ||
1905 | } |
2159 | } |
1906 | 2160 | ||
1907 | /* X300 card with extra non-existent DVI port */ |
2161 | /* X300 card with extra non-existent DVI port */ |
1908 | if (dev->pdev->device == 0x5B60 && |
2162 | if (dev->pdev->device == 0x5B60 && |
1909 | dev->pdev->subsystem_vendor == 0x17af && |
2163 | dev->pdev->subsystem_vendor == 0x17af && |
Line 1995... | Line 2249... | ||
1995 | tmp = RBIOS16(entry); |
2249 | tmp = RBIOS16(entry); |
Line 1996... | Line 2250... | ||
1996 | 2250 | ||
Line 1997... | Line 2251... | ||
1997 | connector = (tmp >> 12) & 0xf; |
2251 | connector = (tmp >> 12) & 0xf; |
1998 | - | ||
1999 | ddc_type = (tmp >> 8) & 0xf; |
- | |
2000 | switch (ddc_type) { |
- | |
2001 | case DDC_MONID: |
2252 | |
2002 | ddc_i2c = |
- | |
2003 | combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
- | |
2004 | break; |
- | |
2005 | case DDC_DVI: |
- | |
2006 | ddc_i2c = |
- | |
2007 | combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
- | |
2008 | break; |
- | |
2009 | case DDC_VGA: |
- | |
2010 | ddc_i2c = |
- | |
2011 | combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
- | |
2012 | break; |
- | |
2013 | case DDC_CRT2: |
- | |
2014 | ddc_i2c = |
- | |
2015 | combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
- | |
2016 | break; |
- | |
2017 | default: |
- | |
Line 2018... | Line 2253... | ||
2018 | break; |
2253 | ddc_type = (tmp >> 8) & 0xf; |
2019 | } |
2254 | ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2020 | 2255 | ||
2021 | switch (connector) { |
2256 | switch (connector) { |
Line 2041... | Line 2276... | ||
2041 | if ((tmp >> 4) & 0x1) |
2276 | if ((tmp >> 4) & 0x1) |
2042 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
2277 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
2043 | else |
2278 | else |
2044 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2279 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2045 | radeon_add_legacy_encoder(dev, |
2280 | radeon_add_legacy_encoder(dev, |
2046 | radeon_get_encoder_id |
2281 | radeon_get_encoder_enum |
2047 | (dev, devices, 0), |
2282 | (dev, devices, 0), |
2048 | devices); |
2283 | devices); |
2049 | radeon_add_legacy_connector(dev, i, devices, |
2284 | radeon_add_legacy_connector(dev, i, devices, |
2050 | legacy_connector_convert |
2285 | legacy_connector_convert |
2051 | [connector], |
2286 | [connector], |
Line 2055... | Line 2290... | ||
2055 | break; |
2290 | break; |
2056 | case CONNECTOR_CRT_LEGACY: |
2291 | case CONNECTOR_CRT_LEGACY: |
2057 | if (tmp & 0x1) { |
2292 | if (tmp & 0x1) { |
2058 | devices = ATOM_DEVICE_CRT2_SUPPORT; |
2293 | devices = ATOM_DEVICE_CRT2_SUPPORT; |
2059 | radeon_add_legacy_encoder(dev, |
2294 | radeon_add_legacy_encoder(dev, |
2060 | radeon_get_encoder_id |
2295 | radeon_get_encoder_enum |
2061 | (dev, |
2296 | (dev, |
2062 | ATOM_DEVICE_CRT2_SUPPORT, |
2297 | ATOM_DEVICE_CRT2_SUPPORT, |
2063 | 2), |
2298 | 2), |
2064 | ATOM_DEVICE_CRT2_SUPPORT); |
2299 | ATOM_DEVICE_CRT2_SUPPORT); |
2065 | } else { |
2300 | } else { |
2066 | devices = ATOM_DEVICE_CRT1_SUPPORT; |
2301 | devices = ATOM_DEVICE_CRT1_SUPPORT; |
2067 | radeon_add_legacy_encoder(dev, |
2302 | radeon_add_legacy_encoder(dev, |
2068 | radeon_get_encoder_id |
2303 | radeon_get_encoder_enum |
2069 | (dev, |
2304 | (dev, |
2070 | ATOM_DEVICE_CRT1_SUPPORT, |
2305 | ATOM_DEVICE_CRT1_SUPPORT, |
2071 | 1), |
2306 | 1), |
2072 | ATOM_DEVICE_CRT1_SUPPORT); |
2307 | ATOM_DEVICE_CRT1_SUPPORT); |
2073 | } |
2308 | } |
Line 2083... | Line 2318... | ||
2083 | case CONNECTOR_DVI_I_LEGACY: |
2318 | case CONNECTOR_DVI_I_LEGACY: |
2084 | devices = 0; |
2319 | devices = 0; |
2085 | if (tmp & 0x1) { |
2320 | if (tmp & 0x1) { |
2086 | devices |= ATOM_DEVICE_CRT2_SUPPORT; |
2321 | devices |= ATOM_DEVICE_CRT2_SUPPORT; |
2087 | radeon_add_legacy_encoder(dev, |
2322 | radeon_add_legacy_encoder(dev, |
2088 | radeon_get_encoder_id |
2323 | radeon_get_encoder_enum |
2089 | (dev, |
2324 | (dev, |
2090 | ATOM_DEVICE_CRT2_SUPPORT, |
2325 | ATOM_DEVICE_CRT2_SUPPORT, |
2091 | 2), |
2326 | 2), |
2092 | ATOM_DEVICE_CRT2_SUPPORT); |
2327 | ATOM_DEVICE_CRT2_SUPPORT); |
2093 | } else { |
2328 | } else { |
2094 | devices |= ATOM_DEVICE_CRT1_SUPPORT; |
2329 | devices |= ATOM_DEVICE_CRT1_SUPPORT; |
2095 | radeon_add_legacy_encoder(dev, |
2330 | radeon_add_legacy_encoder(dev, |
2096 | radeon_get_encoder_id |
2331 | radeon_get_encoder_enum |
2097 | (dev, |
2332 | (dev, |
2098 | ATOM_DEVICE_CRT1_SUPPORT, |
2333 | ATOM_DEVICE_CRT1_SUPPORT, |
2099 | 1), |
2334 | 1), |
2100 | ATOM_DEVICE_CRT1_SUPPORT); |
2335 | ATOM_DEVICE_CRT1_SUPPORT); |
2101 | } |
2336 | } |
2102 | if ((tmp >> 4) & 0x1) { |
2337 | if ((tmp >> 4) & 0x1) { |
2103 | devices |= ATOM_DEVICE_DFP2_SUPPORT; |
2338 | devices |= ATOM_DEVICE_DFP2_SUPPORT; |
2104 | radeon_add_legacy_encoder(dev, |
2339 | radeon_add_legacy_encoder(dev, |
2105 | radeon_get_encoder_id |
2340 | radeon_get_encoder_enum |
2106 | (dev, |
2341 | (dev, |
2107 | ATOM_DEVICE_DFP2_SUPPORT, |
2342 | ATOM_DEVICE_DFP2_SUPPORT, |
2108 | 0), |
2343 | 0), |
2109 | ATOM_DEVICE_DFP2_SUPPORT); |
2344 | ATOM_DEVICE_DFP2_SUPPORT); |
2110 | connector_object_id = combios_check_dl_dvi(dev, 0); |
2345 | connector_object_id = combios_check_dl_dvi(dev, 0); |
2111 | } else { |
2346 | } else { |
2112 | devices |= ATOM_DEVICE_DFP1_SUPPORT; |
2347 | devices |= ATOM_DEVICE_DFP1_SUPPORT; |
2113 | radeon_add_legacy_encoder(dev, |
2348 | radeon_add_legacy_encoder(dev, |
2114 | radeon_get_encoder_id |
2349 | radeon_get_encoder_enum |
2115 | (dev, |
2350 | (dev, |
2116 | ATOM_DEVICE_DFP1_SUPPORT, |
2351 | ATOM_DEVICE_DFP1_SUPPORT, |
2117 | 0), |
2352 | 0), |
2118 | ATOM_DEVICE_DFP1_SUPPORT); |
2353 | ATOM_DEVICE_DFP1_SUPPORT); |
2119 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2354 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
Line 2134... | Line 2369... | ||
2134 | } else { |
2369 | } else { |
2135 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2370 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2136 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2371 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2137 | } |
2372 | } |
2138 | radeon_add_legacy_encoder(dev, |
2373 | radeon_add_legacy_encoder(dev, |
2139 | radeon_get_encoder_id |
2374 | radeon_get_encoder_enum |
2140 | (dev, devices, 0), |
2375 | (dev, devices, 0), |
2141 | devices); |
2376 | devices); |
2142 | radeon_add_legacy_connector(dev, i, devices, |
2377 | radeon_add_legacy_connector(dev, i, devices, |
2143 | legacy_connector_convert |
2378 | legacy_connector_convert |
2144 | [connector], |
2379 | [connector], |
Line 2147... | Line 2382... | ||
2147 | &hpd); |
2382 | &hpd); |
2148 | break; |
2383 | break; |
2149 | case CONNECTOR_CTV_LEGACY: |
2384 | case CONNECTOR_CTV_LEGACY: |
2150 | case CONNECTOR_STV_LEGACY: |
2385 | case CONNECTOR_STV_LEGACY: |
2151 | radeon_add_legacy_encoder(dev, |
2386 | radeon_add_legacy_encoder(dev, |
2152 | radeon_get_encoder_id |
2387 | radeon_get_encoder_enum |
2153 | (dev, |
2388 | (dev, |
2154 | ATOM_DEVICE_TV1_SUPPORT, |
2389 | ATOM_DEVICE_TV1_SUPPORT, |
2155 | 2), |
2390 | 2), |
2156 | ATOM_DEVICE_TV1_SUPPORT); |
2391 | ATOM_DEVICE_TV1_SUPPORT); |
2157 | radeon_add_legacy_connector(dev, i, |
2392 | radeon_add_legacy_connector(dev, i, |
Line 2171... | Line 2406... | ||
2171 | } |
2406 | } |
2172 | } else { |
2407 | } else { |
2173 | uint16_t tmds_info = |
2408 | uint16_t tmds_info = |
2174 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
2409 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
2175 | if (tmds_info) { |
2410 | if (tmds_info) { |
2176 | DRM_DEBUG("Found DFP table, assuming DVI connector\n"); |
2411 | DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); |
Line 2177... | Line 2412... | ||
2177 | 2412 | ||
2178 | radeon_add_legacy_encoder(dev, |
2413 | radeon_add_legacy_encoder(dev, |
2179 | radeon_get_encoder_id(dev, |
2414 | radeon_get_encoder_enum(dev, |
2180 | ATOM_DEVICE_CRT1_SUPPORT, |
2415 | ATOM_DEVICE_CRT1_SUPPORT, |
2181 | 1), |
2416 | 1), |
2182 | ATOM_DEVICE_CRT1_SUPPORT); |
2417 | ATOM_DEVICE_CRT1_SUPPORT); |
2183 | radeon_add_legacy_encoder(dev, |
2418 | radeon_add_legacy_encoder(dev, |
2184 | radeon_get_encoder_id(dev, |
2419 | radeon_get_encoder_enum(dev, |
2185 | ATOM_DEVICE_DFP1_SUPPORT, |
2420 | ATOM_DEVICE_DFP1_SUPPORT, |
2186 | 0), |
2421 | 0), |
Line 2187... | Line 2422... | ||
2187 | ATOM_DEVICE_DFP1_SUPPORT); |
2422 | ATOM_DEVICE_DFP1_SUPPORT); |
2188 | 2423 | ||
2189 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
2424 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2190 | hpd.hpd = RADEON_HPD_NONE; |
2425 | hpd.hpd = RADEON_HPD_1; |
2191 | radeon_add_legacy_connector(dev, |
2426 | radeon_add_legacy_connector(dev, |
2192 | 0, |
2427 | 0, |
2193 | ATOM_DEVICE_CRT1_SUPPORT | |
2428 | ATOM_DEVICE_CRT1_SUPPORT | |
Line 2197... | Line 2432... | ||
2197 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2432 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2198 | &hpd); |
2433 | &hpd); |
2199 | } else { |
2434 | } else { |
2200 | uint16_t crt_info = |
2435 | uint16_t crt_info = |
2201 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
2436 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
2202 | DRM_DEBUG("Found CRT table, assuming VGA connector\n"); |
2437 | DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); |
2203 | if (crt_info) { |
2438 | if (crt_info) { |
2204 | radeon_add_legacy_encoder(dev, |
2439 | radeon_add_legacy_encoder(dev, |
2205 | radeon_get_encoder_id(dev, |
2440 | radeon_get_encoder_enum(dev, |
2206 | ATOM_DEVICE_CRT1_SUPPORT, |
2441 | ATOM_DEVICE_CRT1_SUPPORT, |
2207 | 1), |
2442 | 1), |
2208 | ATOM_DEVICE_CRT1_SUPPORT); |
2443 | ATOM_DEVICE_CRT1_SUPPORT); |
2209 | ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
2444 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2210 | hpd.hpd = RADEON_HPD_NONE; |
2445 | hpd.hpd = RADEON_HPD_NONE; |
2211 | radeon_add_legacy_connector(dev, |
2446 | radeon_add_legacy_connector(dev, |
2212 | 0, |
2447 | 0, |
2213 | ATOM_DEVICE_CRT1_SUPPORT, |
2448 | ATOM_DEVICE_CRT1_SUPPORT, |
2214 | DRM_MODE_CONNECTOR_VGA, |
2449 | DRM_MODE_CONNECTOR_VGA, |
2215 | &ddc_i2c, |
2450 | &ddc_i2c, |
2216 | CONNECTOR_OBJECT_ID_VGA, |
2451 | CONNECTOR_OBJECT_ID_VGA, |
2217 | &hpd); |
2452 | &hpd); |
2218 | } else { |
2453 | } else { |
2219 | DRM_DEBUG("No connector info found\n"); |
2454 | DRM_DEBUG_KMS("No connector info found\n"); |
2220 | return false; |
2455 | return false; |
2221 | } |
2456 | } |
2222 | } |
2457 | } |
2223 | } |
2458 | } |
Line 2229... | Line 2464... | ||
2229 | uint16_t lcd_ddc_info = |
2464 | uint16_t lcd_ddc_info = |
2230 | combios_get_table_offset(dev, |
2465 | combios_get_table_offset(dev, |
2231 | COMBIOS_LCD_DDC_INFO_TABLE); |
2466 | COMBIOS_LCD_DDC_INFO_TABLE); |
Line 2232... | Line 2467... | ||
2232 | 2467 | ||
2233 | radeon_add_legacy_encoder(dev, |
2468 | radeon_add_legacy_encoder(dev, |
2234 | radeon_get_encoder_id(dev, |
2469 | radeon_get_encoder_enum(dev, |
2235 | ATOM_DEVICE_LCD1_SUPPORT, |
2470 | ATOM_DEVICE_LCD1_SUPPORT, |
2236 | 0), |
2471 | 0), |
Line 2237... | Line 2472... | ||
2237 | ATOM_DEVICE_LCD1_SUPPORT); |
2472 | ATOM_DEVICE_LCD1_SUPPORT); |
2238 | 2473 | ||
2239 | if (lcd_ddc_info) { |
2474 | if (lcd_ddc_info) { |
2240 | ddc_type = RBIOS8(lcd_ddc_info + 2); |
- | |
2241 | switch (ddc_type) { |
- | |
2242 | case DDC_MONID: |
- | |
2243 | ddc_i2c = |
- | |
2244 | combios_setup_i2c_bus |
- | |
2245 | (rdev, RADEON_GPIO_MONID); |
- | |
2246 | break; |
- | |
2247 | case DDC_DVI: |
- | |
2248 | ddc_i2c = |
- | |
2249 | combios_setup_i2c_bus |
- | |
2250 | (rdev, RADEON_GPIO_DVI_DDC); |
- | |
2251 | break; |
- | |
2252 | case DDC_VGA: |
- | |
2253 | ddc_i2c = |
- | |
2254 | combios_setup_i2c_bus |
- | |
2255 | (rdev, RADEON_GPIO_VGA_DDC); |
- | |
2256 | break; |
- | |
2257 | case DDC_CRT2: |
- | |
2258 | ddc_i2c = |
- | |
2259 | combios_setup_i2c_bus |
- | |
2260 | (rdev, RADEON_GPIO_CRT2_DDC); |
2475 | ddc_type = RBIOS8(lcd_ddc_info + 2); |
2261 | break; |
2476 | switch (ddc_type) { |
2262 | case DDC_LCD: |
2477 | case DDC_LCD: |
2263 | ddc_i2c = |
- | |
2264 | combios_setup_i2c_bus |
- | |
2265 | (rdev, RADEON_GPIOPAD_MASK); |
- | |
2266 | ddc_i2c.mask_clk_mask = |
- | |
2267 | RBIOS32(lcd_ddc_info + 3); |
- | |
2268 | ddc_i2c.mask_data_mask = |
2478 | ddc_i2c = |
2269 | RBIOS32(lcd_ddc_info + 7); |
- | |
2270 | ddc_i2c.a_clk_mask = |
- | |
2271 | RBIOS32(lcd_ddc_info + 3); |
- | |
2272 | ddc_i2c.a_data_mask = |
- | |
2273 | RBIOS32(lcd_ddc_info + 7); |
2479 | combios_setup_i2c_bus(rdev, |
2274 | ddc_i2c.en_clk_mask = |
- | |
2275 | RBIOS32(lcd_ddc_info + 3); |
2480 | DDC_LCD, |
2276 | ddc_i2c.en_data_mask = |
- | |
2277 | RBIOS32(lcd_ddc_info + 7); |
- | |
2278 | ddc_i2c.y_clk_mask = |
- | |
2279 | RBIOS32(lcd_ddc_info + 3); |
2481 | RBIOS32(lcd_ddc_info + 3), |
2280 | ddc_i2c.y_data_mask = |
2482 | RBIOS32(lcd_ddc_info + 7)); |
2281 | RBIOS32(lcd_ddc_info + 7); |
2483 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2282 | break; |
2484 | break; |
2283 | case DDC_GPIO: |
2485 | case DDC_GPIO: |
2284 | ddc_i2c = |
2486 | ddc_i2c = |
2285 | combios_setup_i2c_bus |
- | |
2286 | (rdev, RADEON_MDGPIO_MASK); |
2487 | combios_setup_i2c_bus(rdev, |
2287 | ddc_i2c.mask_clk_mask = |
- | |
2288 | RBIOS32(lcd_ddc_info + 3); |
- | |
2289 | ddc_i2c.mask_data_mask = |
- | |
2290 | RBIOS32(lcd_ddc_info + 7); |
- | |
2291 | ddc_i2c.a_clk_mask = |
- | |
2292 | RBIOS32(lcd_ddc_info + 3); |
- | |
2293 | ddc_i2c.a_data_mask = |
- | |
2294 | RBIOS32(lcd_ddc_info + 7); |
- | |
2295 | ddc_i2c.en_clk_mask = |
- | |
2296 | RBIOS32(lcd_ddc_info + 3); |
2488 | DDC_GPIO, |
2297 | ddc_i2c.en_data_mask = |
- | |
2298 | RBIOS32(lcd_ddc_info + 7); |
- | |
2299 | ddc_i2c.y_clk_mask = |
- | |
2300 | RBIOS32(lcd_ddc_info + 3); |
2489 | RBIOS32(lcd_ddc_info + 3), |
2301 | ddc_i2c.y_data_mask = |
2490 | RBIOS32(lcd_ddc_info + 7)); |
2302 | RBIOS32(lcd_ddc_info + 7); |
2491 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2303 | break; |
2492 | break; |
- | 2493 | default: |
|
2304 | default: |
2494 | ddc_i2c = |
2305 | ddc_i2c.valid = false; |
2495 | combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2306 | break; |
2496 | break; |
2307 | } |
2497 | } |
2308 | DRM_DEBUG("LCD DDC Info Table found!\n"); |
2498 | DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); |
Line 2309... | Line 2499... | ||
2309 | } else |
2499 | } else |
2310 | ddc_i2c.valid = false; |
2500 | ddc_i2c.valid = false; |
Line 2326... | Line 2516... | ||
2326 | combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
2516 | combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
2327 | if (tv_info) { |
2517 | if (tv_info) { |
2328 | if (RBIOS8(tv_info + 6) == 'T') { |
2518 | if (RBIOS8(tv_info + 6) == 'T') { |
2329 | if (radeon_apply_legacy_tv_quirks(dev)) { |
2519 | if (radeon_apply_legacy_tv_quirks(dev)) { |
2330 | hpd.hpd = RADEON_HPD_NONE; |
2520 | hpd.hpd = RADEON_HPD_NONE; |
- | 2521 | ddc_i2c.valid = false; |
|
2331 | radeon_add_legacy_encoder(dev, |
2522 | radeon_add_legacy_encoder(dev, |
2332 | radeon_get_encoder_id |
2523 | radeon_get_encoder_enum |
2333 | (dev, |
2524 | (dev, |
2334 | ATOM_DEVICE_TV1_SUPPORT, |
2525 | ATOM_DEVICE_TV1_SUPPORT, |
2335 | 2), |
2526 | 2), |
2336 | ATOM_DEVICE_TV1_SUPPORT); |
2527 | ATOM_DEVICE_TV1_SUPPORT); |
2337 | radeon_add_legacy_connector(dev, 6, |
2528 | radeon_add_legacy_connector(dev, 6, |
Line 2348... | Line 2539... | ||
2348 | radeon_link_encoder_connector(dev); |
2539 | radeon_link_encoder_connector(dev); |
Line 2349... | Line 2540... | ||
2349 | 2540 | ||
2350 | return true; |
2541 | return true; |
Line -... | Line 2542... | ||
- | 2542 | } |
|
- | 2543 | ||
- | 2544 | static const char *thermal_controller_names[] = { |
|
- | 2545 | "NONE", |
|
- | 2546 | "lm63", |
|
- | 2547 | "adm1032", |
|
2351 | } |
2548 | }; |
2352 | 2549 | ||
2353 | void radeon_combios_get_power_modes(struct radeon_device *rdev) |
2550 | void radeon_combios_get_power_modes(struct radeon_device *rdev) |
2354 | { |
2551 | { |
2355 | struct drm_device *dev = rdev->ddev; |
2552 | struct drm_device *dev = rdev->ddev; |
2356 | u16 offset, misc, misc2 = 0; |
2553 | u16 offset, misc, misc2 = 0; |
Line 2357... | Line 2554... | ||
2357 | u8 rev, blocks, tmp; |
2554 | u8 rev, blocks, tmp; |
- | 2555 | int state_index = 0; |
|
- | 2556 | ||
- | 2557 | rdev->pm.default_power_state_index = -1; |
|
- | 2558 | ||
- | 2559 | /* allocate 2 power states */ |
|
- | 2560 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); |
|
- | 2561 | if (!rdev->pm.power_state) { |
|
- | 2562 | rdev->pm.default_power_state_index = state_index; |
|
- | 2563 | rdev->pm.num_power_states = 0; |
|
- | 2564 | ||
- | 2565 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
|
- | 2566 | rdev->pm.current_clock_mode_index = 0; |
|
- | 2567 | return; |
|
- | 2568 | } |
|
- | 2569 | ||
- | 2570 | /* check for a thermal chip */ |
|
- | 2571 | offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); |
|
- | 2572 | if (offset) { |
|
- | 2573 | u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; |
|
- | 2574 | struct radeon_i2c_bus_rec i2c_bus; |
|
- | 2575 | ||
- | 2576 | rev = RBIOS8(offset); |
|
- | 2577 | ||
- | 2578 | if (rev == 0) { |
|
- | 2579 | thermal_controller = RBIOS8(offset + 3); |
|
- | 2580 | gpio = RBIOS8(offset + 4) & 0x3f; |
|
- | 2581 | i2c_addr = RBIOS8(offset + 5); |
|
- | 2582 | } else if (rev == 1) { |
|
- | 2583 | thermal_controller = RBIOS8(offset + 4); |
|
- | 2584 | gpio = RBIOS8(offset + 5) & 0x3f; |
|
- | 2585 | i2c_addr = RBIOS8(offset + 6); |
|
- | 2586 | } else if (rev == 2) { |
|
- | 2587 | thermal_controller = RBIOS8(offset + 4); |
|
- | 2588 | gpio = RBIOS8(offset + 5) & 0x3f; |
|
- | 2589 | i2c_addr = RBIOS8(offset + 6); |
|
- | 2590 | clk_bit = RBIOS8(offset + 0xa); |
|
- | 2591 | data_bit = RBIOS8(offset + 0xb); |
|
- | 2592 | } |
|
- | 2593 | if ((thermal_controller > 0) && (thermal_controller < 3)) { |
|
- | 2594 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
|
- | 2595 | thermal_controller_names[thermal_controller], |
|
- | 2596 | i2c_addr >> 1); |
|
- | 2597 | if (gpio == DDC_LCD) { |
|
- | 2598 | /* MM i2c */ |
|
- | 2599 | i2c_bus.valid = true; |
|
- | 2600 | i2c_bus.hw_capable = true; |
|
- | 2601 | i2c_bus.mm_i2c = true; |
|
- | 2602 | i2c_bus.i2c_id = 0xa0; |
|
- | 2603 | } else if (gpio == DDC_GPIO) |
|
- | 2604 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); |
|
- | 2605 | else |
|
- | 2606 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
|
- | 2607 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
|
- | 2608 | if (rdev->pm.i2c_bus) { |
|
- | 2609 | struct i2c_board_info info = { }; |
|
- | 2610 | const char *name = thermal_controller_names[thermal_controller]; |
|
- | 2611 | info.addr = i2c_addr >> 1; |
|
- | 2612 | strlcpy(info.type, name, sizeof(info.type)); |
|
- | 2613 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
|
Line 2358... | Line 2614... | ||
2358 | int state_index = 0; |
2614 | } |
2359 | 2615 | } |
|
2360 | rdev->pm.default_power_state = NULL; |
2616 | } |
2361 | 2617 | ||
Line 2369... | Line 2625... | ||
2369 | rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); |
2625 | rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); |
2370 | rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); |
2626 | rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); |
2371 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
2627 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
2372 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
2628 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
2373 | goto default_mode; |
2629 | goto default_mode; |
2374 | /* skip overclock modes for now */ |
- | |
2375 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk > |
- | |
2376 | rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || |
- | |
2377 | (rdev->pm.power_state[state_index].clock_info[0].sclk > |
- | |
2378 | rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) |
- | |
2379 | goto default_mode; |
- | |
2380 | rdev->pm.power_state[state_index].type = |
2630 | rdev->pm.power_state[state_index].type = |
2381 | POWER_STATE_TYPE_BATTERY; |
2631 | POWER_STATE_TYPE_BATTERY; |
2382 | misc = RBIOS16(offset + 0x5 + 0x0); |
2632 | misc = RBIOS16(offset + 0x5 + 0x0); |
2383 | if (rev > 4) |
2633 | if (rev > 4) |
2384 | misc2 = RBIOS16(offset + 0x5 + 0xe); |
2634 | misc2 = RBIOS16(offset + 0x5 + 0xe); |
- | 2635 | rdev->pm.power_state[state_index].misc = misc; |
|
- | 2636 | rdev->pm.power_state[state_index].misc2 = misc2; |
|
2385 | if (misc & 0x4) { |
2637 | if (misc & 0x4) { |
2386 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
2638 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
2387 | if (misc & 0x8) |
2639 | if (misc & 0x8) |
2388 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2640 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2389 | true; |
2641 | true; |
Line 2426... | Line 2678... | ||
2426 | break; |
2678 | break; |
2427 | } |
2679 | } |
2428 | } else |
2680 | } else |
2429 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2681 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2430 | if (rev > 6) |
2682 | if (rev > 6) |
2431 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = |
2683 | rdev->pm.power_state[state_index].pcie_lanes = |
2432 | RBIOS8(offset + 0x5 + 0x10); |
2684 | RBIOS8(offset + 0x5 + 0x10); |
- | 2685 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
|
2433 | state_index++; |
2686 | state_index++; |
2434 | } else { |
2687 | } else { |
2435 | /* XXX figure out some good default low power mode for mobility cards w/out power tables */ |
2688 | /* XXX figure out some good default low power mode for mobility cards w/out power tables */ |
2436 | } |
2689 | } |
2437 | } else { |
2690 | } else { |
Line 2444... | Line 2697... | ||
2444 | POWER_STATE_TYPE_DEFAULT; |
2697 | POWER_STATE_TYPE_DEFAULT; |
2445 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2698 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2446 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
2699 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
2447 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
2700 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
2448 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
2701 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
- | 2702 | if ((state_index > 0) && |
|
2449 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2703 | (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) |
2450 | if (rdev->asic->get_pcie_lanes) |
2704 | rdev->pm.power_state[state_index].clock_info[0].voltage = |
2451 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); |
2705 | rdev->pm.power_state[0].clock_info[0].voltage; |
2452 | else |
2706 | else |
- | 2707 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
|
2453 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; |
2708 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
- | 2709 | rdev->pm.power_state[state_index].flags = 0; |
|
2454 | rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; |
2710 | rdev->pm.default_power_state_index = state_index; |
2455 | rdev->pm.num_power_states = state_index + 1; |
2711 | rdev->pm.num_power_states = state_index + 1; |
Line 2456... | Line 2712... | ||
2456 | 2712 | ||
2457 | rdev->pm.current_power_state = rdev->pm.default_power_state; |
2713 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2458 | rdev->pm.current_clock_mode = |
- | |
2459 | rdev->pm.default_power_state->default_clock_mode; |
2714 | rdev->pm.current_clock_mode_index = 0; |
Line 2460... | Line 2715... | ||
2460 | } |
2715 | } |
2461 | 2716 | ||
2462 | void radeon_external_tmds_setup(struct drm_encoder *encoder) |
2717 | void radeon_external_tmds_setup(struct drm_encoder *encoder) |
Line 2904... | Line 3159... | ||
2904 | if (offset) { |
3159 | if (offset) { |
2905 | rev = RBIOS8(offset); |
3160 | rev = RBIOS8(offset); |
2906 | if (rev < 3) { |
3161 | if (rev < 3) { |
2907 | mem_cntl = RBIOS32(offset + 1); |
3162 | mem_cntl = RBIOS32(offset + 1); |
2908 | mem_size = RBIOS16(offset + 5); |
3163 | mem_size = RBIOS16(offset + 5); |
2909 | if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && |
3164 | if ((rdev->family < CHIP_R200) && |
2910 | ((dev->pdev->device != 0x515e) |
- | |
2911 | && (dev->pdev->device != 0x5969))) |
3165 | !ASIC_IS_RN50(rdev)) |
2912 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
3166 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
2913 | } |
3167 | } |
2914 | } |
3168 | } |
Line 2915... | Line 3169... | ||
2915 | 3169 | ||
2916 | if (!mem_size) { |
3170 | if (!mem_size) { |
2917 | offset = |
3171 | offset = |
2918 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
3172 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
2919 | if (offset) { |
3173 | if (offset) { |
2920 | rev = RBIOS8(offset - 1); |
3174 | rev = RBIOS8(offset - 1); |
2921 | if (rev < 1) { |
3175 | if (rev < 1) { |
2922 | if (((rdev->flags & RADEON_FAMILY_MASK) < |
3176 | if ((rdev->family < CHIP_R200) |
2923 | CHIP_R200) |
- | |
2924 | && ((dev->pdev->device != 0x515e) |
- | |
2925 | && (dev->pdev->device != 0x5969))) { |
3177 | && !ASIC_IS_RN50(rdev)) { |
2926 | int ram = 0; |
3178 | int ram = 0; |
Line 2927... | Line 3179... | ||
2927 | int mem_addr_mapping = 0; |
3179 | int mem_addr_mapping = 0; |
2928 | 3180 | ||
Line 3005... | Line 3257... | ||
3005 | 3257 | ||
3006 | /* write CONFIG_MEMSIZE */ |
3258 | /* write CONFIG_MEMSIZE */ |
3007 | combios_write_ram_size(dev); |
3259 | combios_write_ram_size(dev); |
Line -... | Line 3260... | ||
- | 3260 | } |
|
- | 3261 | ||
- | 3262 | /* quirk for rs4xx HP nx6125 laptop to make it resume |
|
- | 3263 | * - it hangs on resume inside the dynclk 1 table. |
|
- | 3264 | */ |
|
- | 3265 | if (rdev->family == CHIP_RS480 && |
|
- | 3266 | rdev->pdev->subsystem_vendor == 0x103c && |
|
- | 3267 | rdev->pdev->subsystem_device == 0x308b) |
|
- | 3268 | return; |
|
- | 3269 | ||
- | 3270 | /* quirk for rs4xx HP dv5000 laptop to make it resume |
|
- | 3271 | * - it hangs on resume inside the dynclk 1 table. |
|
- | 3272 | */ |
|
- | 3273 | if (rdev->family == CHIP_RS480 && |
|
- | 3274 | rdev->pdev->subsystem_vendor == 0x103c && |
|
- | 3275 | rdev->pdev->subsystem_device == 0x30a4) |
|
3008 | } |
3276 | return; |
3009 | 3277 | ||
3010 | /* DYN CLK 1 */ |
3278 | /* DYN CLK 1 */ |
3011 | table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
3279 | table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
Line 3068... | Line 3336... | ||
3068 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
3336 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
Line 3069... | Line 3337... | ||
3069 | 3337 | ||
3070 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
3338 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
3071 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
3339 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
3072 | if (connected) { |
3340 | if (connected) { |
3073 | DRM_DEBUG("TV1 connected\n"); |
3341 | DRM_DEBUG_KMS("TV1 connected\n"); |
3074 | /* fix me */ |
3342 | /* fix me */ |
3075 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; |
3343 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; |
3076 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
3344 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
3077 | bios_5_scratch |= RADEON_TV1_ON; |
3345 | bios_5_scratch |= RADEON_TV1_ON; |
3078 | bios_5_scratch |= RADEON_ACC_REQ_TV1; |
3346 | bios_5_scratch |= RADEON_ACC_REQ_TV1; |
3079 | } else { |
3347 | } else { |
3080 | DRM_DEBUG("TV1 disconnected\n"); |
3348 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
3081 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
3349 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
3082 | bios_5_scratch &= ~RADEON_TV1_ON; |
3350 | bios_5_scratch &= ~RADEON_TV1_ON; |
3083 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; |
3351 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; |
3084 | } |
3352 | } |
3085 | } |
3353 | } |
3086 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
3354 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
3087 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
3355 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
3088 | if (connected) { |
3356 | if (connected) { |
3089 | DRM_DEBUG("LCD1 connected\n"); |
3357 | DRM_DEBUG_KMS("LCD1 connected\n"); |
3090 | bios_4_scratch |= RADEON_LCD1_ATTACHED; |
3358 | bios_4_scratch |= RADEON_LCD1_ATTACHED; |
3091 | bios_5_scratch |= RADEON_LCD1_ON; |
3359 | bios_5_scratch |= RADEON_LCD1_ON; |
3092 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; |
3360 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; |
3093 | } else { |
3361 | } else { |
3094 | DRM_DEBUG("LCD1 disconnected\n"); |
3362 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
3095 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
3363 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
3096 | bios_5_scratch &= ~RADEON_LCD1_ON; |
3364 | bios_5_scratch &= ~RADEON_LCD1_ON; |
3097 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; |
3365 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; |
3098 | } |
3366 | } |
3099 | } |
3367 | } |
3100 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
3368 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
3101 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
3369 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
3102 | if (connected) { |
3370 | if (connected) { |
3103 | DRM_DEBUG("CRT1 connected\n"); |
3371 | DRM_DEBUG_KMS("CRT1 connected\n"); |
3104 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
3372 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
3105 | bios_5_scratch |= RADEON_CRT1_ON; |
3373 | bios_5_scratch |= RADEON_CRT1_ON; |
3106 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; |
3374 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; |
3107 | } else { |
3375 | } else { |
3108 | DRM_DEBUG("CRT1 disconnected\n"); |
3376 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
3109 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
3377 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
3110 | bios_5_scratch &= ~RADEON_CRT1_ON; |
3378 | bios_5_scratch &= ~RADEON_CRT1_ON; |
3111 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; |
3379 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; |
3112 | } |
3380 | } |
3113 | } |
3381 | } |
3114 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
3382 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
3115 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
3383 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
3116 | if (connected) { |
3384 | if (connected) { |
3117 | DRM_DEBUG("CRT2 connected\n"); |
3385 | DRM_DEBUG_KMS("CRT2 connected\n"); |
3118 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
3386 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
3119 | bios_5_scratch |= RADEON_CRT2_ON; |
3387 | bios_5_scratch |= RADEON_CRT2_ON; |
3120 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; |
3388 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; |
3121 | } else { |
3389 | } else { |
3122 | DRM_DEBUG("CRT2 disconnected\n"); |
3390 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
3123 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
3391 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
3124 | bios_5_scratch &= ~RADEON_CRT2_ON; |
3392 | bios_5_scratch &= ~RADEON_CRT2_ON; |
3125 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; |
3393 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; |
3126 | } |
3394 | } |
3127 | } |
3395 | } |
3128 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
3396 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
3129 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
3397 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
3130 | if (connected) { |
3398 | if (connected) { |
3131 | DRM_DEBUG("DFP1 connected\n"); |
3399 | DRM_DEBUG_KMS("DFP1 connected\n"); |
3132 | bios_4_scratch |= RADEON_DFP1_ATTACHED; |
3400 | bios_4_scratch |= RADEON_DFP1_ATTACHED; |
3133 | bios_5_scratch |= RADEON_DFP1_ON; |
3401 | bios_5_scratch |= RADEON_DFP1_ON; |
3134 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; |
3402 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; |
3135 | } else { |
3403 | } else { |
3136 | DRM_DEBUG("DFP1 disconnected\n"); |
3404 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
3137 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
3405 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
3138 | bios_5_scratch &= ~RADEON_DFP1_ON; |
3406 | bios_5_scratch &= ~RADEON_DFP1_ON; |
3139 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; |
3407 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; |
3140 | } |
3408 | } |
3141 | } |
3409 | } |
3142 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
3410 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
3143 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
3411 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
3144 | if (connected) { |
3412 | if (connected) { |
3145 | DRM_DEBUG("DFP2 connected\n"); |
3413 | DRM_DEBUG_KMS("DFP2 connected\n"); |
3146 | bios_4_scratch |= RADEON_DFP2_ATTACHED; |
3414 | bios_4_scratch |= RADEON_DFP2_ATTACHED; |
3147 | bios_5_scratch |= RADEON_DFP2_ON; |
3415 | bios_5_scratch |= RADEON_DFP2_ON; |
3148 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; |
3416 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; |
3149 | } else { |
3417 | } else { |
3150 | DRM_DEBUG("DFP2 disconnected\n"); |
3418 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
3151 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
3419 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
3152 | bios_5_scratch &= ~RADEON_DFP2_ON; |
3420 | bios_5_scratch &= ~RADEON_DFP2_ON; |
3153 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; |
3421 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; |
3154 | } |
3422 | } |