WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_clocks.c



 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include 
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"

 

		if (ASIC_IS_AVIVO(rdev)) {
			/* TODO FALLBACK */
		} else {
			DRM_INFO("Using generic clock info\n");

 
			/* may need to be per card */
			rdev->clock.max_pixel_clock = 35000;
 
			if (rdev->flags & RADEON_IS_IGP) {
				p1pll->reference_freq = 1432;
				p2pll->reference_freq = 1432;
				spll->reference_freq = 1432;

	mpll->max_feedback_div = 0xff;
	mpll->best_vco = 0;

 
	if (!rdev->clock.default_sclk)
		rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
	if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)

		rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
 

			} else {
				tmp = RREG32_PLL(RADEON_SCLK_CNTL);
				tmp &= ~(R300_SCLK_FORCE_VAP);
				tmp |= RADEON_SCLK_FORCE_CP;
				WREG32_PLL(RADEON_SCLK_CNTL, tmp);
				mdelay(15);

 
				tmp = RREG32_PLL(R300_SCLK_CNTL2);
				tmp &= ~(R300_SCLK_FORCE_TCL |
					 R300_SCLK_FORCE_GA |

				 RADEON_DYN_STOP_MODE_MASK);

 
			tmp |= (RADEON_ENGIN_DYNCLK_MODE |
				(0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
			WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);

			mdelay(15);
 
			tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
			tmp |= RADEON_SCLK_DYN_START_CNTL;

			WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
			mdelay(15);
 
			/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200

				      RADEON_CFG_ATI_REV_ID_MASK) <
				     RADEON_CFG_ATI_REV_A13)) {
					tmp |= RADEON_SCLK_MORE_FORCEON;
				}
				WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
				mdelay(15);
			}

 
			/* RV200::A11 A12, RV250::A11 A12 */
			if (((rdev->family == CHIP_RV200) ||

			     RADEON_CFG_ATI_REV_A13)) {
				tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
				tmp |= RADEON_TCL_BYPASS_DISABLE;
				WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
			}
			mdelay(15);

 
			/*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
			tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
			tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |

				RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
				RADEON_PIXCLK_LVDS_ALWAYS_ONb |
				RADEON_PIXCLK_TMDS_ALWAYS_ONb);

 
			WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

			mdelay(15);
 
			tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

			tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
				RADEON_PIXCLK_DAC_ALWAYS_ONb);
 
			WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
			mdelay(15);
		}
	} else {

					RADEON_SCLK_FORCE_IDCT |
					RADEON_SCLK_FORCE_VIP);
			}
			WREG32_PLL(RADEON_SCLK_CNTL, tmp);

 

			mdelay(16);
 
			if ((rdev->family == CHIP_R300) ||
			    (rdev->family == CHIP_R350)) {
				tmp = RREG32_PLL(R300_SCLK_CNTL2);
				tmp |= (R300_SCLK_FORCE_TCL |
					R300_SCLK_FORCE_GA |
					R300_SCLK_FORCE_CBA);
				WREG32_PLL(R300_SCLK_CNTL2, tmp);

				mdelay(16);
			}
 
			if (rdev->flags & RADEON_IS_IGP) {
				tmp = RREG32_PLL(RADEON_MCLK_CNTL);
				tmp &= ~(RADEON_FORCEON_MCLKA |
					 RADEON_FORCEON_YCLKA);

				WREG32_PLL(RADEON_MCLK_CNTL, tmp);
				mdelay(16);
			}
 
			if ((rdev->family == CHIP_RV200) ||
			    (rdev->family == CHIP_RV250) ||
			    (rdev->family == CHIP_RV280)) {
				tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

				tmp |= RADEON_SCLK_MORE_FORCEON;
				WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
				mdelay(16);

				 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
				 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
				 RADEON_PIXCLK_TMDS_ALWAYS_ONb);

 
			WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

			mdelay(16);
 
			tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
			tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |

Rev 2160	Rev 2997
Line 23...	Line 23...
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include "drmP.h"	28	#include
29	#include "radeon_drm.h"	29	#include
30	#include "radeon_reg.h"	30	#include "radeon_reg.h"
31	#include "radeon.h"	31	#include "radeon.h"
32	#include "atom.h"	32	#include "atom.h"
Line 33...	Line 33...
33		33
Line 217...	Line 217...
217	if (ASIC_IS_AVIVO(rdev)) {	217	if (ASIC_IS_AVIVO(rdev)) {
218	/* TODO FALLBACK */	218	/* TODO FALLBACK */
219	} else {	219	} else {
220	DRM_INFO("Using generic clock info\n");	220	DRM_INFO("Using generic clock info\n");
Line -...	Line 221...
-		221
-		222	/* may need to be per card */
-		223	rdev->clock.max_pixel_clock = 35000;
221		224
222	if (rdev->flags & RADEON_IS_IGP) {	225	if (rdev->flags & RADEON_IS_IGP) {
223	p1pll->reference_freq = 1432;	226	p1pll->reference_freq = 1432;
224	p2pll->reference_freq = 1432;	227	p2pll->reference_freq = 1432;
225	spll->reference_freq = 1432;	228	spll->reference_freq = 1432;
Line 329...	Line 332...
329	mpll->max_feedback_div = 0xff;	332	mpll->max_feedback_div = 0xff;
330	mpll->best_vco = 0;	333	mpll->best_vco = 0;
Line 331...	Line 334...
331		334
332	if (!rdev->clock.default_sclk)	335	if (!rdev->clock.default_sclk)
333	rdev->clock.default_sclk = radeon_get_engine_clock(rdev);	336	rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
334	if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock)	337	if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
Line 335...	Line 338...
335	rdev->clock.default_mclk = radeon_get_memory_clock(rdev);	338	rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
336		339
Line 628...	Line 631...
628	} else {	631	} else {
629	tmp = RREG32_PLL(RADEON_SCLK_CNTL);	632	tmp = RREG32_PLL(RADEON_SCLK_CNTL);
630	tmp &= ~(R300_SCLK_FORCE_VAP);	633	tmp &= ~(R300_SCLK_FORCE_VAP);
631	tmp \|= RADEON_SCLK_FORCE_CP;	634	tmp \|= RADEON_SCLK_FORCE_CP;
632	WREG32_PLL(RADEON_SCLK_CNTL, tmp);	635	WREG32_PLL(RADEON_SCLK_CNTL, tmp);
633	udelay(15000);	636	mdelay(15);
Line 634...	Line 637...
634		637
635	tmp = RREG32_PLL(R300_SCLK_CNTL2);	638	tmp = RREG32_PLL(R300_SCLK_CNTL2);
636	tmp &= ~(R300_SCLK_FORCE_TCL \|	639	tmp &= ~(R300_SCLK_FORCE_TCL \|
637	R300_SCLK_FORCE_GA \|	640	R300_SCLK_FORCE_GA \|
Line 646...	Line 649...
646	RADEON_DYN_STOP_MODE_MASK);	649	RADEON_DYN_STOP_MODE_MASK);
Line 647...	Line 650...
647		650
648	tmp \|= (RADEON_ENGIN_DYNCLK_MODE \|	651	tmp \|= (RADEON_ENGIN_DYNCLK_MODE \|
649	(0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));	652	(0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
650	WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);	653	WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
Line 651...	Line 654...
651	udelay(15000);	654	mdelay(15);
652		655
653	tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);	656	tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
654	tmp \|= RADEON_SCLK_DYN_START_CNTL;	657	tmp \|= RADEON_SCLK_DYN_START_CNTL;
Line 655...	Line 658...
655	WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);	658	WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
656	udelay(15000);	659	mdelay(15);
657		660
658	/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200	661	/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
Line 691...	Line 694...
691	RADEON_CFG_ATI_REV_ID_MASK) <	694	RADEON_CFG_ATI_REV_ID_MASK) <
692	RADEON_CFG_ATI_REV_A13)) {	695	RADEON_CFG_ATI_REV_A13)) {
693	tmp \|= RADEON_SCLK_MORE_FORCEON;	696	tmp \|= RADEON_SCLK_MORE_FORCEON;
694	}	697	}
695	WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);	698	WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
696	udelay(15000);	699	mdelay(15);
697	}	700	}
Line 698...	Line 701...
698		701
699	/* RV200::A11 A12, RV250::A11 A12 */	702	/* RV200::A11 A12, RV250::A11 A12 */
700	if (((rdev->family == CHIP_RV200) \|\|	703	if (((rdev->family == CHIP_RV200) \|\|
Line 704...	Line 707...
704	RADEON_CFG_ATI_REV_A13)) {	707	RADEON_CFG_ATI_REV_A13)) {
705	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);	708	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
706	tmp \|= RADEON_TCL_BYPASS_DISABLE;	709	tmp \|= RADEON_TCL_BYPASS_DISABLE;
707	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);	710	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
708	}	711	}
709	udelay(15000);	712	mdelay(15);
Line 710...	Line 713...
710		713
711	/enable dynamic mode for display clocks (PIXCLK and PIX2CLK) /	714	/enable dynamic mode for display clocks (PIXCLK and PIX2CLK) /
712	tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);	715	tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
713	tmp \|= (RADEON_PIX2CLK_ALWAYS_ONb \|	716	tmp \|= (RADEON_PIX2CLK_ALWAYS_ONb \|
Line 717...	Line 720...
717	RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb \|	720	RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb \|
718	RADEON_PIXCLK_LVDS_ALWAYS_ONb \|	721	RADEON_PIXCLK_LVDS_ALWAYS_ONb \|
719	RADEON_PIXCLK_TMDS_ALWAYS_ONb);	722	RADEON_PIXCLK_TMDS_ALWAYS_ONb);
Line 720...	Line 723...
720		723
721	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);	724	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
Line 722...	Line 725...
722	udelay(15000);	725	mdelay(15);
723		726
724	tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);	727	tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
Line 725...	Line 728...
725	tmp \|= (RADEON_PIXCLK_ALWAYS_ONb \|	728	tmp \|= (RADEON_PIXCLK_ALWAYS_ONb \|
726	RADEON_PIXCLK_DAC_ALWAYS_ONb);	729	RADEON_PIXCLK_DAC_ALWAYS_ONb);
727		730
728	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);	731	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
729	udelay(15000);	732	mdelay(15);
730	}	733	}
731	} else {	734	} else {
Line 856...	Line 859...
856	RADEON_SCLK_FORCE_IDCT \|	859	RADEON_SCLK_FORCE_IDCT \|
857	RADEON_SCLK_FORCE_VIP);	860	RADEON_SCLK_FORCE_VIP);
858	}	861	}
859	WREG32_PLL(RADEON_SCLK_CNTL, tmp);	862	WREG32_PLL(RADEON_SCLK_CNTL, tmp);
Line 860...	Line 863...
860		863
Line 861...	Line 864...
861	udelay(16000);	864	mdelay(16);
862		865
863	if ((rdev->family == CHIP_R300) \|\|	866	if ((rdev->family == CHIP_R300) \|\|
864	(rdev->family == CHIP_R350)) {	867	(rdev->family == CHIP_R350)) {
865	tmp = RREG32_PLL(R300_SCLK_CNTL2);	868	tmp = RREG32_PLL(R300_SCLK_CNTL2);
866	tmp \|= (R300_SCLK_FORCE_TCL \|	869	tmp \|= (R300_SCLK_FORCE_TCL \|
867	R300_SCLK_FORCE_GA \|	870	R300_SCLK_FORCE_GA \|
868	R300_SCLK_FORCE_CBA);	871	R300_SCLK_FORCE_CBA);
869	WREG32_PLL(R300_SCLK_CNTL2, tmp);	872	WREG32_PLL(R300_SCLK_CNTL2, tmp);
Line 870...	Line 873...
870	udelay(16000);	873	mdelay(16);
871	}	874	}
872		875
873	if (rdev->flags & RADEON_IS_IGP) {	876	if (rdev->flags & RADEON_IS_IGP) {
874	tmp = RREG32_PLL(RADEON_MCLK_CNTL);	877	tmp = RREG32_PLL(RADEON_MCLK_CNTL);
875	tmp &= ~(RADEON_FORCEON_MCLKA \|	878	tmp &= ~(RADEON_FORCEON_MCLKA \|
876	RADEON_FORCEON_YCLKA);	879	RADEON_FORCEON_YCLKA);
Line 877...	Line 880...
877	WREG32_PLL(RADEON_MCLK_CNTL, tmp);	880	WREG32_PLL(RADEON_MCLK_CNTL, tmp);
878	udelay(16000);	881	mdelay(16);
879	}	882	}
880		883
881	if ((rdev->family == CHIP_RV200) \|\|	884	if ((rdev->family == CHIP_RV200) \|\|
882	(rdev->family == CHIP_RV250) \|\|	885	(rdev->family == CHIP_RV250) \|\|
883	(rdev->family == CHIP_RV280)) {	886	(rdev->family == CHIP_RV280)) {
884	tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);	887	tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
Line 885...	Line 888...
885	tmp \|= RADEON_SCLK_MORE_FORCEON;	888	tmp \|= RADEON_SCLK_MORE_FORCEON;
886	WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);	889	WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
887	udelay(16000);	890	mdelay(16);
Line 895...	Line 898...
895	RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb \|	898	RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb \|
896	RADEON_PIXCLK_LVDS_ALWAYS_ONb \|	899	RADEON_PIXCLK_LVDS_ALWAYS_ONb \|
897	RADEON_PIXCLK_TMDS_ALWAYS_ONb);	900	RADEON_PIXCLK_TMDS_ALWAYS_ONb);
Line 898...	Line 901...
898		901
899	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);	902	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
Line 900...	Line 903...
900	udelay(16000);	903	mdelay(16);
901		904
902	tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);	905	tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
903	tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb \|	906	tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb \|

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_clocks.c – Rev 2160 → 2997