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Rev 5078 Rev 6104
Line 28... Line 28...
28 
#include
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#include
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#include "radeon_reg.h"
 29 
#include "radeon_reg.h"
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#include "radeon.h"
 30 
#include "radeon.h"
31 
#include "atom.h"
 31 
#include "atom.h"
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 - 
 
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//#include
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34 
#include
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#include
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/*
 34 
/*
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 * BIOS.
 35 
 * BIOS.
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	return true;
 72 
	return true;
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}
 73 
}
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 74 
 
76 
static bool radeon_read_bios(struct radeon_device *rdev)
 75 
static bool radeon_read_bios(struct radeon_device *rdev)
77 
{
 76 
{
78 
	uint8_t __iomem *bios;
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	uint8_t __iomem *bios, val1, val2;
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    size_t    size;
 78 
	size_t size;
80 
 
 79 
 
81 
	rdev->bios = NULL;
 80 
	rdev->bios = NULL;
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	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
 81 
	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
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	}
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	}
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 181 
 
183 
	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
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	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
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		ret = radeon_atrm_call(atrm_handle,
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		ret = radeon_atrm_call(atrm_handle,
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				       rdev->bios,
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				       rdev->bios,
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						 (i * ATRM_BIOS_PAGE),
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				       (i * ATRM_BIOS_PAGE),
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						 ATRM_BIOS_PAGE);
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				       ATRM_BIOS_PAGE);
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		if (ret < ATRM_BIOS_PAGE)
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		if (ret < ATRM_BIOS_PAGE)
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			break;
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			break;
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	}
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	}
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	return true;
 195 
	return true;
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}
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}
198 
#else
 197 
#else
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static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
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static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
200 
{
 199 
{
201 
    return false;
 200 
	return false;
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}
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}
203 
#endif
 202 
#endif
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 203 
 
205 
static bool ni_read_disabled_bios(struct radeon_device *rdev)
 204 
static bool ni_read_disabled_bios(struct radeon_device *rdev)
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	rom_cntl = RREG32(R600_ROM_CNTL);
 217 
	rom_cntl = RREG32(R600_ROM_CNTL);
Line 219... Line 218...
219 
 
 218 
 
220 
	/* enable the rom */
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	/* enable the rom */
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	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
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	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
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	if (!ASIC_IS_NODCE(rdev)) {
 221 
	if (!ASIC_IS_NODCE(rdev)) {
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	/* Disable VGA mode */
 222 
		/* Disable VGA mode */
224 
	WREG32(AVIVO_D1VGA_CONTROL,
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		WREG32(AVIVO_D1VGA_CONTROL,
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	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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		       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 225 
					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));
227 
	WREG32(AVIVO_D2VGA_CONTROL,
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		WREG32(AVIVO_D2VGA_CONTROL,
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	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 227 
		       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
229 
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 228 
					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));
230 
	WREG32(AVIVO_VGA_RENDER_CONTROL,
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		WREG32(AVIVO_VGA_RENDER_CONTROL,
231 
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 230 
		       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
232 
	}
 231 
	}
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	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 232 
	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
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234 
 
 233 
 
235 
	r = radeon_read_bios(rdev);
 234 
	r = radeon_read_bios(rdev);
236 
 
 235 
 
237 
	/* restore regs */
 236 
	/* restore regs */
238 
	WREG32(R600_BUS_CNTL, bus_cntl);
 237 
	WREG32(R600_BUS_CNTL, bus_cntl);
239 
	if (!ASIC_IS_NODCE(rdev)) {
 238 
	if (!ASIC_IS_NODCE(rdev)) {
240 
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 239 
		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
241 
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 240 
		WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
242 
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 241 
		WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
243 
	}
 242 
	}
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466 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 465 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
467 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
 466 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
468 
	if (rdev->flags & RADEON_IS_PCIE)
 467 
	if (rdev->flags & RADEON_IS_PCIE)
469 
		bus_cntl = RREG32(RV370_BUS_CNTL);
 468 
		bus_cntl = RREG32(RV370_BUS_CNTL);
470 
	else
 469 
	else
471 
	bus_cntl = RREG32(RADEON_BUS_CNTL);
 470 
		bus_cntl = RREG32(RADEON_BUS_CNTL);
472 
	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 471 
	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
473 
	crtc2_gen_cntl = 0;
 472 
	crtc2_gen_cntl = 0;
474 
	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 473 
	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
475 
	fp2_gen_cntl = 0;
 474 
	fp2_gen_cntl = 0;
Line 491... Line 490...
491 
 
 490 
 
492 
	/* enable the rom */
 491 
	/* enable the rom */
493 
	if (rdev->flags & RADEON_IS_PCIE)
 492 
	if (rdev->flags & RADEON_IS_PCIE)
494 
		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 493 
		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
495 
	else
 494 
	else
Line 496... Line 495...
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	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 495 
		WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
497 
 
 496 
 
498 
	/* Turn off mem requests and CRTC for both controllers */
 497 
	/* Turn off mem requests and CRTC for both controllers */
499 
	WREG32(RADEON_CRTC_GEN_CNTL,
 498 
	WREG32(RADEON_CRTC_GEN_CNTL,
Line 521... Line 520...
521 
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 520 
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
522 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
 521 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
523 
	if (rdev->flags & RADEON_IS_PCIE)
 522 
	if (rdev->flags & RADEON_IS_PCIE)
524 
		WREG32(RV370_BUS_CNTL, bus_cntl);
 523 
		WREG32(RV370_BUS_CNTL, bus_cntl);
525 
	else
 524 
	else
526 
	WREG32(RADEON_BUS_CNTL, bus_cntl);
 525 
		WREG32(RADEON_BUS_CNTL, bus_cntl);
527 
	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 526 
	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
528 
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 527 
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
529 
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 528 
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
530 
	}
 529 
	}
531 
	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 530 
	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);