Rev 1321 | Rev 1404 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1321 | Rev 1403 | ||
---|---|---|---|
Line 31... | Line 31... | ||
31 | /* |
31 | /* |
32 | * common functions |
32 | * common functions |
33 | */ |
33 | */ |
34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
- | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
|
36 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Line 37... | Line 38... | ||
37 | 38 | ||
38 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
39 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
Line 74... | Line 75... | ||
74 | uint32_t offset, uint32_t obj_size); |
75 | uint32_t offset, uint32_t obj_size); |
75 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
76 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
76 | void r100_bandwidth_update(struct radeon_device *rdev); |
77 | void r100_bandwidth_update(struct radeon_device *rdev); |
77 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
78 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
78 | int r100_ring_test(struct radeon_device *rdev); |
79 | int r100_ring_test(struct radeon_device *rdev); |
79 | void r100_hdp_flush(struct radeon_device *rdev); |
- | |
80 | void r100_hpd_init(struct radeon_device *rdev); |
80 | void r100_hpd_init(struct radeon_device *rdev); |
81 | void r100_hpd_fini(struct radeon_device *rdev); |
81 | void r100_hpd_fini(struct radeon_device *rdev); |
82 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
82 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
83 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
83 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
84 | enum radeon_hpd_id hpd); |
84 | enum radeon_hpd_id hpd); |
Line 104... | Line 104... | ||
104 | // .copy_blit = &r100_copy_blit, |
104 | // .copy_blit = &r100_copy_blit, |
105 | // .copy_dma = NULL, |
105 | // .copy_dma = NULL, |
106 | // .copy = &r100_copy_blit, |
106 | // .copy = &r100_copy_blit, |
107 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
107 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
108 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
108 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
109 | .get_memory_clock = NULL, |
109 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
110 | .set_memory_clock = NULL, |
110 | .set_memory_clock = NULL, |
111 | .set_pcie_lanes = NULL, |
111 | .set_pcie_lanes = NULL, |
112 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
112 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
113 | .set_surface_reg = r100_set_surface_reg, |
113 | .set_surface_reg = r100_set_surface_reg, |
114 | .clear_surface_reg = r100_clear_surface_reg, |
114 | .clear_surface_reg = r100_clear_surface_reg, |
115 | .bandwidth_update = &r100_bandwidth_update, |
115 | .bandwidth_update = &r100_bandwidth_update, |
116 | .hdp_flush = &r100_hdp_flush, |
- | |
117 | .hpd_init = &r100_hpd_init, |
116 | .hpd_init = &r100_hpd_init, |
118 | .hpd_fini = &r100_hpd_fini, |
117 | .hpd_fini = &r100_hpd_fini, |
119 | .hpd_sense = &r100_hpd_sense, |
118 | .hpd_sense = &r100_hpd_sense, |
120 | .hpd_set_polarity = &r100_hpd_set_polarity, |
119 | .hpd_set_polarity = &r100_hpd_set_polarity, |
121 | }; |
120 | }; |
Line 164... | Line 163... | ||
164 | // .copy_blit = &r100_copy_blit, |
163 | // .copy_blit = &r100_copy_blit, |
165 | // .copy_dma = &r300_copy_dma, |
164 | // .copy_dma = &r300_copy_dma, |
166 | // .copy = &r100_copy_blit, |
165 | // .copy = &r100_copy_blit, |
167 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
166 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
168 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
167 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
169 | .get_memory_clock = NULL, |
168 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
170 | .set_memory_clock = NULL, |
169 | .set_memory_clock = NULL, |
171 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
170 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
172 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
171 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
173 | .set_surface_reg = r100_set_surface_reg, |
172 | .set_surface_reg = r100_set_surface_reg, |
174 | .clear_surface_reg = r100_clear_surface_reg, |
173 | .clear_surface_reg = r100_clear_surface_reg, |
175 | .bandwidth_update = &r100_bandwidth_update, |
174 | .bandwidth_update = &r100_bandwidth_update, |
176 | .hdp_flush = &r100_hdp_flush, |
- | |
177 | .hpd_init = &r100_hpd_init, |
175 | .hpd_init = &r100_hpd_init, |
178 | .hpd_fini = &r100_hpd_fini, |
176 | .hpd_fini = &r100_hpd_fini, |
179 | .hpd_sense = &r100_hpd_sense, |
177 | .hpd_sense = &r100_hpd_sense, |
180 | .hpd_set_polarity = &r100_hpd_set_polarity, |
178 | .hpd_set_polarity = &r100_hpd_set_polarity, |
181 | }; |
179 | }; |
Line 215... | Line 213... | ||
215 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
213 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
216 | .set_clock_gating = &radeon_atom_set_clock_gating, |
214 | .set_clock_gating = &radeon_atom_set_clock_gating, |
217 | .set_surface_reg = r100_set_surface_reg, |
215 | .set_surface_reg = r100_set_surface_reg, |
218 | .clear_surface_reg = r100_clear_surface_reg, |
216 | .clear_surface_reg = r100_clear_surface_reg, |
219 | .bandwidth_update = &r100_bandwidth_update, |
217 | .bandwidth_update = &r100_bandwidth_update, |
220 | .hdp_flush = &r100_hdp_flush, |
- | |
221 | .hpd_init = &r100_hpd_init, |
218 | .hpd_init = &r100_hpd_init, |
222 | .hpd_fini = &r100_hpd_fini, |
219 | .hpd_fini = &r100_hpd_fini, |
223 | .hpd_sense = &r100_hpd_sense, |
220 | .hpd_sense = &r100_hpd_sense, |
224 | .hpd_set_polarity = &r100_hpd_set_polarity, |
221 | .hpd_set_polarity = &r100_hpd_set_polarity, |
225 | }; |
222 | }; |
Line 257... | Line 254... | ||
257 | // .copy_blit = &r100_copy_blit, |
254 | // .copy_blit = &r100_copy_blit, |
258 | // .copy_dma = &r300_copy_dma, |
255 | // .copy_dma = &r300_copy_dma, |
259 | // .copy = &r100_copy_blit, |
256 | // .copy = &r100_copy_blit, |
260 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
257 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
261 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
258 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
262 | .get_memory_clock = NULL, |
259 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
263 | .set_memory_clock = NULL, |
260 | .set_memory_clock = NULL, |
264 | .set_pcie_lanes = NULL, |
261 | .set_pcie_lanes = NULL, |
265 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
262 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
266 | .set_surface_reg = r100_set_surface_reg, |
263 | .set_surface_reg = r100_set_surface_reg, |
267 | .clear_surface_reg = r100_clear_surface_reg, |
264 | .clear_surface_reg = r100_clear_surface_reg, |
268 | .bandwidth_update = &r100_bandwidth_update, |
265 | .bandwidth_update = &r100_bandwidth_update, |
269 | .hdp_flush = &r100_hdp_flush, |
- | |
270 | .hpd_init = &r100_hpd_init, |
266 | .hpd_init = &r100_hpd_init, |
271 | .hpd_fini = &r100_hpd_fini, |
267 | .hpd_fini = &r100_hpd_fini, |
272 | .hpd_sense = &r100_hpd_sense, |
268 | .hpd_sense = &r100_hpd_sense, |
273 | .hpd_set_polarity = &r100_hpd_set_polarity, |
269 | .hpd_set_polarity = &r100_hpd_set_polarity, |
274 | }; |
270 | }; |
Line 321... | Line 317... | ||
321 | .get_memory_clock = &radeon_atom_get_memory_clock, |
317 | .get_memory_clock = &radeon_atom_get_memory_clock, |
322 | .set_memory_clock = &radeon_atom_set_memory_clock, |
318 | .set_memory_clock = &radeon_atom_set_memory_clock, |
323 | .set_pcie_lanes = NULL, |
319 | .set_pcie_lanes = NULL, |
324 | .set_clock_gating = &radeon_atom_set_clock_gating, |
320 | .set_clock_gating = &radeon_atom_set_clock_gating, |
325 | .bandwidth_update = &rs600_bandwidth_update, |
321 | .bandwidth_update = &rs600_bandwidth_update, |
326 | .hdp_flush = &r100_hdp_flush, |
- | |
327 | .hpd_init = &rs600_hpd_init, |
322 | .hpd_init = &rs600_hpd_init, |
328 | .hpd_fini = &rs600_hpd_fini, |
323 | .hpd_fini = &rs600_hpd_fini, |
329 | .hpd_sense = &rs600_hpd_sense, |
324 | .hpd_sense = &rs600_hpd_sense, |
330 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
325 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
331 | }; |
326 | }; |
Line 369... | Line 364... | ||
369 | .set_pcie_lanes = NULL, |
364 | .set_pcie_lanes = NULL, |
370 | .set_clock_gating = &radeon_atom_set_clock_gating, |
365 | .set_clock_gating = &radeon_atom_set_clock_gating, |
371 | .set_surface_reg = r100_set_surface_reg, |
366 | .set_surface_reg = r100_set_surface_reg, |
372 | .clear_surface_reg = r100_clear_surface_reg, |
367 | .clear_surface_reg = r100_clear_surface_reg, |
373 | .bandwidth_update = &rs690_bandwidth_update, |
368 | .bandwidth_update = &rs690_bandwidth_update, |
374 | .hdp_flush = &r100_hdp_flush, |
- | |
375 | .hpd_init = &rs600_hpd_init, |
369 | .hpd_init = &rs600_hpd_init, |
376 | .hpd_fini = &rs600_hpd_fini, |
370 | .hpd_fini = &rs600_hpd_fini, |
377 | .hpd_sense = &rs600_hpd_sense, |
371 | .hpd_sense = &rs600_hpd_sense, |
378 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
372 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
379 | }; |
373 | }; |
Line 421... | Line 415... | ||
421 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
415 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
422 | .set_clock_gating = &radeon_atom_set_clock_gating, |
416 | .set_clock_gating = &radeon_atom_set_clock_gating, |
423 | .set_surface_reg = r100_set_surface_reg, |
417 | .set_surface_reg = r100_set_surface_reg, |
424 | .clear_surface_reg = r100_clear_surface_reg, |
418 | .clear_surface_reg = r100_clear_surface_reg, |
425 | .bandwidth_update = &rv515_bandwidth_update, |
419 | .bandwidth_update = &rv515_bandwidth_update, |
426 | .hdp_flush = &r100_hdp_flush, |
- | |
427 | .hpd_init = &rs600_hpd_init, |
420 | .hpd_init = &rs600_hpd_init, |
428 | .hpd_fini = &rs600_hpd_fini, |
421 | .hpd_fini = &rs600_hpd_fini, |
429 | .hpd_sense = &rs600_hpd_sense, |
422 | .hpd_sense = &rs600_hpd_sense, |
430 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
423 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
431 | }; |
424 | }; |
Line 464... | Line 457... | ||
464 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
457 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
465 | .set_clock_gating = &radeon_atom_set_clock_gating, |
458 | .set_clock_gating = &radeon_atom_set_clock_gating, |
466 | .set_surface_reg = r100_set_surface_reg, |
459 | .set_surface_reg = r100_set_surface_reg, |
467 | .clear_surface_reg = r100_clear_surface_reg, |
460 | .clear_surface_reg = r100_clear_surface_reg, |
468 | .bandwidth_update = &rv515_bandwidth_update, |
461 | .bandwidth_update = &rv515_bandwidth_update, |
469 | .hdp_flush = &r100_hdp_flush, |
- | |
470 | .hpd_init = &rs600_hpd_init, |
462 | .hpd_init = &rs600_hpd_init, |
471 | .hpd_fini = &rs600_hpd_fini, |
463 | .hpd_fini = &rs600_hpd_fini, |
472 | .hpd_sense = &rs600_hpd_sense, |
464 | .hpd_sense = &rs600_hpd_sense, |
473 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
465 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
474 | }; |
466 | }; |
Line 505... | Line 497... | ||
505 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
497 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
506 | int r600_ring_test(struct radeon_device *rdev); |
498 | int r600_ring_test(struct radeon_device *rdev); |
507 | int r600_copy_blit(struct radeon_device *rdev, |
499 | int r600_copy_blit(struct radeon_device *rdev, |
508 | uint64_t src_offset, uint64_t dst_offset, |
500 | uint64_t src_offset, uint64_t dst_offset, |
509 | unsigned num_pages, struct radeon_fence *fence); |
501 | unsigned num_pages, struct radeon_fence *fence); |
510 | void r600_hdp_flush(struct radeon_device *rdev); |
- | |
511 | void r600_hpd_init(struct radeon_device *rdev); |
502 | void r600_hpd_init(struct radeon_device *rdev); |
512 | void r600_hpd_fini(struct radeon_device *rdev); |
503 | void r600_hpd_fini(struct radeon_device *rdev); |
513 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
504 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
514 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
505 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
515 | enum radeon_hpd_id hpd); |
506 | enum radeon_hpd_id hpd); |
Line 540... | Line 531... | ||
540 | .set_pcie_lanes = NULL, |
531 | .set_pcie_lanes = NULL, |
541 | .set_clock_gating = &radeon_atom_set_clock_gating, |
532 | .set_clock_gating = &radeon_atom_set_clock_gating, |
542 | .set_surface_reg = r600_set_surface_reg, |
533 | .set_surface_reg = r600_set_surface_reg, |
543 | .clear_surface_reg = r600_clear_surface_reg, |
534 | .clear_surface_reg = r600_clear_surface_reg, |
544 | .bandwidth_update = &rv515_bandwidth_update, |
535 | .bandwidth_update = &rv515_bandwidth_update, |
545 | .hdp_flush = &r600_hdp_flush, |
- | |
546 | .hpd_init = &r600_hpd_init, |
536 | .hpd_init = &r600_hpd_init, |
547 | .hpd_fini = &r600_hpd_fini, |
537 | .hpd_fini = &r600_hpd_fini, |
548 | .hpd_sense = &r600_hpd_sense, |
538 | .hpd_sense = &r600_hpd_sense, |
549 | .hpd_set_polarity = &r600_hpd_set_polarity, |
539 | .hpd_set_polarity = &r600_hpd_set_polarity, |
550 | }; |
540 | }; |
Line 584... | Line 574... | ||
584 | .set_pcie_lanes = NULL, |
574 | .set_pcie_lanes = NULL, |
585 | .set_clock_gating = &radeon_atom_set_clock_gating, |
575 | .set_clock_gating = &radeon_atom_set_clock_gating, |
586 | .set_surface_reg = r600_set_surface_reg, |
576 | .set_surface_reg = r600_set_surface_reg, |
587 | .clear_surface_reg = r600_clear_surface_reg, |
577 | .clear_surface_reg = r600_clear_surface_reg, |
588 | .bandwidth_update = &rv515_bandwidth_update, |
578 | .bandwidth_update = &rv515_bandwidth_update, |
589 | .hdp_flush = &r600_hdp_flush, |
- | |
590 | .hpd_init = &r600_hpd_init, |
579 | .hpd_init = &r600_hpd_init, |
591 | .hpd_fini = &r600_hpd_fini, |
580 | .hpd_fini = &r600_hpd_fini, |
592 | .hpd_sense = &r600_hpd_sense, |
581 | .hpd_sense = &r600_hpd_sense, |
593 | .hpd_set_polarity = &r600_hpd_set_polarity, |
582 | .hpd_set_polarity = &r600_hpd_set_polarity, |
594 | }; |
583 | }; |