Rev 1233 | Rev 1321 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1233 | Rev 1268 | ||
|---|---|---|---|
| Line 29... | Line 29... | ||
| 29 | #define __RADEON_ASIC_H__ |
29 | #define __RADEON_ASIC_H__ |
| Line 30... | Line 30... | ||
| 30 | 30 | ||
| 31 | /* |
31 | /* |
| 32 | * common functions |
32 | * common functions |
| - | 33 | */ |
|
| 33 | */ |
34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
| 34 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| Line -... | Line 36... | ||
| - | 36 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
|
| 35 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
37 | |
| - | 38 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
|
| 36 | 39 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
|
| 37 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
40 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
| Line 38... | Line 41... | ||
| 38 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
41 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 39 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
42 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
| Line 93... | Line 96... | ||
| 93 | // .fence_ring_emit = &r100_fence_ring_emit, |
96 | // .fence_ring_emit = &r100_fence_ring_emit, |
| 94 | // .cs_parse = &r100_cs_parse, |
97 | // .cs_parse = &r100_cs_parse, |
| 95 | // .copy_blit = &r100_copy_blit, |
98 | // .copy_blit = &r100_copy_blit, |
| 96 | // .copy_dma = NULL, |
99 | // .copy_dma = NULL, |
| 97 | // .copy = &r100_copy_blit, |
100 | // .copy = &r100_copy_blit, |
| - | 101 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
|
| 98 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
102 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| - | 103 | .get_memory_clock = NULL, |
|
| 99 | .set_memory_clock = NULL, |
104 | .set_memory_clock = NULL, |
| 100 | .set_pcie_lanes = NULL, |
105 | .set_pcie_lanes = NULL, |
| 101 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
106 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 102 | .set_surface_reg = r100_set_surface_reg, |
107 | .set_surface_reg = r100_set_surface_reg, |
| 103 | .clear_surface_reg = r100_clear_surface_reg, |
108 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 146... | Line 151... | ||
| 146 | // .fence_ring_emit = &r300_fence_ring_emit, |
151 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 147 | // .cs_parse = &r300_cs_parse, |
152 | // .cs_parse = &r300_cs_parse, |
| 148 | // .copy_blit = &r100_copy_blit, |
153 | // .copy_blit = &r100_copy_blit, |
| 149 | // .copy_dma = &r300_copy_dma, |
154 | // .copy_dma = &r300_copy_dma, |
| 150 | // .copy = &r100_copy_blit, |
155 | // .copy = &r100_copy_blit, |
| - | 156 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
|
| 151 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
157 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| - | 158 | .get_memory_clock = NULL, |
|
| 152 | .set_memory_clock = NULL, |
159 | .set_memory_clock = NULL, |
| 153 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
160 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 154 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
161 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 155 | .set_surface_reg = r100_set_surface_reg, |
162 | .set_surface_reg = r100_set_surface_reg, |
| 156 | .clear_surface_reg = r100_clear_surface_reg, |
163 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 183... | Line 190... | ||
| 183 | // .fence_ring_emit = &r300_fence_ring_emit, |
190 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 184 | // .cs_parse = &r300_cs_parse, |
191 | // .cs_parse = &r300_cs_parse, |
| 185 | // .copy_blit = &r100_copy_blit, |
192 | // .copy_blit = &r100_copy_blit, |
| 186 | // .copy_dma = &r300_copy_dma, |
193 | // .copy_dma = &r300_copy_dma, |
| 187 | // .copy = &r100_copy_blit, |
194 | // .copy = &r100_copy_blit, |
| - | 195 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| 188 | .set_engine_clock = &radeon_atom_set_engine_clock, |
196 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| - | 197 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| 189 | .set_memory_clock = &radeon_atom_set_memory_clock, |
198 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 190 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
199 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 191 | .set_clock_gating = &radeon_atom_set_clock_gating, |
200 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 192 | .set_surface_reg = r100_set_surface_reg, |
201 | .set_surface_reg = r100_set_surface_reg, |
| 193 | .clear_surface_reg = r100_clear_surface_reg, |
202 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 225... | Line 234... | ||
| 225 | // .fence_ring_emit = &r300_fence_ring_emit, |
234 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 226 | // .cs_parse = &r300_cs_parse, |
235 | // .cs_parse = &r300_cs_parse, |
| 227 | // .copy_blit = &r100_copy_blit, |
236 | // .copy_blit = &r100_copy_blit, |
| 228 | // .copy_dma = &r300_copy_dma, |
237 | // .copy_dma = &r300_copy_dma, |
| 229 | // .copy = &r100_copy_blit, |
238 | // .copy = &r100_copy_blit, |
| - | 239 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
|
| 230 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
240 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| - | 241 | .get_memory_clock = NULL, |
|
| 231 | .set_memory_clock = NULL, |
242 | .set_memory_clock = NULL, |
| 232 | .set_pcie_lanes = NULL, |
243 | .set_pcie_lanes = NULL, |
| 233 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
244 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 234 | .set_surface_reg = r100_set_surface_reg, |
245 | .set_surface_reg = r100_set_surface_reg, |
| 235 | .clear_surface_reg = r100_clear_surface_reg, |
246 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 271... | Line 282... | ||
| 271 | // .fence_ring_emit = &r300_fence_ring_emit, |
282 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 272 | // .cs_parse = &r300_cs_parse, |
283 | // .cs_parse = &r300_cs_parse, |
| 273 | // .copy_blit = &r100_copy_blit, |
284 | // .copy_blit = &r100_copy_blit, |
| 274 | // .copy_dma = &r300_copy_dma, |
285 | // .copy_dma = &r300_copy_dma, |
| 275 | // .copy = &r100_copy_blit, |
286 | // .copy = &r100_copy_blit, |
| - | 287 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| 276 | .set_engine_clock = &radeon_atom_set_engine_clock, |
288 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| - | 289 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| 277 | .set_memory_clock = &radeon_atom_set_memory_clock, |
290 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 278 | .set_pcie_lanes = NULL, |
291 | .set_pcie_lanes = NULL, |
| 279 | .set_clock_gating = &radeon_atom_set_clock_gating, |
292 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 280 | .bandwidth_update = &rs600_bandwidth_update, |
293 | .bandwidth_update = &rs600_bandwidth_update, |
| 281 | }; |
294 | }; |
| Line 310... | Line 323... | ||
| 310 | // .fence_ring_emit = &r300_fence_ring_emit, |
323 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 311 | // .cs_parse = &r300_cs_parse, |
324 | // .cs_parse = &r300_cs_parse, |
| 312 | // .copy_blit = &r100_copy_blit, |
325 | // .copy_blit = &r100_copy_blit, |
| 313 | // .copy_dma = &r300_copy_dma, |
326 | // .copy_dma = &r300_copy_dma, |
| 314 | // .copy = &r300_copy_dma, |
327 | // .copy = &r300_copy_dma, |
| - | 328 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| 315 | .set_engine_clock = &radeon_atom_set_engine_clock, |
329 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| - | 330 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| 316 | .set_memory_clock = &radeon_atom_set_memory_clock, |
331 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 317 | .set_pcie_lanes = NULL, |
332 | .set_pcie_lanes = NULL, |
| 318 | .set_clock_gating = &radeon_atom_set_clock_gating, |
333 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 319 | .set_surface_reg = r100_set_surface_reg, |
334 | .set_surface_reg = r100_set_surface_reg, |
| 320 | .clear_surface_reg = r100_clear_surface_reg, |
335 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 355... | Line 370... | ||
| 355 | // .fence_ring_emit = &r300_fence_ring_emit, |
370 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 356 | // .cs_parse = &r300_cs_parse, |
371 | // .cs_parse = &r300_cs_parse, |
| 357 | // .copy_blit = &r100_copy_blit, |
372 | // .copy_blit = &r100_copy_blit, |
| 358 | // .copy_dma = &r300_copy_dma, |
373 | // .copy_dma = &r300_copy_dma, |
| 359 | // .copy = &r100_copy_blit, |
374 | // .copy = &r100_copy_blit, |
| - | 375 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| 360 | .set_engine_clock = &radeon_atom_set_engine_clock, |
376 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| - | 377 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| 361 | .set_memory_clock = &radeon_atom_set_memory_clock, |
378 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 362 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
379 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 363 | .set_clock_gating = &radeon_atom_set_clock_gating, |
380 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 364 | .set_surface_reg = r100_set_surface_reg, |
381 | .set_surface_reg = r100_set_surface_reg, |
| 365 | .clear_surface_reg = r100_clear_surface_reg, |
382 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 391... | Line 408... | ||
| 391 | // .fence_ring_emit = &r300_fence_ring_emit, |
408 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 392 | // .cs_parse = &r300_cs_parse, |
409 | // .cs_parse = &r300_cs_parse, |
| 393 | // .copy_blit = &r100_copy_blit, |
410 | // .copy_blit = &r100_copy_blit, |
| 394 | // .copy_dma = &r300_copy_dma, |
411 | // .copy_dma = &r300_copy_dma, |
| 395 | // .copy = &r100_copy_blit, |
412 | // .copy = &r100_copy_blit, |
| - | 413 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| 396 | .set_engine_clock = &radeon_atom_set_engine_clock, |
414 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| - | 415 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| 397 | .set_memory_clock = &radeon_atom_set_memory_clock, |
416 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 398 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
417 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 399 | .set_clock_gating = &radeon_atom_set_clock_gating, |
418 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 400 | .set_surface_reg = r100_set_surface_reg, |
419 | .set_surface_reg = r100_set_surface_reg, |
| 401 | .clear_surface_reg = r100_clear_surface_reg, |
420 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 454... | Line 473... | ||
| 454 | // .fence_ring_emit = &r600_fence_ring_emit, |
473 | // .fence_ring_emit = &r600_fence_ring_emit, |
| 455 | // .cs_parse = &r600_cs_parse, |
474 | // .cs_parse = &r600_cs_parse, |
| 456 | // .copy_blit = &r600_copy_blit, |
475 | // .copy_blit = &r600_copy_blit, |
| 457 | // .copy_dma = &r600_copy_blit, |
476 | // .copy_dma = &r600_copy_blit, |
| 458 | // .copy = &r600_copy_blit, |
477 | // .copy = &r600_copy_blit, |
| - | 478 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| 459 | .set_engine_clock = &radeon_atom_set_engine_clock, |
479 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| - | 480 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| 460 | .set_memory_clock = &radeon_atom_set_memory_clock, |
481 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 461 | .set_pcie_lanes = NULL, |
482 | .set_pcie_lanes = NULL, |
| 462 | .set_clock_gating = &radeon_atom_set_clock_gating, |
483 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 463 | .set_surface_reg = r600_set_surface_reg, |
484 | .set_surface_reg = r600_set_surface_reg, |
| 464 | .clear_surface_reg = r600_clear_surface_reg, |
485 | .clear_surface_reg = r600_clear_surface_reg, |
| Line 491... | Line 512... | ||
| 491 | // .fence_ring_emit = &r600_fence_ring_emit, |
512 | // .fence_ring_emit = &r600_fence_ring_emit, |
| 492 | // .cs_parse = &r600_cs_parse, |
513 | // .cs_parse = &r600_cs_parse, |
| 493 | // .copy_blit = &r600_copy_blit, |
514 | // .copy_blit = &r600_copy_blit, |
| 494 | // .copy_dma = &r600_copy_blit, |
515 | // .copy_dma = &r600_copy_blit, |
| 495 | // .copy = &r600_copy_blit, |
516 | // .copy = &r600_copy_blit, |
| - | 517 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| 496 | .set_engine_clock = &radeon_atom_set_engine_clock, |
518 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| - | 519 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| 497 | .set_memory_clock = &radeon_atom_set_memory_clock, |
520 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 498 | .set_pcie_lanes = NULL, |
521 | .set_pcie_lanes = NULL, |
| 499 | .set_clock_gating = &radeon_atom_set_clock_gating, |
522 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 500 | .set_surface_reg = r600_set_surface_reg, |
523 | .set_surface_reg = r600_set_surface_reg, |
| 501 | .clear_surface_reg = r600_clear_surface_reg, |
524 | .clear_surface_reg = r600_clear_surface_reg, |