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Line 59... Line 59...
59
void r100_cp_fini(struct radeon_device *rdev);
59
void r100_cp_fini(struct radeon_device *rdev);
60
void r100_cp_disable(struct radeon_device *rdev);
60
void r100_cp_disable(struct radeon_device *rdev);
61
void r100_ring_start(struct radeon_device *rdev);
61
void r100_ring_start(struct radeon_device *rdev);
62
int r100_irq_set(struct radeon_device *rdev);
62
int r100_irq_set(struct radeon_device *rdev);
63
int r100_irq_process(struct radeon_device *rdev);
63
int r100_irq_process(struct radeon_device *rdev);
64
//void r100_fence_ring_emit(struct radeon_device *rdev,
64
void r100_fence_ring_emit(struct radeon_device *rdev,
65
//             struct radeon_fence *fence);
65
			  struct radeon_fence *fence);
66
//int r100_cs_parse(struct radeon_cs_parser *p);
66
int r100_cs_parse(struct radeon_cs_parser *p);
67
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
67
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
68
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
68
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
69
//int r100_copy_blit(struct radeon_device *rdev,
69
int r100_copy_blit(struct radeon_device *rdev,
70
//          uint64_t src_offset,
70
		   uint64_t src_offset,
71
//          uint64_t dst_offset,
71
		   uint64_t dst_offset,
72
//          unsigned num_pages,
72
		   unsigned num_pages,
73
//          struct radeon_fence *fence);
73
		   struct radeon_fence *fence);
Line 74... Line -...
74
 
-
 
75
 
-
 
76
#if 0
74
 
77
 
75
 
78
static struct radeon_asic r100_asic = {
76
static struct radeon_asic r100_asic = {
79
	.init = &r100_init,
77
	.init = &r100_init,
80
	.errata = &r100_errata,
78
	.errata = &r100_errata,
81
	.vram_info = &r100_vram_info,
79
	.vram_info = &r100_vram_info,
82
	.gpu_reset = &r100_gpu_reset,
80
	.gpu_reset = &r100_gpu_reset,
83
	.mc_init = &r100_mc_init,
81
	.mc_init = &r100_mc_init,
84
	.mc_fini = &r100_mc_fini,
82
	.mc_fini = &r100_mc_fini,
85
	.wb_init = &r100_wb_init,
83
//   .wb_init = &r100_wb_init,
86
	.wb_fini = &r100_wb_fini,
84
//   .wb_fini = &r100_wb_fini,
87
	.gart_enable = &r100_gart_enable,
85
	.gart_enable = &r100_gart_enable,
88
	.gart_disable = &r100_pci_gart_disable,
86
	.gart_disable = &r100_pci_gart_disable,
89
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
87
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
90
	.gart_set_page = &r100_pci_gart_set_page,
88
	.gart_set_page = &r100_pci_gart_set_page,
91
	.cp_init = &r100_cp_init,
89
	.cp_init = &r100_cp_init,
92
	.cp_fini = &r100_cp_fini,
90
//   .cp_fini = &r100_cp_fini,
93
	.cp_disable = &r100_cp_disable,
91
//   .cp_disable = &r100_cp_disable,
94
	.ring_start = &r100_ring_start,
92
	.ring_start = &r100_ring_start,
95
	.irq_set = &r100_irq_set,
93
//   .irq_set = &r100_irq_set,
96
	.irq_process = &r100_irq_process,
94
//   .irq_process = &r100_irq_process,
97
 //  .fence_ring_emit = &r100_fence_ring_emit,
95
 //  .fence_ring_emit = &r100_fence_ring_emit,
98
 //  .cs_parse = &r100_cs_parse,
96
 //  .cs_parse = &r100_cs_parse,
99
 //  .copy_blit = &r100_copy_blit,
97
 //  .copy_blit = &r100_copy_blit,
100
 //  .copy_dma = NULL,
98
 //  .copy_dma = NULL,
101
 //  .copy = &r100_copy_blit,
99
 //  .copy = &r100_copy_blit,
102
	.set_engine_clock = &radeon_legacy_set_engine_clock,
100
//   .set_engine_clock = &radeon_legacy_set_engine_clock,
103
	.set_memory_clock = NULL,
101
//   .set_memory_clock = NULL,
104
	.set_pcie_lanes = NULL,
102
//   .set_pcie_lanes = NULL,
Line 105... Line 103...
105
	.set_clock_gating = &radeon_legacy_set_clock_gating,
103
//   .set_clock_gating = &radeon_legacy_set_clock_gating,
106
};
104
};
Line 114... Line 112...
114
void r300_vram_info(struct radeon_device *rdev);
112
void r300_vram_info(struct radeon_device *rdev);
115
int r300_gpu_reset(struct radeon_device *rdev);
113
int r300_gpu_reset(struct radeon_device *rdev);
116
int r300_mc_init(struct radeon_device *rdev);
114
int r300_mc_init(struct radeon_device *rdev);
117
void r300_mc_fini(struct radeon_device *rdev);
115
void r300_mc_fini(struct radeon_device *rdev);
118
void r300_ring_start(struct radeon_device *rdev);
116
void r300_ring_start(struct radeon_device *rdev);
119
//void r300_fence_ring_emit(struct radeon_device *rdev,
117
void r300_fence_ring_emit(struct radeon_device *rdev,
120
//             struct radeon_fence *fence);
118
			  struct radeon_fence *fence);
121
//int r300_cs_parse(struct radeon_cs_parser *p);
119
int r300_cs_parse(struct radeon_cs_parser *p);
122
int r300_gart_enable(struct radeon_device *rdev);
120
int r300_gart_enable(struct radeon_device *rdev);
123
void rv370_pcie_gart_disable(struct radeon_device *rdev);
121
void rv370_pcie_gart_disable(struct radeon_device *rdev);
124
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
122
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
125
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
123
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
126
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
124
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
127
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
125
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
128
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
126
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
129
//int r300_copy_dma(struct radeon_device *rdev,
127
int r300_copy_dma(struct radeon_device *rdev,
130
//         uint64_t src_offset,
128
		  uint64_t src_offset,
131
//         uint64_t dst_offset,
129
		  uint64_t dst_offset,
132
//         unsigned num_pages,
130
		  unsigned num_pages,
133
//         struct radeon_fence *fence);
131
		  struct radeon_fence *fence);
Line 134... Line 132...
134
 
132
 
135
 
133
 
136
static struct radeon_asic r300_asic = {
134
static struct radeon_asic r300_asic = {
137
	.init = &r300_init,
135
	.init = &r300_init,
138
	.errata = &r300_errata,
136
	.errata = &r300_errata,
139
	.vram_info = &r300_vram_info,
137
	.vram_info = &r300_vram_info,
140
	.gpu_reset = &r300_gpu_reset,
138
	.gpu_reset = &r300_gpu_reset,
141
	.mc_init = &r300_mc_init,
139
	.mc_init = &r300_mc_init,
142
	.mc_fini = &r300_mc_fini,
140
	.mc_fini = &r300_mc_fini,
143
	.wb_init = &r100_wb_init,
141
//   .wb_init = &r100_wb_init,
144
	.wb_fini = &r100_wb_fini,
142
//   .wb_fini = &r100_wb_fini,
145
	.gart_enable = &r300_gart_enable,
143
	.gart_enable = &r300_gart_enable,
146
	.gart_disable = &r100_pci_gart_disable,
144
	.gart_disable = &r100_pci_gart_disable,
147
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
145
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
148
	.gart_set_page = &r100_pci_gart_set_page,
146
	.gart_set_page = &r100_pci_gart_set_page,
149
	.cp_init = &r100_cp_init,
147
	.cp_init = &r100_cp_init,
150
	.cp_fini = &r100_cp_fini,
148
//   .cp_fini = &r100_cp_fini,
151
	.cp_disable = &r100_cp_disable,
149
//   .cp_disable = &r100_cp_disable,
152
	.ring_start = &r300_ring_start,
150
	.ring_start = &r300_ring_start,
153
	.irq_set = &r100_irq_set,
151
//   .irq_set = &r100_irq_set,
154
	.irq_process = &r100_irq_process,
152
//   .irq_process = &r100_irq_process,
155
 //  .fence_ring_emit = &r300_fence_ring_emit,
153
 //  .fence_ring_emit = &r300_fence_ring_emit,
156
 //  .cs_parse = &r300_cs_parse,
154
 //  .cs_parse = &r300_cs_parse,
157
 //  .copy_blit = &r100_copy_blit,
155
 //  .copy_blit = &r100_copy_blit,
158
 //  .copy_dma = &r300_copy_dma,
156
 //  .copy_dma = &r300_copy_dma,
159
 //  .copy = &r100_copy_blit,
157
 //  .copy = &r100_copy_blit,
160
	.set_engine_clock = &radeon_legacy_set_engine_clock,
158
 //  .set_engine_clock = &radeon_legacy_set_engine_clock,
161
	.set_memory_clock = NULL,
159
 //  .set_memory_clock = NULL,
162
	.set_pcie_lanes = &rv370_set_pcie_lanes,
160
//   .set_pcie_lanes = &rv370_set_pcie_lanes,
Line -... Line 161...
-
 
161
//   .set_clock_gating = &radeon_legacy_set_clock_gating,
163
	.set_clock_gating = &radeon_legacy_set_clock_gating,
162
};
164
};
163
 
165
 
164
 
166
/*
165
/*
167
 * r420,r423,rv410
166
 * r420,r423,rv410
Line 175... Line 174...
175
	.errata = &r420_errata,
174
	.errata = &r420_errata,
176
	.vram_info = &r420_vram_info,
175
	.vram_info = &r420_vram_info,
177
	.gpu_reset = &r300_gpu_reset,
176
	.gpu_reset = &r300_gpu_reset,
178
	.mc_init = &r420_mc_init,
177
	.mc_init = &r420_mc_init,
179
	.mc_fini = &r420_mc_fini,
178
	.mc_fini = &r420_mc_fini,
180
	.wb_init = &r100_wb_init,
179
//   .wb_init = &r100_wb_init,
181
	.wb_fini = &r100_wb_fini,
180
//   .wb_fini = &r100_wb_fini,
182
	.gart_enable = &r300_gart_enable,
181
	.gart_enable = &r300_gart_enable,
183
	.gart_disable = &rv370_pcie_gart_disable,
182
	.gart_disable = &rv370_pcie_gart_disable,
184
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
183
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
185
	.gart_set_page = &rv370_pcie_gart_set_page,
184
	.gart_set_page = &rv370_pcie_gart_set_page,
186
	.cp_init = &r100_cp_init,
185
	.cp_init = &r100_cp_init,
187
	.cp_fini = &r100_cp_fini,
186
//   .cp_fini = &r100_cp_fini,
188
	.cp_disable = &r100_cp_disable,
187
//   .cp_disable = &r100_cp_disable,
189
	.ring_start = &r300_ring_start,
188
	.ring_start = &r300_ring_start,
190
	.irq_set = &r100_irq_set,
189
//   .irq_set = &r100_irq_set,
191
	.irq_process = &r100_irq_process,
190
//   .irq_process = &r100_irq_process,
192
//   .fence_ring_emit = &r300_fence_ring_emit,
191
//   .fence_ring_emit = &r300_fence_ring_emit,
193
//   .cs_parse = &r300_cs_parse,
192
//   .cs_parse = &r300_cs_parse,
194
//   .copy_blit = &r100_copy_blit,
193
//   .copy_blit = &r100_copy_blit,
195
//   .copy_dma = &r300_copy_dma,
194
//   .copy_dma = &r300_copy_dma,
196
//   .copy = &r100_copy_blit,
195
//   .copy = &r100_copy_blit,
197
	.set_engine_clock = &radeon_atom_set_engine_clock,
196
//   .set_engine_clock = &radeon_atom_set_engine_clock,
198
	.set_memory_clock = &radeon_atom_set_memory_clock,
197
//   .set_memory_clock = &radeon_atom_set_memory_clock,
199
	.set_pcie_lanes = &rv370_set_pcie_lanes,
198
//   .set_pcie_lanes = &rv370_set_pcie_lanes,
200
	.set_clock_gating = &radeon_atom_set_clock_gating,
199
//   .set_clock_gating = &radeon_atom_set_clock_gating,
201
};
200
};
Line 202... Line 201...
202
 
201
 
203
 
202
 
Line 219... Line 218...
219
	.errata = &rs400_errata,
218
	.errata = &rs400_errata,
220
	.vram_info = &rs400_vram_info,
219
	.vram_info = &rs400_vram_info,
221
	.gpu_reset = &r300_gpu_reset,
220
	.gpu_reset = &r300_gpu_reset,
222
	.mc_init = &rs400_mc_init,
221
	.mc_init = &rs400_mc_init,
223
	.mc_fini = &rs400_mc_fini,
222
	.mc_fini = &rs400_mc_fini,
224
	.wb_init = &r100_wb_init,
223
//   .wb_init = &r100_wb_init,
225
	.wb_fini = &r100_wb_fini,
224
//   .wb_fini = &r100_wb_fini,
226
	.gart_enable = &rs400_gart_enable,
225
	.gart_enable = &rs400_gart_enable,
227
	.gart_disable = &rs400_gart_disable,
226
	.gart_disable = &rs400_gart_disable,
228
	.gart_tlb_flush = &rs400_gart_tlb_flush,
227
	.gart_tlb_flush = &rs400_gart_tlb_flush,
229
	.gart_set_page = &rs400_gart_set_page,
228
	.gart_set_page = &rs400_gart_set_page,
230
	.cp_init = &r100_cp_init,
229
	.cp_init = &r100_cp_init,
231
	.cp_fini = &r100_cp_fini,
230
//   .cp_fini = &r100_cp_fini,
232
	.cp_disable = &r100_cp_disable,
231
//   .cp_disable = &r100_cp_disable,
233
	.ring_start = &r300_ring_start,
232
	.ring_start = &r300_ring_start,
234
	.irq_set = &r100_irq_set,
233
//   .irq_set = &r100_irq_set,
235
	.irq_process = &r100_irq_process,
234
//   .irq_process = &r100_irq_process,
236
//   .fence_ring_emit = &r300_fence_ring_emit,
235
//   .fence_ring_emit = &r300_fence_ring_emit,
237
//   .cs_parse = &r300_cs_parse,
236
//   .cs_parse = &r300_cs_parse,
238
//   .copy_blit = &r100_copy_blit,
237
//   .copy_blit = &r100_copy_blit,
239
//   .copy_dma = &r300_copy_dma,
238
//   .copy_dma = &r300_copy_dma,
240
//   .copy = &r100_copy_blit,
239
//   .copy = &r100_copy_blit,
241
	.set_engine_clock = &radeon_legacy_set_engine_clock,
240
//   .set_engine_clock = &radeon_legacy_set_engine_clock,
242
	.set_memory_clock = NULL,
241
//   .set_memory_clock = NULL,
243
	.set_pcie_lanes = NULL,
242
//   .set_pcie_lanes = NULL,
244
	.set_clock_gating = &radeon_legacy_set_clock_gating,
243
//   .set_clock_gating = &radeon_legacy_set_clock_gating,
245
};
244
};
Line 246... Line 245...
246
 
245
 
247
 
246
 
Line 257... Line 256...
257
void rs600_gart_disable(struct radeon_device *rdev);
256
void rs600_gart_disable(struct radeon_device *rdev);
258
void rs600_gart_tlb_flush(struct radeon_device *rdev);
257
void rs600_gart_tlb_flush(struct radeon_device *rdev);
259
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
258
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
260
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
259
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
261
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
260
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-
 
261
 
262
static struct radeon_asic rs600_asic = {
262
static struct radeon_asic rs600_asic = {
263
	.init = &r300_init,
263
	.init = &r300_init,
264
	.errata = &rs600_errata,
264
	.errata = &rs600_errata,
265
	.vram_info = &rs600_vram_info,
265
	.vram_info = &rs600_vram_info,
266
	.gpu_reset = &r300_gpu_reset,
266
	.gpu_reset = &r300_gpu_reset,
267
	.mc_init = &rs600_mc_init,
267
	.mc_init = &rs600_mc_init,
268
	.mc_fini = &rs600_mc_fini,
268
	.mc_fini = &rs600_mc_fini,
269
	.wb_init = &r100_wb_init,
269
//   .wb_init = &r100_wb_init,
270
	.wb_fini = &r100_wb_fini,
270
//   .wb_fini = &r100_wb_fini,
271
	.gart_enable = &rs600_gart_enable,
271
	.gart_enable = &rs600_gart_enable,
272
	.gart_disable = &rs600_gart_disable,
272
	.gart_disable = &rs600_gart_disable,
273
	.gart_tlb_flush = &rs600_gart_tlb_flush,
273
	.gart_tlb_flush = &rs600_gart_tlb_flush,
274
	.gart_set_page = &rs600_gart_set_page,
274
	.gart_set_page = &rs600_gart_set_page,
275
	.cp_init = &r100_cp_init,
275
	.cp_init = &r100_cp_init,
276
	.cp_fini = &r100_cp_fini,
276
//   .cp_fini = &r100_cp_fini,
277
	.cp_disable = &r100_cp_disable,
277
//   .cp_disable = &r100_cp_disable,
278
	.ring_start = &r300_ring_start,
278
	.ring_start = &r300_ring_start,
279
	.irq_set = &rs600_irq_set,
279
//   .irq_set = &rs600_irq_set,
280
	.irq_process = &r100_irq_process,
280
//   .irq_process = &r100_irq_process,
281
//   .fence_ring_emit = &r300_fence_ring_emit,
281
//   .fence_ring_emit = &r300_fence_ring_emit,
282
//   .cs_parse = &r300_cs_parse,
282
//   .cs_parse = &r300_cs_parse,
283
//   .copy_blit = &r100_copy_blit,
283
//   .copy_blit = &r100_copy_blit,
284
//   .copy_dma = &r300_copy_dma,
284
//   .copy_dma = &r300_copy_dma,
285
//   .copy = &r100_copy_blit,
285
//   .copy = &r100_copy_blit,
286
	.set_engine_clock = &radeon_atom_set_engine_clock,
286
//   .set_engine_clock = &radeon_atom_set_engine_clock,
287
	.set_memory_clock = &radeon_atom_set_memory_clock,
287
//   .set_memory_clock = &radeon_atom_set_memory_clock,
288
	.set_pcie_lanes = NULL,
288
//   .set_pcie_lanes = NULL,
289
	.set_clock_gating = &radeon_atom_set_clock_gating,
289
//   .set_clock_gating = &radeon_atom_set_clock_gating,
290
};
290
};
Line 291... Line 291...
291
 
291
 
292
 
292
 
Line 304... Line 304...
304
	.errata = &rs690_errata,
304
	.errata = &rs690_errata,
305
	.vram_info = &rs690_vram_info,
305
	.vram_info = &rs690_vram_info,
306
	.gpu_reset = &r300_gpu_reset,
306
	.gpu_reset = &r300_gpu_reset,
307
	.mc_init = &rs690_mc_init,
307
	.mc_init = &rs690_mc_init,
308
	.mc_fini = &rs690_mc_fini,
308
	.mc_fini = &rs690_mc_fini,
309
	.wb_init = &r100_wb_init,
309
//   .wb_init = &r100_wb_init,
310
	.wb_fini = &r100_wb_fini,
310
//   .wb_fini = &r100_wb_fini,
311
	.gart_enable = &rs400_gart_enable,
311
	.gart_enable = &rs400_gart_enable,
312
	.gart_disable = &rs400_gart_disable,
312
	.gart_disable = &rs400_gart_disable,
313
	.gart_tlb_flush = &rs400_gart_tlb_flush,
313
	.gart_tlb_flush = &rs400_gart_tlb_flush,
314
	.gart_set_page = &rs400_gart_set_page,
314
	.gart_set_page = &rs400_gart_set_page,
315
	.cp_init = &r100_cp_init,
315
	.cp_init = &r100_cp_init,
316
	.cp_fini = &r100_cp_fini,
316
//   .cp_fini = &r100_cp_fini,
317
	.cp_disable = &r100_cp_disable,
317
//   .cp_disable = &r100_cp_disable,
318
	.ring_start = &r300_ring_start,
318
	.ring_start = &r300_ring_start,
319
	.irq_set = &rs600_irq_set,
319
//   .irq_set = &rs600_irq_set,
320
	.irq_process = &r100_irq_process,
320
//   .irq_process = &r100_irq_process,
321
 //  .fence_ring_emit = &r300_fence_ring_emit,
321
 //  .fence_ring_emit = &r300_fence_ring_emit,
322
 //  .cs_parse = &r300_cs_parse,
322
 //  .cs_parse = &r300_cs_parse,
323
 //  .copy_blit = &r100_copy_blit,
323
 //  .copy_blit = &r100_copy_blit,
324
 //  .copy_dma = &r300_copy_dma,
324
 //  .copy_dma = &r300_copy_dma,
325
//   .copy = &r300_copy_dma,
325
//   .copy = &r300_copy_dma,
326
	.set_engine_clock = &radeon_atom_set_engine_clock,
326
//   .set_engine_clock = &radeon_atom_set_engine_clock,
327
	.set_memory_clock = &radeon_atom_set_memory_clock,
327
//   .set_memory_clock = &radeon_atom_set_memory_clock,
328
	.set_pcie_lanes = NULL,
328
//   .set_pcie_lanes = NULL,
329
	.set_clock_gating = &radeon_atom_set_clock_gating,
329
//   .set_clock_gating = &radeon_atom_set_clock_gating,
330
};
330
};
Line 331... Line -...
331
 
-
 
332
#endif
331
 
333
/*
332
/*
334
 * rv515
333
 * rv515
335
 */
334
 */
336
int rv515_init(struct radeon_device *rdev);
335
int rv515_init(struct radeon_device *rdev);
Line 343... Line 342...
343
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
342
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
344
void rv515_ring_start(struct radeon_device *rdev);
343
void rv515_ring_start(struct radeon_device *rdev);
345
uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
344
uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
346
void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
345
void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Line 347... Line 346...
347
 
346
 
348
/*
347
 
349
static struct radeon_asic rv515_asic = {
348
static struct radeon_asic rv515_asic = {
350
	.init = &rv515_init,
349
	.init = &rv515_init,
351
	.errata = &rv515_errata,
350
	.errata = &rv515_errata,
352
	.vram_info = &rv515_vram_info,
351
	.vram_info = &rv515_vram_info,
353
	.gpu_reset = &rv515_gpu_reset,
352
	.gpu_reset = &rv515_gpu_reset,
354
	.mc_init = &rv515_mc_init,
353
	.mc_init = &rv515_mc_init,
355
	.mc_fini = &rv515_mc_fini,
354
	.mc_fini = &rv515_mc_fini,
356
	.wb_init = &r100_wb_init,
355
//   .wb_init = &r100_wb_init,
357
	.wb_fini = &r100_wb_fini,
356
//   .wb_fini = &r100_wb_fini,
358
	.gart_enable = &r300_gart_enable,
357
	.gart_enable = &r300_gart_enable,
359
	.gart_disable = &rv370_pcie_gart_disable,
358
	.gart_disable = &rv370_pcie_gart_disable,
360
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
359
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
361
	.gart_set_page = &rv370_pcie_gart_set_page,
360
	.gart_set_page = &rv370_pcie_gart_set_page,
362
	.cp_init = &r100_cp_init,
361
	.cp_init = &r100_cp_init,
363
	.cp_fini = &r100_cp_fini,
362
//   .cp_fini = &r100_cp_fini,
364
	.cp_disable = &r100_cp_disable,
363
//   .cp_disable = &r100_cp_disable,
365
	.ring_start = &rv515_ring_start,
364
    .ring_start = &rv515_ring_start,
366
	.irq_set = &r100_irq_set,
365
//   .irq_set = &r100_irq_set,
367
	.irq_process = &r100_irq_process,
366
//   .irq_process = &r100_irq_process,
368
//   .fence_ring_emit = &r300_fence_ring_emit,
367
//   .fence_ring_emit = &r300_fence_ring_emit,
369
//   .cs_parse = &r300_cs_parse,
368
//   .cs_parse = &r300_cs_parse,
370
//   .copy_blit = &r100_copy_blit,
369
//   .copy_blit = &r100_copy_blit,
371
//   .copy_dma = &r300_copy_dma,
370
//   .copy_dma = &r300_copy_dma,
372
//   .copy = &r100_copy_blit,
371
//   .copy = &r100_copy_blit,
373
	.set_engine_clock = &radeon_atom_set_engine_clock,
372
//   .set_engine_clock = &radeon_atom_set_engine_clock,
374
	.set_memory_clock = &radeon_atom_set_memory_clock,
373
//   .set_memory_clock = &radeon_atom_set_memory_clock,
375
	.set_pcie_lanes = &rv370_set_pcie_lanes,
374
//   .set_pcie_lanes = &rv370_set_pcie_lanes,
376
	.set_clock_gating = &radeon_atom_set_clock_gating,
375
//   .set_clock_gating = &radeon_atom_set_clock_gating,
Line 377... Line -...
377
};
-
 
378
 
-
 
379
*/
-
 
380
 
-
 
381
 
-
 
382
int r300_gart_enable(struct radeon_device *rdev);
-
 
383
void rv370_pcie_gart_disable(struct radeon_device *rdev);
-
 
384
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
-
 
385
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
-
 
386
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
-
 
387
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-
 
Line 388... Line 376...
388
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
376
};
389
 
377
 
390
 
378
 
391
/*
379
/*