WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_asic.c



 
/*
 * ASIC

 */
 
static const struct radeon_asic_ring r100_gfx_ring = {
	.ib_execute = &r100_ring_ib_execute,
	.emit_fence = &r100_fence_ring_emit,
	.emit_semaphore = &r100_semaphore_ring_emit,

//		.pre_page_flip = &r100_pre_page_flip,
//		.page_flip = &r100_page_flip,
	},
};

 
static const struct radeon_asic_ring r300_gfx_ring = {
	.ib_execute = &r100_ring_ib_execute,
	.emit_fence = &r300_fence_ring_emit,
	.emit_semaphore = &r100_semaphore_ring_emit,
	.cs_parse = &r300_cs_parse,

	.get_rptr = &r100_gfx_get_rptr,
	.get_wptr = &r100_gfx_get_wptr,
	.set_wptr = &r100_gfx_set_wptr,
};

 
static const struct radeon_asic_ring rv515_gfx_ring = {
	.ib_execute = &r100_ring_ib_execute,
	.emit_fence = &r300_fence_ring_emit,
	.emit_semaphore = &r100_semaphore_ring_emit,
	.cs_parse = &r300_cs_parse,

//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rs600_page_flip,
	},
};

 
static const struct radeon_asic_ring r600_gfx_ring = {
	.ib_execute = &r600_ring_ib_execute,
	.emit_fence = &r600_fence_ring_emit,
	.emit_semaphore = &r600_semaphore_ring_emit,
	.cs_parse = &r600_cs_parse,

	.get_rptr = &r600_gfx_get_rptr,
	.get_wptr = &r600_gfx_get_wptr,
	.set_wptr = &r600_gfx_set_wptr,
};

 
static const struct radeon_asic_ring r600_dma_ring = {
	.ib_execute = &r600_dma_ring_ib_execute,
	.emit_fence = &r600_dma_fence_ring_emit,
	.emit_semaphore = &r600_dma_semaphore_ring_emit,
	.cs_parse = &r600_dma_cs_parse,

//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rs600_page_flip,
	},
};

 
static const struct radeon_asic_ring rv6xx_uvd_ring = {
	.ib_execute = &uvd_v1_0_ib_execute,
	.emit_fence = &uvd_v1_0_fence_emit,
	.emit_semaphore = &uvd_v1_0_semaphore_emit,
	.cs_parse = &radeon_uvd_cs_parse,

//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rs600_page_flip,
	},
};

 
static const struct radeon_asic_ring rv770_uvd_ring = {
	.ib_execute = &uvd_v1_0_ib_execute,
	.emit_fence = &uvd_v2_2_fence_emit,
	.emit_semaphore = &uvd_v2_2_semaphore_emit,
	.cs_parse = &radeon_uvd_cs_parse,

//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rv770_page_flip,
	},
};

 
static const struct radeon_asic_ring evergreen_gfx_ring = {
	.ib_execute = &evergreen_ring_ib_execute,
	.emit_fence = &r600_fence_ring_emit,
	.emit_semaphore = &r600_semaphore_ring_emit,
	.cs_parse = &evergreen_cs_parse,

	.get_rptr = &r600_gfx_get_rptr,
	.get_wptr = &r600_gfx_get_wptr,
	.set_wptr = &r600_gfx_set_wptr,
};

 
static const struct radeon_asic_ring evergreen_dma_ring = {
	.ib_execute = &evergreen_dma_ring_ib_execute,
	.emit_fence = &evergreen_dma_fence_ring_emit,
	.emit_semaphore = &r600_dma_semaphore_ring_emit,
	.cs_parse = &evergreen_dma_cs_parse,

//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},
};

 
static const struct radeon_asic_ring cayman_gfx_ring = {
	.ib_execute = &cayman_ring_ib_execute,
	.ib_parse = &evergreen_ib_parse,
	.emit_fence = &cayman_fence_ring_emit,
	.emit_semaphore = &r600_semaphore_ring_emit,

	.get_rptr = &cayman_gfx_get_rptr,
	.get_wptr = &cayman_gfx_get_wptr,
	.set_wptr = &cayman_gfx_set_wptr,
};

 
static const struct radeon_asic_ring cayman_dma_ring = {
	.ib_execute = &cayman_dma_ring_ib_execute,
	.ib_parse = &evergreen_dma_ib_parse,
	.emit_fence = &evergreen_dma_fence_ring_emit,
	.emit_semaphore = &r600_dma_semaphore_ring_emit,

	.get_rptr = &cayman_dma_get_rptr,
	.get_wptr = &cayman_dma_get_wptr,
	.set_wptr = &cayman_dma_set_wptr
};

 
static const struct radeon_asic_ring cayman_uvd_ring = {
	.ib_execute = &uvd_v1_0_ib_execute,
	.emit_fence = &uvd_v2_2_fence_emit,
	.emit_semaphore = &uvd_v3_1_semaphore_emit,
	.cs_parse = &radeon_uvd_cs_parse,

//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},
};

 
static const struct radeon_asic_ring trinity_vce_ring = {
	.ib_execute = &radeon_vce_ib_execute,
	.emit_fence = &radeon_vce_fence_emit,
	.emit_semaphore = &radeon_vce_semaphore_emit,
	.cs_parse = &radeon_vce_cs_parse,

//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},
};

 
static const struct radeon_asic_ring si_gfx_ring = {
	.ib_execute = &si_ring_ib_execute,
	.ib_parse = &si_ib_parse,
	.emit_fence = &si_fence_ring_emit,
	.emit_semaphore = &r600_semaphore_ring_emit,

	.get_rptr = &cayman_gfx_get_rptr,
	.get_wptr = &cayman_gfx_get_wptr,
	.set_wptr = &cayman_gfx_set_wptr,
};

 
static const struct radeon_asic_ring si_dma_ring = {
	.ib_execute = &cayman_dma_ring_ib_execute,
	.ib_parse = &evergreen_dma_ib_parse,
	.emit_fence = &evergreen_dma_fence_ring_emit,
	.emit_semaphore = &r600_dma_semaphore_ring_emit,

//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},
};

 
static const struct radeon_asic_ring ci_gfx_ring = {
	.ib_execute = &cik_ring_ib_execute,
	.ib_parse = &cik_ib_parse,
	.emit_fence = &cik_fence_gfx_ring_emit,
	.emit_semaphore = &cik_semaphore_ring_emit,

	.get_rptr = &cik_gfx_get_rptr,
	.get_wptr = &cik_gfx_get_wptr,
	.set_wptr = &cik_gfx_set_wptr,
};

 
static const struct radeon_asic_ring ci_cp_ring = {
	.ib_execute = &cik_ring_ib_execute,
	.ib_parse = &cik_ib_parse,
	.emit_fence = &cik_fence_compute_ring_emit,
	.emit_semaphore = &cik_semaphore_ring_emit,

	.get_rptr = &cik_compute_get_rptr,
	.get_wptr = &cik_compute_get_wptr,
	.set_wptr = &cik_compute_set_wptr,
};

 
static const struct radeon_asic_ring ci_dma_ring = {
	.ib_execute = &cik_sdma_ring_ib_execute,
	.ib_parse = &cik_ib_parse,
	.emit_fence = &cik_sdma_fence_ring_emit,
	.emit_semaphore = &cik_sdma_semaphore_ring_emit,

	.get_rptr = &cik_sdma_get_rptr,
	.get_wptr = &cik_sdma_get_wptr,
	.set_wptr = &cik_sdma_set_wptr,
};

 
static const struct radeon_asic_ring ci_vce_ring = {
	.ib_execute = &radeon_vce_ib_execute,
	.emit_fence = &radeon_vce_fence_emit,
	.emit_semaphore = &radeon_vce_semaphore_emit,
	.cs_parse = &radeon_vce_cs_parse,

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 6321 → 6938

Rev 6321		Rev 6938
Line 177...		Line 177...
177		177
178	/*	178	/*
179	* ASIC	179	* ASIC
Line 180...		Line 180...
180	*/	180	*/
181		181
182	static struct radeon_asic_ring r100_gfx_ring = {	182	static const struct radeon_asic_ring r100_gfx_ring = {
183	.ib_execute = &r100_ring_ib_execute,	183	.ib_execute = &r100_ring_ib_execute,
184	.emit_fence = &r100_fence_ring_emit,	184	.emit_fence = &r100_fence_ring_emit,
185	.emit_semaphore = &r100_semaphore_ring_emit,	185	.emit_semaphore = &r100_semaphore_ring_emit,
Line 326...		Line 326...
326	// .pre_page_flip = &r100_pre_page_flip,	326	// .pre_page_flip = &r100_pre_page_flip,
327	// .page_flip = &r100_page_flip,	327	// .page_flip = &r100_page_flip,
328	},	328	},
329	};	329	};
Line 330...		Line 330...
330		330
331	static struct radeon_asic_ring r300_gfx_ring = {	331	static const struct radeon_asic_ring r300_gfx_ring = {
332	.ib_execute = &r100_ring_ib_execute,	332	.ib_execute = &r100_ring_ib_execute,
333	.emit_fence = &r300_fence_ring_emit,	333	.emit_fence = &r300_fence_ring_emit,
334	.emit_semaphore = &r100_semaphore_ring_emit,	334	.emit_semaphore = &r100_semaphore_ring_emit,
335	.cs_parse = &r300_cs_parse,	335	.cs_parse = &r300_cs_parse,
Line 340...		Line 340...
340	.get_rptr = &r100_gfx_get_rptr,	340	.get_rptr = &r100_gfx_get_rptr,
341	.get_wptr = &r100_gfx_get_wptr,	341	.get_wptr = &r100_gfx_get_wptr,
342	.set_wptr = &r100_gfx_set_wptr,	342	.set_wptr = &r100_gfx_set_wptr,
343	};	343	};
Line 344...		Line 344...
344		344
345	static struct radeon_asic_ring rv515_gfx_ring = {	345	static const struct radeon_asic_ring rv515_gfx_ring = {
346	.ib_execute = &r100_ring_ib_execute,	346	.ib_execute = &r100_ring_ib_execute,
347	.emit_fence = &r300_fence_ring_emit,	347	.emit_fence = &r300_fence_ring_emit,
348	.emit_semaphore = &r100_semaphore_ring_emit,	348	.emit_semaphore = &r100_semaphore_ring_emit,
349	.cs_parse = &r300_cs_parse,	349	.cs_parse = &r300_cs_parse,
Line 898...		Line 898...
898	// .pre_page_flip = &rs600_pre_page_flip,	898	// .pre_page_flip = &rs600_pre_page_flip,
899	// .page_flip = &rs600_page_flip,	899	// .page_flip = &rs600_page_flip,
900	},	900	},
901	};	901	};
Line 902...		Line 902...
902		902
903	static struct radeon_asic_ring r600_gfx_ring = {	903	static const struct radeon_asic_ring r600_gfx_ring = {
904	.ib_execute = &r600_ring_ib_execute,	904	.ib_execute = &r600_ring_ib_execute,
905	.emit_fence = &r600_fence_ring_emit,	905	.emit_fence = &r600_fence_ring_emit,
906	.emit_semaphore = &r600_semaphore_ring_emit,	906	.emit_semaphore = &r600_semaphore_ring_emit,
907	.cs_parse = &r600_cs_parse,	907	.cs_parse = &r600_cs_parse,
Line 911...		Line 911...
911	.get_rptr = &r600_gfx_get_rptr,	911	.get_rptr = &r600_gfx_get_rptr,
912	.get_wptr = &r600_gfx_get_wptr,	912	.get_wptr = &r600_gfx_get_wptr,
913	.set_wptr = &r600_gfx_set_wptr,	913	.set_wptr = &r600_gfx_set_wptr,
914	};	914	};
Line 915...		Line 915...
915		915
916	static struct radeon_asic_ring r600_dma_ring = {	916	static const struct radeon_asic_ring r600_dma_ring = {
917	.ib_execute = &r600_dma_ring_ib_execute,	917	.ib_execute = &r600_dma_ring_ib_execute,
918	.emit_fence = &r600_dma_fence_ring_emit,	918	.emit_fence = &r600_dma_fence_ring_emit,
919	.emit_semaphore = &r600_dma_semaphore_ring_emit,	919	.emit_semaphore = &r600_dma_semaphore_ring_emit,
920	.cs_parse = &r600_dma_cs_parse,	920	.cs_parse = &r600_dma_cs_parse,
Line 996...		Line 996...
996	// .pre_page_flip = &rs600_pre_page_flip,	996	// .pre_page_flip = &rs600_pre_page_flip,
997	// .page_flip = &rs600_page_flip,	997	// .page_flip = &rs600_page_flip,
998	},	998	},
999	};	999	};
Line 1000...		Line 1000...
1000		1000
1001	static struct radeon_asic_ring rv6xx_uvd_ring = {	1001	static const struct radeon_asic_ring rv6xx_uvd_ring = {
1002	.ib_execute = &uvd_v1_0_ib_execute,	1002	.ib_execute = &uvd_v1_0_ib_execute,
1003	.emit_fence = &uvd_v1_0_fence_emit,	1003	.emit_fence = &uvd_v1_0_fence_emit,
1004	.emit_semaphore = &uvd_v1_0_semaphore_emit,	1004	.emit_semaphore = &uvd_v1_0_semaphore_emit,
1005	.cs_parse = &radeon_uvd_cs_parse,	1005	.cs_parse = &radeon_uvd_cs_parse,
Line 1195...		Line 1195...
1195	// .pre_page_flip = &rs600_pre_page_flip,	1195	// .pre_page_flip = &rs600_pre_page_flip,
1196	// .page_flip = &rs600_page_flip,	1196	// .page_flip = &rs600_page_flip,
1197	},	1197	},
1198	};	1198	};
Line 1199...		Line 1199...
1199		1199
1200	static struct radeon_asic_ring rv770_uvd_ring = {	1200	static const struct radeon_asic_ring rv770_uvd_ring = {
1201	.ib_execute = &uvd_v1_0_ib_execute,	1201	.ib_execute = &uvd_v1_0_ib_execute,
1202	.emit_fence = &uvd_v2_2_fence_emit,	1202	.emit_fence = &uvd_v2_2_fence_emit,
1203	.emit_semaphore = &uvd_v2_2_semaphore_emit,	1203	.emit_semaphore = &uvd_v2_2_semaphore_emit,
1204	.cs_parse = &radeon_uvd_cs_parse,	1204	.cs_parse = &radeon_uvd_cs_parse,
Line 1302...		Line 1302...
1302	// .pre_page_flip = &rs600_pre_page_flip,	1302	// .pre_page_flip = &rs600_pre_page_flip,
1303	// .page_flip = &rv770_page_flip,	1303	// .page_flip = &rv770_page_flip,
1304	},	1304	},
1305	};	1305	};
Line 1306...		Line 1306...
1306		1306
1307	static struct radeon_asic_ring evergreen_gfx_ring = {	1307	static const struct radeon_asic_ring evergreen_gfx_ring = {
1308	.ib_execute = &evergreen_ring_ib_execute,	1308	.ib_execute = &evergreen_ring_ib_execute,
1309	.emit_fence = &r600_fence_ring_emit,	1309	.emit_fence = &r600_fence_ring_emit,
1310	.emit_semaphore = &r600_semaphore_ring_emit,	1310	.emit_semaphore = &r600_semaphore_ring_emit,
1311	.cs_parse = &evergreen_cs_parse,	1311	.cs_parse = &evergreen_cs_parse,
Line 1315...		Line 1315...
1315	.get_rptr = &r600_gfx_get_rptr,	1315	.get_rptr = &r600_gfx_get_rptr,
1316	.get_wptr = &r600_gfx_get_wptr,	1316	.get_wptr = &r600_gfx_get_wptr,
1317	.set_wptr = &r600_gfx_set_wptr,	1317	.set_wptr = &r600_gfx_set_wptr,
1318	};	1318	};
Line 1319...		Line 1319...
1319		1319
1320	static struct radeon_asic_ring evergreen_dma_ring = {	1320	static const struct radeon_asic_ring evergreen_dma_ring = {
1321	.ib_execute = &evergreen_dma_ring_ib_execute,	1321	.ib_execute = &evergreen_dma_ring_ib_execute,
1322	.emit_fence = &evergreen_dma_fence_ring_emit,	1322	.emit_fence = &evergreen_dma_fence_ring_emit,
1323	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1323	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1324	.cs_parse = &evergreen_dma_cs_parse,	1324	.cs_parse = &evergreen_dma_cs_parse,
Line 1607...		Line 1607...
1607	// .pre_page_flip = &evergreen_pre_page_flip,	1607	// .pre_page_flip = &evergreen_pre_page_flip,
1608	// .page_flip = &evergreen_page_flip,	1608	// .page_flip = &evergreen_page_flip,
1609	},	1609	},
1610	};	1610	};
Line 1611...		Line 1611...
1611		1611
1612	static struct radeon_asic_ring cayman_gfx_ring = {	1612	static const struct radeon_asic_ring cayman_gfx_ring = {
1613	.ib_execute = &cayman_ring_ib_execute,	1613	.ib_execute = &cayman_ring_ib_execute,
1614	.ib_parse = &evergreen_ib_parse,	1614	.ib_parse = &evergreen_ib_parse,
1615	.emit_fence = &cayman_fence_ring_emit,	1615	.emit_fence = &cayman_fence_ring_emit,
1616	.emit_semaphore = &r600_semaphore_ring_emit,	1616	.emit_semaphore = &r600_semaphore_ring_emit,
Line 1622...		Line 1622...
1622	.get_rptr = &cayman_gfx_get_rptr,	1622	.get_rptr = &cayman_gfx_get_rptr,
1623	.get_wptr = &cayman_gfx_get_wptr,	1623	.get_wptr = &cayman_gfx_get_wptr,
1624	.set_wptr = &cayman_gfx_set_wptr,	1624	.set_wptr = &cayman_gfx_set_wptr,
1625	};	1625	};
Line 1626...		Line 1626...
1626		1626
1627	static struct radeon_asic_ring cayman_dma_ring = {	1627	static const struct radeon_asic_ring cayman_dma_ring = {
1628	.ib_execute = &cayman_dma_ring_ib_execute,	1628	.ib_execute = &cayman_dma_ring_ib_execute,
1629	.ib_parse = &evergreen_dma_ib_parse,	1629	.ib_parse = &evergreen_dma_ib_parse,
1630	.emit_fence = &evergreen_dma_fence_ring_emit,	1630	.emit_fence = &evergreen_dma_fence_ring_emit,
1631	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1631	.emit_semaphore = &r600_dma_semaphore_ring_emit,
Line 1637...		Line 1637...
1637	.get_rptr = &cayman_dma_get_rptr,	1637	.get_rptr = &cayman_dma_get_rptr,
1638	.get_wptr = &cayman_dma_get_wptr,	1638	.get_wptr = &cayman_dma_get_wptr,
1639	.set_wptr = &cayman_dma_set_wptr	1639	.set_wptr = &cayman_dma_set_wptr
1640	};	1640	};
Line 1641...		Line 1641...
1641		1641
1642	static struct radeon_asic_ring cayman_uvd_ring = {	1642	static const struct radeon_asic_ring cayman_uvd_ring = {
1643	.ib_execute = &uvd_v1_0_ib_execute,	1643	.ib_execute = &uvd_v1_0_ib_execute,
1644	.emit_fence = &uvd_v2_2_fence_emit,	1644	.emit_fence = &uvd_v2_2_fence_emit,
1645	.emit_semaphore = &uvd_v3_1_semaphore_emit,	1645	.emit_semaphore = &uvd_v3_1_semaphore_emit,
1646	.cs_parse = &radeon_uvd_cs_parse,	1646	.cs_parse = &radeon_uvd_cs_parse,
Line 1755...		Line 1755...
1755	// .pre_page_flip = &evergreen_pre_page_flip,	1755	// .pre_page_flip = &evergreen_pre_page_flip,
1756	// .page_flip = &evergreen_page_flip,	1756	// .page_flip = &evergreen_page_flip,
1757	},	1757	},
1758	};	1758	};
Line 1759...		Line 1759...
1759		1759
1760	static struct radeon_asic_ring trinity_vce_ring = {	1760	static const struct radeon_asic_ring trinity_vce_ring = {
1761	.ib_execute = &radeon_vce_ib_execute,	1761	.ib_execute = &radeon_vce_ib_execute,
1762	.emit_fence = &radeon_vce_fence_emit,	1762	.emit_fence = &radeon_vce_fence_emit,
1763	.emit_semaphore = &radeon_vce_semaphore_emit,	1763	.emit_semaphore = &radeon_vce_semaphore_emit,
1764	.cs_parse = &radeon_vce_cs_parse,	1764	.cs_parse = &radeon_vce_cs_parse,
Line 1876...		Line 1876...
1876	// .pre_page_flip = &evergreen_pre_page_flip,	1876	// .pre_page_flip = &evergreen_pre_page_flip,
1877	// .page_flip = &evergreen_page_flip,	1877	// .page_flip = &evergreen_page_flip,
1878	},	1878	},
1879	};	1879	};
Line 1880...		Line 1880...
1880		1880
1881	static struct radeon_asic_ring si_gfx_ring = {	1881	static const struct radeon_asic_ring si_gfx_ring = {
1882	.ib_execute = &si_ring_ib_execute,	1882	.ib_execute = &si_ring_ib_execute,
1883	.ib_parse = &si_ib_parse,	1883	.ib_parse = &si_ib_parse,
1884	.emit_fence = &si_fence_ring_emit,	1884	.emit_fence = &si_fence_ring_emit,
1885	.emit_semaphore = &r600_semaphore_ring_emit,	1885	.emit_semaphore = &r600_semaphore_ring_emit,
Line 1891...		Line 1891...
1891	.get_rptr = &cayman_gfx_get_rptr,	1891	.get_rptr = &cayman_gfx_get_rptr,
1892	.get_wptr = &cayman_gfx_get_wptr,	1892	.get_wptr = &cayman_gfx_get_wptr,
1893	.set_wptr = &cayman_gfx_set_wptr,	1893	.set_wptr = &cayman_gfx_set_wptr,
1894	};	1894	};
Line 1895...		Line 1895...
1895		1895
1896	static struct radeon_asic_ring si_dma_ring = {	1896	static const struct radeon_asic_ring si_dma_ring = {
1897	.ib_execute = &cayman_dma_ring_ib_execute,	1897	.ib_execute = &cayman_dma_ring_ib_execute,
1898	.ib_parse = &evergreen_dma_ib_parse,	1898	.ib_parse = &evergreen_dma_ib_parse,
1899	.emit_fence = &evergreen_dma_fence_ring_emit,	1899	.emit_fence = &evergreen_dma_fence_ring_emit,
1900	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1900	.emit_semaphore = &r600_dma_semaphore_ring_emit,
Line 2018...		Line 2018...
2018	// .pre_page_flip = &evergreen_pre_page_flip,	2018	// .pre_page_flip = &evergreen_pre_page_flip,
2019	// .page_flip = &evergreen_page_flip,	2019	// .page_flip = &evergreen_page_flip,
2020	},	2020	},
2021	};	2021	};
Line 2022...		Line 2022...
2022		2022
2023	static struct radeon_asic_ring ci_gfx_ring = {	2023	static const struct radeon_asic_ring ci_gfx_ring = {
2024	.ib_execute = &cik_ring_ib_execute,	2024	.ib_execute = &cik_ring_ib_execute,
2025	.ib_parse = &cik_ib_parse,	2025	.ib_parse = &cik_ib_parse,
2026	.emit_fence = &cik_fence_gfx_ring_emit,	2026	.emit_fence = &cik_fence_gfx_ring_emit,
2027	.emit_semaphore = &cik_semaphore_ring_emit,	2027	.emit_semaphore = &cik_semaphore_ring_emit,
Line 2033...		Line 2033...
2033	.get_rptr = &cik_gfx_get_rptr,	2033	.get_rptr = &cik_gfx_get_rptr,
2034	.get_wptr = &cik_gfx_get_wptr,	2034	.get_wptr = &cik_gfx_get_wptr,
2035	.set_wptr = &cik_gfx_set_wptr,	2035	.set_wptr = &cik_gfx_set_wptr,
2036	};	2036	};
Line 2037...		Line 2037...
2037		2037
2038	static struct radeon_asic_ring ci_cp_ring = {	2038	static const struct radeon_asic_ring ci_cp_ring = {
2039	.ib_execute = &cik_ring_ib_execute,	2039	.ib_execute = &cik_ring_ib_execute,
2040	.ib_parse = &cik_ib_parse,	2040	.ib_parse = &cik_ib_parse,
2041	.emit_fence = &cik_fence_compute_ring_emit,	2041	.emit_fence = &cik_fence_compute_ring_emit,
2042	.emit_semaphore = &cik_semaphore_ring_emit,	2042	.emit_semaphore = &cik_semaphore_ring_emit,
Line 2048...		Line 2048...
2048	.get_rptr = &cik_compute_get_rptr,	2048	.get_rptr = &cik_compute_get_rptr,
2049	.get_wptr = &cik_compute_get_wptr,	2049	.get_wptr = &cik_compute_get_wptr,
2050	.set_wptr = &cik_compute_set_wptr,	2050	.set_wptr = &cik_compute_set_wptr,
2051	};	2051	};
Line 2052...		Line 2052...
2052		2052
2053	static struct radeon_asic_ring ci_dma_ring = {	2053	static const struct radeon_asic_ring ci_dma_ring = {
2054	.ib_execute = &cik_sdma_ring_ib_execute,	2054	.ib_execute = &cik_sdma_ring_ib_execute,
2055	.ib_parse = &cik_ib_parse,	2055	.ib_parse = &cik_ib_parse,
2056	.emit_fence = &cik_sdma_fence_ring_emit,	2056	.emit_fence = &cik_sdma_fence_ring_emit,
2057	.emit_semaphore = &cik_sdma_semaphore_ring_emit,	2057	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
Line 2063...		Line 2063...
2063	.get_rptr = &cik_sdma_get_rptr,	2063	.get_rptr = &cik_sdma_get_rptr,
2064	.get_wptr = &cik_sdma_get_wptr,	2064	.get_wptr = &cik_sdma_get_wptr,
2065	.set_wptr = &cik_sdma_set_wptr,	2065	.set_wptr = &cik_sdma_set_wptr,
2066	};	2066	};
Line 2067...		Line 2067...
2067		2067
2068	static struct radeon_asic_ring ci_vce_ring = {	2068	static const struct radeon_asic_ring ci_vce_ring = {
2069	.ib_execute = &radeon_vce_ib_execute,	2069	.ib_execute = &radeon_vce_ib_execute,
2070	.emit_fence = &radeon_vce_fence_emit,	2070	.emit_fence = &radeon_vce_fence_emit,
2071	.emit_semaphore = &radeon_vce_semaphore_emit,	2071	.emit_semaphore = &radeon_vce_semaphore_emit,
2072	.cs_parse = &radeon_vce_cs_parse,	2072	.cs_parse = &radeon_vce_cs_parse,