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| Rev 2997 | Rev 3120 | ||
|---|---|---|---|
| Line 683... | Line 683... | ||
| 683 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
683 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
| 684 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
684 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 685 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
685 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 686 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
686 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
| 687 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
687 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
| 688 | // .get_pcie_lanes = NULL, |
688 | .get_pcie_lanes = NULL, |
| 689 | // .set_pcie_lanes = NULL, |
689 | .set_pcie_lanes = NULL, |
| 690 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
690 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
| 691 | }, |
691 | }, |
| 692 | .pflip = { |
692 | .pflip = { |
| 693 | // .pre_page_flip = &rs600_pre_page_flip, |
693 | // .pre_page_flip = &rs600_pre_page_flip, |
| 694 | // .page_flip = &rs600_page_flip, |
694 | // .page_flip = &rs600_page_flip, |
| Line 759... | Line 759... | ||
| 759 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
759 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
| 760 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
760 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 761 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
761 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 762 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
762 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
| 763 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
763 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
| 764 | // .get_pcie_lanes = NULL, |
764 | .get_pcie_lanes = NULL, |
| 765 | // .set_pcie_lanes = NULL, |
765 | .set_pcie_lanes = NULL, |
| 766 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
766 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
| 767 | }, |
767 | }, |
| 768 | .pflip = { |
768 | .pflip = { |
| 769 | // .pre_page_flip = &rs600_pre_page_flip, |
769 | // .pre_page_flip = &rs600_pre_page_flip, |
| 770 | // .page_flip = &rs600_page_flip, |
770 | // .page_flip = &rs600_page_flip, |
| Line 988... | Line 988... | ||
| 988 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
988 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 989 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
989 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
| 990 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
990 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
| 991 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
991 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
| 992 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
992 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
| 993 | // .set_clock_gating = NULL, |
993 | .set_clock_gating = NULL, |
| 994 | }, |
994 | }, |
| 995 | .pflip = { |
995 | .pflip = { |
| 996 | // .pre_page_flip = &rs600_pre_page_flip, |
996 | // .pre_page_flip = &rs600_pre_page_flip, |
| 997 | // .page_flip = &rs600_page_flip, |
997 | // .page_flip = &rs600_page_flip, |
| 998 | // .post_page_flip = &rs600_post_page_flip, |
998 | // .post_page_flip = &rs600_post_page_flip, |
| Line 1059... | Line 1059... | ||
| 1059 | // .finish = &rs600_pm_finish, |
1059 | // .finish = &rs600_pm_finish, |
| 1060 | // .init_profile = &rs780_pm_init_profile, |
1060 | // .init_profile = &rs780_pm_init_profile, |
| 1061 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1061 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1062 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1062 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1063 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1063 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1064 | // .get_memory_clock = NULL, |
1064 | .get_memory_clock = NULL, |
| 1065 | // .set_memory_clock = NULL, |
1065 | .set_memory_clock = NULL, |
| 1066 | // .get_pcie_lanes = NULL, |
1066 | .get_pcie_lanes = NULL, |
| 1067 | // .set_pcie_lanes = NULL, |
1067 | .set_pcie_lanes = NULL, |
| 1068 | // .set_clock_gating = NULL, |
1068 | .set_clock_gating = NULL, |
| 1069 | }, |
1069 | }, |
| 1070 | .pflip = { |
1070 | .pflip = { |
| 1071 | // .pre_page_flip = &rs600_pre_page_flip, |
1071 | // .pre_page_flip = &rs600_pre_page_flip, |
| 1072 | // .page_flip = &rs600_page_flip, |
1072 | // .page_flip = &rs600_page_flip, |
| 1073 | // .post_page_flip = &rs600_post_page_flip, |
1073 | // .post_page_flip = &rs600_post_page_flip, |
| Line 1284... | Line 1284... | ||
| 1284 | // .finish = &evergreen_pm_finish, |
1284 | // .finish = &evergreen_pm_finish, |
| 1285 | // .init_profile = &sumo_pm_init_profile, |
1285 | // .init_profile = &sumo_pm_init_profile, |
| 1286 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1286 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1287 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1287 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1288 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1288 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1289 | // .get_memory_clock = NULL, |
1289 | .get_memory_clock = NULL, |
| 1290 | // .set_memory_clock = NULL, |
1290 | .set_memory_clock = NULL, |
| 1291 | // .get_pcie_lanes = NULL, |
1291 | .get_pcie_lanes = NULL, |
| 1292 | // .set_pcie_lanes = NULL, |
1292 | .set_pcie_lanes = NULL, |
| 1293 | // .set_clock_gating = NULL, |
1293 | .set_clock_gating = NULL, |
| 1294 | }, |
1294 | }, |
| 1295 | .pflip = { |
1295 | .pflip = { |
| 1296 | // .pre_page_flip = &evergreen_pre_page_flip, |
1296 | // .pre_page_flip = &evergreen_pre_page_flip, |
| 1297 | // .page_flip = &evergreen_page_flip, |
1297 | // .page_flip = &evergreen_page_flip, |
| 1298 | // .post_page_flip = &evergreen_post_page_flip, |
1298 | // .post_page_flip = &evergreen_post_page_flip, |
| Line 1361... | Line 1361... | ||
| 1361 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1361 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1362 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1362 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1363 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1363 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1364 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1364 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1365 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1365 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1366 | // .get_pcie_lanes = NULL, |
1366 | .get_pcie_lanes = NULL, |
| 1367 | // .set_pcie_lanes = NULL, |
1367 | .set_pcie_lanes = NULL, |
| 1368 | // .set_clock_gating = NULL, |
1368 | .set_clock_gating = NULL, |
| 1369 | }, |
1369 | }, |
| 1370 | .pflip = { |
1370 | .pflip = { |
| 1371 | // .pre_page_flip = &evergreen_pre_page_flip, |
1371 | // .pre_page_flip = &evergreen_pre_page_flip, |
| 1372 | // .page_flip = &evergreen_page_flip, |
1372 | // .page_flip = &evergreen_page_flip, |
| 1373 | // .post_page_flip = &evergreen_post_page_flip, |
1373 | // .post_page_flip = &evergreen_post_page_flip, |
| Line 1466... | Line 1466... | ||
| 1466 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1466 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1467 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1467 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1468 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1468 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1469 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1469 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1470 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1470 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1471 | // .get_pcie_lanes = NULL, |
1471 | .get_pcie_lanes = NULL, |
| 1472 | // .set_pcie_lanes = NULL, |
1472 | .set_pcie_lanes = NULL, |
| 1473 | // .set_clock_gating = NULL, |
1473 | .set_clock_gating = NULL, |
| 1474 | }, |
1474 | }, |
| 1475 | .pflip = { |
1475 | .pflip = { |
| 1476 | // .pre_page_flip = &evergreen_pre_page_flip, |
1476 | // .pre_page_flip = &evergreen_pre_page_flip, |
| 1477 | // .page_flip = &evergreen_page_flip, |
1477 | // .page_flip = &evergreen_page_flip, |
| 1478 | // .post_page_flip = &evergreen_post_page_flip, |
1478 | // .post_page_flip = &evergreen_post_page_flip, |
| Line 1569... | Line 1569... | ||
| 1569 | // .finish = &evergreen_pm_finish, |
1569 | // .finish = &evergreen_pm_finish, |
| 1570 | // .init_profile = &sumo_pm_init_profile, |
1570 | // .init_profile = &sumo_pm_init_profile, |
| 1571 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1571 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1572 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1572 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1573 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1573 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1574 | // .get_memory_clock = NULL, |
1574 | .get_memory_clock = NULL, |
| 1575 | // .set_memory_clock = NULL, |
1575 | .set_memory_clock = NULL, |
| 1576 | // .get_pcie_lanes = NULL, |
1576 | .get_pcie_lanes = NULL, |
| 1577 | // .set_pcie_lanes = NULL, |
1577 | .set_pcie_lanes = NULL, |
| 1578 | // .set_clock_gating = NULL, |
1578 | .set_clock_gating = NULL, |
| 1579 | }, |
1579 | }, |
| 1580 | .pflip = { |
1580 | .pflip = { |
| 1581 | // .pre_page_flip = &evergreen_pre_page_flip, |
1581 | // .pre_page_flip = &evergreen_pre_page_flip, |
| 1582 | // .page_flip = &evergreen_page_flip, |
1582 | // .page_flip = &evergreen_page_flip, |
| 1583 | // .post_page_flip = &evergreen_post_page_flip, |
1583 | // .post_page_flip = &evergreen_post_page_flip, |
| Line 1608... | Line 1608... | ||
| 1608 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1608 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1609 | .ib_execute = &si_ring_ib_execute, |
1609 | .ib_execute = &si_ring_ib_execute, |
| 1610 | // .ib_parse = &si_ib_parse, |
1610 | // .ib_parse = &si_ib_parse, |
| 1611 | .emit_fence = &si_fence_ring_emit, |
1611 | .emit_fence = &si_fence_ring_emit, |
| 1612 | .emit_semaphore = &r600_semaphore_ring_emit, |
1612 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1613 | // .cs_parse = NULL, |
1613 | .cs_parse = NULL, |
| 1614 | .ring_test = &r600_ring_test, |
1614 | .ring_test = &r600_ring_test, |
| 1615 | .ib_test = &r600_ib_test, |
1615 | .ib_test = &r600_ib_test, |
| 1616 | .is_lockup = &si_gpu_is_lockup, |
1616 | .is_lockup = &si_gpu_is_lockup, |
| 1617 | .vm_flush = &si_vm_flush, |
1617 | .vm_flush = &si_vm_flush, |
| 1618 | }, |
1618 | }, |
| 1619 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
1619 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
| 1620 | .ib_execute = &si_ring_ib_execute, |
1620 | .ib_execute = &si_ring_ib_execute, |
| 1621 | // .ib_parse = &si_ib_parse, |
1621 | // .ib_parse = &si_ib_parse, |
| 1622 | .emit_fence = &si_fence_ring_emit, |
1622 | .emit_fence = &si_fence_ring_emit, |
| 1623 | .emit_semaphore = &r600_semaphore_ring_emit, |
1623 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1624 | // .cs_parse = NULL, |
1624 | .cs_parse = NULL, |
| 1625 | .ring_test = &r600_ring_test, |
1625 | .ring_test = &r600_ring_test, |
| 1626 | .ib_test = &r600_ib_test, |
1626 | .ib_test = &r600_ib_test, |
| 1627 | .is_lockup = &si_gpu_is_lockup, |
1627 | .is_lockup = &si_gpu_is_lockup, |
| 1628 | .vm_flush = &si_vm_flush, |
1628 | .vm_flush = &si_vm_flush, |
| 1629 | }, |
1629 | }, |
| 1630 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
1630 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
| 1631 | .ib_execute = &si_ring_ib_execute, |
1631 | .ib_execute = &si_ring_ib_execute, |
| 1632 | // .ib_parse = &si_ib_parse, |
1632 | // .ib_parse = &si_ib_parse, |
| 1633 | .emit_fence = &si_fence_ring_emit, |
1633 | .emit_fence = &si_fence_ring_emit, |
| 1634 | .emit_semaphore = &r600_semaphore_ring_emit, |
1634 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1635 | // .cs_parse = NULL, |
1635 | .cs_parse = NULL, |
| 1636 | .ring_test = &r600_ring_test, |
1636 | .ring_test = &r600_ring_test, |
| 1637 | .ib_test = &r600_ib_test, |
1637 | .ib_test = &r600_ib_test, |
| 1638 | .is_lockup = &si_gpu_is_lockup, |
1638 | .is_lockup = &si_gpu_is_lockup, |
| 1639 | .vm_flush = &si_vm_flush, |
1639 | .vm_flush = &si_vm_flush, |
| 1640 | } |
1640 | } |
| Line 1676... | Line 1676... | ||
| 1676 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1676 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1677 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1677 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1678 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1678 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1679 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1679 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1680 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1680 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1681 | // .get_pcie_lanes = NULL, |
1681 | .get_pcie_lanes = NULL, |
| 1682 | // .set_pcie_lanes = NULL, |
1682 | .set_pcie_lanes = NULL, |
| 1683 | // .set_clock_gating = NULL, |
1683 | .set_clock_gating = NULL, |
| 1684 | }, |
1684 | }, |
| 1685 | .pflip = { |
1685 | .pflip = { |
| 1686 | // .pre_page_flip = &evergreen_pre_page_flip, |
1686 | // .pre_page_flip = &evergreen_pre_page_flip, |
| 1687 | // .page_flip = &evergreen_page_flip, |
1687 | // .page_flip = &evergreen_page_flip, |
| 1688 | // .post_page_flip = &evergreen_post_page_flip, |
1688 | // .post_page_flip = &evergreen_post_page_flip, |