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Rev 2007 Rev 2160
1 
/*
 1 
/*
2 
 * Copyright 2008 Advanced Micro Devices, Inc.
 2 
 * Copyright 2008 Advanced Micro Devices, Inc.
3 
 * Copyright 2008 Red Hat Inc.
 3 
 * Copyright 2008 Red Hat Inc.
4 
 * Copyright 2009 Jerome Glisse.
 4 
 * Copyright 2009 Jerome Glisse.
5 
 *
 5 
 *
6 
 * Permission is hereby granted, free of charge, to any person obtaining a
 6 
 * Permission is hereby granted, free of charge, to any person obtaining a
7 
 * copy of this software and associated documentation files (the "Software"),
 7 
 * copy of this software and associated documentation files (the "Software"),
8 
 * to deal in the Software without restriction, including without limitation
 8 
 * to deal in the Software without restriction, including without limitation
9 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 9 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 
 * and/or sell copies of the Software, and to permit persons to whom the
 10 
 * and/or sell copies of the Software, and to permit persons to whom the
11 
 * Software is furnished to do so, subject to the following conditions:
 11 
 * Software is furnished to do so, subject to the following conditions:
12 
 *
 12 
 *
13 
 * The above copyright notice and this permission notice shall be included in
 13 
 * The above copyright notice and this permission notice shall be included in
14 
 * all copies or substantial portions of the Software.
 14 
 * all copies or substantial portions of the Software.
15 
 *
 15 
 *
16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 
 * OTHER DEALINGS IN THE SOFTWARE.
 22 
 * OTHER DEALINGS IN THE SOFTWARE.
23 
 *
 23 
 *
24 
 * Authors: Dave Airlie
 24 
 * Authors: Dave Airlie
25 
 *          Alex Deucher
 25 
 *          Alex Deucher
26 
 *          Jerome Glisse
 26 
 *          Jerome Glisse
27 
 */
 27 
 */
28 
 
 28 
 
29 
//#include
29 
//#include
30 
#include
30 
#include
31 
#include
31 
#include
32 
#include
32 
#include
33 
//#include
33 
//#include
34 
//#include
34 
//#include
35 
#include "radeon_reg.h"
 35 
#include "radeon_reg.h"
36 
#include "radeon.h"
 36 
#include "radeon.h"
37 
#include "radeon_asic.h"
 37 
#include "radeon_asic.h"
38 
#include "atom.h"
 38 
#include "atom.h"
39 
 
 39 
 
40 
/*
 40 
/*
41 
 * Registers accessors functions.
 41 
 * Registers accessors functions.
42 
 */
 42 
 */
43 
static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
 43 
static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44 
{
 44 
{
45 
	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 45 
	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 
	BUG_ON(1);
 46 
	BUG_ON(1);
47 
	return 0;
 47 
	return 0;
48 
}
 48 
}
49 
 
 49 
 
50 
static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 50 
static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51 
{
 51 
{
52 
	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 52 
	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 
		  reg, v);
 53 
		  reg, v);
54 
	BUG_ON(1);
 54 
	BUG_ON(1);
55 
}
 55 
}
56 
 
 56 
 
57 
static void radeon_register_accessor_init(struct radeon_device *rdev)
 57 
static void radeon_register_accessor_init(struct radeon_device *rdev)
58 
{
 58 
{
59 
	rdev->mc_rreg = &radeon_invalid_rreg;
 59 
	rdev->mc_rreg = &radeon_invalid_rreg;
60 
	rdev->mc_wreg = &radeon_invalid_wreg;
 60 
	rdev->mc_wreg = &radeon_invalid_wreg;
61 
	rdev->pll_rreg = &radeon_invalid_rreg;
 61 
	rdev->pll_rreg = &radeon_invalid_rreg;
62 
	rdev->pll_wreg = &radeon_invalid_wreg;
 62 
	rdev->pll_wreg = &radeon_invalid_wreg;
63 
	rdev->pciep_rreg = &radeon_invalid_rreg;
 63 
	rdev->pciep_rreg = &radeon_invalid_rreg;
64 
	rdev->pciep_wreg = &radeon_invalid_wreg;
 64 
	rdev->pciep_wreg = &radeon_invalid_wreg;
65 
 
 65 
 
66 
	/* Don't change order as we are overridding accessor. */
 66 
	/* Don't change order as we are overridding accessor. */
67 
	if (rdev->family < CHIP_RV515) {
 67 
	if (rdev->family < CHIP_RV515) {
68 
		rdev->pcie_reg_mask = 0xff;
 68 
		rdev->pcie_reg_mask = 0xff;
69 
	} else {
 69 
	} else {
70 
		rdev->pcie_reg_mask = 0x7ff;
 70 
		rdev->pcie_reg_mask = 0x7ff;
71 
	}
 71 
	}
72 
	/* FIXME: not sure here */
 72 
	/* FIXME: not sure here */
73 
	if (rdev->family <= CHIP_R580) {
 73 
	if (rdev->family <= CHIP_R580) {
74 
		rdev->pll_rreg = &r100_pll_rreg;
 74 
		rdev->pll_rreg = &r100_pll_rreg;
75 
		rdev->pll_wreg = &r100_pll_wreg;
 75 
		rdev->pll_wreg = &r100_pll_wreg;
76 
	}
 76 
	}
77 
	if (rdev->family >= CHIP_R420) {
 77 
	if (rdev->family >= CHIP_R420) {
78 
		rdev->mc_rreg = &r420_mc_rreg;
 78 
		rdev->mc_rreg = &r420_mc_rreg;
79 
		rdev->mc_wreg = &r420_mc_wreg;
 79 
		rdev->mc_wreg = &r420_mc_wreg;
80 
	}
 80 
	}
81 
	if (rdev->family >= CHIP_RV515) {
 81 
	if (rdev->family >= CHIP_RV515) {
82 
		rdev->mc_rreg = &rv515_mc_rreg;
 82 
		rdev->mc_rreg = &rv515_mc_rreg;
83 
		rdev->mc_wreg = &rv515_mc_wreg;
 83 
		rdev->mc_wreg = &rv515_mc_wreg;
84 
	}
 84 
	}
85 
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 85 
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 
		rdev->mc_rreg = &rs400_mc_rreg;
 86 
		rdev->mc_rreg = &rs400_mc_rreg;
87 
		rdev->mc_wreg = &rs400_mc_wreg;
 87 
		rdev->mc_wreg = &rs400_mc_wreg;
88 
	}
 88 
	}
89 
	if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 89 
	if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 
		rdev->mc_rreg = &rs690_mc_rreg;
 90 
		rdev->mc_rreg = &rs690_mc_rreg;
91 
		rdev->mc_wreg = &rs690_mc_wreg;
 91 
		rdev->mc_wreg = &rs690_mc_wreg;
92 
	}
 92 
	}
93 
	if (rdev->family == CHIP_RS600) {
 93 
	if (rdev->family == CHIP_RS600) {
94 
		rdev->mc_rreg = &rs600_mc_rreg;
 94 
		rdev->mc_rreg = &rs600_mc_rreg;
95 
		rdev->mc_wreg = &rs600_mc_wreg;
 95 
		rdev->mc_wreg = &rs600_mc_wreg;
96 
	}
 96 
	}
97 
	if (rdev->family >= CHIP_R600) {
 97 
	if (rdev->family >= CHIP_R600) {
98 
		rdev->pciep_rreg = &r600_pciep_rreg;
 98 
		rdev->pciep_rreg = &r600_pciep_rreg;
99 
		rdev->pciep_wreg = &r600_pciep_wreg;
 99 
		rdev->pciep_wreg = &r600_pciep_wreg;
100 
	}
 100 
	}
101 
}
 101 
}
102 
 
 102 
 
103 
 
 103 
 
104 
/* helper to disable agp */
 104 
/* helper to disable agp */
105 
void radeon_agp_disable(struct radeon_device *rdev)
 105 
void radeon_agp_disable(struct radeon_device *rdev)
106 
{
 106 
{
107 
	rdev->flags &= ~RADEON_IS_AGP;
 107 
	rdev->flags &= ~RADEON_IS_AGP;
108 
	if (rdev->family >= CHIP_R600) {
 108 
	if (rdev->family >= CHIP_R600) {
109 
		DRM_INFO("Forcing AGP to PCIE mode\n");
 109 
		DRM_INFO("Forcing AGP to PCIE mode\n");
110 
		rdev->flags |= RADEON_IS_PCIE;
 110 
		rdev->flags |= RADEON_IS_PCIE;
111 
	} else if (rdev->family >= CHIP_RV515 ||
 111 
	} else if (rdev->family >= CHIP_RV515 ||
112 
			rdev->family == CHIP_RV380 ||
 112 
			rdev->family == CHIP_RV380 ||
113 
			rdev->family == CHIP_RV410 ||
 113 
			rdev->family == CHIP_RV410 ||
114 
			rdev->family == CHIP_R423) {
 114 
			rdev->family == CHIP_R423) {
115 
		DRM_INFO("Forcing AGP to PCIE mode\n");
 115 
		DRM_INFO("Forcing AGP to PCIE mode\n");
116 
		rdev->flags |= RADEON_IS_PCIE;
 116 
		rdev->flags |= RADEON_IS_PCIE;
117 
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 117 
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
118 
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 118 
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
119 
	} else {
 119 
	} else {
120 
		DRM_INFO("Forcing AGP to PCI mode\n");
 120 
		DRM_INFO("Forcing AGP to PCI mode\n");
121 
		rdev->flags |= RADEON_IS_PCI;
 121 
		rdev->flags |= RADEON_IS_PCI;
122 
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 122 
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
123 
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 123 
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
124 
	}
 124 
	}
125 
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 125 
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126 
}
 126 
}
127 
 
 127 
 
128 
/*
 128 
/*
129 
 * ASIC
 129 
 * ASIC
130 
 */
 130 
 */
131 
static struct radeon_asic r100_asic = {
 131 
static struct radeon_asic r100_asic = {
132 
	.init = &r100_init,
 132 
	.init = &r100_init,
133 
//	.fini = &r100_fini,
 133 
//	.fini = &r100_fini,
134 
//	.suspend = &r100_suspend,
 134 
//	.suspend = &r100_suspend,
135 
//	.resume = &r100_resume,
 135 
//	.resume = &r100_resume,
136 
//	.vga_set_state = &r100_vga_set_state,
 136 
//	.vga_set_state = &r100_vga_set_state,
137 
	.gpu_is_lockup = &r100_gpu_is_lockup,
 137 
	.gpu_is_lockup = &r100_gpu_is_lockup,
138 
	.asic_reset = &r100_asic_reset,
 138 
	.asic_reset = &r100_asic_reset,
139 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 139 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
140 
	.gart_set_page = &r100_pci_gart_set_page,
 140 
	.gart_set_page = &r100_pci_gart_set_page,
141 
	.cp_commit = &r100_cp_commit,
 141 
	.cp_commit = &r100_cp_commit,
142 
	.ring_start = &r100_ring_start,
 142 
	.ring_start = &r100_ring_start,
143 
	.ring_test = &r100_ring_test,
 143 
	.ring_test = &r100_ring_test,
144 
	.ring_ib_execute = &r100_ring_ib_execute,
 144 
	.ring_ib_execute = &r100_ring_ib_execute,
145 
	.irq_set = &r100_irq_set,
 145 
	.irq_set = &r100_irq_set,
146 
	.irq_process = &r100_irq_process,
 146 
	.irq_process = &r100_irq_process,
147 
//	.get_vblank_counter = &r100_get_vblank_counter,
 147 
//	.get_vblank_counter = &r100_get_vblank_counter,
148 
	.fence_ring_emit = &r100_fence_ring_emit,
 148 
	.fence_ring_emit = &r100_fence_ring_emit,
149 
//	.cs_parse = &r100_cs_parse,
 149 
//	.cs_parse = &r100_cs_parse,
150 
	.copy_blit = &r100_copy_blit,
 150 
	.copy_blit = &r100_copy_blit,
151 
	.copy_dma = NULL,
 151 
	.copy_dma = NULL,
152 
	.copy = &r100_copy_blit,
 152 
	.copy = &r100_copy_blit,
153 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 153 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
154 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 154 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
155 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 155 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
156 
	.set_memory_clock = NULL,
 156 
	.set_memory_clock = NULL,
157 
	.get_pcie_lanes = NULL,
 157 
	.get_pcie_lanes = NULL,
158 
	.set_pcie_lanes = NULL,
 158 
	.set_pcie_lanes = NULL,
159 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 159 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
160 
	.set_surface_reg = r100_set_surface_reg,
 160 
	.set_surface_reg = r100_set_surface_reg,
161 
	.clear_surface_reg = r100_clear_surface_reg,
 161 
	.clear_surface_reg = r100_clear_surface_reg,
162 
	.bandwidth_update = &r100_bandwidth_update,
 162 
	.bandwidth_update = &r100_bandwidth_update,
163 
	.hpd_init = &r100_hpd_init,
 163 
	.hpd_init = &r100_hpd_init,
164 
	.hpd_fini = &r100_hpd_fini,
 164 
	.hpd_fini = &r100_hpd_fini,
165 
	.hpd_sense = &r100_hpd_sense,
 165 
	.hpd_sense = &r100_hpd_sense,
166 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 166 
	.hpd_set_polarity = &r100_hpd_set_polarity,
167 
	.ioctl_wait_idle = NULL,
 167 
	.ioctl_wait_idle = NULL,
168 
	.gui_idle = &r100_gui_idle,
 168 
	.gui_idle = &r100_gui_idle,
169 
};
 169 
};
170 
 
 170 
 
171 
static struct radeon_asic r200_asic = {
 171 
static struct radeon_asic r200_asic = {
172 
	.init = &r100_init,
 172 
	.init = &r100_init,
173 
//	.fini = &r100_fini,
 173 
//	.fini = &r100_fini,
174 
//	.suspend = &r100_suspend,
 174 
//	.suspend = &r100_suspend,
175 
//	.resume = &r100_resume,
 175 
//	.resume = &r100_resume,
176 
//	.vga_set_state = &r100_vga_set_state,
 176 
//	.vga_set_state = &r100_vga_set_state,
177 
	.gpu_is_lockup = &r100_gpu_is_lockup,
 177 
	.gpu_is_lockup = &r100_gpu_is_lockup,
178 
	.asic_reset = &r100_asic_reset,
 178 
	.asic_reset = &r100_asic_reset,
179 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 179 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
180 
	.gart_set_page = &r100_pci_gart_set_page,
 180 
	.gart_set_page = &r100_pci_gart_set_page,
181 
	.cp_commit = &r100_cp_commit,
 181 
	.cp_commit = &r100_cp_commit,
182 
	.ring_start = &r100_ring_start,
 182 
	.ring_start = &r100_ring_start,
183 
	.ring_test = &r100_ring_test,
 183 
	.ring_test = &r100_ring_test,
184 
	.ring_ib_execute = &r100_ring_ib_execute,
 184 
	.ring_ib_execute = &r100_ring_ib_execute,
185 
	.irq_set = &r100_irq_set,
 185 
	.irq_set = &r100_irq_set,
186 
	.irq_process = &r100_irq_process,
 186 
	.irq_process = &r100_irq_process,
187 
//	.get_vblank_counter = &r100_get_vblank_counter,
 187 
//	.get_vblank_counter = &r100_get_vblank_counter,
188 
	.fence_ring_emit = &r100_fence_ring_emit,
 188 
	.fence_ring_emit = &r100_fence_ring_emit,
189 
//	.cs_parse = &r100_cs_parse,
 189 
//	.cs_parse = &r100_cs_parse,
190 
	.copy_blit = &r100_copy_blit,
 190 
	.copy_blit = &r100_copy_blit,
191 
	.copy_dma = &r200_copy_dma,
 191 
	.copy_dma = &r200_copy_dma,
192 
	.copy = &r100_copy_blit,
 192 
	.copy = &r100_copy_blit,
193 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 193 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
194 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 194 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
195 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 195 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
196 
	.set_memory_clock = NULL,
 196 
	.set_memory_clock = NULL,
197 
	.set_pcie_lanes = NULL,
 197 
	.set_pcie_lanes = NULL,
198 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 198 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
199 
	.set_surface_reg = r100_set_surface_reg,
 199 
	.set_surface_reg = r100_set_surface_reg,
200 
	.clear_surface_reg = r100_clear_surface_reg,
 200 
	.clear_surface_reg = r100_clear_surface_reg,
201 
	.bandwidth_update = &r100_bandwidth_update,
 201 
	.bandwidth_update = &r100_bandwidth_update,
202 
	.hpd_init = &r100_hpd_init,
 202 
	.hpd_init = &r100_hpd_init,
203 
	.hpd_fini = &r100_hpd_fini,
 203 
	.hpd_fini = &r100_hpd_fini,
204 
	.hpd_sense = &r100_hpd_sense,
 204 
	.hpd_sense = &r100_hpd_sense,
205 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 205 
	.hpd_set_polarity = &r100_hpd_set_polarity,
206 
	.ioctl_wait_idle = NULL,
 206 
	.ioctl_wait_idle = NULL,
207 
	.gui_idle = &r100_gui_idle,
 207 
	.gui_idle = &r100_gui_idle,
208 
};
 208 
};
209 
 
 209 
 
210 
static struct radeon_asic r300_asic = {
 210 
static struct radeon_asic r300_asic = {
211 
	.init = &r300_init,
 211 
	.init = &r300_init,
212 
//	.fini = &r300_fini,
 212 
//	.fini = &r300_fini,
213 
//	.suspend = &r300_suspend,
 213 
//	.suspend = &r300_suspend,
214 
//	.resume = &r300_resume,
 214 
//	.resume = &r300_resume,
215 
//	.vga_set_state = &r100_vga_set_state,
 215 
//	.vga_set_state = &r100_vga_set_state,
216 
	.asic_reset = &r300_asic_reset,
 216 
	.asic_reset = &r300_asic_reset,
217 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 217 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
218 
	.gart_set_page = &r100_pci_gart_set_page,
 218 
	.gart_set_page = &r100_pci_gart_set_page,
219 
	.cp_commit = &r100_cp_commit,
 219 
	.cp_commit = &r100_cp_commit,
220 
	.ring_start = &r300_ring_start,
 220 
	.ring_start = &r300_ring_start,
221 
	.ring_test = &r100_ring_test,
 221 
	.ring_test = &r100_ring_test,
222 
	.ring_ib_execute = &r100_ring_ib_execute,
 222 
	.ring_ib_execute = &r100_ring_ib_execute,
223 
	.irq_set = &r100_irq_set,
 223 
	.irq_set = &r100_irq_set,
224 
	.irq_process = &r100_irq_process,
 224 
	.irq_process = &r100_irq_process,
225 
//	.get_vblank_counter = &r100_get_vblank_counter,
 225 
//	.get_vblank_counter = &r100_get_vblank_counter,
226 
	.fence_ring_emit = &r300_fence_ring_emit,
 226 
	.fence_ring_emit = &r300_fence_ring_emit,
227 
//	.cs_parse = &r300_cs_parse,
 227 
//	.cs_parse = &r300_cs_parse,
228 
	.copy_blit = &r100_copy_blit,
 228 
	.copy_blit = &r100_copy_blit,
229 
	.copy_dma = &r200_copy_dma,
 229 
	.copy_dma = &r200_copy_dma,
230 
	.copy = &r100_copy_blit,
 230 
	.copy = &r100_copy_blit,
231 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 231 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
232 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 232 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
233 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 233 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
234 
	.set_memory_clock = NULL,
 234 
	.set_memory_clock = NULL,
235 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 235 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
236 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 236 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
237 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 237 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
238 
	.set_surface_reg = r100_set_surface_reg,
 238 
	.set_surface_reg = r100_set_surface_reg,
239 
	.clear_surface_reg = r100_clear_surface_reg,
 239 
	.clear_surface_reg = r100_clear_surface_reg,
240 
	.bandwidth_update = &r100_bandwidth_update,
 240 
	.bandwidth_update = &r100_bandwidth_update,
241 
	.hpd_init = &r100_hpd_init,
 241 
	.hpd_init = &r100_hpd_init,
242 
	.hpd_fini = &r100_hpd_fini,
 242 
	.hpd_fini = &r100_hpd_fini,
243 
	.hpd_sense = &r100_hpd_sense,
 243 
	.hpd_sense = &r100_hpd_sense,
244 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 244 
	.hpd_set_polarity = &r100_hpd_set_polarity,
245 
	.ioctl_wait_idle = NULL,
 245 
	.ioctl_wait_idle = NULL,
246 
	.gui_idle = &r100_gui_idle,
 246 
	.gui_idle = &r100_gui_idle,
247 
};
 247 
};
248 
 
 248 
 
249 
static struct radeon_asic r300_asic_pcie = {
 249 
static struct radeon_asic r300_asic_pcie = {
250 
	.init = &r300_init,
 250 
	.init = &r300_init,
251 
//	.fini = &r300_fini,
 251 
//	.fini = &r300_fini,
252 
//	.suspend = &r300_suspend,
 252 
//	.suspend = &r300_suspend,
253 
//	.resume = &r300_resume,
 253 
//	.resume = &r300_resume,
254 
//	.vga_set_state = &r100_vga_set_state,
 254 
//	.vga_set_state = &r100_vga_set_state,
255 
	.asic_reset = &r300_asic_reset,
 255 
	.asic_reset = &r300_asic_reset,
256 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 256 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
257 
	.gart_set_page = &rv370_pcie_gart_set_page,
 257 
	.gart_set_page = &rv370_pcie_gart_set_page,
258 
	.cp_commit = &r100_cp_commit,
 258 
	.cp_commit = &r100_cp_commit,
259 
	.ring_start = &r300_ring_start,
 259 
	.ring_start = &r300_ring_start,
260 
	.ring_test = &r100_ring_test,
 260 
	.ring_test = &r100_ring_test,
261 
	.ring_ib_execute = &r100_ring_ib_execute,
 261 
	.ring_ib_execute = &r100_ring_ib_execute,
262 
	.irq_set = &r100_irq_set,
 262 
	.irq_set = &r100_irq_set,
263 
	.irq_process = &r100_irq_process,
 263 
	.irq_process = &r100_irq_process,
264 
//	.get_vblank_counter = &r100_get_vblank_counter,
 264 
//	.get_vblank_counter = &r100_get_vblank_counter,
265 
	.fence_ring_emit = &r300_fence_ring_emit,
 265 
	.fence_ring_emit = &r300_fence_ring_emit,
266 
//	.cs_parse = &r300_cs_parse,
 266 
//	.cs_parse = &r300_cs_parse,
267 
	.copy_blit = &r100_copy_blit,
 267 
	.copy_blit = &r100_copy_blit,
268 
	.copy_dma = &r200_copy_dma,
 268 
	.copy_dma = &r200_copy_dma,
269 
	.copy = &r100_copy_blit,
 269 
	.copy = &r100_copy_blit,
270 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 270 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
271 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 271 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
272 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 272 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
273 
	.set_memory_clock = NULL,
 273 
	.set_memory_clock = NULL,
274 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 274 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
275 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 275 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
276 
	.set_surface_reg = r100_set_surface_reg,
 276 
	.set_surface_reg = r100_set_surface_reg,
277 
	.clear_surface_reg = r100_clear_surface_reg,
 277 
	.clear_surface_reg = r100_clear_surface_reg,
278 
	.bandwidth_update = &r100_bandwidth_update,
 278 
	.bandwidth_update = &r100_bandwidth_update,
279 
	.hpd_init = &r100_hpd_init,
 279 
	.hpd_init = &r100_hpd_init,
280 
	.hpd_fini = &r100_hpd_fini,
 280 
	.hpd_fini = &r100_hpd_fini,
281 
	.hpd_sense = &r100_hpd_sense,
 281 
	.hpd_sense = &r100_hpd_sense,
282 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 282 
	.hpd_set_polarity = &r100_hpd_set_polarity,
283 
	.ioctl_wait_idle = NULL,
 283 
	.ioctl_wait_idle = NULL,
284 
	.gui_idle = &r100_gui_idle,
 284 
	.gui_idle = &r100_gui_idle,
285 
};
 285 
};
286 
 
 286 
 
287 
static struct radeon_asic r420_asic = {
 287 
static struct radeon_asic r420_asic = {
288 
	.init = &r420_init,
 288 
	.init = &r420_init,
289 
//	.fini = &r420_fini,
 289 
//	.fini = &r420_fini,
290 
//	.suspend = &r420_suspend,
 290 
//	.suspend = &r420_suspend,
291 
//	.resume = &r420_resume,
 291 
//	.resume = &r420_resume,
292 
//	.vga_set_state = &r100_vga_set_state,
 292 
//	.vga_set_state = &r100_vga_set_state,
293 
	.asic_reset = &r300_asic_reset,
 293 
	.asic_reset = &r300_asic_reset,
294 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 294 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
295 
	.gart_set_page = &rv370_pcie_gart_set_page,
 295 
	.gart_set_page = &rv370_pcie_gart_set_page,
296 
	.cp_commit = &r100_cp_commit,
 296 
	.cp_commit = &r100_cp_commit,
297 
	.ring_start = &r300_ring_start,
 297 
	.ring_start = &r300_ring_start,
298 
	.ring_test = &r100_ring_test,
 298 
	.ring_test = &r100_ring_test,
299 
	.ring_ib_execute = &r100_ring_ib_execute,
 299 
	.ring_ib_execute = &r100_ring_ib_execute,
300 
	.irq_set = &r100_irq_set,
 300 
	.irq_set = &r100_irq_set,
301 
	.irq_process = &r100_irq_process,
 301 
	.irq_process = &r100_irq_process,
302 
//	.get_vblank_counter = &r100_get_vblank_counter,
 302 
//	.get_vblank_counter = &r100_get_vblank_counter,
303 
	.fence_ring_emit = &r300_fence_ring_emit,
 303 
	.fence_ring_emit = &r300_fence_ring_emit,
304 
//	.cs_parse = &r300_cs_parse,
 304 
//	.cs_parse = &r300_cs_parse,
305 
	.copy_blit = &r100_copy_blit,
 305 
	.copy_blit = &r100_copy_blit,
306 
	.copy_dma = &r200_copy_dma,
 306 
	.copy_dma = &r200_copy_dma,
307 
	.copy = &r100_copy_blit,
 307 
	.copy = &r100_copy_blit,
308 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 308 
	.get_engine_clock = &radeon_atom_get_engine_clock,
309 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 309 
	.set_engine_clock = &radeon_atom_set_engine_clock,
310 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 310 
	.get_memory_clock = &radeon_atom_get_memory_clock,
311 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 311 
	.set_memory_clock = &radeon_atom_set_memory_clock,
312 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 312 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
313 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 313 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
314 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 314 
	.set_clock_gating = &radeon_atom_set_clock_gating,
315 
	.set_surface_reg = r100_set_surface_reg,
 315 
	.set_surface_reg = r100_set_surface_reg,
316 
	.clear_surface_reg = r100_clear_surface_reg,
 316 
	.clear_surface_reg = r100_clear_surface_reg,
317 
	.bandwidth_update = &r100_bandwidth_update,
 317 
	.bandwidth_update = &r100_bandwidth_update,
318 
	.hpd_init = &r100_hpd_init,
 318 
	.hpd_init = &r100_hpd_init,
319 
	.hpd_fini = &r100_hpd_fini,
 319 
	.hpd_fini = &r100_hpd_fini,
320 
	.hpd_sense = &r100_hpd_sense,
 320 
	.hpd_sense = &r100_hpd_sense,
321 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 321 
	.hpd_set_polarity = &r100_hpd_set_polarity,
322 
	.ioctl_wait_idle = NULL,
 322 
	.ioctl_wait_idle = NULL,
- 
 
 323 
	.gui_idle = &r100_gui_idle,
323 
};
 324 
};
324 
 
 325 
 
325 
static struct radeon_asic rs400_asic = {
 326 
static struct radeon_asic rs400_asic = {
326 
	.init = &rs400_init,
 327 
	.init = &rs400_init,
327 
//	.fini = &rs400_fini,
 328 
//	.fini = &rs400_fini,
328 
//	.suspend = &rs400_suspend,
 329 
//	.suspend = &rs400_suspend,
329 
//	.resume = &rs400_resume,
 330 
//	.resume = &rs400_resume,
330 
//	.vga_set_state = &r100_vga_set_state,
 331 
//	.vga_set_state = &r100_vga_set_state,
331 
	.asic_reset = &r300_asic_reset,
 332 
	.asic_reset = &r300_asic_reset,
332 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
 333 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
333 
	.gart_set_page = &rs400_gart_set_page,
 334 
	.gart_set_page = &rs400_gart_set_page,
334 
	.cp_commit = &r100_cp_commit,
 335 
	.cp_commit = &r100_cp_commit,
335 
	.ring_start = &r300_ring_start,
 336 
	.ring_start = &r300_ring_start,
336 
	.ring_test = &r100_ring_test,
 337 
	.ring_test = &r100_ring_test,
337 
	.ring_ib_execute = &r100_ring_ib_execute,
 338 
	.ring_ib_execute = &r100_ring_ib_execute,
338 
	.irq_set = &r100_irq_set,
 339 
	.irq_set = &r100_irq_set,
339 
	.irq_process = &r100_irq_process,
 340 
	.irq_process = &r100_irq_process,
340 
//	.get_vblank_counter = &r100_get_vblank_counter,
 341 
//	.get_vblank_counter = &r100_get_vblank_counter,
341 
	.fence_ring_emit = &r300_fence_ring_emit,
 342 
	.fence_ring_emit = &r300_fence_ring_emit,
342 
//	.cs_parse = &r300_cs_parse,
 343 
//	.cs_parse = &r300_cs_parse,
343 
	.copy_blit = &r100_copy_blit,
 344 
	.copy_blit = &r100_copy_blit,
344 
	.copy_dma = &r200_copy_dma,
 345 
	.copy_dma = &r200_copy_dma,
345 
	.copy = &r100_copy_blit,
 346 
	.copy = &r100_copy_blit,
346 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 347 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
347 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 348 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
348 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 349 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
349 
	.set_memory_clock = NULL,
 350 
	.set_memory_clock = NULL,
350 
	.get_pcie_lanes = NULL,
 351 
	.get_pcie_lanes = NULL,
351 
	.set_pcie_lanes = NULL,
 352 
	.set_pcie_lanes = NULL,
352 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 353 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
353 
	.set_surface_reg = r100_set_surface_reg,
 354 
	.set_surface_reg = r100_set_surface_reg,
354 
	.clear_surface_reg = r100_clear_surface_reg,
 355 
	.clear_surface_reg = r100_clear_surface_reg,
355 
	.bandwidth_update = &r100_bandwidth_update,
 356 
	.bandwidth_update = &r100_bandwidth_update,
356 
	.hpd_init = &r100_hpd_init,
 357 
	.hpd_init = &r100_hpd_init,
357 
	.hpd_fini = &r100_hpd_fini,
 358 
	.hpd_fini = &r100_hpd_fini,
358 
	.hpd_sense = &r100_hpd_sense,
 359 
	.hpd_sense = &r100_hpd_sense,
359 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 360 
	.hpd_set_polarity = &r100_hpd_set_polarity,
360 
	.ioctl_wait_idle = NULL,
 361 
	.ioctl_wait_idle = NULL,
- 
 
 362 
	.gui_idle = &r100_gui_idle,
361 
};
 363 
};
362 
 
 364 
 
363 
static struct radeon_asic rs600_asic = {
 365 
static struct radeon_asic rs600_asic = {
364 
	.init = &rs600_init,
 366 
	.init = &rs600_init,
365 
//	.fini = &rs600_fini,
 367 
//	.fini = &rs600_fini,
366 
//	.suspend = &rs600_suspend,
 368 
//	.suspend = &rs600_suspend,
367 
//	.resume = &rs600_resume,
 369 
//	.resume = &rs600_resume,
368 
//	.vga_set_state = &r100_vga_set_state,
 370 
//	.vga_set_state = &r100_vga_set_state,
369 
	.asic_reset = &rs600_asic_reset,
 371 
	.asic_reset = &rs600_asic_reset,
370 
	.gart_tlb_flush = &rs600_gart_tlb_flush,
 372 
	.gart_tlb_flush = &rs600_gart_tlb_flush,
371 
	.gart_set_page = &rs600_gart_set_page,
 373 
	.gart_set_page = &rs600_gart_set_page,
372 
	.cp_commit = &r100_cp_commit,
 374 
	.cp_commit = &r100_cp_commit,
373 
	.ring_start = &r300_ring_start,
 375 
	.ring_start = &r300_ring_start,
374 
	.ring_test = &r100_ring_test,
 376 
	.ring_test = &r100_ring_test,
375 
	.ring_ib_execute = &r100_ring_ib_execute,
 377 
	.ring_ib_execute = &r100_ring_ib_execute,
376 
	.irq_set = &rs600_irq_set,
 378 
	.irq_set = &rs600_irq_set,
377 
	.irq_process = &rs600_irq_process,
 379 
	.irq_process = &rs600_irq_process,
378 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 380 
//	.get_vblank_counter = &rs600_get_vblank_counter,
379 
	.fence_ring_emit = &r300_fence_ring_emit,
 381 
	.fence_ring_emit = &r300_fence_ring_emit,
380 
//   .cs_parse = &r300_cs_parse,
 382 
//   .cs_parse = &r300_cs_parse,
381 
    .copy_blit = &r100_copy_blit,
 383 
    .copy_blit = &r100_copy_blit,
382 
	.copy_dma = &r200_copy_dma,
 384 
	.copy_dma = &r200_copy_dma,
383 
    .copy = &r100_copy_blit,
 385 
    .copy = &r100_copy_blit,
384 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 386 
	.get_engine_clock = &radeon_atom_get_engine_clock,
385 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 387 
	.set_engine_clock = &radeon_atom_set_engine_clock,
386 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 388 
	.get_memory_clock = &radeon_atom_get_memory_clock,
387 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 389 
	.set_memory_clock = &radeon_atom_set_memory_clock,
388 
	.get_pcie_lanes = NULL,
 390 
	.get_pcie_lanes = NULL,
389 
	.set_pcie_lanes = NULL,
 391 
	.set_pcie_lanes = NULL,
390 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 392 
	.set_clock_gating = &radeon_atom_set_clock_gating,
391 
	.set_surface_reg = r100_set_surface_reg,
 393 
	.set_surface_reg = r100_set_surface_reg,
392 
	.clear_surface_reg = r100_clear_surface_reg,
 394 
	.clear_surface_reg = r100_clear_surface_reg,
393 
	.bandwidth_update = &rs600_bandwidth_update,
 395 
	.bandwidth_update = &rs600_bandwidth_update,
394 
	.hpd_init = &rs600_hpd_init,
 396 
	.hpd_init = &rs600_hpd_init,
395 
	.hpd_fini = &rs600_hpd_fini,
 397 
	.hpd_fini = &rs600_hpd_fini,
396 
	.hpd_sense = &rs600_hpd_sense,
 398 
	.hpd_sense = &rs600_hpd_sense,
397 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 399 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
398 
	.ioctl_wait_idle = NULL,
 400 
	.ioctl_wait_idle = NULL,
- 
 
 401 
	.gui_idle = &r100_gui_idle,
399 
};
 402 
};
400 
 
 403 
 
401 
static struct radeon_asic rs690_asic = {
 404 
static struct radeon_asic rs690_asic = {
402 
	.init = &rs690_init,
 405 
	.init = &rs690_init,
403 
//	.fini = &rs690_fini,
 406 
//	.fini = &rs690_fini,
404 
//	.suspend = &rs690_suspend,
 407 
//	.suspend = &rs690_suspend,
405 
//	.resume = &rs690_resume,
 408 
//	.resume = &rs690_resume,
406 
//	.vga_set_state = &r100_vga_set_state,
 409 
//	.vga_set_state = &r100_vga_set_state,
407 
	.asic_reset = &rs600_asic_reset,
 410 
	.asic_reset = &rs600_asic_reset,
408 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
 411 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
409 
	.gart_set_page = &rs400_gart_set_page,
 412 
	.gart_set_page = &rs400_gart_set_page,
410 
	.cp_commit = &r100_cp_commit,
 413 
	.cp_commit = &r100_cp_commit,
411 
	.ring_start = &r300_ring_start,
 414 
	.ring_start = &r300_ring_start,
412 
	.ring_test = &r100_ring_test,
 415 
	.ring_test = &r100_ring_test,
413 
	.ring_ib_execute = &r100_ring_ib_execute,
 416 
	.ring_ib_execute = &r100_ring_ib_execute,
414 
	.irq_set = &rs600_irq_set,
 417 
	.irq_set = &rs600_irq_set,
415 
	.irq_process = &rs600_irq_process,
 418 
	.irq_process = &rs600_irq_process,
416 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 419 
//	.get_vblank_counter = &rs600_get_vblank_counter,
417 
	.fence_ring_emit = &r300_fence_ring_emit,
 420 
	.fence_ring_emit = &r300_fence_ring_emit,
418 
//	.cs_parse = &r300_cs_parse,
 421 
//	.cs_parse = &r300_cs_parse,
419 
	.copy_blit = &r100_copy_blit,
 422 
	.copy_blit = &r100_copy_blit,
420 
	.copy_dma = &r200_copy_dma,
 423 
	.copy_dma = &r200_copy_dma,
421 
	.copy = &r200_copy_dma,
 424 
	.copy = &r200_copy_dma,
422 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 425 
	.get_engine_clock = &radeon_atom_get_engine_clock,
423 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 426 
	.set_engine_clock = &radeon_atom_set_engine_clock,
424 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 427 
	.get_memory_clock = &radeon_atom_get_memory_clock,
425 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 428 
	.set_memory_clock = &radeon_atom_set_memory_clock,
426 
	.get_pcie_lanes = NULL,
 429 
	.get_pcie_lanes = NULL,
427 
	.set_pcie_lanes = NULL,
 430 
	.set_pcie_lanes = NULL,
428 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 431 
	.set_clock_gating = &radeon_atom_set_clock_gating,
429 
	.set_surface_reg = r100_set_surface_reg,
 432 
	.set_surface_reg = r100_set_surface_reg,
430 
	.clear_surface_reg = r100_clear_surface_reg,
 433 
	.clear_surface_reg = r100_clear_surface_reg,
431 
	.bandwidth_update = &rs690_bandwidth_update,
 434 
	.bandwidth_update = &rs690_bandwidth_update,
432 
	.hpd_init = &rs600_hpd_init,
 435 
	.hpd_init = &rs600_hpd_init,
433 
	.hpd_fini = &rs600_hpd_fini,
 436 
	.hpd_fini = &rs600_hpd_fini,
434 
	.hpd_sense = &rs600_hpd_sense,
 437 
	.hpd_sense = &rs600_hpd_sense,
435 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 438 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
436 
	.ioctl_wait_idle = NULL,
 439 
	.ioctl_wait_idle = NULL,
- 
 
 440 
	.gui_idle = &r100_gui_idle,
437 
};
 441 
};
438 
 
 442 
 
439 
static struct radeon_asic rv515_asic = {
 443 
static struct radeon_asic rv515_asic = {
440 
	.init = &rv515_init,
 444 
	.init = &rv515_init,
441 
//	.fini = &rv515_fini,
 445 
//	.fini = &rv515_fini,
442 
//	.suspend = &rv515_suspend,
 446 
//	.suspend = &rv515_suspend,
443 
//	.resume = &rv515_resume,
 447 
//	.resume = &rv515_resume,
444 
//	.vga_set_state = &r100_vga_set_state,
 448 
//	.vga_set_state = &r100_vga_set_state,
445 
	.asic_reset = &rs600_asic_reset,
 449 
	.asic_reset = &rs600_asic_reset,
446 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 450 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
447 
	.gart_set_page = &rv370_pcie_gart_set_page,
 451 
	.gart_set_page = &rv370_pcie_gart_set_page,
448 
	.cp_commit = &r100_cp_commit,
 452 
	.cp_commit = &r100_cp_commit,
449 
	.ring_start = &rv515_ring_start,
 453 
	.ring_start = &rv515_ring_start,
450 
	.ring_test = &r100_ring_test,
 454 
	.ring_test = &r100_ring_test,
451 
	.ring_ib_execute = &r100_ring_ib_execute,
 455 
	.ring_ib_execute = &r100_ring_ib_execute,
452 
	.irq_set = &rs600_irq_set,
 456 
	.irq_set = &rs600_irq_set,
453 
	.irq_process = &rs600_irq_process,
 457 
	.irq_process = &rs600_irq_process,
454 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 458 
//	.get_vblank_counter = &rs600_get_vblank_counter,
455 
	.fence_ring_emit = &r300_fence_ring_emit,
 459 
	.fence_ring_emit = &r300_fence_ring_emit,
456 
//	.cs_parse = &r300_cs_parse,
 460 
//	.cs_parse = &r300_cs_parse,
457 
	.copy_blit = &r100_copy_blit,
 461 
	.copy_blit = &r100_copy_blit,
458 
	.copy_dma = &r200_copy_dma,
 462 
	.copy_dma = &r200_copy_dma,
459 
	.copy = &r100_copy_blit,
 463 
	.copy = &r100_copy_blit,
460 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 464 
	.get_engine_clock = &radeon_atom_get_engine_clock,
461 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 465 
	.set_engine_clock = &radeon_atom_set_engine_clock,
462 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 466 
	.get_memory_clock = &radeon_atom_get_memory_clock,
463 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 467 
	.set_memory_clock = &radeon_atom_set_memory_clock,
464 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 468 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
465 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 469 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
466 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 470 
	.set_clock_gating = &radeon_atom_set_clock_gating,
467 
	.set_surface_reg = r100_set_surface_reg,
 471 
	.set_surface_reg = r100_set_surface_reg,
468 
	.clear_surface_reg = r100_clear_surface_reg,
 472 
	.clear_surface_reg = r100_clear_surface_reg,
469 
	.bandwidth_update = &rv515_bandwidth_update,
 473 
	.bandwidth_update = &rv515_bandwidth_update,
470 
	.hpd_init = &rs600_hpd_init,
 474 
	.hpd_init = &rs600_hpd_init,
471 
	.hpd_fini = &rs600_hpd_fini,
 475 
	.hpd_fini = &rs600_hpd_fini,
472 
	.hpd_sense = &rs600_hpd_sense,
 476 
	.hpd_sense = &rs600_hpd_sense,
473 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 477 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
474 
	.ioctl_wait_idle = NULL,
 478 
	.ioctl_wait_idle = NULL,
- 
 
 479 
	.gui_idle = &r100_gui_idle,
475 
};
 480 
};
476 
 
 481 
 
477 
static struct radeon_asic r520_asic = {
 482 
static struct radeon_asic r520_asic = {
478 
	.init = &r520_init,
 483 
	.init = &r520_init,
479 
//	.fini = &rv515_fini,
 484 
//	.fini = &rv515_fini,
480 
//	.suspend = &rv515_suspend,
 485 
//	.suspend = &rv515_suspend,
481 
//	.resume = &r520_resume,
 486 
//	.resume = &r520_resume,
482 
//	.vga_set_state = &r100_vga_set_state,
 487 
//	.vga_set_state = &r100_vga_set_state,
483 
	.asic_reset = &rs600_asic_reset,
 488 
	.asic_reset = &rs600_asic_reset,
484 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 489 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
485 
	.gart_set_page = &rv370_pcie_gart_set_page,
 490 
	.gart_set_page = &rv370_pcie_gart_set_page,
486 
	.cp_commit = &r100_cp_commit,
 491 
	.cp_commit = &r100_cp_commit,
487 
	.ring_start = &rv515_ring_start,
 492 
	.ring_start = &rv515_ring_start,
488 
	.ring_test = &r100_ring_test,
 493 
	.ring_test = &r100_ring_test,
489 
	.ring_ib_execute = &r100_ring_ib_execute,
 494 
	.ring_ib_execute = &r100_ring_ib_execute,
490 
	.irq_set = &rs600_irq_set,
 495 
	.irq_set = &rs600_irq_set,
491 
	.irq_process = &rs600_irq_process,
 496 
	.irq_process = &rs600_irq_process,
492 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 497 
//	.get_vblank_counter = &rs600_get_vblank_counter,
493 
	.fence_ring_emit = &r300_fence_ring_emit,
 498 
	.fence_ring_emit = &r300_fence_ring_emit,
494 
//	.cs_parse = &r300_cs_parse,
 499 
//	.cs_parse = &r300_cs_parse,
495 
	.copy_blit = &r100_copy_blit,
 500 
	.copy_blit = &r100_copy_blit,
496 
	.copy_dma = &r200_copy_dma,
 501 
	.copy_dma = &r200_copy_dma,
497 
	.copy = &r100_copy_blit,
 502 
	.copy = &r100_copy_blit,
498 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 503 
	.get_engine_clock = &radeon_atom_get_engine_clock,
499 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 504 
	.set_engine_clock = &radeon_atom_set_engine_clock,
500 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 505 
	.get_memory_clock = &radeon_atom_get_memory_clock,
501 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 506 
	.set_memory_clock = &radeon_atom_set_memory_clock,
502 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 507 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
503 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 508 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
504 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 509 
	.set_clock_gating = &radeon_atom_set_clock_gating,
505 
	.set_surface_reg = r100_set_surface_reg,
 510 
	.set_surface_reg = r100_set_surface_reg,
506 
	.clear_surface_reg = r100_clear_surface_reg,
 511 
	.clear_surface_reg = r100_clear_surface_reg,
507 
	.bandwidth_update = &rv515_bandwidth_update,
 512 
	.bandwidth_update = &rv515_bandwidth_update,
508 
	.hpd_init = &rs600_hpd_init,
 513 
	.hpd_init = &rs600_hpd_init,
509 
	.hpd_fini = &rs600_hpd_fini,
 514 
	.hpd_fini = &rs600_hpd_fini,
510 
	.hpd_sense = &rs600_hpd_sense,
 515 
	.hpd_sense = &rs600_hpd_sense,
511 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 516 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
512 
	.ioctl_wait_idle = NULL,
 517 
	.ioctl_wait_idle = NULL,
- 
 
 518 
	.gui_idle = &r100_gui_idle,
513 
};
 519 
};
514 
 
 520 
 
515 
static struct radeon_asic r600_asic = {
 521 
static struct radeon_asic r600_asic = {
516 
	.init = &r600_init,
 522 
	.init = &r600_init,
517 
//	.fini = &r600_fini,
 523 
//	.fini = &r600_fini,
518 
//	.suspend = &r600_suspend,
 524 
//	.suspend = &r600_suspend,
519 
//	.resume = &r600_resume,
 525 
//	.resume = &r600_resume,
520 
	.cp_commit = &r600_cp_commit,
 526 
	.cp_commit = &r600_cp_commit,
521 
	.vga_set_state = &r600_vga_set_state,
 527 
	.vga_set_state = &r600_vga_set_state,
522 
	.asic_reset = &r600_asic_reset,
 528 
	.asic_reset = &r600_asic_reset,
523 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 529 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
524 
	.gart_set_page = &rs600_gart_set_page,
 530 
	.gart_set_page = &rs600_gart_set_page,
525 
	.ring_test = &r600_ring_test,
 531 
	.ring_test = &r600_ring_test,
526 
	.ring_ib_execute = &r600_ring_ib_execute,
 532 
	.ring_ib_execute = &r600_ring_ib_execute,
527 
	.irq_set = &r600_irq_set,
 533 
	.irq_set = &r600_irq_set,
528 
	.irq_process = &r600_irq_process,
 534 
	.irq_process = &r600_irq_process,
529 
	.fence_ring_emit = &r600_fence_ring_emit,
 535 
	.fence_ring_emit = &r600_fence_ring_emit,
530 
//	.cs_parse = &r600_cs_parse,
 536 
//	.cs_parse = &r600_cs_parse,
531 
	.copy_blit = &r600_copy_blit,
 537 
	.copy_blit = &r600_copy_blit,
532 
	.copy_dma = &r600_copy_blit,
 538 
	.copy_dma = NULL,
533 
	.copy = &r600_copy_blit,
 539 
	.copy = &r600_copy_blit,
534 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 540 
	.get_engine_clock = &radeon_atom_get_engine_clock,
535 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 541 
	.set_engine_clock = &radeon_atom_set_engine_clock,
536 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 542 
	.get_memory_clock = &radeon_atom_get_memory_clock,
537 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 543 
	.set_memory_clock = &radeon_atom_set_memory_clock,
538 
	.get_pcie_lanes = &r600_get_pcie_lanes,
 544 
	.get_pcie_lanes = &r600_get_pcie_lanes,
539 
	.set_pcie_lanes = &r600_set_pcie_lanes,
 545 
	.set_pcie_lanes = &r600_set_pcie_lanes,
540 
	.set_clock_gating = NULL,
 546 
	.set_clock_gating = NULL,
541 
	.set_surface_reg = r600_set_surface_reg,
 547 
	.set_surface_reg = r600_set_surface_reg,
542 
	.clear_surface_reg = r600_clear_surface_reg,
 548 
	.clear_surface_reg = r600_clear_surface_reg,
543 
	.bandwidth_update = &rv515_bandwidth_update,
 549 
	.bandwidth_update = &rv515_bandwidth_update,
544 
	.hpd_init = &r600_hpd_init,
 550 
	.hpd_init = &r600_hpd_init,
545 
	.hpd_fini = &r600_hpd_fini,
 551 
	.hpd_fini = &r600_hpd_fini,
546 
	.hpd_sense = &r600_hpd_sense,
 552 
	.hpd_sense = &r600_hpd_sense,
547 
	.hpd_set_polarity = &r600_hpd_set_polarity,
 553 
	.hpd_set_polarity = &r600_hpd_set_polarity,
548 
//	.ioctl_wait_idle = r600_ioctl_wait_idle,
 554 
//	.ioctl_wait_idle = r600_ioctl_wait_idle,
549 
};
 555 
};
550 
 
 556 
 
551 
static struct radeon_asic rs780_asic = {
 557 
static struct radeon_asic rs780_asic = {
552 
	.init = &r600_init,
 558 
	.init = &r600_init,
553 
//	.fini = &r600_fini,
 559 
//	.fini = &r600_fini,
554 
//	.suspend = &r600_suspend,
 560 
//	.suspend = &r600_suspend,
555 
//	.resume = &r600_resume,
 561 
//	.resume = &r600_resume,
556 
	.cp_commit = &r600_cp_commit,
 562 
	.cp_commit = &r600_cp_commit,
557 
	.gpu_is_lockup = &r600_gpu_is_lockup,
 563 
	.gpu_is_lockup = &r600_gpu_is_lockup,
558 
	.vga_set_state = &r600_vga_set_state,
 564 
	.vga_set_state = &r600_vga_set_state,
559 
	.asic_reset = &r600_asic_reset,
 565 
	.asic_reset = &r600_asic_reset,
560 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 566 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
561 
	.gart_set_page = &rs600_gart_set_page,
 567 
	.gart_set_page = &rs600_gart_set_page,
562 
	.ring_test = &r600_ring_test,
 568 
	.ring_test = &r600_ring_test,
563 
	.ring_ib_execute = &r600_ring_ib_execute,
 569 
	.ring_ib_execute = &r600_ring_ib_execute,
564 
	.irq_set = &r600_irq_set,
 570 
	.irq_set = &r600_irq_set,
565 
	.irq_process = &r600_irq_process,
 571 
	.irq_process = &r600_irq_process,
566 
	.fence_ring_emit = &r600_fence_ring_emit,
 572 
	.fence_ring_emit = &r600_fence_ring_emit,
567 
//	.cs_parse = &r600_cs_parse,
 573 
//	.cs_parse = &r600_cs_parse,
568 
	.copy_blit = &r600_copy_blit,
 574 
	.copy_blit = &r600_copy_blit,
569 
	.copy_dma = &r600_copy_blit,
 575 
	.copy_dma = NULL,
570 
	.copy = &r600_copy_blit,
 576 
	.copy = &r600_copy_blit,
571 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 577 
	.get_engine_clock = &radeon_atom_get_engine_clock,
572 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 578 
	.set_engine_clock = &radeon_atom_set_engine_clock,
573 
	.get_memory_clock = NULL,
 579 
	.get_memory_clock = NULL,
574 
	.set_memory_clock = NULL,
 580 
	.set_memory_clock = NULL,
575 
	.get_pcie_lanes = NULL,
 581 
	.get_pcie_lanes = NULL,
576 
	.set_pcie_lanes = NULL,
 582 
	.set_pcie_lanes = NULL,
577 
	.set_clock_gating = NULL,
 583 
	.set_clock_gating = NULL,
578 
	.set_surface_reg = r600_set_surface_reg,
 584 
	.set_surface_reg = r600_set_surface_reg,
579 
	.clear_surface_reg = r600_clear_surface_reg,
 585 
	.clear_surface_reg = r600_clear_surface_reg,
580 
	.bandwidth_update = &rs690_bandwidth_update,
 586 
	.bandwidth_update = &rs690_bandwidth_update,
581 
	.hpd_init = &r600_hpd_init,
 587 
	.hpd_init = &r600_hpd_init,
582 
	.hpd_fini = &r600_hpd_fini,
 588 
	.hpd_fini = &r600_hpd_fini,
583 
	.hpd_sense = &r600_hpd_sense,
 589 
	.hpd_sense = &r600_hpd_sense,
584 
	.hpd_set_polarity = &r600_hpd_set_polarity,
 590 
	.hpd_set_polarity = &r600_hpd_set_polarity,
585 
};
 591 
};
586 
 
 592 
 
587 
static struct radeon_asic rv770_asic = {
 593 
static struct radeon_asic rv770_asic = {
588 
	.init = &rv770_init,
 594 
	.init = &rv770_init,
589 
//	.fini = &rv770_fini,
 595 
//	.fini = &rv770_fini,
590 
//	.suspend = &rv770_suspend,
 596 
//	.suspend = &rv770_suspend,
591 
//	.resume = &rv770_resume,
 597 
//	.resume = &rv770_resume,
592 
	.cp_commit = &r600_cp_commit,
 598 
	.cp_commit = &r600_cp_commit,
593 
	.asic_reset = &r600_asic_reset,
 599 
	.asic_reset = &r600_asic_reset,
594 
	.vga_set_state = &r600_vga_set_state,
 600 
	.vga_set_state = &r600_vga_set_state,
595 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 601 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
596 
	.gart_set_page = &rs600_gart_set_page,
 602 
	.gart_set_page = &rs600_gart_set_page,
597 
	.ring_test = &r600_ring_test,
 603 
	.ring_test = &r600_ring_test,
598 
	.ring_ib_execute = &r600_ring_ib_execute,
 604 
	.ring_ib_execute = &r600_ring_ib_execute,
599 
	.irq_set = &r600_irq_set,
 605 
	.irq_set = &r600_irq_set,
600 
	.irq_process = &r600_irq_process,
 606 
	.irq_process = &r600_irq_process,
601 
	.fence_ring_emit = &r600_fence_ring_emit,
 607 
	.fence_ring_emit = &r600_fence_ring_emit,
602 
//	.cs_parse = &r600_cs_parse,
 608 
//	.cs_parse = &r600_cs_parse,
603 
	.copy_blit = &r600_copy_blit,
 609 
	.copy_blit = &r600_copy_blit,
604 
	.copy_dma = &r600_copy_blit,
 610 
	.copy_dma = NULL,
605 
	.copy = &r600_copy_blit,
 611 
	.copy = &r600_copy_blit,
606 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 612 
	.get_engine_clock = &radeon_atom_get_engine_clock,
607 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 613 
	.set_engine_clock = &radeon_atom_set_engine_clock,
608 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 614 
	.get_memory_clock = &radeon_atom_get_memory_clock,
609 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 615 
	.set_memory_clock = &radeon_atom_set_memory_clock,
610 
	.get_pcie_lanes = &r600_get_pcie_lanes,
 616 
	.get_pcie_lanes = &r600_get_pcie_lanes,
611 
	.set_pcie_lanes = &r600_set_pcie_lanes,
 617 
	.set_pcie_lanes = &r600_set_pcie_lanes,
612 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 618 
	.set_clock_gating = &radeon_atom_set_clock_gating,
613 
	.set_surface_reg = r600_set_surface_reg,
 619 
	.set_surface_reg = r600_set_surface_reg,
614 
	.clear_surface_reg = r600_clear_surface_reg,
 620 
	.clear_surface_reg = r600_clear_surface_reg,
615 
	.bandwidth_update = &rv515_bandwidth_update,
 621 
	.bandwidth_update = &rv515_bandwidth_update,
616 
	.hpd_init = &r600_hpd_init,
 622 
	.hpd_init = &r600_hpd_init,
617 
	.hpd_fini = &r600_hpd_fini,
 623 
	.hpd_fini = &r600_hpd_fini,
618 
	.hpd_sense = &r600_hpd_sense,
 624 
	.hpd_sense = &r600_hpd_sense,
619 
	.hpd_set_polarity = &r600_hpd_set_polarity,
 625 
	.hpd_set_polarity = &r600_hpd_set_polarity,
620 
};
 626 
};
621 
 
 627 
 
622 
static struct radeon_asic evergreen_asic = {
 628 
static struct radeon_asic evergreen_asic = {
623 
	.init = &evergreen_init,
 629 
	.init = &evergreen_init,
624 
//	.fini = &evergreen_fini,
 630 
//	.fini = &evergreen_fini,
625 
//	.suspend = &evergreen_suspend,
 631 
//	.suspend = &evergreen_suspend,
626 
//	.resume = &evergreen_resume,
 632 
//	.resume = &evergreen_resume,
627 
	.cp_commit = &r600_cp_commit,
 633 
	.cp_commit = &r600_cp_commit,
628 
	.asic_reset = &evergreen_asic_reset,
 634 
	.asic_reset = &evergreen_asic_reset,
629 
	.vga_set_state = &r600_vga_set_state,
 635 
	.vga_set_state = &r600_vga_set_state,
630 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 636 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
631 
	.gart_set_page = &rs600_gart_set_page,
 637 
	.gart_set_page = &rs600_gart_set_page,
632 
	.ring_test = &r600_ring_test,
 638 
	.ring_test = &r600_ring_test,
633 
	.ring_ib_execute = &evergreen_ring_ib_execute,
 639 
	.ring_ib_execute = &evergreen_ring_ib_execute,
634 
	.irq_set = &evergreen_irq_set,
 640 
	.irq_set = &evergreen_irq_set,
635 
	.irq_process = &evergreen_irq_process,
 641 
	.irq_process = &evergreen_irq_process,
636 
	.fence_ring_emit = &r600_fence_ring_emit,
 642 
	.fence_ring_emit = &r600_fence_ring_emit,
637 
//	.cs_parse = &evergreen_cs_parse,
 643 
//	.cs_parse = &evergreen_cs_parse,
638 
	.copy_blit = &evergreen_copy_blit,
 644 
	.copy_blit = &evergreen_copy_blit,
639 
	.copy_dma = &evergreen_copy_blit,
 645 
	.copy_dma = NULL,
640 
	.copy = &evergreen_copy_blit,
 646 
	.copy = &evergreen_copy_blit,
641 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 647 
	.get_engine_clock = &radeon_atom_get_engine_clock,
642 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 648 
	.set_engine_clock = &radeon_atom_set_engine_clock,
643 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 649 
	.get_memory_clock = &radeon_atom_get_memory_clock,
644 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 650 
	.set_memory_clock = &radeon_atom_set_memory_clock,
645 
	.get_pcie_lanes = &r600_get_pcie_lanes,
 651 
	.get_pcie_lanes = &r600_get_pcie_lanes,
646 
	.set_pcie_lanes = &r600_set_pcie_lanes,
 652 
	.set_pcie_lanes = &r600_set_pcie_lanes,
647 
	.set_clock_gating = NULL,
 653 
	.set_clock_gating = NULL,
648 
	.set_surface_reg = r600_set_surface_reg,
 654 
	.set_surface_reg = r600_set_surface_reg,
649 
	.clear_surface_reg = r600_clear_surface_reg,
 655 
	.clear_surface_reg = r600_clear_surface_reg,
650 
	.bandwidth_update = &evergreen_bandwidth_update,
 656 
	.bandwidth_update = &evergreen_bandwidth_update,
651 
	.hpd_init = &evergreen_hpd_init,
 657 
	.hpd_init = &evergreen_hpd_init,
652 
	.hpd_fini = &evergreen_hpd_fini,
 658 
	.hpd_fini = &evergreen_hpd_fini,
653 
	.hpd_sense = &evergreen_hpd_sense,
 659 
	.hpd_sense = &evergreen_hpd_sense,
654 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
 660 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
655 
 
 661 
 
656 
};
 662 
};
657 
 
 663 
 
658 
static struct radeon_asic sumo_asic = {
 664 
static struct radeon_asic sumo_asic = {
659 
	.init = &evergreen_init,
 665 
	.init = &evergreen_init,
660 
//	.fini = &evergreen_fini,
 666 
//	.fini = &evergreen_fini,
661 
//	.suspend = &evergreen_suspend,
 667 
//	.suspend = &evergreen_suspend,
662 
//	.resume = &evergreen_resume,
 668 
//	.resume = &evergreen_resume,
663 
	.cp_commit = &r600_cp_commit,
 669 
	.cp_commit = &r600_cp_commit,
664 
	.asic_reset = &evergreen_asic_reset,
 670 
	.asic_reset = &evergreen_asic_reset,
665 
	.vga_set_state = &r600_vga_set_state,
 671 
	.vga_set_state = &r600_vga_set_state,
666 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 672 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
667 
	.gart_set_page = &rs600_gart_set_page,
 673 
	.gart_set_page = &rs600_gart_set_page,
668 
	.ring_test = &r600_ring_test,
 674 
	.ring_test = &r600_ring_test,
669 
	.ring_ib_execute = &evergreen_ring_ib_execute,
 675 
	.ring_ib_execute = &evergreen_ring_ib_execute,
670 
	.irq_set = &evergreen_irq_set,
 676 
	.irq_set = &evergreen_irq_set,
671 
	.irq_process = &evergreen_irq_process,
 677 
	.irq_process = &evergreen_irq_process,
672 
	.fence_ring_emit = &r600_fence_ring_emit,
 678 
	.fence_ring_emit = &r600_fence_ring_emit,
673 
//	.cs_parse = &r600_cs_parse,
 679 
//	.cs_parse = &r600_cs_parse,
674 
	.copy_blit = &evergreen_copy_blit,
 680 
	.copy_blit = &evergreen_copy_blit,
675 
	.copy_dma = &evergreen_copy_blit,
 681 
	.copy_dma = NULL,
676 
	.copy = &evergreen_copy_blit,
 682 
	.copy = &evergreen_copy_blit,
677 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 683 
	.get_engine_clock = &radeon_atom_get_engine_clock,
678 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 684 
	.set_engine_clock = &radeon_atom_set_engine_clock,
679 
	.get_memory_clock = NULL,
 685 
	.get_memory_clock = NULL,
680 
	.set_memory_clock = NULL,
 686 
	.set_memory_clock = NULL,
681 
	.get_pcie_lanes = NULL,
 687 
	.get_pcie_lanes = NULL,
682 
	.set_pcie_lanes = NULL,
 688 
	.set_pcie_lanes = NULL,
683 
	.set_clock_gating = NULL,
 689 
	.set_clock_gating = NULL,
684 
	.set_surface_reg = r600_set_surface_reg,
 690 
	.set_surface_reg = r600_set_surface_reg,
685 
	.clear_surface_reg = r600_clear_surface_reg,
 691 
	.clear_surface_reg = r600_clear_surface_reg,
686 
	.bandwidth_update = &evergreen_bandwidth_update,
 692 
	.bandwidth_update = &evergreen_bandwidth_update,
687 
	.hpd_init = &evergreen_hpd_init,
 693 
	.hpd_init = &evergreen_hpd_init,
688 
	.hpd_fini = &evergreen_hpd_fini,
 694 
	.hpd_fini = &evergreen_hpd_fini,
689 
	.hpd_sense = &evergreen_hpd_sense,
 695 
	.hpd_sense = &evergreen_hpd_sense,
690 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
 696 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
691 
};
 697 
};
692 
 
 698 
 
693 
static struct radeon_asic btc_asic = {
 699 
static struct radeon_asic btc_asic = {
694 
	.init = &evergreen_init,
 700 
	.init = &evergreen_init,
695 
//	.fini = &evergreen_fini,
 701 
//	.fini = &evergreen_fini,
696 
//	.suspend = &evergreen_suspend,
 702 
//	.suspend = &evergreen_suspend,
697 
//	.resume = &evergreen_resume,
 703 
//	.resume = &evergreen_resume,
698 
	.cp_commit = &r600_cp_commit,
 704 
	.cp_commit = &r600_cp_commit,
699 
	.asic_reset = &evergreen_asic_reset,
 705 
	.asic_reset = &evergreen_asic_reset,
700 
	.vga_set_state = &r600_vga_set_state,
 706 
	.vga_set_state = &r600_vga_set_state,
701 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 707 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
702 
	.gart_set_page = &rs600_gart_set_page,
 708 
	.gart_set_page = &rs600_gart_set_page,
703 
	.ring_test = &r600_ring_test,
 709 
	.ring_test = &r600_ring_test,
704 
	.ring_ib_execute = &evergreen_ring_ib_execute,
 710 
	.ring_ib_execute = &evergreen_ring_ib_execute,
705 
	.irq_set = &evergreen_irq_set,
 711 
	.irq_set = &evergreen_irq_set,
706 
	.irq_process = &evergreen_irq_process,
 712 
	.irq_process = &evergreen_irq_process,
707 
	.fence_ring_emit = &r600_fence_ring_emit,
 713 
	.fence_ring_emit = &r600_fence_ring_emit,
708 
//	.cs_parse = &evergreen_cs_parse,
 714 
//	.cs_parse = &evergreen_cs_parse,
709 
	.copy_blit = &evergreen_copy_blit,
 715 
	.copy_blit = &evergreen_copy_blit,
710 
	.copy_dma = &evergreen_copy_blit,
 716 
	.copy_dma = NULL,
711 
	.copy = &evergreen_copy_blit,
 717 
	.copy = &evergreen_copy_blit,
712 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 718 
	.get_engine_clock = &radeon_atom_get_engine_clock,
713 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 719 
	.set_engine_clock = &radeon_atom_set_engine_clock,
714 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 720 
	.get_memory_clock = &radeon_atom_get_memory_clock,
715 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 721 
	.set_memory_clock = &radeon_atom_set_memory_clock,
716 
	.get_pcie_lanes = NULL,
 722 
	.get_pcie_lanes = NULL,
717 
	.set_pcie_lanes = NULL,
 723 
	.set_pcie_lanes = NULL,
718 
	.set_clock_gating = NULL,
 724 
	.set_clock_gating = NULL,
719 
	.set_surface_reg = r600_set_surface_reg,
 725 
	.set_surface_reg = r600_set_surface_reg,
720 
	.clear_surface_reg = r600_clear_surface_reg,
 726 
	.clear_surface_reg = r600_clear_surface_reg,
721 
	.bandwidth_update = &evergreen_bandwidth_update,
 727 
	.bandwidth_update = &evergreen_bandwidth_update,
722 
	.hpd_init = &evergreen_hpd_init,
 728 
	.hpd_init = &evergreen_hpd_init,
723 
	.hpd_fini = &evergreen_hpd_fini,
 729 
	.hpd_fini = &evergreen_hpd_fini,
724 
	.hpd_sense = &evergreen_hpd_sense,
 730 
	.hpd_sense = &evergreen_hpd_sense,
725 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
 731 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
726 
};
 732 
};
727 
 
 733 
 
728 
static struct radeon_asic cayman_asic = {
 734 
static struct radeon_asic cayman_asic = {
729 
	.init = &cayman_init,
 735 
	.init = &cayman_init,
730 
//	.fini = &evergreen_fini,
 736 
//	.fini = &evergreen_fini,
731 
//	.suspend = &evergreen_suspend,
 737 
//	.suspend = &evergreen_suspend,
732 
//	.resume = &evergreen_resume,
 738 
//	.resume = &evergreen_resume,
733 
	.cp_commit = &r600_cp_commit,
 739 
	.cp_commit = &r600_cp_commit,
734 
	.asic_reset = &cayman_asic_reset,
 740 
	.asic_reset = &cayman_asic_reset,
735 
	.vga_set_state = &r600_vga_set_state,
 741 
	.vga_set_state = &r600_vga_set_state,
736 
	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
 742 
	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
737 
	.gart_set_page = &rs600_gart_set_page,
 743 
	.gart_set_page = &rs600_gart_set_page,
738 
	.ring_test = &r600_ring_test,
 744 
	.ring_test = &r600_ring_test,
739 
	.ring_ib_execute = &evergreen_ring_ib_execute,
 745 
	.ring_ib_execute = &evergreen_ring_ib_execute,
740 
	.irq_set = &evergreen_irq_set,
 746 
	.irq_set = &evergreen_irq_set,
741 
	.irq_process = &evergreen_irq_process,
 747 
	.irq_process = &evergreen_irq_process,
742 
	.fence_ring_emit = &r600_fence_ring_emit,
 748 
	.fence_ring_emit = &r600_fence_ring_emit,
743 
//	.cs_parse = &evergreen_cs_parse,
 749 
//	.cs_parse = &evergreen_cs_parse,
744 
	.copy_blit = &evergreen_copy_blit,
 750 
	.copy_blit = &evergreen_copy_blit,
745 
	.copy_dma = &evergreen_copy_blit,
 751 
	.copy_dma = NULL,
746 
	.copy = &evergreen_copy_blit,
 752 
	.copy = &evergreen_copy_blit,
747 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 753 
	.get_engine_clock = &radeon_atom_get_engine_clock,
748 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 754 
	.set_engine_clock = &radeon_atom_set_engine_clock,
749 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 755 
	.get_memory_clock = &radeon_atom_get_memory_clock,
750 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 756 
	.set_memory_clock = &radeon_atom_set_memory_clock,
751 
	.get_pcie_lanes = NULL,
 757 
	.get_pcie_lanes = NULL,
752 
	.set_pcie_lanes = NULL,
 758 
	.set_pcie_lanes = NULL,
753 
	.set_clock_gating = NULL,
 759 
	.set_clock_gating = NULL,
754 
	.set_surface_reg = r600_set_surface_reg,
 760 
	.set_surface_reg = r600_set_surface_reg,
755 
	.clear_surface_reg = r600_clear_surface_reg,
 761 
	.clear_surface_reg = r600_clear_surface_reg,
756 
	.bandwidth_update = &evergreen_bandwidth_update,
 762 
	.bandwidth_update = &evergreen_bandwidth_update,
757 
	.hpd_init = &evergreen_hpd_init,
 763 
	.hpd_init = &evergreen_hpd_init,
758 
	.hpd_fini = &evergreen_hpd_fini,
 764 
	.hpd_fini = &evergreen_hpd_fini,
759 
	.hpd_sense = &evergreen_hpd_sense,
 765 
	.hpd_sense = &evergreen_hpd_sense,
760 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
 766 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
761 
};
 767 
};
762 
 
 768 
 
763 
int radeon_asic_init(struct radeon_device *rdev)
 769 
int radeon_asic_init(struct radeon_device *rdev)
764 
{
 770 
{
765 
	radeon_register_accessor_init(rdev);
 771 
	radeon_register_accessor_init(rdev);
766 
 
 772 
 
767 
	/* set the number of crtcs */
 773 
	/* set the number of crtcs */
768 
	if (rdev->flags & RADEON_SINGLE_CRTC)
 774 
	if (rdev->flags & RADEON_SINGLE_CRTC)
769 
		rdev->num_crtc = 1;
 775 
		rdev->num_crtc = 1;
770 
	else
 776 
	else
771 
		rdev->num_crtc = 2;
 777 
		rdev->num_crtc = 2;
772 
 
 778 
 
773 
	switch (rdev->family) {
 779 
	switch (rdev->family) {
774 
	case CHIP_R100:
 780 
	case CHIP_R100:
775 
	case CHIP_RV100:
 781 
	case CHIP_RV100:
776 
	case CHIP_RS100:
 782 
	case CHIP_RS100:
777 
	case CHIP_RV200:
 783 
	case CHIP_RV200:
778 
	case CHIP_RS200:
 784 
	case CHIP_RS200:
779 
		rdev->asic = &r100_asic;
 785 
		rdev->asic = &r100_asic;
780 
		break;
 786 
		break;
781 
	case CHIP_R200:
 787 
	case CHIP_R200:
782 
	case CHIP_RV250:
 788 
	case CHIP_RV250:
783 
	case CHIP_RS300:
 789 
	case CHIP_RS300:
784 
	case CHIP_RV280:
 790 
	case CHIP_RV280:
785 
		rdev->asic = &r200_asic;
 791 
		rdev->asic = &r200_asic;
786 
		break;
 792 
		break;
787 
	case CHIP_R300:
 793 
	case CHIP_R300:
788 
	case CHIP_R350:
 794 
	case CHIP_R350:
789 
	case CHIP_RV350:
 795 
	case CHIP_RV350:
790 
	case CHIP_RV380:
 796 
	case CHIP_RV380:
791 
		if (rdev->flags & RADEON_IS_PCIE)
 797 
		if (rdev->flags & RADEON_IS_PCIE)
792 
			rdev->asic = &r300_asic_pcie;
 798 
			rdev->asic = &r300_asic_pcie;
793 
		else
 799 
		else
794 
			rdev->asic = &r300_asic;
 800 
			rdev->asic = &r300_asic;
795 
		break;
 801 
		break;
796 
	case CHIP_R420:
 802 
	case CHIP_R420:
797 
	case CHIP_R423:
 803 
	case CHIP_R423:
798 
	case CHIP_RV410:
 804 
	case CHIP_RV410:
799 
		rdev->asic = &r420_asic;
 805 
		rdev->asic = &r420_asic;
800 
		/* handle macs */
 806 
		/* handle macs */
801 
		if (rdev->bios == NULL) {
 807 
		if (rdev->bios == NULL) {
802 
			rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
 808 
			rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
803 
			rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
 809 
			rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
804 
			rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
 810 
			rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
805 
			rdev->asic->set_memory_clock = NULL;
 811 
			rdev->asic->set_memory_clock = NULL;
806 
		}
 812 
		}
807 
		break;
 813 
		break;
808 
	case CHIP_RS400:
 814 
	case CHIP_RS400:
809 
	case CHIP_RS480:
 815 
	case CHIP_RS480:
810 
		rdev->asic = &rs400_asic;
 816 
		rdev->asic = &rs400_asic;
811 
		break;
 817 
		break;
812 
	case CHIP_RS600:
 818 
	case CHIP_RS600:
813 
		rdev->asic = &rs600_asic;
 819 
		rdev->asic = &rs600_asic;
814 
		break;
 820 
		break;
815 
	case CHIP_RS690:
 821 
	case CHIP_RS690:
816 
	case CHIP_RS740:
 822 
	case CHIP_RS740:
817 
		rdev->asic = &rs690_asic;
 823 
		rdev->asic = &rs690_asic;
818 
		break;
 824 
		break;
819 
	case CHIP_RV515:
 825 
	case CHIP_RV515:
820 
		rdev->asic = &rv515_asic;
 826 
		rdev->asic = &rv515_asic;
821 
		break;
 827 
		break;
822 
	case CHIP_R520:
 828 
	case CHIP_R520:
823 
	case CHIP_RV530:
 829 
	case CHIP_RV530:
824 
	case CHIP_RV560:
 830 
	case CHIP_RV560:
825 
	case CHIP_RV570:
 831 
	case CHIP_RV570:
826 
	case CHIP_R580:
 832 
	case CHIP_R580:
827 
		rdev->asic = &r520_asic;
 833 
		rdev->asic = &r520_asic;
828 
		break;
 834 
		break;
829 
	case CHIP_R600:
 835 
	case CHIP_R600:
830 
	case CHIP_RV610:
 836 
	case CHIP_RV610:
831 
	case CHIP_RV630:
 837 
	case CHIP_RV630:
832 
	case CHIP_RV620:
 838 
	case CHIP_RV620:
833 
	case CHIP_RV635:
 839 
	case CHIP_RV635:
834 
	case CHIP_RV670:
 840 
	case CHIP_RV670:
835 
		rdev->asic = &r600_asic;
 841 
		rdev->asic = &r600_asic;
836 
		break;
 842 
		break;
837 
	case CHIP_RS780:
 843 
	case CHIP_RS780:
838 
	case CHIP_RS880:
 844 
	case CHIP_RS880:
839 
		rdev->asic = &rs780_asic;
 845 
		rdev->asic = &rs780_asic;
840 
		break;
 846 
		break;
841 
	case CHIP_RV770:
 847 
	case CHIP_RV770:
842 
	case CHIP_RV730:
 848 
	case CHIP_RV730:
843 
	case CHIP_RV710:
 849 
	case CHIP_RV710:
844 
	case CHIP_RV740:
 850 
	case CHIP_RV740:
845 
		rdev->asic = &rv770_asic;
 851 
		rdev->asic = &rv770_asic;
846 
		break;
 852 
		break;
847 
	case CHIP_CEDAR:
 853 
	case CHIP_CEDAR:
848 
	case CHIP_REDWOOD:
 854 
	case CHIP_REDWOOD:
849 
	case CHIP_JUNIPER:
 855 
	case CHIP_JUNIPER:
850 
	case CHIP_CYPRESS:
 856 
	case CHIP_CYPRESS:
851 
	case CHIP_HEMLOCK:
 857 
	case CHIP_HEMLOCK:
852 
		/* set num crtcs */
 858 
		/* set num crtcs */
853 
		if (rdev->family == CHIP_CEDAR)
 859 
		if (rdev->family == CHIP_CEDAR)
854 
			rdev->num_crtc = 4;
 860 
			rdev->num_crtc = 4;
855 
		else
 861 
		else
856 
			rdev->num_crtc = 6;
 862 
			rdev->num_crtc = 6;
857 
		rdev->asic = &evergreen_asic;
 863 
		rdev->asic = &evergreen_asic;
858 
		break;
 864 
		break;
859 
	case CHIP_PALM:
 865 
	case CHIP_PALM:
860 
	case CHIP_SUMO:
 866 
	case CHIP_SUMO:
861 
	case CHIP_SUMO2:
 867 
	case CHIP_SUMO2:
862 
		rdev->asic = &sumo_asic;
 868 
		rdev->asic = &sumo_asic;
863 
		break;
 869 
		break;
864 
	case CHIP_BARTS:
 870 
	case CHIP_BARTS:
865 
	case CHIP_TURKS:
 871 
	case CHIP_TURKS:
866 
	case CHIP_CAICOS:
 872 
	case CHIP_CAICOS:
867 
		/* set num crtcs */
 873 
		/* set num crtcs */
868 
		if (rdev->family == CHIP_CAICOS)
 874 
		if (rdev->family == CHIP_CAICOS)
869 
			rdev->num_crtc = 4;
 875 
			rdev->num_crtc = 4;
870 
		else
 876 
		else
871 
			rdev->num_crtc = 6;
 877 
			rdev->num_crtc = 6;
872 
		rdev->asic = &btc_asic;
 878 
		rdev->asic = &btc_asic;
873 
		break;
 879 
		break;
874 
	case CHIP_CAYMAN:
 880 
	case CHIP_CAYMAN:
875 
		rdev->asic = &cayman_asic;
 881 
		rdev->asic = &cayman_asic;
876 
		/* set num crtcs */
 882 
		/* set num crtcs */
877 
		rdev->num_crtc = 6;
 883 
		rdev->num_crtc = 6;
878 
		break;
 884 
		break;
879 
	default:
 885 
	default:
880 
		/* FIXME: not supported yet */
 886 
		/* FIXME: not supported yet */
881 
		return -EINVAL;
 887 
		return -EINVAL;
882 
	}
 888 
	}
883 
 
 889 
 
884 
	if (rdev->flags & RADEON_IS_IGP) {
 890 
	if (rdev->flags & RADEON_IS_IGP) {
885 
		rdev->asic->get_memory_clock = NULL;
 891 
		rdev->asic->get_memory_clock = NULL;
886 
		rdev->asic->set_memory_clock = NULL;
 892 
		rdev->asic->set_memory_clock = NULL;
887 
	}
 893 
	}
888 
 
 894 
 
889 
	return 0;
 895 
	return 0;
890 
}
 896 
}