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1 
/*
 1 
/*
2 
 * Copyright 2008 Advanced Micro Devices, Inc.
 2 
 * Copyright 2008 Advanced Micro Devices, Inc.
3 
 * Copyright 2008 Red Hat Inc.
 3 
 * Copyright 2008 Red Hat Inc.
4 
 * Copyright 2009 Jerome Glisse.
 4 
 * Copyright 2009 Jerome Glisse.
5 
 *
 5 
 *
6 
 * Permission is hereby granted, free of charge, to any person obtaining a
 6 
 * Permission is hereby granted, free of charge, to any person obtaining a
7 
 * copy of this software and associated documentation files (the "Software"),
 7 
 * copy of this software and associated documentation files (the "Software"),
8 
 * to deal in the Software without restriction, including without limitation
 8 
 * to deal in the Software without restriction, including without limitation
9 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 9 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 
 * and/or sell copies of the Software, and to permit persons to whom the
 10 
 * and/or sell copies of the Software, and to permit persons to whom the
11 
 * Software is furnished to do so, subject to the following conditions:
 11 
 * Software is furnished to do so, subject to the following conditions:
12 
 *
 12 
 *
13 
 * The above copyright notice and this permission notice shall be included in
 13 
 * The above copyright notice and this permission notice shall be included in
14 
 * all copies or substantial portions of the Software.
 14 
 * all copies or substantial portions of the Software.
15 
 *
 15 
 *
16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 
 * OTHER DEALINGS IN THE SOFTWARE.
 22 
 * OTHER DEALINGS IN THE SOFTWARE.
23 
 *
 23 
 *
24 
 * Authors: Dave Airlie
 24 
 * Authors: Dave Airlie
25 
 *          Alex Deucher
 25 
 *          Alex Deucher
26 
 *          Jerome Glisse
 26 
 *          Jerome Glisse
27 
 */
 27 
 */
28 
 
 28 
 
29 
//#include
29 
//#include
30 
#include
30 
#include
31 
#include
31 
#include
32 
#include
32 
#include
33 
//#include
33 
//#include
34 
//#include
34 
//#include
35 
#include "radeon_reg.h"
 35 
#include "radeon_reg.h"
36 
#include "radeon.h"
 36 
#include "radeon.h"
37 
#include "radeon_asic.h"
 37 
#include "radeon_asic.h"
38 
#include "atom.h"
 38 
#include "atom.h"
39 
 
 39 
 
40 
/*
 40 
/*
41 
 * Registers accessors functions.
 41 
 * Registers accessors functions.
42 
 */
 42 
 */
43 
static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
 43 
static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44 
{
 44 
{
45 
	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 45 
	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 
	BUG_ON(1);
 46 
	BUG_ON(1);
47 
	return 0;
 47 
	return 0;
48 
}
 48 
}
49 
 
 49 
 
50 
static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 50 
static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51 
{
 51 
{
52 
	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 52 
	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 
		  reg, v);
 53 
		  reg, v);
54 
	BUG_ON(1);
 54 
	BUG_ON(1);
55 
}
 55 
}
56 
 
 56 
 
57 
static void radeon_register_accessor_init(struct radeon_device *rdev)
 57 
static void radeon_register_accessor_init(struct radeon_device *rdev)
58 
{
 58 
{
59 
	rdev->mc_rreg = &radeon_invalid_rreg;
 59 
	rdev->mc_rreg = &radeon_invalid_rreg;
60 
	rdev->mc_wreg = &radeon_invalid_wreg;
 60 
	rdev->mc_wreg = &radeon_invalid_wreg;
61 
	rdev->pll_rreg = &radeon_invalid_rreg;
 61 
	rdev->pll_rreg = &radeon_invalid_rreg;
62 
	rdev->pll_wreg = &radeon_invalid_wreg;
 62 
	rdev->pll_wreg = &radeon_invalid_wreg;
63 
	rdev->pciep_rreg = &radeon_invalid_rreg;
 63 
	rdev->pciep_rreg = &radeon_invalid_rreg;
64 
	rdev->pciep_wreg = &radeon_invalid_wreg;
 64 
	rdev->pciep_wreg = &radeon_invalid_wreg;
65 
 
 65 
 
66 
	/* Don't change order as we are overridding accessor. */
 66 
	/* Don't change order as we are overridding accessor. */
67 
	if (rdev->family < CHIP_RV515) {
 67 
	if (rdev->family < CHIP_RV515) {
68 
		rdev->pcie_reg_mask = 0xff;
 68 
		rdev->pcie_reg_mask = 0xff;
69 
	} else {
 69 
	} else {
70 
		rdev->pcie_reg_mask = 0x7ff;
 70 
		rdev->pcie_reg_mask = 0x7ff;
71 
	}
 71 
	}
72 
	/* FIXME: not sure here */
 72 
	/* FIXME: not sure here */
73 
	if (rdev->family <= CHIP_R580) {
 73 
	if (rdev->family <= CHIP_R580) {
74 
		rdev->pll_rreg = &r100_pll_rreg;
 74 
		rdev->pll_rreg = &r100_pll_rreg;
75 
		rdev->pll_wreg = &r100_pll_wreg;
 75 
		rdev->pll_wreg = &r100_pll_wreg;
76 
	}
 76 
	}
77 
	if (rdev->family >= CHIP_R420) {
 77 
	if (rdev->family >= CHIP_R420) {
78 
		rdev->mc_rreg = &r420_mc_rreg;
 78 
		rdev->mc_rreg = &r420_mc_rreg;
79 
		rdev->mc_wreg = &r420_mc_wreg;
 79 
		rdev->mc_wreg = &r420_mc_wreg;
80 
	}
 80 
	}
81 
	if (rdev->family >= CHIP_RV515) {
 81 
	if (rdev->family >= CHIP_RV515) {
82 
		rdev->mc_rreg = &rv515_mc_rreg;
 82 
		rdev->mc_rreg = &rv515_mc_rreg;
83 
		rdev->mc_wreg = &rv515_mc_wreg;
 83 
		rdev->mc_wreg = &rv515_mc_wreg;
84 
	}
 84 
	}
85 
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 85 
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 
		rdev->mc_rreg = &rs400_mc_rreg;
 86 
		rdev->mc_rreg = &rs400_mc_rreg;
87 
		rdev->mc_wreg = &rs400_mc_wreg;
 87 
		rdev->mc_wreg = &rs400_mc_wreg;
88 
	}
 88 
	}
89 
	if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 89 
	if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 
		rdev->mc_rreg = &rs690_mc_rreg;
 90 
		rdev->mc_rreg = &rs690_mc_rreg;
91 
		rdev->mc_wreg = &rs690_mc_wreg;
 91 
		rdev->mc_wreg = &rs690_mc_wreg;
92 
	}
 92 
	}
93 
	if (rdev->family == CHIP_RS600) {
 93 
	if (rdev->family == CHIP_RS600) {
94 
		rdev->mc_rreg = &rs600_mc_rreg;
 94 
		rdev->mc_rreg = &rs600_mc_rreg;
95 
		rdev->mc_wreg = &rs600_mc_wreg;
 95 
		rdev->mc_wreg = &rs600_mc_wreg;
96 
	}
 96 
	}
97 
	if (rdev->family >= CHIP_R600) {
 97 
	if (rdev->family >= CHIP_R600) {
98 
		rdev->pciep_rreg = &r600_pciep_rreg;
 98 
		rdev->pciep_rreg = &r600_pciep_rreg;
99 
		rdev->pciep_wreg = &r600_pciep_wreg;
 99 
		rdev->pciep_wreg = &r600_pciep_wreg;
100 
	}
 100 
	}
101 
}
 101 
}
102 
 
 102 
 
103 
 
 103 
 
104 
/* helper to disable agp */
 104 
/* helper to disable agp */
105 
void radeon_agp_disable(struct radeon_device *rdev)
 105 
void radeon_agp_disable(struct radeon_device *rdev)
106 
{
 106 
{
107 
	rdev->flags &= ~RADEON_IS_AGP;
 107 
	rdev->flags &= ~RADEON_IS_AGP;
108 
	if (rdev->family >= CHIP_R600) {
 108 
	if (rdev->family >= CHIP_R600) {
109 
		DRM_INFO("Forcing AGP to PCIE mode\n");
 109 
		DRM_INFO("Forcing AGP to PCIE mode\n");
110 
		rdev->flags |= RADEON_IS_PCIE;
 110 
		rdev->flags |= RADEON_IS_PCIE;
111 
	} else if (rdev->family >= CHIP_RV515 ||
 111 
	} else if (rdev->family >= CHIP_RV515 ||
112 
			rdev->family == CHIP_RV380 ||
 112 
			rdev->family == CHIP_RV380 ||
113 
			rdev->family == CHIP_RV410 ||
 113 
			rdev->family == CHIP_RV410 ||
114 
			rdev->family == CHIP_R423) {
 114 
			rdev->family == CHIP_R423) {
115 
		DRM_INFO("Forcing AGP to PCIE mode\n");
 115 
		DRM_INFO("Forcing AGP to PCIE mode\n");
116 
		rdev->flags |= RADEON_IS_PCIE;
 116 
		rdev->flags |= RADEON_IS_PCIE;
117 
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 117 
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
118 
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 118 
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
119 
	} else {
 119 
	} else {
120 
		DRM_INFO("Forcing AGP to PCI mode\n");
 120 
		DRM_INFO("Forcing AGP to PCI mode\n");
121 
		rdev->flags |= RADEON_IS_PCI;
 121 
		rdev->flags |= RADEON_IS_PCI;
122 
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 122 
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
123 
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 123 
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
124 
	}
 124 
	}
125 
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 125 
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126 
}
 126 
}
127 
 
 127 
 
128 
/*
 128 
/*
129 
 * ASIC
 129 
 * ASIC
130 
 */
 130 
 */
131 
static struct radeon_asic r100_asic = {
 131 
static struct radeon_asic r100_asic = {
132 
	.init = &r100_init,
 132 
	.init = &r100_init,
133 
//	.fini = &r100_fini,
 133 
//	.fini = &r100_fini,
134 
//	.suspend = &r100_suspend,
 134 
//	.suspend = &r100_suspend,
135 
//	.resume = &r100_resume,
 135 
//	.resume = &r100_resume,
136 
//	.vga_set_state = &r100_vga_set_state,
 136 
//	.vga_set_state = &r100_vga_set_state,
137 
	.asic_reset = &r100_asic_reset,
 137 
	.asic_reset = &r100_asic_reset,
138 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 138 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
139 
	.gart_set_page = &r100_pci_gart_set_page,
 139 
	.gart_set_page = &r100_pci_gart_set_page,
140 
	.cp_commit = &r100_cp_commit,
 140 
	.cp_commit = &r100_cp_commit,
141 
	.ring_start = &r100_ring_start,
 141 
	.ring_start = &r100_ring_start,
142 
	.ring_test = &r100_ring_test,
 142 
	.ring_test = &r100_ring_test,
143 
//	.ring_ib_execute = &r100_ring_ib_execute,
 143 
//	.ring_ib_execute = &r100_ring_ib_execute,
144 
//	.irq_set = &r100_irq_set,
 144 
//	.irq_set = &r100_irq_set,
145 
//	.irq_process = &r100_irq_process,
 145 
//	.irq_process = &r100_irq_process,
146 
//	.get_vblank_counter = &r100_get_vblank_counter,
 146 
//	.get_vblank_counter = &r100_get_vblank_counter,
147 
	.fence_ring_emit = &r100_fence_ring_emit,
 147 
	.fence_ring_emit = &r100_fence_ring_emit,
148 
//	.cs_parse = &r100_cs_parse,
 148 
//	.cs_parse = &r100_cs_parse,
149 
//	.copy_blit = &r100_copy_blit,
 149 
//	.copy_blit = &r100_copy_blit,
150 
//	.copy_dma = NULL,
 150 
//	.copy_dma = NULL,
151 
//	.copy = &r100_copy_blit,
 151 
//	.copy = &r100_copy_blit,
152 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 152 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
153 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 153 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
154 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 154 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
155 
	.set_memory_clock = NULL,
 155 
	.set_memory_clock = NULL,
156 
	.get_pcie_lanes = NULL,
 156 
	.get_pcie_lanes = NULL,
157 
	.set_pcie_lanes = NULL,
 157 
	.set_pcie_lanes = NULL,
158 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 158 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
159 
	.set_surface_reg = r100_set_surface_reg,
 159 
	.set_surface_reg = r100_set_surface_reg,
160 
	.clear_surface_reg = r100_clear_surface_reg,
 160 
	.clear_surface_reg = r100_clear_surface_reg,
161 
	.bandwidth_update = &r100_bandwidth_update,
 161 
	.bandwidth_update = &r100_bandwidth_update,
162 
	.hpd_init = &r100_hpd_init,
 162 
	.hpd_init = &r100_hpd_init,
163 
	.hpd_fini = &r100_hpd_fini,
 163 
	.hpd_fini = &r100_hpd_fini,
164 
	.hpd_sense = &r100_hpd_sense,
 164 
	.hpd_sense = &r100_hpd_sense,
165 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 165 
	.hpd_set_polarity = &r100_hpd_set_polarity,
166 
	.ioctl_wait_idle = NULL,
 166 
	.ioctl_wait_idle = NULL,
167 
};
 167 
};
168 
 
 168 
 
169 
static struct radeon_asic r200_asic = {
 169 
static struct radeon_asic r200_asic = {
170 
	.init = &r100_init,
 170 
	.init = &r100_init,
171 
//	.fini = &r100_fini,
 171 
//	.fini = &r100_fini,
172 
//	.suspend = &r100_suspend,
 172 
//	.suspend = &r100_suspend,
173 
//	.resume = &r100_resume,
 173 
//	.resume = &r100_resume,
174 
//	.vga_set_state = &r100_vga_set_state,
 174 
//	.vga_set_state = &r100_vga_set_state,
175 
	.asic_reset = &r100_asic_reset,
 175 
	.asic_reset = &r100_asic_reset,
176 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 176 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
177 
	.gart_set_page = &r100_pci_gart_set_page,
 177 
	.gart_set_page = &r100_pci_gart_set_page,
178 
	.cp_commit = &r100_cp_commit,
 178 
	.cp_commit = &r100_cp_commit,
179 
	.ring_start = &r100_ring_start,
 179 
	.ring_start = &r100_ring_start,
180 
	.ring_test = &r100_ring_test,
 180 
	.ring_test = &r100_ring_test,
181 
//	.ring_ib_execute = &r100_ring_ib_execute,
 181 
//	.ring_ib_execute = &r100_ring_ib_execute,
182 
//	.irq_set = &r100_irq_set,
 182 
//	.irq_set = &r100_irq_set,
183 
//	.irq_process = &r100_irq_process,
 183 
//	.irq_process = &r100_irq_process,
184 
//	.get_vblank_counter = &r100_get_vblank_counter,
 184 
//	.get_vblank_counter = &r100_get_vblank_counter,
185 
	.fence_ring_emit = &r100_fence_ring_emit,
 185 
	.fence_ring_emit = &r100_fence_ring_emit,
186 
//	.cs_parse = &r100_cs_parse,
 186 
//	.cs_parse = &r100_cs_parse,
187 
//	.copy_blit = &r100_copy_blit,
 187 
//	.copy_blit = &r100_copy_blit,
188 
//	.copy_dma = NULL,
 188 
//	.copy_dma = NULL,
189 
//	.copy = &r100_copy_blit,
 189 
//	.copy = &r100_copy_blit,
190 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 190 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
191 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 191 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
192 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 192 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
193 
	.set_memory_clock = NULL,
 193 
	.set_memory_clock = NULL,
194 
	.set_pcie_lanes = NULL,
 194 
	.set_pcie_lanes = NULL,
195 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 195 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
196 
	.set_surface_reg = r100_set_surface_reg,
 196 
	.set_surface_reg = r100_set_surface_reg,
197 
	.clear_surface_reg = r100_clear_surface_reg,
 197 
	.clear_surface_reg = r100_clear_surface_reg,
198 
	.bandwidth_update = &r100_bandwidth_update,
 198 
	.bandwidth_update = &r100_bandwidth_update,
199 
	.hpd_init = &r100_hpd_init,
 199 
	.hpd_init = &r100_hpd_init,
200 
	.hpd_fini = &r100_hpd_fini,
 200 
	.hpd_fini = &r100_hpd_fini,
201 
	.hpd_sense = &r100_hpd_sense,
 201 
	.hpd_sense = &r100_hpd_sense,
202 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 202 
	.hpd_set_polarity = &r100_hpd_set_polarity,
203 
	.ioctl_wait_idle = NULL,
 203 
	.ioctl_wait_idle = NULL,
204 
};
 204 
};
205 
 
 205 
 
206 
static struct radeon_asic r300_asic = {
 206 
static struct radeon_asic r300_asic = {
207 
	.init = &r300_init,
 207 
	.init = &r300_init,
208 
//	.fini = &r300_fini,
 208 
//	.fini = &r300_fini,
209 
//	.suspend = &r300_suspend,
 209 
//	.suspend = &r300_suspend,
210 
//	.resume = &r300_resume,
 210 
//	.resume = &r300_resume,
211 
//	.vga_set_state = &r100_vga_set_state,
 211 
//	.vga_set_state = &r100_vga_set_state,
212 
	.asic_reset = &r300_asic_reset,
 212 
	.asic_reset = &r300_asic_reset,
213 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 213 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
214 
	.gart_set_page = &r100_pci_gart_set_page,
 214 
	.gart_set_page = &r100_pci_gart_set_page,
215 
	.cp_commit = &r100_cp_commit,
 215 
	.cp_commit = &r100_cp_commit,
216 
	.ring_start = &r300_ring_start,
 216 
	.ring_start = &r300_ring_start,
217 
	.ring_test = &r100_ring_test,
 217 
	.ring_test = &r100_ring_test,
218 
//	.ring_ib_execute = &r100_ring_ib_execute,
 218 
//	.ring_ib_execute = &r100_ring_ib_execute,
219 
//	.irq_set = &r100_irq_set,
 219 
//	.irq_set = &r100_irq_set,
220 
//	.irq_process = &r100_irq_process,
 220 
//	.irq_process = &r100_irq_process,
221 
//	.get_vblank_counter = &r100_get_vblank_counter,
 221 
//	.get_vblank_counter = &r100_get_vblank_counter,
222 
	.fence_ring_emit = &r300_fence_ring_emit,
 222 
	.fence_ring_emit = &r300_fence_ring_emit,
223 
//	.cs_parse = &r300_cs_parse,
 223 
//	.cs_parse = &r300_cs_parse,
224 
//	.copy_blit = &r100_copy_blit,
 224 
//	.copy_blit = &r100_copy_blit,
225 
//	.copy_dma = &r300_copy_dma,
 225 
//	.copy_dma = &r300_copy_dma,
226 
//	.copy = &r100_copy_blit,
 226 
//	.copy = &r100_copy_blit,
227 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 227 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
228 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 228 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
229 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 229 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
230 
	.set_memory_clock = NULL,
 230 
	.set_memory_clock = NULL,
231 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 231 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
232 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 232 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
233 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 233 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
234 
	.set_surface_reg = r100_set_surface_reg,
 234 
	.set_surface_reg = r100_set_surface_reg,
235 
	.clear_surface_reg = r100_clear_surface_reg,
 235 
	.clear_surface_reg = r100_clear_surface_reg,
236 
	.bandwidth_update = &r100_bandwidth_update,
 236 
	.bandwidth_update = &r100_bandwidth_update,
237 
	.hpd_init = &r100_hpd_init,
 237 
	.hpd_init = &r100_hpd_init,
238 
	.hpd_fini = &r100_hpd_fini,
 238 
	.hpd_fini = &r100_hpd_fini,
239 
	.hpd_sense = &r100_hpd_sense,
 239 
	.hpd_sense = &r100_hpd_sense,
240 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 240 
	.hpd_set_polarity = &r100_hpd_set_polarity,
241 
	.ioctl_wait_idle = NULL,
 241 
	.ioctl_wait_idle = NULL,
242 
};
 242 
};
243 
 
 243 
 
244 
static struct radeon_asic r300_asic_pcie = {
 244 
static struct radeon_asic r300_asic_pcie = {
245 
	.init = &r300_init,
 245 
	.init = &r300_init,
246 
//	.fini = &r300_fini,
 246 
//	.fini = &r300_fini,
247 
//	.suspend = &r300_suspend,
 247 
//	.suspend = &r300_suspend,
248 
//	.resume = &r300_resume,
 248 
//	.resume = &r300_resume,
249 
//	.vga_set_state = &r100_vga_set_state,
 249 
//	.vga_set_state = &r100_vga_set_state,
250 
	.asic_reset = &r300_asic_reset,
 250 
	.asic_reset = &r300_asic_reset,
251 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 251 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
252 
	.gart_set_page = &rv370_pcie_gart_set_page,
 252 
	.gart_set_page = &rv370_pcie_gart_set_page,
253 
	.cp_commit = &r100_cp_commit,
 253 
	.cp_commit = &r100_cp_commit,
254 
	.ring_start = &r300_ring_start,
 254 
	.ring_start = &r300_ring_start,
255 
	.ring_test = &r100_ring_test,
 255 
	.ring_test = &r100_ring_test,
256 
//	.ring_ib_execute = &r100_ring_ib_execute,
 256 
//	.ring_ib_execute = &r100_ring_ib_execute,
257 
//	.irq_set = &r100_irq_set,
 257 
//	.irq_set = &r100_irq_set,
258 
//	.irq_process = &r100_irq_process,
 258 
//	.irq_process = &r100_irq_process,
259 
//	.get_vblank_counter = &r100_get_vblank_counter,
 259 
//	.get_vblank_counter = &r100_get_vblank_counter,
260 
	.fence_ring_emit = &r300_fence_ring_emit,
 260 
	.fence_ring_emit = &r300_fence_ring_emit,
261 
//	.cs_parse = &r300_cs_parse,
 261 
//	.cs_parse = &r300_cs_parse,
262 
//	.copy_blit = &r100_copy_blit,
 262 
//	.copy_blit = &r100_copy_blit,
263 
//	.copy_dma = &r300_copy_dma,
 263 
//	.copy_dma = &r300_copy_dma,
264 
//	.copy = &r100_copy_blit,
 264 
//	.copy = &r100_copy_blit,
265 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 265 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
266 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 266 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
267 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 267 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
268 
	.set_memory_clock = NULL,
 268 
	.set_memory_clock = NULL,
269 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 269 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
270 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 270 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
271 
	.set_surface_reg = r100_set_surface_reg,
 271 
	.set_surface_reg = r100_set_surface_reg,
272 
	.clear_surface_reg = r100_clear_surface_reg,
 272 
	.clear_surface_reg = r100_clear_surface_reg,
273 
	.bandwidth_update = &r100_bandwidth_update,
 273 
	.bandwidth_update = &r100_bandwidth_update,
274 
	.hpd_init = &r100_hpd_init,
 274 
	.hpd_init = &r100_hpd_init,
275 
	.hpd_fini = &r100_hpd_fini,
 275 
	.hpd_fini = &r100_hpd_fini,
276 
	.hpd_sense = &r100_hpd_sense,
 276 
	.hpd_sense = &r100_hpd_sense,
277 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 277 
	.hpd_set_polarity = &r100_hpd_set_polarity,
278 
	.ioctl_wait_idle = NULL,
 278 
	.ioctl_wait_idle = NULL,
279 
};
 279 
};
280 
 
 280 
 
281 
static struct radeon_asic r420_asic = {
 281 
static struct radeon_asic r420_asic = {
282 
	.init = &r420_init,
 282 
	.init = &r420_init,
283 
//	.fini = &r420_fini,
 283 
//	.fini = &r420_fini,
284 
//	.suspend = &r420_suspend,
 284 
//	.suspend = &r420_suspend,
285 
//	.resume = &r420_resume,
 285 
//	.resume = &r420_resume,
286 
//	.vga_set_state = &r100_vga_set_state,
 286 
//	.vga_set_state = &r100_vga_set_state,
287 
	.asic_reset = &r300_asic_reset,
 287 
	.asic_reset = &r300_asic_reset,
288 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 288 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
289 
	.gart_set_page = &rv370_pcie_gart_set_page,
 289 
	.gart_set_page = &rv370_pcie_gart_set_page,
290 
	.cp_commit = &r100_cp_commit,
 290 
	.cp_commit = &r100_cp_commit,
291 
	.ring_start = &r300_ring_start,
 291 
	.ring_start = &r300_ring_start,
292 
	.ring_test = &r100_ring_test,
 292 
	.ring_test = &r100_ring_test,
293 
//	.ring_ib_execute = &r100_ring_ib_execute,
 293 
//	.ring_ib_execute = &r100_ring_ib_execute,
294 
//	.irq_set = &r100_irq_set,
 294 
//	.irq_set = &r100_irq_set,
295 
//	.irq_process = &r100_irq_process,
 295 
//	.irq_process = &r100_irq_process,
296 
//	.get_vblank_counter = &r100_get_vblank_counter,
 296 
//	.get_vblank_counter = &r100_get_vblank_counter,
297 
	.fence_ring_emit = &r300_fence_ring_emit,
 297 
	.fence_ring_emit = &r300_fence_ring_emit,
298 
//	.cs_parse = &r300_cs_parse,
 298 
//	.cs_parse = &r300_cs_parse,
299 
//	.copy_blit = &r100_copy_blit,
 299 
//	.copy_blit = &r100_copy_blit,
300 
//	.copy_dma = &r300_copy_dma,
 300 
//	.copy_dma = &r300_copy_dma,
301 
//	.copy = &r100_copy_blit,
 301 
//	.copy = &r100_copy_blit,
302 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 302 
	.get_engine_clock = &radeon_atom_get_engine_clock,
303 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 303 
	.set_engine_clock = &radeon_atom_set_engine_clock,
304 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 304 
	.get_memory_clock = &radeon_atom_get_memory_clock,
305 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 305 
	.set_memory_clock = &radeon_atom_set_memory_clock,
306 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 306 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
307 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 307 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
308 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 308 
	.set_clock_gating = &radeon_atom_set_clock_gating,
309 
	.set_surface_reg = r100_set_surface_reg,
 309 
	.set_surface_reg = r100_set_surface_reg,
310 
	.clear_surface_reg = r100_clear_surface_reg,
 310 
	.clear_surface_reg = r100_clear_surface_reg,
311 
	.bandwidth_update = &r100_bandwidth_update,
 311 
	.bandwidth_update = &r100_bandwidth_update,
312 
	.hpd_init = &r100_hpd_init,
 312 
	.hpd_init = &r100_hpd_init,
313 
	.hpd_fini = &r100_hpd_fini,
 313 
	.hpd_fini = &r100_hpd_fini,
314 
	.hpd_sense = &r100_hpd_sense,
 314 
	.hpd_sense = &r100_hpd_sense,
315 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 315 
	.hpd_set_polarity = &r100_hpd_set_polarity,
316 
	.ioctl_wait_idle = NULL,
 316 
	.ioctl_wait_idle = NULL,
317 
};
 317 
};
318 
 
 318 
 
319 
static struct radeon_asic rs400_asic = {
 319 
static struct radeon_asic rs400_asic = {
320 
	.init = &rs400_init,
 320 
	.init = &rs400_init,
321 
//	.fini = &rs400_fini,
 321 
//	.fini = &rs400_fini,
322 
//	.suspend = &rs400_suspend,
 322 
//	.suspend = &rs400_suspend,
323 
//	.resume = &rs400_resume,
 323 
//	.resume = &rs400_resume,
324 
//	.vga_set_state = &r100_vga_set_state,
 324 
//	.vga_set_state = &r100_vga_set_state,
325 
	.asic_reset = &r300_asic_reset,
 325 
	.asic_reset = &r300_asic_reset,
326 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
 326 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
327 
	.gart_set_page = &rs400_gart_set_page,
 327 
	.gart_set_page = &rs400_gart_set_page,
328 
	.cp_commit = &r100_cp_commit,
 328 
	.cp_commit = &r100_cp_commit,
329 
	.ring_start = &r300_ring_start,
 329 
	.ring_start = &r300_ring_start,
330 
	.ring_test = &r100_ring_test,
 330 
	.ring_test = &r100_ring_test,
331 
//	.ring_ib_execute = &r100_ring_ib_execute,
 331 
//	.ring_ib_execute = &r100_ring_ib_execute,
332 
//	.irq_set = &r100_irq_set,
 332 
//	.irq_set = &r100_irq_set,
333 
//	.irq_process = &r100_irq_process,
 333 
//	.irq_process = &r100_irq_process,
334 
//	.get_vblank_counter = &r100_get_vblank_counter,
 334 
//	.get_vblank_counter = &r100_get_vblank_counter,
335 
	.fence_ring_emit = &r300_fence_ring_emit,
 335 
	.fence_ring_emit = &r300_fence_ring_emit,
336 
//	.cs_parse = &r300_cs_parse,
 336 
//	.cs_parse = &r300_cs_parse,
337 
//	.copy_blit = &r100_copy_blit,
 337 
//	.copy_blit = &r100_copy_blit,
338 
//	.copy_dma = &r300_copy_dma,
 338 
//	.copy_dma = &r300_copy_dma,
339 
//	.copy = &r100_copy_blit,
 339 
//	.copy = &r100_copy_blit,
340 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 340 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
341 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 341 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
342 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 342 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
343 
	.set_memory_clock = NULL,
 343 
	.set_memory_clock = NULL,
344 
	.get_pcie_lanes = NULL,
 344 
	.get_pcie_lanes = NULL,
345 
	.set_pcie_lanes = NULL,
 345 
	.set_pcie_lanes = NULL,
346 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 346 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
347 
	.set_surface_reg = r100_set_surface_reg,
 347 
	.set_surface_reg = r100_set_surface_reg,
348 
	.clear_surface_reg = r100_clear_surface_reg,
 348 
	.clear_surface_reg = r100_clear_surface_reg,
349 
	.bandwidth_update = &r100_bandwidth_update,
 349 
	.bandwidth_update = &r100_bandwidth_update,
350 
	.hpd_init = &r100_hpd_init,
 350 
	.hpd_init = &r100_hpd_init,
351 
	.hpd_fini = &r100_hpd_fini,
 351 
	.hpd_fini = &r100_hpd_fini,
352 
	.hpd_sense = &r100_hpd_sense,
 352 
	.hpd_sense = &r100_hpd_sense,
353 
	.hpd_set_polarity = &r100_hpd_set_polarity,
 353 
	.hpd_set_polarity = &r100_hpd_set_polarity,
354 
	.ioctl_wait_idle = NULL,
 354 
	.ioctl_wait_idle = NULL,
355 
};
 355 
};
356 
 
 356 
 
357 
static struct radeon_asic rs600_asic = {
 357 
static struct radeon_asic rs600_asic = {
358 
	.init = &rs600_init,
 358 
	.init = &rs600_init,
359 
//	.fini = &rs600_fini,
 359 
//	.fini = &rs600_fini,
360 
//	.suspend = &rs600_suspend,
 360 
//	.suspend = &rs600_suspend,
361 
//	.resume = &rs600_resume,
 361 
//	.resume = &rs600_resume,
362 
//	.vga_set_state = &r100_vga_set_state,
 362 
//	.vga_set_state = &r100_vga_set_state,
363 
	.asic_reset = &rs600_asic_reset,
 363 
	.asic_reset = &rs600_asic_reset,
364 
	.gart_tlb_flush = &rs600_gart_tlb_flush,
 364 
	.gart_tlb_flush = &rs600_gart_tlb_flush,
365 
	.gart_set_page = &rs600_gart_set_page,
 365 
	.gart_set_page = &rs600_gart_set_page,
366 
	.cp_commit = &r100_cp_commit,
 366 
	.cp_commit = &r100_cp_commit,
367 
	.ring_start = &r300_ring_start,
 367 
	.ring_start = &r300_ring_start,
368 
	.ring_test = &r100_ring_test,
 368 
	.ring_test = &r100_ring_test,
369 
//	.ring_ib_execute = &r100_ring_ib_execute,
 369 
//	.ring_ib_execute = &r100_ring_ib_execute,
370 
//	.irq_set = &rs600_irq_set,
 370 
//	.irq_set = &rs600_irq_set,
371 
//	.irq_process = &rs600_irq_process,
 371 
//	.irq_process = &rs600_irq_process,
372 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 372 
//	.get_vblank_counter = &rs600_get_vblank_counter,
373 
	.fence_ring_emit = &r300_fence_ring_emit,
 373 
	.fence_ring_emit = &r300_fence_ring_emit,
374 
//   .cs_parse = &r300_cs_parse,
 374 
//   .cs_parse = &r300_cs_parse,
375 
//   .copy_blit = &r100_copy_blit,
 375 
//   .copy_blit = &r100_copy_blit,
376 
//   .copy_dma = &r300_copy_dma,
 376 
//   .copy_dma = &r300_copy_dma,
377 
//   .copy = &r100_copy_blit,
 377 
//   .copy = &r100_copy_blit,
378 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 378 
	.get_engine_clock = &radeon_atom_get_engine_clock,
379 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 379 
	.set_engine_clock = &radeon_atom_set_engine_clock,
380 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 380 
	.get_memory_clock = &radeon_atom_get_memory_clock,
381 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 381 
	.set_memory_clock = &radeon_atom_set_memory_clock,
382 
	.get_pcie_lanes = NULL,
 382 
	.get_pcie_lanes = NULL,
383 
	.set_pcie_lanes = NULL,
 383 
	.set_pcie_lanes = NULL,
384 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 384 
	.set_clock_gating = &radeon_atom_set_clock_gating,
385 
	.set_surface_reg = r100_set_surface_reg,
 385 
	.set_surface_reg = r100_set_surface_reg,
386 
	.clear_surface_reg = r100_clear_surface_reg,
 386 
	.clear_surface_reg = r100_clear_surface_reg,
387 
	.bandwidth_update = &rs600_bandwidth_update,
 387 
	.bandwidth_update = &rs600_bandwidth_update,
388 
	.hpd_init = &rs600_hpd_init,
 388 
	.hpd_init = &rs600_hpd_init,
389 
	.hpd_fini = &rs600_hpd_fini,
 389 
	.hpd_fini = &rs600_hpd_fini,
390 
	.hpd_sense = &rs600_hpd_sense,
 390 
	.hpd_sense = &rs600_hpd_sense,
391 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 391 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
392 
	.ioctl_wait_idle = NULL,
 392 
	.ioctl_wait_idle = NULL,
393 
};
 393 
};
394 
 
 394 
 
395 
static struct radeon_asic rs690_asic = {
 395 
static struct radeon_asic rs690_asic = {
396 
	.init = &rs690_init,
 396 
	.init = &rs690_init,
397 
//	.fini = &rs690_fini,
 397 
//	.fini = &rs690_fini,
398 
//	.suspend = &rs690_suspend,
 398 
//	.suspend = &rs690_suspend,
399 
//	.resume = &rs690_resume,
 399 
//	.resume = &rs690_resume,
400 
//	.vga_set_state = &r100_vga_set_state,
 400 
//	.vga_set_state = &r100_vga_set_state,
401 
	.asic_reset = &rs600_asic_reset,
 401 
	.asic_reset = &rs600_asic_reset,
402 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
 402 
	.gart_tlb_flush = &rs400_gart_tlb_flush,
403 
	.gart_set_page = &rs400_gart_set_page,
 403 
	.gart_set_page = &rs400_gart_set_page,
404 
	.cp_commit = &r100_cp_commit,
 404 
	.cp_commit = &r100_cp_commit,
405 
	.ring_start = &r300_ring_start,
 405 
	.ring_start = &r300_ring_start,
406 
	.ring_test = &r100_ring_test,
 406 
	.ring_test = &r100_ring_test,
407 
//	.ring_ib_execute = &r100_ring_ib_execute,
 407 
//	.ring_ib_execute = &r100_ring_ib_execute,
408 
//	.irq_set = &rs600_irq_set,
 408 
//	.irq_set = &rs600_irq_set,
409 
//	.irq_process = &rs600_irq_process,
 409 
//	.irq_process = &rs600_irq_process,
410 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 410 
//	.get_vblank_counter = &rs600_get_vblank_counter,
411 
	.fence_ring_emit = &r300_fence_ring_emit,
 411 
	.fence_ring_emit = &r300_fence_ring_emit,
412 
//	.cs_parse = &r300_cs_parse,
 412 
//	.cs_parse = &r300_cs_parse,
413 
//	.copy_blit = &r100_copy_blit,
 413 
//	.copy_blit = &r100_copy_blit,
414 
//	.copy_dma = &r300_copy_dma,
 414 
//	.copy_dma = &r300_copy_dma,
415 
//	.copy = &r300_copy_dma,
 415 
//	.copy = &r300_copy_dma,
416 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 416 
	.get_engine_clock = &radeon_atom_get_engine_clock,
417 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 417 
	.set_engine_clock = &radeon_atom_set_engine_clock,
418 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 418 
	.get_memory_clock = &radeon_atom_get_memory_clock,
419 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 419 
	.set_memory_clock = &radeon_atom_set_memory_clock,
420 
	.get_pcie_lanes = NULL,
 420 
	.get_pcie_lanes = NULL,
421 
	.set_pcie_lanes = NULL,
 421 
	.set_pcie_lanes = NULL,
422 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 422 
	.set_clock_gating = &radeon_atom_set_clock_gating,
423 
	.set_surface_reg = r100_set_surface_reg,
 423 
	.set_surface_reg = r100_set_surface_reg,
424 
	.clear_surface_reg = r100_clear_surface_reg,
 424 
	.clear_surface_reg = r100_clear_surface_reg,
425 
	.bandwidth_update = &rs690_bandwidth_update,
 425 
	.bandwidth_update = &rs690_bandwidth_update,
426 
	.hpd_init = &rs600_hpd_init,
 426 
	.hpd_init = &rs600_hpd_init,
427 
	.hpd_fini = &rs600_hpd_fini,
 427 
	.hpd_fini = &rs600_hpd_fini,
428 
	.hpd_sense = &rs600_hpd_sense,
 428 
	.hpd_sense = &rs600_hpd_sense,
429 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 429 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
430 
	.ioctl_wait_idle = NULL,
 430 
	.ioctl_wait_idle = NULL,
431 
};
 431 
};
432 
 
 432 
 
433 
static struct radeon_asic rv515_asic = {
 433 
static struct radeon_asic rv515_asic = {
434 
	.init = &rv515_init,
 434 
	.init = &rv515_init,
435 
//	.fini = &rv515_fini,
 435 
//	.fini = &rv515_fini,
436 
//	.suspend = &rv515_suspend,
 436 
//	.suspend = &rv515_suspend,
437 
//	.resume = &rv515_resume,
 437 
//	.resume = &rv515_resume,
438 
//	.vga_set_state = &r100_vga_set_state,
 438 
//	.vga_set_state = &r100_vga_set_state,
439 
	.asic_reset = &rs600_asic_reset,
 439 
	.asic_reset = &rs600_asic_reset,
440 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 440 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
441 
	.gart_set_page = &rv370_pcie_gart_set_page,
 441 
	.gart_set_page = &rv370_pcie_gart_set_page,
442 
	.cp_commit = &r100_cp_commit,
 442 
	.cp_commit = &r100_cp_commit,
443 
	.ring_start = &rv515_ring_start,
 443 
	.ring_start = &rv515_ring_start,
444 
	.ring_test = &r100_ring_test,
 444 
	.ring_test = &r100_ring_test,
445 
//	.ring_ib_execute = &r100_ring_ib_execute,
 445 
//	.ring_ib_execute = &r100_ring_ib_execute,
446 
//	.irq_set = &rs600_irq_set,
 446 
//	.irq_set = &rs600_irq_set,
447 
//	.irq_process = &rs600_irq_process,
 447 
//	.irq_process = &rs600_irq_process,
448 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 448 
//	.get_vblank_counter = &rs600_get_vblank_counter,
449 
	.fence_ring_emit = &r300_fence_ring_emit,
 449 
	.fence_ring_emit = &r300_fence_ring_emit,
450 
//	.cs_parse = &r300_cs_parse,
 450 
//	.cs_parse = &r300_cs_parse,
451 
//	.copy_blit = &r100_copy_blit,
 451 
//	.copy_blit = &r100_copy_blit,
452 
//	.copy_dma = &r300_copy_dma,
 452 
//	.copy_dma = &r300_copy_dma,
453 
//	.copy = &r100_copy_blit,
 453 
//	.copy = &r100_copy_blit,
454 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 454 
	.get_engine_clock = &radeon_atom_get_engine_clock,
455 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 455 
	.set_engine_clock = &radeon_atom_set_engine_clock,
456 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 456 
	.get_memory_clock = &radeon_atom_get_memory_clock,
457 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 457 
	.set_memory_clock = &radeon_atom_set_memory_clock,
458 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 458 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
459 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 459 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
460 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 460 
	.set_clock_gating = &radeon_atom_set_clock_gating,
461 
	.set_surface_reg = r100_set_surface_reg,
 461 
	.set_surface_reg = r100_set_surface_reg,
462 
	.clear_surface_reg = r100_clear_surface_reg,
 462 
	.clear_surface_reg = r100_clear_surface_reg,
463 
	.bandwidth_update = &rv515_bandwidth_update,
 463 
	.bandwidth_update = &rv515_bandwidth_update,
464 
	.hpd_init = &rs600_hpd_init,
 464 
	.hpd_init = &rs600_hpd_init,
465 
	.hpd_fini = &rs600_hpd_fini,
 465 
	.hpd_fini = &rs600_hpd_fini,
466 
	.hpd_sense = &rs600_hpd_sense,
 466 
	.hpd_sense = &rs600_hpd_sense,
467 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 467 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
468 
	.ioctl_wait_idle = NULL,
 468 
	.ioctl_wait_idle = NULL,
469 
};
 469 
};
470 
 
 470 
 
471 
static struct radeon_asic r520_asic = {
 471 
static struct radeon_asic r520_asic = {
472 
	.init = &r520_init,
 472 
	.init = &r520_init,
473 
//	.fini = &rv515_fini,
 473 
//	.fini = &rv515_fini,
474 
//	.suspend = &rv515_suspend,
 474 
//	.suspend = &rv515_suspend,
475 
//	.resume = &r520_resume,
 475 
//	.resume = &r520_resume,
476 
//	.vga_set_state = &r100_vga_set_state,
 476 
//	.vga_set_state = &r100_vga_set_state,
477 
	.asic_reset = &rs600_asic_reset,
 477 
	.asic_reset = &rs600_asic_reset,
478 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 478 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
479 
	.gart_set_page = &rv370_pcie_gart_set_page,
 479 
	.gart_set_page = &rv370_pcie_gart_set_page,
480 
	.cp_commit = &r100_cp_commit,
 480 
	.cp_commit = &r100_cp_commit,
481 
	.ring_start = &rv515_ring_start,
 481 
	.ring_start = &rv515_ring_start,
482 
	.ring_test = &r100_ring_test,
 482 
	.ring_test = &r100_ring_test,
483 
//	.ring_ib_execute = &r100_ring_ib_execute,
 483 
//	.ring_ib_execute = &r100_ring_ib_execute,
484 
//	.irq_set = &rs600_irq_set,
 484 
//	.irq_set = &rs600_irq_set,
485 
//	.irq_process = &rs600_irq_process,
 485 
//	.irq_process = &rs600_irq_process,
486 
//	.get_vblank_counter = &rs600_get_vblank_counter,
 486 
//	.get_vblank_counter = &rs600_get_vblank_counter,
487 
	.fence_ring_emit = &r300_fence_ring_emit,
 487 
	.fence_ring_emit = &r300_fence_ring_emit,
488 
//	.cs_parse = &r300_cs_parse,
 488 
//	.cs_parse = &r300_cs_parse,
489 
//	.copy_blit = &r100_copy_blit,
 489 
//	.copy_blit = &r100_copy_blit,
490 
//	.copy_dma = &r300_copy_dma,
 490 
//	.copy_dma = &r300_copy_dma,
491 
//	.copy = &r100_copy_blit,
 491 
//	.copy = &r100_copy_blit,
492 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 492 
	.get_engine_clock = &radeon_atom_get_engine_clock,
493 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 493 
	.set_engine_clock = &radeon_atom_set_engine_clock,
494 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 494 
	.get_memory_clock = &radeon_atom_get_memory_clock,
495 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 495 
	.set_memory_clock = &radeon_atom_set_memory_clock,
496 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 496 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
497 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 497 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
498 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 498 
	.set_clock_gating = &radeon_atom_set_clock_gating,
499 
	.set_surface_reg = r100_set_surface_reg,
 499 
	.set_surface_reg = r100_set_surface_reg,
500 
	.clear_surface_reg = r100_clear_surface_reg,
 500 
	.clear_surface_reg = r100_clear_surface_reg,
501 
	.bandwidth_update = &rv515_bandwidth_update,
 501 
	.bandwidth_update = &rv515_bandwidth_update,
502 
	.hpd_init = &rs600_hpd_init,
 502 
	.hpd_init = &rs600_hpd_init,
503 
	.hpd_fini = &rs600_hpd_fini,
 503 
	.hpd_fini = &rs600_hpd_fini,
504 
	.hpd_sense = &rs600_hpd_sense,
 504 
	.hpd_sense = &rs600_hpd_sense,
505 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 505 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
506 
	.ioctl_wait_idle = NULL,
 506 
	.ioctl_wait_idle = NULL,
507 
};
 507 
};
508 
 
 508 
 
509 
static struct radeon_asic r600_asic = {
 509 
static struct radeon_asic r600_asic = {
510 
	.init = &r600_init,
 510 
	.init = &r600_init,
511 
//	.fini = &r600_fini,
 511 
//	.fini = &r600_fini,
512 
//	.suspend = &r600_suspend,
 512 
//	.suspend = &r600_suspend,
513 
//	.resume = &r600_resume,
 513 
//	.resume = &r600_resume,
514 
	.cp_commit = &r600_cp_commit,
 514 
	.cp_commit = &r600_cp_commit,
515 
	.vga_set_state = &r600_vga_set_state,
 515 
	.vga_set_state = &r600_vga_set_state,
516 
	.asic_reset = &r600_asic_reset,
 516 
	.asic_reset = &r600_asic_reset,
517 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 517 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
518 
	.gart_set_page = &rs600_gart_set_page,
 518 
	.gart_set_page = &rs600_gart_set_page,
519 
	.ring_test = &r600_ring_test,
 519 
	.ring_test = &r600_ring_test,
520 
//	.ring_ib_execute = &r600_ring_ib_execute,
 520 
//	.ring_ib_execute = &r600_ring_ib_execute,
521 
//	.irq_set = &r600_irq_set,
 521 
	.irq_set = &r600_irq_set,
522 
//	.irq_process = &r600_irq_process,
 522 
	.irq_process = &r600_irq_process,
523 
	.fence_ring_emit = &r600_fence_ring_emit,
 523 
	.fence_ring_emit = &r600_fence_ring_emit,
524 
//	.cs_parse = &r600_cs_parse,
 524 
//	.cs_parse = &r600_cs_parse,
525 
//	.copy_blit = &r600_copy_blit,
 525 
//	.copy_blit = &r600_copy_blit,
526 
//	.copy_dma = &r600_copy_blit,
 526 
//	.copy_dma = &r600_copy_blit,
527 
//	.copy = &r600_copy_blit,
 527 
//	.copy = &r600_copy_blit,
528 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 528 
	.get_engine_clock = &radeon_atom_get_engine_clock,
529 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 529 
	.set_engine_clock = &radeon_atom_set_engine_clock,
530 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 530 
	.get_memory_clock = &radeon_atom_get_memory_clock,
531 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 531 
	.set_memory_clock = &radeon_atom_set_memory_clock,
532 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 532 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
533 
	.set_pcie_lanes = NULL,
 533 
	.set_pcie_lanes = NULL,
534 
	.set_clock_gating = NULL,
 534 
	.set_clock_gating = NULL,
535 
	.set_surface_reg = r600_set_surface_reg,
 535 
	.set_surface_reg = r600_set_surface_reg,
536 
	.clear_surface_reg = r600_clear_surface_reg,
 536 
	.clear_surface_reg = r600_clear_surface_reg,
537 
	.bandwidth_update = &rv515_bandwidth_update,
 537 
	.bandwidth_update = &rv515_bandwidth_update,
538 
	.hpd_init = &r600_hpd_init,
 538 
	.hpd_init = &r600_hpd_init,
539 
	.hpd_fini = &r600_hpd_fini,
 539 
	.hpd_fini = &r600_hpd_fini,
540 
	.hpd_sense = &r600_hpd_sense,
 540 
	.hpd_sense = &r600_hpd_sense,
541 
	.hpd_set_polarity = &r600_hpd_set_polarity,
 541 
	.hpd_set_polarity = &r600_hpd_set_polarity,
542 
//	.ioctl_wait_idle = r600_ioctl_wait_idle,
 542 
//	.ioctl_wait_idle = r600_ioctl_wait_idle,
543 
};
 543 
};
544 
 
 544 
 
545 
static struct radeon_asic rs780_asic = {
 545 
static struct radeon_asic rs780_asic = {
546 
	.init = &r600_init,
 546 
	.init = &r600_init,
547 
//	.fini = &r600_fini,
 547 
//	.fini = &r600_fini,
548 
//	.suspend = &r600_suspend,
 548 
//	.suspend = &r600_suspend,
549 
//	.resume = &r600_resume,
 549 
//	.resume = &r600_resume,
550 
	.cp_commit = &r600_cp_commit,
 550 
	.cp_commit = &r600_cp_commit,
551 
	.gpu_is_lockup = &r600_gpu_is_lockup,
 551 
	.gpu_is_lockup = &r600_gpu_is_lockup,
552 
	.vga_set_state = &r600_vga_set_state,
 552 
	.vga_set_state = &r600_vga_set_state,
553 
	.asic_reset = &r600_asic_reset,
 553 
	.asic_reset = &r600_asic_reset,
554 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 554 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
555 
	.gart_set_page = &rs600_gart_set_page,
 555 
	.gart_set_page = &rs600_gart_set_page,
556 
	.ring_test = &r600_ring_test,
 556 
	.ring_test = &r600_ring_test,
557 
//	.ring_ib_execute = &r600_ring_ib_execute,
 557 
//	.ring_ib_execute = &r600_ring_ib_execute,
558 
//	.irq_set = &r600_irq_set,
 558 
	.irq_set = &r600_irq_set,
559 
//	.irq_process = &r600_irq_process,
 559 
	.irq_process = &r600_irq_process,
560 
	.fence_ring_emit = &r600_fence_ring_emit,
 560 
	.fence_ring_emit = &r600_fence_ring_emit,
561 
//	.cs_parse = &r600_cs_parse,
 561 
//	.cs_parse = &r600_cs_parse,
562 
//	.copy_blit = &r600_copy_blit,
 562 
//	.copy_blit = &r600_copy_blit,
563 
//	.copy_dma = &r600_copy_blit,
 563 
//	.copy_dma = &r600_copy_blit,
564 
//	.copy = &r600_copy_blit,
 564 
//	.copy = &r600_copy_blit,
565 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 565 
	.get_engine_clock = &radeon_atom_get_engine_clock,
566 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 566 
	.set_engine_clock = &radeon_atom_set_engine_clock,
567 
	.get_memory_clock = NULL,
 567 
	.get_memory_clock = NULL,
568 
	.set_memory_clock = NULL,
 568 
	.set_memory_clock = NULL,
569 
	.get_pcie_lanes = NULL,
 569 
	.get_pcie_lanes = NULL,
570 
	.set_pcie_lanes = NULL,
 570 
	.set_pcie_lanes = NULL,
571 
	.set_clock_gating = NULL,
 571 
	.set_clock_gating = NULL,
572 
	.set_surface_reg = r600_set_surface_reg,
 572 
	.set_surface_reg = r600_set_surface_reg,
573 
	.clear_surface_reg = r600_clear_surface_reg,
 573 
	.clear_surface_reg = r600_clear_surface_reg,
574 
	.bandwidth_update = &rs690_bandwidth_update,
 574 
	.bandwidth_update = &rs690_bandwidth_update,
575 
	.hpd_init = &r600_hpd_init,
 575 
	.hpd_init = &r600_hpd_init,
576 
	.hpd_fini = &r600_hpd_fini,
 576 
	.hpd_fini = &r600_hpd_fini,
577 
	.hpd_sense = &r600_hpd_sense,
 577 
	.hpd_sense = &r600_hpd_sense,
578 
	.hpd_set_polarity = &r600_hpd_set_polarity,
 578 
	.hpd_set_polarity = &r600_hpd_set_polarity,
579 
};
 579 
};
580 
 
 580 
 
581 
static struct radeon_asic rv770_asic = {
 581 
static struct radeon_asic rv770_asic = {
582 
	.init = &rv770_init,
 582 
	.init = &rv770_init,
583 
//	.fini = &rv770_fini,
 583 
//	.fini = &rv770_fini,
584 
//	.suspend = &rv770_suspend,
 584 
//	.suspend = &rv770_suspend,
585 
//	.resume = &rv770_resume,
 585 
//	.resume = &rv770_resume,
586 
	.cp_commit = &r600_cp_commit,
 586 
	.cp_commit = &r600_cp_commit,
587 
	.asic_reset = &r600_asic_reset,
 587 
	.asic_reset = &r600_asic_reset,
588 
	.vga_set_state = &r600_vga_set_state,
 588 
	.vga_set_state = &r600_vga_set_state,
589 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 589 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
590 
	.gart_set_page = &rs600_gart_set_page,
 590 
	.gart_set_page = &rs600_gart_set_page,
591 
	.ring_test = &r600_ring_test,
 591 
	.ring_test = &r600_ring_test,
592 
//	.ring_ib_execute = &r600_ring_ib_execute,
 592 
	.ring_ib_execute = &r600_ring_ib_execute,
593 
//	.irq_set = &r600_irq_set,
 593 
	.irq_set = &r600_irq_set,
594 
//	.irq_process = &r600_irq_process,
 594 
	.irq_process = &r600_irq_process,
595 
	.fence_ring_emit = &r600_fence_ring_emit,
 595 
	.fence_ring_emit = &r600_fence_ring_emit,
596 
//	.cs_parse = &r600_cs_parse,
 596 
//	.cs_parse = &r600_cs_parse,
597 
//	.copy_blit = &r600_copy_blit,
 597 
//	.copy_blit = &r600_copy_blit,
598 
//	.copy_dma = &r600_copy_blit,
 598 
//	.copy_dma = &r600_copy_blit,
599 
//	.copy = &r600_copy_blit,
 599 
//	.copy = &r600_copy_blit,
600 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 600 
	.get_engine_clock = &radeon_atom_get_engine_clock,
601 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 601 
	.set_engine_clock = &radeon_atom_set_engine_clock,
602 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 602 
	.get_memory_clock = &radeon_atom_get_memory_clock,
603 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 603 
	.set_memory_clock = &radeon_atom_set_memory_clock,
604 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
 604 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
605 
	.set_pcie_lanes = NULL,
 605 
	.set_pcie_lanes = NULL,
606 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 606 
	.set_clock_gating = &radeon_atom_set_clock_gating,
607 
	.set_surface_reg = r600_set_surface_reg,
 607 
	.set_surface_reg = r600_set_surface_reg,
608 
	.clear_surface_reg = r600_clear_surface_reg,
 608 
	.clear_surface_reg = r600_clear_surface_reg,
609 
	.bandwidth_update = &rv515_bandwidth_update,
 609 
	.bandwidth_update = &rv515_bandwidth_update,
610 
	.hpd_init = &r600_hpd_init,
 610 
	.hpd_init = &r600_hpd_init,
611 
	.hpd_fini = &r600_hpd_fini,
 611 
	.hpd_fini = &r600_hpd_fini,
612 
	.hpd_sense = &r600_hpd_sense,
 612 
	.hpd_sense = &r600_hpd_sense,
613 
	.hpd_set_polarity = &r600_hpd_set_polarity,
 613 
	.hpd_set_polarity = &r600_hpd_set_polarity,
614 
};
 614 
};
615 
 
 615 
 
616 
static struct radeon_asic evergreen_asic = {
 616 
static struct radeon_asic evergreen_asic = {
617 
	.init = &evergreen_init,
 617 
	.init = &evergreen_init,
618 
//	.fini = &evergreen_fini,
 618 
//	.fini = &evergreen_fini,
619 
//	.suspend = &evergreen_suspend,
 619 
//	.suspend = &evergreen_suspend,
620 
//	.resume = &evergreen_resume,
 620 
//	.resume = &evergreen_resume,
621 
	.cp_commit = &r600_cp_commit,
 621 
	.cp_commit = &r600_cp_commit,
622 
	.asic_reset = &evergreen_asic_reset,
 622 
	.asic_reset = &evergreen_asic_reset,
623 
	.vga_set_state = &r600_vga_set_state,
 623 
	.vga_set_state = &r600_vga_set_state,
624 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 624 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
625 
	.gart_set_page = &rs600_gart_set_page,
 625 
	.gart_set_page = &rs600_gart_set_page,
626 
	.ring_test = &r600_ring_test,
 626 
	.ring_test = &r600_ring_test,
627 
//	.ring_ib_execute = &r600_ring_ib_execute,
 627 
//	.ring_ib_execute = &r600_ring_ib_execute,
628 
//	.irq_set = &r600_irq_set,
 628 
//	.irq_set = &r600_irq_set,
629 
//	.irq_process = &r600_irq_process,
 629 
//	.irq_process = &r600_irq_process,
630 
	.fence_ring_emit = &r600_fence_ring_emit,
 630 
	.fence_ring_emit = &r600_fence_ring_emit,
631 
//	.cs_parse = &r600_cs_parse,
 631 
//	.cs_parse = &r600_cs_parse,
632 
//	.copy_blit = &r600_copy_blit,
 632 
//	.copy_blit = &r600_copy_blit,
633 
//	.copy_dma = &r600_copy_blit,
 633 
//	.copy_dma = &r600_copy_blit,
634 
//	.copy = &r600_copy_blit,
 634 
//	.copy = &r600_copy_blit,
635 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 635 
	.get_engine_clock = &radeon_atom_get_engine_clock,
636 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 636 
	.set_engine_clock = &radeon_atom_set_engine_clock,
637 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 637 
	.get_memory_clock = &radeon_atom_get_memory_clock,
638 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 638 
	.set_memory_clock = &radeon_atom_set_memory_clock,
639 
	.get_pcie_lanes = &r600_get_pcie_lanes,
 639 
	.get_pcie_lanes = &r600_get_pcie_lanes,
640 
	.set_pcie_lanes = &r600_set_pcie_lanes,
 640 
	.set_pcie_lanes = &r600_set_pcie_lanes,
641 
	.set_clock_gating = NULL,
 641 
	.set_clock_gating = NULL,
642 
	.set_surface_reg = r600_set_surface_reg,
 642 
	.set_surface_reg = r600_set_surface_reg,
643 
	.clear_surface_reg = r600_clear_surface_reg,
 643 
	.clear_surface_reg = r600_clear_surface_reg,
644 
	.bandwidth_update = &evergreen_bandwidth_update,
 644 
	.bandwidth_update = &evergreen_bandwidth_update,
645 
 
 645 
 
646 
};
 646 
};
647 
 
 647 
 
648 
static struct radeon_asic sumo_asic = {
 648 
static struct radeon_asic sumo_asic = {
649 
	.init = &evergreen_init,
 649 
	.init = &evergreen_init,
650 
//	.fini = &evergreen_fini,
 650 
//	.fini = &evergreen_fini,
651 
//	.suspend = &evergreen_suspend,
 651 
//	.suspend = &evergreen_suspend,
652 
//	.resume = &evergreen_resume,
 652 
//	.resume = &evergreen_resume,
653 
	.cp_commit = &r600_cp_commit,
 653 
	.cp_commit = &r600_cp_commit,
654 
	.asic_reset = &evergreen_asic_reset,
 654 
	.asic_reset = &evergreen_asic_reset,
655 
	.vga_set_state = &r600_vga_set_state,
 655 
	.vga_set_state = &r600_vga_set_state,
656 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 656 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
657 
	.gart_set_page = &rs600_gart_set_page,
 657 
	.gart_set_page = &rs600_gart_set_page,
658 
	.ring_test = &r600_ring_test,
 658 
	.ring_test = &r600_ring_test,
659 
//	.ring_ib_execute = &r600_ring_ib_execute,
 659 
//	.ring_ib_execute = &r600_ring_ib_execute,
660 
//	.irq_set = &r600_irq_set,
 660 
//	.irq_set = &r600_irq_set,
661 
//	.irq_process = &r600_irq_process,
 661 
//	.irq_process = &r600_irq_process,
662 
	.fence_ring_emit = &r600_fence_ring_emit,
 662 
	.fence_ring_emit = &r600_fence_ring_emit,
663 
//	.cs_parse = &r600_cs_parse,
 663 
//	.cs_parse = &r600_cs_parse,
664 
//	.copy_blit = &r600_copy_blit,
 664 
//	.copy_blit = &r600_copy_blit,
665 
//	.copy_dma = &r600_copy_blit,
 665 
//	.copy_dma = &r600_copy_blit,
666 
//	.copy = &r600_copy_blit,
 666 
//	.copy = &r600_copy_blit,
667 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 667 
	.get_engine_clock = &radeon_atom_get_engine_clock,
668 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 668 
	.set_engine_clock = &radeon_atom_set_engine_clock,
669 
	.get_memory_clock = NULL,
 669 
	.get_memory_clock = NULL,
670 
	.set_memory_clock = NULL,
 670 
	.set_memory_clock = NULL,
671 
	.get_pcie_lanes = NULL,
 671 
	.get_pcie_lanes = NULL,
672 
	.set_pcie_lanes = NULL,
 672 
	.set_pcie_lanes = NULL,
673 
	.set_clock_gating = NULL,
 673 
	.set_clock_gating = NULL,
674 
	.set_surface_reg = r600_set_surface_reg,
 674 
	.set_surface_reg = r600_set_surface_reg,
675 
	.clear_surface_reg = r600_clear_surface_reg,
 675 
	.clear_surface_reg = r600_clear_surface_reg,
676 
	.bandwidth_update = &evergreen_bandwidth_update,
 676 
	.bandwidth_update = &evergreen_bandwidth_update,
677 
};
 677 
};
678 
 
 678 
 
679 
 
 679 
 
680 
static struct radeon_asic btc_asic = {
 680 
static struct radeon_asic btc_asic = {
681 
	.init = &evergreen_init,
 681 
	.init = &evergreen_init,
682 
//	.fini = &evergreen_fini,
 682 
//	.fini = &evergreen_fini,
683 
//	.suspend = &evergreen_suspend,
 683 
//	.suspend = &evergreen_suspend,
684 
//	.resume = &evergreen_resume,
 684 
//	.resume = &evergreen_resume,
685 
	.cp_commit = &r600_cp_commit,
 685 
	.cp_commit = &r600_cp_commit,
686 
	.asic_reset = &evergreen_asic_reset,
 686 
	.asic_reset = &evergreen_asic_reset,
687 
	.vga_set_state = &r600_vga_set_state,
 687 
	.vga_set_state = &r600_vga_set_state,
688 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 688 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
689 
	.gart_set_page = &rs600_gart_set_page,
 689 
	.gart_set_page = &rs600_gart_set_page,
690 
	.ring_test = &r600_ring_test,
 690 
	.ring_test = &r600_ring_test,
691 
//	.ring_ib_execute = &r600_ring_ib_execute,
 691 
//	.ring_ib_execute = &r600_ring_ib_execute,
692 
//	.irq_set = &r600_irq_set,
 692 
//	.irq_set = &r600_irq_set,
693 
//	.irq_process = &r600_irq_process,
 693 
//	.irq_process = &r600_irq_process,
694 
	.fence_ring_emit = &r600_fence_ring_emit,
 694 
	.fence_ring_emit = &r600_fence_ring_emit,
695 
//	.cs_parse = &r600_cs_parse,
 695 
//	.cs_parse = &r600_cs_parse,
696 
//	.copy_blit = &r600_copy_blit,
 696 
//	.copy_blit = &r600_copy_blit,
697 
//	.copy_dma = &r600_copy_blit,
 697 
//	.copy_dma = &r600_copy_blit,
698 
//	.copy = &r600_copy_blit,
 698 
//	.copy = &r600_copy_blit,
699 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 699 
	.get_engine_clock = &radeon_atom_get_engine_clock,
700 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 700 
	.set_engine_clock = &radeon_atom_set_engine_clock,
701 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 701 
	.get_memory_clock = &radeon_atom_get_memory_clock,
702 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 702 
	.set_memory_clock = &radeon_atom_set_memory_clock,
703 
	.get_pcie_lanes = NULL,
 703 
	.get_pcie_lanes = NULL,
704 
	.set_pcie_lanes = NULL,
 704 
	.set_pcie_lanes = NULL,
705 
	.set_clock_gating = NULL,
 705 
	.set_clock_gating = NULL,
706 
	.set_surface_reg = r600_set_surface_reg,
 706 
	.set_surface_reg = r600_set_surface_reg,
707 
	.clear_surface_reg = r600_clear_surface_reg,
 707 
	.clear_surface_reg = r600_clear_surface_reg,
708 
	.bandwidth_update = &evergreen_bandwidth_update,
 708 
	.bandwidth_update = &evergreen_bandwidth_update,
- 
 
 709 
	.hpd_init = &evergreen_hpd_init,
- 
 
 710 
	.hpd_sense = &evergreen_hpd_sense,
709 
};
 711 
};
710 
 
 - 
 
711 
 
 - 
 
712 
#if 0
 712 
 
713 
static struct radeon_asic cayman_asic = {
 713 
static struct radeon_asic cayman_asic = {
714 
	.init = &cayman_init,
 714 
	.init = &cayman_init,
715 
	.fini = &cayman_fini,
 715 
//	.fini = &evergreen_fini,
716 
	.suspend = &cayman_suspend,
 716 
//	.suspend = &evergreen_suspend,
717 
	.resume = &cayman_resume,
 717 
//	.resume = &evergreen_resume,
718 
	.cp_commit = &r600_cp_commit,
 - 
 
719 
	.gpu_is_lockup = &cayman_gpu_is_lockup,
 718 
	.cp_commit = &r600_cp_commit,
720 
	.asic_reset = &cayman_asic_reset,
 719 
	.asic_reset = &cayman_asic_reset,
721 
	.vga_set_state = &r600_vga_set_state,
 720 
	.vga_set_state = &r600_vga_set_state,
722 
	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
 721 
	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
723 
	.gart_set_page = &rs600_gart_set_page,
 722 
	.gart_set_page = &rs600_gart_set_page,
724 
	.ring_test = &r600_ring_test,
 723 
	.ring_test = &r600_ring_test,
725 
	.ring_ib_execute = &evergreen_ring_ib_execute,
 724 
//	.ring_ib_execute = &r600_ring_ib_execute,
726 
	.irq_set = &evergreen_irq_set,
 725 
//	.irq_set = &r600_irq_set,
727 
	.irq_process = &evergreen_irq_process,
 726 
//	.irq_process = &r600_irq_process,
728 
	.get_vblank_counter = &evergreen_get_vblank_counter,
 - 
 
729 
	.fence_ring_emit = &r600_fence_ring_emit,
 727 
	.fence_ring_emit = &r600_fence_ring_emit,
730 
//	.cs_parse = &r600_cs_parse,
 728 
//	.cs_parse = &r600_cs_parse,
731 
//	.copy_blit = &r600_copy_blit,
 729 
//	.copy_blit = &r600_copy_blit,
732 
//	.copy_dma = &r600_copy_blit,
 730 
//	.copy_dma = &r600_copy_blit,
733 
//	.copy = &r600_copy_blit,
 731 
//	.copy = &r600_copy_blit,
734 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 732 
	.get_engine_clock = &radeon_atom_get_engine_clock,
735 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 733 
	.set_engine_clock = &radeon_atom_set_engine_clock,
736 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 734 
	.get_memory_clock = &radeon_atom_get_memory_clock,
737 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 735 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 736 
	.get_pcie_lanes = NULL,
738 
	.set_pcie_lanes = NULL,
 737 
	.set_pcie_lanes = NULL,
739 
	.set_clock_gating = NULL,
 738 
	.set_clock_gating = NULL,
740 
	.set_surface_reg = r600_set_surface_reg,
 739 
	.set_surface_reg = r600_set_surface_reg,
741 
	.clear_surface_reg = r600_clear_surface_reg,
 740 
	.clear_surface_reg = r600_clear_surface_reg,
742 
	.bandwidth_update = &evergreen_bandwidth_update,
 741 
	.bandwidth_update = &evergreen_bandwidth_update,
743 
	.gui_idle = &r600_gui_idle,
 - 
 
744 
	.pm_misc = &evergreen_pm_misc,
 - 
 
745 
	.pm_prepare = &evergreen_pm_prepare,
 - 
 
746 
	.pm_finish = &evergreen_pm_finish,
 - 
 
747 
	.pm_init_profile = &r600_pm_init_profile,
 - 
 
748 
	.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 - 
 
749 
	.pre_page_flip = &evergreen_pre_page_flip,
 - 
 
750 
	.page_flip = &evergreen_page_flip,
 - 
 
751 
	.post_page_flip = &evergreen_post_page_flip,
 - 
 
752 
};
 742 
};
753 
#endif
 - 
 
754 
 
 743 
 
755 
int radeon_asic_init(struct radeon_device *rdev)
 744 
int radeon_asic_init(struct radeon_device *rdev)
756 
{
 745 
{
757 
	radeon_register_accessor_init(rdev);
 746 
	radeon_register_accessor_init(rdev);
758 
 
 747 
 
759 
	/* set the number of crtcs */
 748 
	/* set the number of crtcs */
760 
	if (rdev->flags & RADEON_SINGLE_CRTC)
 749 
	if (rdev->flags & RADEON_SINGLE_CRTC)
761 
		rdev->num_crtc = 1;
 750 
		rdev->num_crtc = 1;
762 
	else
 751 
	else
763 
		rdev->num_crtc = 2;
 752 
		rdev->num_crtc = 2;
764 
 
 753 
 
765 
	switch (rdev->family) {
 754 
	switch (rdev->family) {
766 
	case CHIP_R100:
 755 
	case CHIP_R100:
767 
	case CHIP_RV100:
 756 
	case CHIP_RV100:
768 
	case CHIP_RS100:
 757 
	case CHIP_RS100:
769 
	case CHIP_RV200:
 758 
	case CHIP_RV200:
770 
	case CHIP_RS200:
 759 
	case CHIP_RS200:
771 
		rdev->asic = &r100_asic;
 760 
		rdev->asic = &r100_asic;
772 
		break;
 761 
		break;
773 
	case CHIP_R200:
 762 
	case CHIP_R200:
774 
	case CHIP_RV250:
 763 
	case CHIP_RV250:
775 
	case CHIP_RS300:
 764 
	case CHIP_RS300:
776 
	case CHIP_RV280:
 765 
	case CHIP_RV280:
777 
		rdev->asic = &r200_asic;
 766 
		rdev->asic = &r200_asic;
778 
		break;
 767 
		break;
779 
	case CHIP_R300:
 768 
	case CHIP_R300:
780 
	case CHIP_R350:
 769 
	case CHIP_R350:
781 
	case CHIP_RV350:
 770 
	case CHIP_RV350:
782 
	case CHIP_RV380:
 771 
	case CHIP_RV380:
783 
		if (rdev->flags & RADEON_IS_PCIE)
 772 
		if (rdev->flags & RADEON_IS_PCIE)
784 
			rdev->asic = &r300_asic_pcie;
 773 
			rdev->asic = &r300_asic_pcie;
785 
		else
 774 
		else
786 
			rdev->asic = &r300_asic;
 775 
			rdev->asic = &r300_asic;
787 
		break;
 776 
		break;
788 
	case CHIP_R420:
 777 
	case CHIP_R420:
789 
	case CHIP_R423:
 778 
	case CHIP_R423:
790 
	case CHIP_RV410:
 779 
	case CHIP_RV410:
791 
		rdev->asic = &r420_asic;
 780 
		rdev->asic = &r420_asic;
792 
		/* handle macs */
 781 
		/* handle macs */
793 
		if (rdev->bios == NULL) {
 782 
		if (rdev->bios == NULL) {
794 
			rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
 783 
			rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
795 
			rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
 784 
			rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
796 
			rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
 785 
			rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
797 
			rdev->asic->set_memory_clock = NULL;
 786 
			rdev->asic->set_memory_clock = NULL;
798 
		}
 787 
		}
799 
		break;
 788 
		break;
800 
	case CHIP_RS400:
 789 
	case CHIP_RS400:
801 
	case CHIP_RS480:
 790 
	case CHIP_RS480:
802 
		rdev->asic = &rs400_asic;
 791 
		rdev->asic = &rs400_asic;
803 
		break;
 792 
		break;
804 
	case CHIP_RS600:
 793 
	case CHIP_RS600:
805 
		rdev->asic = &rs600_asic;
 794 
		rdev->asic = &rs600_asic;
806 
		break;
 795 
		break;
807 
	case CHIP_RS690:
 796 
	case CHIP_RS690:
808 
	case CHIP_RS740:
 797 
	case CHIP_RS740:
809 
		rdev->asic = &rs690_asic;
 798 
		rdev->asic = &rs690_asic;
810 
		break;
 799 
		break;
811 
	case CHIP_RV515:
 800 
	case CHIP_RV515:
812 
		rdev->asic = &rv515_asic;
 801 
		rdev->asic = &rv515_asic;
813 
		break;
 802 
		break;
814 
	case CHIP_R520:
 803 
	case CHIP_R520:
815 
	case CHIP_RV530:
 804 
	case CHIP_RV530:
816 
	case CHIP_RV560:
 805 
	case CHIP_RV560:
817 
	case CHIP_RV570:
 806 
	case CHIP_RV570:
818 
	case CHIP_R580:
 807 
	case CHIP_R580:
819 
		rdev->asic = &r520_asic;
 808 
		rdev->asic = &r520_asic;
820 
		break;
 809 
		break;
821 
	case CHIP_R600:
 810 
	case CHIP_R600:
822 
	case CHIP_RV610:
 811 
	case CHIP_RV610:
823 
	case CHIP_RV630:
 812 
	case CHIP_RV630:
824 
	case CHIP_RV620:
 813 
	case CHIP_RV620:
825 
	case CHIP_RV635:
 814 
	case CHIP_RV635:
826 
	case CHIP_RV670:
 815 
	case CHIP_RV670:
827 
		rdev->asic = &r600_asic;
 816 
		rdev->asic = &r600_asic;
828 
		break;
 817 
		break;
829 
	case CHIP_RS780:
 818 
	case CHIP_RS780:
830 
	case CHIP_RS880:
 819 
	case CHIP_RS880:
831 
		rdev->asic = &rs780_asic;
 820 
		rdev->asic = &rs780_asic;
832 
		break;
 821 
		break;
833 
	case CHIP_RV770:
 822 
	case CHIP_RV770:
834 
	case CHIP_RV730:
 823 
	case CHIP_RV730:
835 
	case CHIP_RV710:
 824 
	case CHIP_RV710:
836 
	case CHIP_RV740:
 825 
	case CHIP_RV740:
837 
		rdev->asic = &rv770_asic;
 826 
		rdev->asic = &rv770_asic;
838 
		break;
 827 
		break;
839 
	case CHIP_CEDAR:
 828 
	case CHIP_CEDAR:
840 
	case CHIP_REDWOOD:
 829 
	case CHIP_REDWOOD:
841 
	case CHIP_JUNIPER:
 830 
	case CHIP_JUNIPER:
842 
	case CHIP_CYPRESS:
 831 
	case CHIP_CYPRESS:
843 
	case CHIP_HEMLOCK:
 832 
	case CHIP_HEMLOCK:
844 
		/* set num crtcs */
 833 
		/* set num crtcs */
845 
		if (rdev->family == CHIP_CEDAR)
 834 
		if (rdev->family == CHIP_CEDAR)
846 
			rdev->num_crtc = 4;
 835 
			rdev->num_crtc = 4;
847 
		else
 836 
		else
848 
			rdev->num_crtc = 6;
 837 
			rdev->num_crtc = 6;
849 
		rdev->asic = &evergreen_asic;
 838 
		rdev->asic = &evergreen_asic;
850 
		break;
 839 
		break;
851 
	case CHIP_PALM:
 840 
	case CHIP_PALM:
852 
	case CHIP_SUMO:
 841 
	case CHIP_SUMO:
853 
	case CHIP_SUMO2:
 842 
	case CHIP_SUMO2:
854 
		rdev->asic = &sumo_asic;
 843 
		rdev->asic = &sumo_asic;
855 
		break;
 844 
		break;
856 
	case CHIP_BARTS:
 845 
	case CHIP_BARTS:
857 
	case CHIP_TURKS:
 846 
	case CHIP_TURKS:
858 
	case CHIP_CAICOS:
 847 
	case CHIP_CAICOS:
859 
		/* set num crtcs */
 848 
		/* set num crtcs */
860 
		if (rdev->family == CHIP_CAICOS)
 849 
		if (rdev->family == CHIP_CAICOS)
861 
			rdev->num_crtc = 4;
 850 
			rdev->num_crtc = 4;
862 
		else
 851 
		else
863 
			rdev->num_crtc = 6;
 852 
			rdev->num_crtc = 6;
864 
		rdev->asic = &btc_asic;
 853 
		rdev->asic = &btc_asic;
865 
		break;
 854 
		break;
- 
 
 855 
	case CHIP_CAYMAN:
- 
 
 856 
		rdev->asic = &cayman_asic;
- 
 
 857 
		/* set num crtcs */
- 
 
 858 
		rdev->num_crtc = 6;
866 
 
 859 
		break;
867 
	default:
 860 
	default:
868 
		/* FIXME: not supported yet */
 861 
		/* FIXME: not supported yet */
869 
		return -EINVAL;
 862 
		return -EINVAL;
870 
	}
 863 
	}
871 
 
 864 
 
872 
	if (rdev->flags & RADEON_IS_IGP) {
 865 
	if (rdev->flags & RADEON_IS_IGP) {
873 
		rdev->asic->get_memory_clock = NULL;
 866 
		rdev->asic->get_memory_clock = NULL;
874 
		rdev->asic->set_memory_clock = NULL;
 867 
		rdev->asic->set_memory_clock = NULL;
875 
	}
 868 
	}
876 
 
 869 
 
877 
	return 0;
 870 
	return 0;
878 
}
 871 
}