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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #ifndef __RADEON_H__ |
28 | #ifndef __RADEON_H__ |
29 | #define __RADEON_H__ |
29 | #define __RADEON_H__ |
30 | 30 | ||
31 | /* TODO: Here are things that needs to be done : |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should |
32 | * - surface allocator & initializer : (bit like scratch reg) should |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
34 | * related to surface |
34 | * related to surface |
35 | * - WB : write back stuff (do it bit like scratch reg things) |
35 | * - WB : write back stuff (do it bit like scratch reg things) |
36 | * - Vblank : look at Jesse's rework and what we should do |
36 | * - Vblank : look at Jesse's rework and what we should do |
37 | * - r600/r700: gart & cp |
37 | * - r600/r700: gart & cp |
38 | * - cs : clean cs ioctl use bitmap & things like that. |
38 | * - cs : clean cs ioctl use bitmap & things like that. |
39 | * - power management stuff |
39 | * - power management stuff |
40 | * - Barrier in gart code |
40 | * - Barrier in gart code |
41 | * - Unmappabled vram ? |
41 | * - Unmappabled vram ? |
42 | * - TESTING, TESTING, TESTING |
42 | * - TESTING, TESTING, TESTING |
43 | */ |
43 | */ |
44 | 44 | ||
45 | /* Initialization path: |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
46 | * We expect that acceleration initialization might fail for various |
47 | * reasons even thought we work hard to make it works on most |
47 | * reasons even thought we work hard to make it works on most |
48 | * configurations. In order to still have a working userspace in such |
48 | * configurations. In order to still have a working userspace in such |
49 | * situation the init path must succeed up to the memory controller |
49 | * situation the init path must succeed up to the memory controller |
50 | * initialization point. Failure before this point are considered as |
50 | * initialization point. Failure before this point are considered as |
51 | * fatal error. Here is the init callchain : |
51 | * fatal error. Here is the init callchain : |
52 | * radeon_device_init perform common structure, mutex initialization |
52 | * radeon_device_init perform common structure, mutex initialization |
53 | * asic_init setup the GPU memory layout and perform all |
53 | * asic_init setup the GPU memory layout and perform all |
54 | * one time initialization (failure in this |
54 | * one time initialization (failure in this |
55 | * function are considered fatal) |
55 | * function are considered fatal) |
56 | * asic_startup setup the GPU acceleration, in order to |
56 | * asic_startup setup the GPU acceleration, in order to |
57 | * follow guideline the first thing this |
57 | * follow guideline the first thing this |
58 | * function should do is setting the GPU |
58 | * function should do is setting the GPU |
59 | * memory controller (only MC setup failure |
59 | * memory controller (only MC setup failure |
60 | * are considered as fatal) |
60 | * are considered as fatal) |
61 | */ |
61 | */ |
62 | 62 | ||
63 | #include |
63 | #include |
64 | #include |
64 | #include |
65 | #include |
65 | #include |
66 | #include |
66 | #include |
67 | #include |
67 | #include |
68 | #include |
68 | #include |
69 | #include |
69 | #include |
70 | 70 | ||
71 | #include |
71 | #include |
72 | #include |
72 | #include |
73 | #include |
73 | #include |
74 | #include |
74 | #include |
75 | #include |
75 | #include |
76 | #include |
76 | #include |
77 | 77 | ||
78 | #include |
78 | #include |
79 | 79 | ||
80 | #include |
80 | #include |
81 | #include |
81 | #include |
82 | 82 | ||
83 | #include "radeon_family.h" |
83 | #include "radeon_family.h" |
84 | #include "radeon_mode.h" |
84 | #include "radeon_mode.h" |
85 | #include "radeon_reg.h" |
85 | #include "radeon_reg.h" |
86 | 86 | ||
87 | #include |
87 | #include |
88 | 88 | ||
89 | /* |
89 | /* |
90 | * Modules parameters. |
90 | * Modules parameters. |
91 | */ |
91 | */ |
92 | extern int radeon_no_wb; |
92 | extern int radeon_no_wb; |
93 | extern int radeon_modeset; |
93 | extern int radeon_modeset; |
94 | extern int radeon_dynclks; |
94 | extern int radeon_dynclks; |
95 | extern int radeon_r4xx_atom; |
95 | extern int radeon_r4xx_atom; |
96 | extern int radeon_agpmode; |
96 | extern int radeon_agpmode; |
97 | extern int radeon_vram_limit; |
97 | extern int radeon_vram_limit; |
98 | extern int radeon_gart_size; |
98 | extern int radeon_gart_size; |
99 | extern int radeon_benchmarking; |
99 | extern int radeon_benchmarking; |
100 | extern int radeon_testing; |
100 | extern int radeon_testing; |
101 | extern int radeon_connector_table; |
101 | extern int radeon_connector_table; |
102 | extern int radeon_tv; |
102 | extern int radeon_tv; |
103 | extern int radeon_audio; |
103 | extern int radeon_audio; |
104 | extern int radeon_disp_priority; |
104 | extern int radeon_disp_priority; |
105 | extern int radeon_hw_i2c; |
105 | extern int radeon_hw_i2c; |
106 | extern int radeon_pcie_gen2; |
106 | extern int radeon_pcie_gen2; |
107 | extern int radeon_msi; |
107 | extern int radeon_msi; |
108 | extern int radeon_lockup_timeout; |
108 | extern int radeon_lockup_timeout; |
109 | extern int radeon_fastfb; |
109 | extern int radeon_fastfb; |
110 | extern int radeon_dpm; |
110 | extern int radeon_dpm; |
111 | extern int radeon_aspm; |
111 | extern int radeon_aspm; |
112 | extern int radeon_runtime_pm; |
112 | extern int radeon_runtime_pm; |
113 | extern int radeon_hard_reset; |
113 | extern int radeon_hard_reset; |
114 | extern int radeon_vm_size; |
114 | extern int radeon_vm_size; |
115 | extern int radeon_vm_block_size; |
115 | extern int radeon_vm_block_size; |
116 | extern int radeon_deep_color; |
116 | extern int radeon_deep_color; |
117 | extern int radeon_use_pflipirq; |
117 | extern int radeon_use_pflipirq; |
118 | extern int radeon_bapm; |
118 | extern int radeon_bapm; |
119 | extern int radeon_backlight; |
119 | extern int radeon_backlight; |
120 | extern int radeon_auxch; |
120 | extern int radeon_auxch; |
121 | extern int radeon_mst; |
121 | extern int radeon_mst; |
122 | 122 | ||
123 | /* |
123 | /* |
124 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
124 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
125 | * symbol; |
125 | * symbol; |
126 | */ |
126 | */ |
127 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
127 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
128 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
128 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
- | 129 | #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ |
|
129 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
130 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
130 | #define RADEON_IB_POOL_SIZE 16 |
131 | #define RADEON_IB_POOL_SIZE 16 |
131 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
132 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
132 | #define RADEONFB_CONN_LIMIT 4 |
133 | #define RADEONFB_CONN_LIMIT 4 |
133 | #define RADEON_BIOS_NUM_SCRATCH 8 |
134 | #define RADEON_BIOS_NUM_SCRATCH 8 |
134 | 135 | ||
135 | /* internal ring indices */ |
136 | /* internal ring indices */ |
136 | /* r1xx+ has gfx CP ring */ |
137 | /* r1xx+ has gfx CP ring */ |
137 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
138 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
138 | 139 | ||
139 | /* cayman has 2 compute CP rings */ |
140 | /* cayman has 2 compute CP rings */ |
140 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
141 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
141 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
142 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
142 | 143 | ||
143 | /* R600+ has an async dma ring */ |
144 | /* R600+ has an async dma ring */ |
144 | #define R600_RING_TYPE_DMA_INDEX 3 |
145 | #define R600_RING_TYPE_DMA_INDEX 3 |
145 | /* cayman add a second async dma ring */ |
146 | /* cayman add a second async dma ring */ |
146 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
147 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
147 | 148 | ||
148 | /* R600+ */ |
149 | /* R600+ */ |
149 | #define R600_RING_TYPE_UVD_INDEX 5 |
150 | #define R600_RING_TYPE_UVD_INDEX 5 |
150 | 151 | ||
151 | /* TN+ */ |
152 | /* TN+ */ |
152 | #define TN_RING_TYPE_VCE1_INDEX 6 |
153 | #define TN_RING_TYPE_VCE1_INDEX 6 |
153 | #define TN_RING_TYPE_VCE2_INDEX 7 |
154 | #define TN_RING_TYPE_VCE2_INDEX 7 |
154 | 155 | ||
155 | /* max number of rings */ |
156 | /* max number of rings */ |
156 | #define RADEON_NUM_RINGS 8 |
157 | #define RADEON_NUM_RINGS 8 |
157 | 158 | ||
158 | /* number of hw syncs before falling back on blocking */ |
159 | /* number of hw syncs before falling back on blocking */ |
159 | #define RADEON_NUM_SYNCS 4 |
160 | #define RADEON_NUM_SYNCS 4 |
160 | 161 | ||
161 | /* hardcode those limit for now */ |
162 | /* hardcode those limit for now */ |
162 | #define RADEON_VA_IB_OFFSET (1 << 20) |
163 | #define RADEON_VA_IB_OFFSET (1 << 20) |
163 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
164 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
164 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
165 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
165 | 166 | ||
166 | /* hard reset data */ |
167 | /* hard reset data */ |
167 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b |
168 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b |
168 | 169 | ||
169 | /* reset flags */ |
170 | /* reset flags */ |
170 | #define RADEON_RESET_GFX (1 << 0) |
171 | #define RADEON_RESET_GFX (1 << 0) |
171 | #define RADEON_RESET_COMPUTE (1 << 1) |
172 | #define RADEON_RESET_COMPUTE (1 << 1) |
172 | #define RADEON_RESET_DMA (1 << 2) |
173 | #define RADEON_RESET_DMA (1 << 2) |
173 | #define RADEON_RESET_CP (1 << 3) |
174 | #define RADEON_RESET_CP (1 << 3) |
174 | #define RADEON_RESET_GRBM (1 << 4) |
175 | #define RADEON_RESET_GRBM (1 << 4) |
175 | #define RADEON_RESET_DMA1 (1 << 5) |
176 | #define RADEON_RESET_DMA1 (1 << 5) |
176 | #define RADEON_RESET_RLC (1 << 6) |
177 | #define RADEON_RESET_RLC (1 << 6) |
177 | #define RADEON_RESET_SEM (1 << 7) |
178 | #define RADEON_RESET_SEM (1 << 7) |
178 | #define RADEON_RESET_IH (1 << 8) |
179 | #define RADEON_RESET_IH (1 << 8) |
179 | #define RADEON_RESET_VMC (1 << 9) |
180 | #define RADEON_RESET_VMC (1 << 9) |
180 | #define RADEON_RESET_MC (1 << 10) |
181 | #define RADEON_RESET_MC (1 << 10) |
181 | #define RADEON_RESET_DISPLAY (1 << 11) |
182 | #define RADEON_RESET_DISPLAY (1 << 11) |
182 | 183 | ||
183 | /* CG block flags */ |
184 | /* CG block flags */ |
184 | #define RADEON_CG_BLOCK_GFX (1 << 0) |
185 | #define RADEON_CG_BLOCK_GFX (1 << 0) |
185 | #define RADEON_CG_BLOCK_MC (1 << 1) |
186 | #define RADEON_CG_BLOCK_MC (1 << 1) |
186 | #define RADEON_CG_BLOCK_SDMA (1 << 2) |
187 | #define RADEON_CG_BLOCK_SDMA (1 << 2) |
187 | #define RADEON_CG_BLOCK_UVD (1 << 3) |
188 | #define RADEON_CG_BLOCK_UVD (1 << 3) |
188 | #define RADEON_CG_BLOCK_VCE (1 << 4) |
189 | #define RADEON_CG_BLOCK_VCE (1 << 4) |
189 | #define RADEON_CG_BLOCK_HDP (1 << 5) |
190 | #define RADEON_CG_BLOCK_HDP (1 << 5) |
190 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
191 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
191 | 192 | ||
192 | /* CG flags */ |
193 | /* CG flags */ |
193 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) |
194 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) |
194 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) |
195 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) |
195 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) |
196 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) |
196 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) |
197 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) |
197 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) |
198 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) |
198 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) |
199 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) |
199 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) |
200 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) |
200 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) |
201 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) |
201 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) |
202 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) |
202 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) |
203 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) |
203 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) |
204 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) |
204 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) |
205 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) |
205 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) |
206 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) |
206 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) |
207 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) |
207 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) |
208 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) |
208 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) |
209 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) |
209 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) |
210 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) |
210 | 211 | ||
211 | /* PG flags */ |
212 | /* PG flags */ |
212 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
213 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
213 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
214 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
214 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) |
215 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) |
215 | #define RADEON_PG_SUPPORT_UVD (1 << 3) |
216 | #define RADEON_PG_SUPPORT_UVD (1 << 3) |
216 | #define RADEON_PG_SUPPORT_VCE (1 << 4) |
217 | #define RADEON_PG_SUPPORT_VCE (1 << 4) |
217 | #define RADEON_PG_SUPPORT_CP (1 << 5) |
218 | #define RADEON_PG_SUPPORT_CP (1 << 5) |
218 | #define RADEON_PG_SUPPORT_GDS (1 << 6) |
219 | #define RADEON_PG_SUPPORT_GDS (1 << 6) |
219 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) |
220 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) |
220 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) |
221 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) |
221 | #define RADEON_PG_SUPPORT_ACP (1 << 9) |
222 | #define RADEON_PG_SUPPORT_ACP (1 << 9) |
222 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) |
223 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) |
223 | 224 | ||
224 | /* max cursor sizes (in pixels) */ |
225 | /* max cursor sizes (in pixels) */ |
225 | #define CURSOR_WIDTH 64 |
226 | #define CURSOR_WIDTH 64 |
226 | #define CURSOR_HEIGHT 64 |
227 | #define CURSOR_HEIGHT 64 |
227 | 228 | ||
228 | #define CIK_CURSOR_WIDTH 128 |
229 | #define CIK_CURSOR_WIDTH 128 |
229 | #define CIK_CURSOR_HEIGHT 128 |
230 | #define CIK_CURSOR_HEIGHT 128 |
230 | 231 | ||
231 | /* |
232 | /* |
232 | * Errata workarounds. |
233 | * Errata workarounds. |
233 | */ |
234 | */ |
234 | enum radeon_pll_errata { |
235 | enum radeon_pll_errata { |
235 | CHIP_ERRATA_R300_CG = 0x00000001, |
236 | CHIP_ERRATA_R300_CG = 0x00000001, |
236 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
237 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
237 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
238 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
238 | }; |
239 | }; |
239 | 240 | ||
240 | 241 | ||
241 | struct radeon_device; |
242 | struct radeon_device; |
242 | 243 | ||
243 | 244 | ||
244 | /* |
245 | /* |
245 | * BIOS. |
246 | * BIOS. |
246 | */ |
247 | */ |
247 | bool radeon_get_bios(struct radeon_device *rdev); |
248 | bool radeon_get_bios(struct radeon_device *rdev); |
248 | 249 | ||
249 | /* |
250 | /* |
250 | * Dummy page |
251 | * Dummy page |
251 | */ |
252 | */ |
252 | struct radeon_dummy_page { |
253 | struct radeon_dummy_page { |
253 | uint64_t entry; |
254 | uint64_t entry; |
254 | struct page *page; |
255 | struct page *page; |
255 | dma_addr_t addr; |
256 | dma_addr_t addr; |
256 | }; |
257 | }; |
257 | int radeon_dummy_page_init(struct radeon_device *rdev); |
258 | int radeon_dummy_page_init(struct radeon_device *rdev); |
258 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
259 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
259 | 260 | ||
260 | 261 | ||
261 | /* |
262 | /* |
262 | * Clocks |
263 | * Clocks |
263 | */ |
264 | */ |
264 | struct radeon_clock { |
265 | struct radeon_clock { |
265 | struct radeon_pll p1pll; |
266 | struct radeon_pll p1pll; |
266 | struct radeon_pll p2pll; |
267 | struct radeon_pll p2pll; |
267 | struct radeon_pll dcpll; |
268 | struct radeon_pll dcpll; |
268 | struct radeon_pll spll; |
269 | struct radeon_pll spll; |
269 | struct radeon_pll mpll; |
270 | struct radeon_pll mpll; |
270 | /* 10 Khz units */ |
271 | /* 10 Khz units */ |
271 | uint32_t default_mclk; |
272 | uint32_t default_mclk; |
272 | uint32_t default_sclk; |
273 | uint32_t default_sclk; |
273 | uint32_t default_dispclk; |
274 | uint32_t default_dispclk; |
274 | uint32_t current_dispclk; |
275 | uint32_t current_dispclk; |
275 | uint32_t dp_extclk; |
276 | uint32_t dp_extclk; |
276 | uint32_t max_pixel_clock; |
277 | uint32_t max_pixel_clock; |
277 | uint32_t vco_freq; |
278 | uint32_t vco_freq; |
278 | }; |
279 | }; |
279 | 280 | ||
280 | /* |
281 | /* |
281 | * Power management |
282 | * Power management |
282 | */ |
283 | */ |
283 | int radeon_pm_init(struct radeon_device *rdev); |
284 | int radeon_pm_init(struct radeon_device *rdev); |
284 | int radeon_pm_late_init(struct radeon_device *rdev); |
285 | int radeon_pm_late_init(struct radeon_device *rdev); |
285 | void radeon_pm_fini(struct radeon_device *rdev); |
286 | void radeon_pm_fini(struct radeon_device *rdev); |
286 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
287 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
287 | void radeon_pm_suspend(struct radeon_device *rdev); |
288 | void radeon_pm_suspend(struct radeon_device *rdev); |
288 | void radeon_pm_resume(struct radeon_device *rdev); |
289 | void radeon_pm_resume(struct radeon_device *rdev); |
289 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
290 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
290 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
291 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
291 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
292 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
292 | u8 clock_type, |
293 | u8 clock_type, |
293 | u32 clock, |
294 | u32 clock, |
294 | bool strobe_mode, |
295 | bool strobe_mode, |
295 | struct atom_clock_dividers *dividers); |
296 | struct atom_clock_dividers *dividers); |
296 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
297 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
297 | u32 clock, |
298 | u32 clock, |
298 | bool strobe_mode, |
299 | bool strobe_mode, |
299 | struct atom_mpll_param *mpll_param); |
300 | struct atom_mpll_param *mpll_param); |
300 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
301 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
301 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
302 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
302 | u16 voltage_level, u8 voltage_type, |
303 | u16 voltage_level, u8 voltage_type, |
303 | u32 *gpio_value, u32 *gpio_mask); |
304 | u32 *gpio_value, u32 *gpio_mask); |
304 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
305 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
305 | u32 eng_clock, u32 mem_clock); |
306 | u32 eng_clock, u32 mem_clock); |
306 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
307 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
307 | u8 voltage_type, u16 *voltage_step); |
308 | u8 voltage_type, u16 *voltage_step); |
308 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
309 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
309 | u16 voltage_id, u16 *voltage); |
310 | u16 voltage_id, u16 *voltage); |
310 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
311 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
311 | u16 *voltage, |
312 | u16 *voltage, |
312 | u16 leakage_idx); |
313 | u16 leakage_idx); |
313 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
314 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
314 | u16 *leakage_id); |
315 | u16 *leakage_id); |
315 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
316 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
316 | u16 *vddc, u16 *vddci, |
317 | u16 *vddc, u16 *vddci, |
317 | u16 virtual_voltage_id, |
318 | u16 virtual_voltage_id, |
318 | u16 vbios_voltage_id); |
319 | u16 vbios_voltage_id); |
319 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, |
320 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, |
320 | u16 virtual_voltage_id, |
321 | u16 virtual_voltage_id, |
321 | u16 *voltage); |
322 | u16 *voltage); |
322 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
323 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
323 | u8 voltage_type, |
324 | u8 voltage_type, |
324 | u16 nominal_voltage, |
325 | u16 nominal_voltage, |
325 | u16 *true_voltage); |
326 | u16 *true_voltage); |
326 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
327 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
327 | u8 voltage_type, u16 *min_voltage); |
328 | u8 voltage_type, u16 *min_voltage); |
328 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
329 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
329 | u8 voltage_type, u16 *max_voltage); |
330 | u8 voltage_type, u16 *max_voltage); |
330 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
331 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
331 | u8 voltage_type, u8 voltage_mode, |
332 | u8 voltage_type, u8 voltage_mode, |
332 | struct atom_voltage_table *voltage_table); |
333 | struct atom_voltage_table *voltage_table); |
333 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
334 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
334 | u8 voltage_type, u8 voltage_mode); |
335 | u8 voltage_type, u8 voltage_mode); |
335 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
336 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
336 | u8 voltage_type, |
337 | u8 voltage_type, |
337 | u8 *svd_gpio_id, u8 *svc_gpio_id); |
338 | u8 *svd_gpio_id, u8 *svc_gpio_id); |
338 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
339 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
339 | u32 mem_clock); |
340 | u32 mem_clock); |
340 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
341 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
341 | u32 mem_clock); |
342 | u32 mem_clock); |
342 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
343 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
343 | u8 module_index, |
344 | u8 module_index, |
344 | struct atom_mc_reg_table *reg_table); |
345 | struct atom_mc_reg_table *reg_table); |
345 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
346 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
346 | u8 module_index, struct atom_memory_info *mem_info); |
347 | u8 module_index, struct atom_memory_info *mem_info); |
347 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
348 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
348 | bool gddr5, u8 module_index, |
349 | bool gddr5, u8 module_index, |
349 | struct atom_memory_clock_range_table *mclk_range_table); |
350 | struct atom_memory_clock_range_table *mclk_range_table); |
350 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
351 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
351 | u16 voltage_id, u16 *voltage); |
352 | u16 voltage_id, u16 *voltage); |
352 | void rs690_pm_info(struct radeon_device *rdev); |
353 | void rs690_pm_info(struct radeon_device *rdev); |
353 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
354 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
354 | unsigned *bankh, unsigned *mtaspect, |
355 | unsigned *bankh, unsigned *mtaspect, |
355 | unsigned *tile_split); |
356 | unsigned *tile_split); |
356 | 357 | ||
357 | /* |
358 | /* |
358 | * Fences. |
359 | * Fences. |
359 | */ |
360 | */ |
360 | struct radeon_fence_driver { |
361 | struct radeon_fence_driver { |
361 | struct radeon_device *rdev; |
362 | struct radeon_device *rdev; |
362 | uint32_t scratch_reg; |
363 | uint32_t scratch_reg; |
363 | uint64_t gpu_addr; |
364 | uint64_t gpu_addr; |
364 | volatile uint32_t *cpu_addr; |
365 | volatile uint32_t *cpu_addr; |
365 | /* sync_seq is protected by ring emission lock */ |
366 | /* sync_seq is protected by ring emission lock */ |
366 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
367 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
367 | atomic64_t last_seq; |
368 | atomic64_t last_seq; |
368 | bool initialized, delayed_irq; |
369 | bool initialized, delayed_irq; |
369 | struct delayed_work lockup_work; |
370 | struct delayed_work lockup_work; |
370 | }; |
371 | }; |
371 | 372 | ||
372 | struct radeon_fence { |
373 | struct radeon_fence { |
373 | struct fence base; |
374 | struct fence base; |
374 | 375 | ||
375 | struct radeon_device *rdev; |
376 | struct radeon_device *rdev; |
376 | uint64_t seq; |
377 | uint64_t seq; |
377 | /* RB, DMA, etc. */ |
378 | /* RB, DMA, etc. */ |
378 | unsigned ring; |
379 | unsigned ring; |
379 | bool is_vm_update; |
380 | bool is_vm_update; |
380 | 381 | ||
381 | wait_queue_t fence_wake; |
382 | wait_queue_t fence_wake; |
382 | }; |
383 | }; |
383 | 384 | ||
384 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
385 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
385 | int radeon_fence_driver_init(struct radeon_device *rdev); |
386 | int radeon_fence_driver_init(struct radeon_device *rdev); |
386 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
387 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
387 | void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); |
388 | void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); |
388 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
389 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
389 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
390 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
390 | bool radeon_fence_signaled(struct radeon_fence *fence); |
391 | bool radeon_fence_signaled(struct radeon_fence *fence); |
- | 392 | long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); |
|
391 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
393 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
392 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
394 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
393 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); |
395 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); |
394 | int radeon_fence_wait_any(struct radeon_device *rdev, |
396 | int radeon_fence_wait_any(struct radeon_device *rdev, |
395 | struct radeon_fence **fences, |
397 | struct radeon_fence **fences, |
396 | bool intr); |
398 | bool intr); |
397 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
399 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
398 | void radeon_fence_unref(struct radeon_fence **fence); |
400 | void radeon_fence_unref(struct radeon_fence **fence); |
399 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
401 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
400 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
402 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
401 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
403 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
402 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
404 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
403 | struct radeon_fence *b) |
405 | struct radeon_fence *b) |
404 | { |
406 | { |
405 | if (!a) { |
407 | if (!a) { |
406 | return b; |
408 | return b; |
407 | } |
409 | } |
408 | 410 | ||
409 | if (!b) { |
411 | if (!b) { |
410 | return a; |
412 | return a; |
411 | } |
413 | } |
412 | 414 | ||
413 | BUG_ON(a->ring != b->ring); |
415 | BUG_ON(a->ring != b->ring); |
414 | 416 | ||
415 | if (a->seq > b->seq) { |
417 | if (a->seq > b->seq) { |
416 | return a; |
418 | return a; |
417 | } else { |
419 | } else { |
418 | return b; |
420 | return b; |
419 | } |
421 | } |
420 | } |
422 | } |
421 | 423 | ||
422 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
424 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
423 | struct radeon_fence *b) |
425 | struct radeon_fence *b) |
424 | { |
426 | { |
425 | if (!a) { |
427 | if (!a) { |
426 | return false; |
428 | return false; |
427 | } |
429 | } |
428 | 430 | ||
429 | if (!b) { |
431 | if (!b) { |
430 | return true; |
432 | return true; |
431 | } |
433 | } |
432 | 434 | ||
433 | BUG_ON(a->ring != b->ring); |
435 | BUG_ON(a->ring != b->ring); |
434 | 436 | ||
435 | return a->seq < b->seq; |
437 | return a->seq < b->seq; |
436 | } |
438 | } |
437 | 439 | ||
438 | /* |
440 | /* |
439 | * Tiling registers |
441 | * Tiling registers |
440 | */ |
442 | */ |
441 | struct radeon_surface_reg { |
443 | struct radeon_surface_reg { |
442 | struct radeon_bo *bo; |
444 | struct radeon_bo *bo; |
443 | }; |
445 | }; |
444 | 446 | ||
445 | #define RADEON_GEM_MAX_SURFACES 8 |
447 | #define RADEON_GEM_MAX_SURFACES 8 |
446 | 448 | ||
447 | /* |
449 | /* |
448 | * TTM. |
450 | * TTM. |
449 | */ |
451 | */ |
450 | struct radeon_mman { |
452 | struct radeon_mman { |
451 | struct ttm_bo_global_ref bo_global_ref; |
453 | struct ttm_bo_global_ref bo_global_ref; |
452 | struct drm_global_reference mem_global_ref; |
454 | struct drm_global_reference mem_global_ref; |
453 | struct ttm_bo_device bdev; |
455 | struct ttm_bo_device bdev; |
454 | bool mem_global_referenced; |
456 | bool mem_global_referenced; |
455 | bool initialized; |
457 | bool initialized; |
456 | 458 | ||
457 | #if defined(CONFIG_DEBUG_FS) |
459 | #if defined(CONFIG_DEBUG_FS) |
458 | struct dentry *vram; |
460 | struct dentry *vram; |
459 | struct dentry *gtt; |
461 | struct dentry *gtt; |
460 | #endif |
462 | #endif |
461 | }; |
463 | }; |
462 | 464 | ||
463 | struct radeon_bo_list { |
465 | struct radeon_bo_list { |
464 | struct radeon_bo *robj; |
466 | struct radeon_bo *robj; |
465 | struct ttm_validate_buffer tv; |
467 | struct ttm_validate_buffer tv; |
466 | uint64_t gpu_offset; |
468 | uint64_t gpu_offset; |
467 | unsigned prefered_domains; |
469 | unsigned prefered_domains; |
468 | unsigned allowed_domains; |
470 | unsigned allowed_domains; |
469 | uint32_t tiling_flags; |
471 | uint32_t tiling_flags; |
470 | }; |
472 | }; |
471 | 473 | ||
472 | /* bo virtual address in a specific vm */ |
474 | /* bo virtual address in a specific vm */ |
473 | struct radeon_bo_va { |
475 | struct radeon_bo_va { |
474 | /* protected by bo being reserved */ |
476 | /* protected by bo being reserved */ |
475 | struct list_head bo_list; |
477 | struct list_head bo_list; |
476 | uint32_t flags; |
478 | uint32_t flags; |
477 | uint64_t addr; |
- | |
478 | struct radeon_fence *last_pt_update; |
479 | struct radeon_fence *last_pt_update; |
479 | unsigned ref_count; |
480 | unsigned ref_count; |
480 | 481 | ||
481 | /* protected by vm mutex */ |
482 | /* protected by vm mutex */ |
482 | struct interval_tree_node it; |
483 | struct interval_tree_node it; |
483 | struct list_head vm_status; |
484 | struct list_head vm_status; |
484 | 485 | ||
485 | /* constant after initialization */ |
486 | /* constant after initialization */ |
486 | struct radeon_vm *vm; |
487 | struct radeon_vm *vm; |
487 | struct radeon_bo *bo; |
488 | struct radeon_bo *bo; |
488 | }; |
489 | }; |
489 | 490 | ||
490 | struct radeon_bo { |
491 | struct radeon_bo { |
491 | /* Protected by gem.mutex */ |
492 | /* Protected by gem.mutex */ |
492 | struct list_head list; |
493 | struct list_head list; |
493 | /* Protected by tbo.reserved */ |
494 | /* Protected by tbo.reserved */ |
494 | u32 initial_domain; |
495 | u32 initial_domain; |
495 | struct ttm_place placements[4]; |
496 | struct ttm_place placements[4]; |
496 | struct ttm_placement placement; |
497 | struct ttm_placement placement; |
497 | struct ttm_buffer_object tbo; |
498 | struct ttm_buffer_object tbo; |
498 | struct ttm_bo_kmap_obj kmap; |
499 | struct ttm_bo_kmap_obj kmap; |
499 | u32 flags; |
500 | u32 flags; |
500 | unsigned pin_count; |
501 | unsigned pin_count; |
501 | void *kptr; |
502 | void *kptr; |
502 | u32 tiling_flags; |
503 | u32 tiling_flags; |
503 | u32 pitch; |
504 | u32 pitch; |
504 | int surface_reg; |
505 | int surface_reg; |
505 | /* list of all virtual address to which this bo |
506 | /* list of all virtual address to which this bo |
506 | * is associated to |
507 | * is associated to |
507 | */ |
508 | */ |
508 | struct list_head va; |
509 | struct list_head va; |
509 | /* Constant after initialization */ |
510 | /* Constant after initialization */ |
510 | struct radeon_device *rdev; |
511 | struct radeon_device *rdev; |
511 | struct drm_gem_object gem_base; |
512 | struct drm_gem_object gem_base; |
512 | 513 | ||
513 | pid_t pid; |
514 | pid_t pid; |
514 | 515 | ||
515 | struct radeon_mn *mn; |
516 | struct radeon_mn *mn; |
516 | struct list_head mn_list; |
517 | struct list_head mn_list; |
517 | }; |
518 | }; |
518 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
519 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
519 | 520 | ||
520 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
521 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
521 | 522 | ||
522 | /* sub-allocation manager, it has to be protected by another lock. |
523 | /* sub-allocation manager, it has to be protected by another lock. |
523 | * By conception this is an helper for other part of the driver |
524 | * By conception this is an helper for other part of the driver |
524 | * like the indirect buffer or semaphore, which both have their |
525 | * like the indirect buffer or semaphore, which both have their |
525 | * locking. |
526 | * locking. |
526 | * |
527 | * |
527 | * Principe is simple, we keep a list of sub allocation in offset |
528 | * Principe is simple, we keep a list of sub allocation in offset |
528 | * order (first entry has offset == 0, last entry has the highest |
529 | * order (first entry has offset == 0, last entry has the highest |
529 | * offset). |
530 | * offset). |
530 | * |
531 | * |
531 | * When allocating new object we first check if there is room at |
532 | * When allocating new object we first check if there is room at |
532 | * the end total_size - (last_object_offset + last_object_size) >= |
533 | * the end total_size - (last_object_offset + last_object_size) >= |
533 | * alloc_size. If so we allocate new object there. |
534 | * alloc_size. If so we allocate new object there. |
534 | * |
535 | * |
535 | * When there is not enough room at the end, we start waiting for |
536 | * When there is not enough room at the end, we start waiting for |
536 | * each sub object until we reach object_offset+object_size >= |
537 | * each sub object until we reach object_offset+object_size >= |
537 | * alloc_size, this object then become the sub object we return. |
538 | * alloc_size, this object then become the sub object we return. |
538 | * |
539 | * |
539 | * Alignment can't be bigger than page size. |
540 | * Alignment can't be bigger than page size. |
540 | * |
541 | * |
541 | * Hole are not considered for allocation to keep things simple. |
542 | * Hole are not considered for allocation to keep things simple. |
542 | * Assumption is that there won't be hole (all object on same |
543 | * Assumption is that there won't be hole (all object on same |
543 | * alignment). |
544 | * alignment). |
544 | */ |
545 | */ |
545 | struct radeon_sa_manager { |
546 | struct radeon_sa_manager { |
546 | wait_queue_head_t wq; |
547 | wait_queue_head_t wq; |
547 | struct radeon_bo *bo; |
548 | struct radeon_bo *bo; |
548 | struct list_head *hole; |
549 | struct list_head *hole; |
549 | struct list_head flist[RADEON_NUM_RINGS]; |
550 | struct list_head flist[RADEON_NUM_RINGS]; |
550 | struct list_head olist; |
551 | struct list_head olist; |
551 | unsigned size; |
552 | unsigned size; |
552 | uint64_t gpu_addr; |
553 | uint64_t gpu_addr; |
553 | void *cpu_ptr; |
554 | void *cpu_ptr; |
554 | uint32_t domain; |
555 | uint32_t domain; |
555 | uint32_t align; |
556 | uint32_t align; |
556 | }; |
557 | }; |
557 | 558 | ||
558 | struct radeon_sa_bo; |
559 | struct radeon_sa_bo; |
559 | 560 | ||
560 | /* sub-allocation buffer */ |
561 | /* sub-allocation buffer */ |
561 | struct radeon_sa_bo { |
562 | struct radeon_sa_bo { |
562 | struct list_head olist; |
563 | struct list_head olist; |
563 | struct list_head flist; |
564 | struct list_head flist; |
564 | struct radeon_sa_manager *manager; |
565 | struct radeon_sa_manager *manager; |
565 | unsigned soffset; |
566 | unsigned soffset; |
566 | unsigned eoffset; |
567 | unsigned eoffset; |
567 | struct radeon_fence *fence; |
568 | struct radeon_fence *fence; |
568 | }; |
569 | }; |
569 | 570 | ||
570 | /* |
571 | /* |
571 | * GEM objects. |
572 | * GEM objects. |
572 | */ |
573 | */ |
573 | struct radeon_gem { |
574 | struct radeon_gem { |
574 | struct mutex mutex; |
575 | struct mutex mutex; |
575 | struct list_head objects; |
576 | struct list_head objects; |
576 | }; |
577 | }; |
577 | 578 | ||
578 | int radeon_gem_init(struct radeon_device *rdev); |
579 | int radeon_gem_init(struct radeon_device *rdev); |
579 | void radeon_gem_fini(struct radeon_device *rdev); |
580 | void radeon_gem_fini(struct radeon_device *rdev); |
580 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
581 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
581 | int alignment, int initial_domain, |
582 | int alignment, int initial_domain, |
582 | u32 flags, bool kernel, |
583 | u32 flags, bool kernel, |
583 | struct drm_gem_object **obj); |
584 | struct drm_gem_object **obj); |
584 | 585 | ||
585 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
586 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
586 | struct drm_device *dev, |
587 | struct drm_device *dev, |
587 | struct drm_mode_create_dumb *args); |
588 | struct drm_mode_create_dumb *args); |
588 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
589 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
589 | struct drm_device *dev, |
590 | struct drm_device *dev, |
590 | uint32_t handle, uint64_t *offset_p); |
591 | uint32_t handle, uint64_t *offset_p); |
591 | 592 | ||
592 | /* |
593 | /* |
593 | * Semaphores. |
594 | * Semaphores. |
594 | */ |
595 | */ |
595 | struct radeon_semaphore { |
596 | struct radeon_semaphore { |
596 | struct radeon_sa_bo *sa_bo; |
597 | struct radeon_sa_bo *sa_bo; |
597 | signed waiters; |
598 | signed waiters; |
598 | uint64_t gpu_addr; |
599 | uint64_t gpu_addr; |
599 | }; |
600 | }; |
600 | 601 | ||
601 | int radeon_semaphore_create(struct radeon_device *rdev, |
602 | int radeon_semaphore_create(struct radeon_device *rdev, |
602 | struct radeon_semaphore **semaphore); |
603 | struct radeon_semaphore **semaphore); |
603 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
604 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
604 | struct radeon_semaphore *semaphore); |
605 | struct radeon_semaphore *semaphore); |
605 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
606 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
606 | struct radeon_semaphore *semaphore); |
607 | struct radeon_semaphore *semaphore); |
607 | void radeon_semaphore_free(struct radeon_device *rdev, |
608 | void radeon_semaphore_free(struct radeon_device *rdev, |
608 | struct radeon_semaphore **semaphore, |
609 | struct radeon_semaphore **semaphore, |
609 | struct radeon_fence *fence); |
610 | struct radeon_fence *fence); |
610 | 611 | ||
611 | /* |
612 | /* |
612 | * Synchronization |
613 | * Synchronization |
613 | */ |
614 | */ |
614 | struct radeon_sync { |
615 | struct radeon_sync { |
615 | struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; |
616 | struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; |
616 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
617 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
617 | struct radeon_fence *last_vm_update; |
618 | struct radeon_fence *last_vm_update; |
618 | }; |
619 | }; |
619 | 620 | ||
620 | void radeon_sync_create(struct radeon_sync *sync); |
621 | void radeon_sync_create(struct radeon_sync *sync); |
621 | void radeon_sync_fence(struct radeon_sync *sync, |
622 | void radeon_sync_fence(struct radeon_sync *sync, |
622 | struct radeon_fence *fence); |
623 | struct radeon_fence *fence); |
623 | int radeon_sync_resv(struct radeon_device *rdev, |
624 | int radeon_sync_resv(struct radeon_device *rdev, |
624 | struct radeon_sync *sync, |
625 | struct radeon_sync *sync, |
625 | struct reservation_object *resv, |
626 | struct reservation_object *resv, |
626 | bool shared); |
627 | bool shared); |
627 | int radeon_sync_rings(struct radeon_device *rdev, |
628 | int radeon_sync_rings(struct radeon_device *rdev, |
628 | struct radeon_sync *sync, |
629 | struct radeon_sync *sync, |
629 | int waiting_ring); |
630 | int waiting_ring); |
630 | void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, |
631 | void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, |
631 | struct radeon_fence *fence); |
632 | struct radeon_fence *fence); |
632 | 633 | ||
633 | /* |
634 | /* |
634 | * GART structures, functions & helpers |
635 | * GART structures, functions & helpers |
635 | */ |
636 | */ |
636 | struct radeon_mc; |
637 | struct radeon_mc; |
637 | 638 | ||
638 | #define RADEON_GPU_PAGE_SIZE 4096 |
639 | #define RADEON_GPU_PAGE_SIZE 4096 |
639 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
640 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
640 | #define RADEON_GPU_PAGE_SHIFT 12 |
641 | #define RADEON_GPU_PAGE_SHIFT 12 |
641 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
642 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
642 | 643 | ||
643 | #define RADEON_GART_PAGE_DUMMY 0 |
644 | #define RADEON_GART_PAGE_DUMMY 0 |
644 | #define RADEON_GART_PAGE_VALID (1 << 0) |
645 | #define RADEON_GART_PAGE_VALID (1 << 0) |
645 | #define RADEON_GART_PAGE_READ (1 << 1) |
646 | #define RADEON_GART_PAGE_READ (1 << 1) |
646 | #define RADEON_GART_PAGE_WRITE (1 << 2) |
647 | #define RADEON_GART_PAGE_WRITE (1 << 2) |
647 | #define RADEON_GART_PAGE_SNOOP (1 << 3) |
648 | #define RADEON_GART_PAGE_SNOOP (1 << 3) |
648 | 649 | ||
649 | struct radeon_gart { |
650 | struct radeon_gart { |
650 | dma_addr_t table_addr; |
651 | dma_addr_t table_addr; |
651 | struct radeon_bo *robj; |
652 | struct radeon_bo *robj; |
652 | void *ptr; |
653 | void *ptr; |
653 | unsigned num_gpu_pages; |
654 | unsigned num_gpu_pages; |
654 | unsigned num_cpu_pages; |
655 | unsigned num_cpu_pages; |
655 | unsigned table_size; |
656 | unsigned table_size; |
656 | struct page **pages; |
657 | struct page **pages; |
657 | uint64_t *pages_entry; |
658 | uint64_t *pages_entry; |
658 | bool ready; |
659 | bool ready; |
659 | }; |
660 | }; |
660 | 661 | ||
661 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
662 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
662 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
663 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
663 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
664 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
664 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
665 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
665 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
666 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
666 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
667 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
667 | int radeon_gart_init(struct radeon_device *rdev); |
668 | int radeon_gart_init(struct radeon_device *rdev); |
668 | void radeon_gart_fini(struct radeon_device *rdev); |
669 | void radeon_gart_fini(struct radeon_device *rdev); |
669 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
670 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
670 | int pages); |
671 | int pages); |
671 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
672 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
672 | int pages, struct page **pagelist, |
673 | int pages, struct page **pagelist, |
673 | dma_addr_t *dma_addr, uint32_t flags); |
674 | dma_addr_t *dma_addr, uint32_t flags); |
674 | 675 | ||
675 | 676 | ||
676 | /* |
677 | /* |
677 | * GPU MC structures, functions & helpers |
678 | * GPU MC structures, functions & helpers |
678 | */ |
679 | */ |
679 | struct radeon_mc { |
680 | struct radeon_mc { |
680 | resource_size_t aper_size; |
681 | resource_size_t aper_size; |
681 | resource_size_t aper_base; |
682 | resource_size_t aper_base; |
682 | resource_size_t agp_base; |
683 | resource_size_t agp_base; |
683 | /* for some chips with <= 32MB we need to lie |
684 | /* for some chips with <= 32MB we need to lie |
684 | * about vram size near mc fb location */ |
685 | * about vram size near mc fb location */ |
685 | u64 mc_vram_size; |
686 | u64 mc_vram_size; |
686 | u64 visible_vram_size; |
687 | u64 visible_vram_size; |
687 | u64 gtt_size; |
688 | u64 gtt_size; |
688 | u64 gtt_start; |
689 | u64 gtt_start; |
689 | u64 gtt_end; |
690 | u64 gtt_end; |
690 | u64 vram_start; |
691 | u64 vram_start; |
691 | u64 vram_end; |
692 | u64 vram_end; |
692 | unsigned vram_width; |
693 | unsigned vram_width; |
693 | u64 real_vram_size; |
694 | u64 real_vram_size; |
694 | int vram_mtrr; |
695 | int vram_mtrr; |
695 | bool vram_is_ddr; |
696 | bool vram_is_ddr; |
696 | bool igp_sideport_enabled; |
697 | bool igp_sideport_enabled; |
697 | u64 gtt_base_align; |
698 | u64 gtt_base_align; |
698 | u64 mc_mask; |
699 | u64 mc_mask; |
699 | }; |
700 | }; |
700 | 701 | ||
701 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
702 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
702 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
703 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
703 | 704 | ||
704 | /* |
705 | /* |
705 | * GPU scratch registers structures, functions & helpers |
706 | * GPU scratch registers structures, functions & helpers |
706 | */ |
707 | */ |
707 | struct radeon_scratch { |
708 | struct radeon_scratch { |
708 | unsigned num_reg; |
709 | unsigned num_reg; |
709 | uint32_t reg_base; |
710 | uint32_t reg_base; |
710 | bool free[32]; |
711 | bool free[32]; |
711 | uint32_t reg[32]; |
712 | uint32_t reg[32]; |
712 | }; |
713 | }; |
713 | 714 | ||
714 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
715 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
715 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
716 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
716 | 717 | ||
717 | /* |
718 | /* |
718 | * GPU doorbell structures, functions & helpers |
719 | * GPU doorbell structures, functions & helpers |
719 | */ |
720 | */ |
720 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
721 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
721 | 722 | ||
722 | struct radeon_doorbell { |
723 | struct radeon_doorbell { |
723 | /* doorbell mmio */ |
724 | /* doorbell mmio */ |
724 | resource_size_t base; |
725 | resource_size_t base; |
725 | resource_size_t size; |
726 | resource_size_t size; |
726 | u32 __iomem *ptr; |
727 | u32 __iomem *ptr; |
727 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ |
728 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ |
728 | DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); |
729 | DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); |
729 | }; |
730 | }; |
730 | 731 | ||
731 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); |
732 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); |
732 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); |
733 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); |
733 | void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, |
734 | void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, |
734 | phys_addr_t *aperture_base, |
735 | phys_addr_t *aperture_base, |
735 | size_t *aperture_size, |
736 | size_t *aperture_size, |
736 | size_t *start_offset); |
737 | size_t *start_offset); |
737 | 738 | ||
738 | /* |
739 | /* |
739 | * IRQS. |
740 | * IRQS. |
740 | */ |
741 | */ |
741 | struct r500_irq_stat_regs { |
742 | struct r500_irq_stat_regs { |
742 | u32 disp_int; |
743 | u32 disp_int; |
743 | u32 hdmi0_status; |
744 | u32 hdmi0_status; |
744 | }; |
745 | }; |
745 | 746 | ||
746 | struct r600_irq_stat_regs { |
747 | struct r600_irq_stat_regs { |
747 | u32 disp_int; |
748 | u32 disp_int; |
748 | u32 disp_int_cont; |
749 | u32 disp_int_cont; |
749 | u32 disp_int_cont2; |
750 | u32 disp_int_cont2; |
750 | u32 d1grph_int; |
751 | u32 d1grph_int; |
751 | u32 d2grph_int; |
752 | u32 d2grph_int; |
752 | u32 hdmi0_status; |
753 | u32 hdmi0_status; |
753 | u32 hdmi1_status; |
754 | u32 hdmi1_status; |
754 | }; |
755 | }; |
755 | 756 | ||
756 | struct evergreen_irq_stat_regs { |
757 | struct evergreen_irq_stat_regs { |
757 | u32 disp_int; |
758 | u32 disp_int; |
758 | u32 disp_int_cont; |
759 | u32 disp_int_cont; |
759 | u32 disp_int_cont2; |
760 | u32 disp_int_cont2; |
760 | u32 disp_int_cont3; |
761 | u32 disp_int_cont3; |
761 | u32 disp_int_cont4; |
762 | u32 disp_int_cont4; |
762 | u32 disp_int_cont5; |
763 | u32 disp_int_cont5; |
763 | u32 d1grph_int; |
764 | u32 d1grph_int; |
764 | u32 d2grph_int; |
765 | u32 d2grph_int; |
765 | u32 d3grph_int; |
766 | u32 d3grph_int; |
766 | u32 d4grph_int; |
767 | u32 d4grph_int; |
767 | u32 d5grph_int; |
768 | u32 d5grph_int; |
768 | u32 d6grph_int; |
769 | u32 d6grph_int; |
769 | u32 afmt_status1; |
770 | u32 afmt_status1; |
770 | u32 afmt_status2; |
771 | u32 afmt_status2; |
771 | u32 afmt_status3; |
772 | u32 afmt_status3; |
772 | u32 afmt_status4; |
773 | u32 afmt_status4; |
773 | u32 afmt_status5; |
774 | u32 afmt_status5; |
774 | u32 afmt_status6; |
775 | u32 afmt_status6; |
775 | }; |
776 | }; |
776 | 777 | ||
777 | struct cik_irq_stat_regs { |
778 | struct cik_irq_stat_regs { |
778 | u32 disp_int; |
779 | u32 disp_int; |
779 | u32 disp_int_cont; |
780 | u32 disp_int_cont; |
780 | u32 disp_int_cont2; |
781 | u32 disp_int_cont2; |
781 | u32 disp_int_cont3; |
782 | u32 disp_int_cont3; |
782 | u32 disp_int_cont4; |
783 | u32 disp_int_cont4; |
783 | u32 disp_int_cont5; |
784 | u32 disp_int_cont5; |
784 | u32 disp_int_cont6; |
785 | u32 disp_int_cont6; |
785 | u32 d1grph_int; |
786 | u32 d1grph_int; |
786 | u32 d2grph_int; |
787 | u32 d2grph_int; |
787 | u32 d3grph_int; |
788 | u32 d3grph_int; |
788 | u32 d4grph_int; |
789 | u32 d4grph_int; |
789 | u32 d5grph_int; |
790 | u32 d5grph_int; |
790 | u32 d6grph_int; |
791 | u32 d6grph_int; |
791 | }; |
792 | }; |
792 | 793 | ||
793 | union radeon_irq_stat_regs { |
794 | union radeon_irq_stat_regs { |
794 | struct r500_irq_stat_regs r500; |
795 | struct r500_irq_stat_regs r500; |
795 | struct r600_irq_stat_regs r600; |
796 | struct r600_irq_stat_regs r600; |
796 | struct evergreen_irq_stat_regs evergreen; |
797 | struct evergreen_irq_stat_regs evergreen; |
797 | struct cik_irq_stat_regs cik; |
798 | struct cik_irq_stat_regs cik; |
798 | }; |
799 | }; |
799 | 800 | ||
800 | struct radeon_irq { |
801 | struct radeon_irq { |
801 | bool installed; |
802 | bool installed; |
802 | spinlock_t lock; |
803 | spinlock_t lock; |
803 | atomic_t ring_int[RADEON_NUM_RINGS]; |
804 | atomic_t ring_int[RADEON_NUM_RINGS]; |
804 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
805 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
805 | atomic_t pflip[RADEON_MAX_CRTCS]; |
806 | atomic_t pflip[RADEON_MAX_CRTCS]; |
806 | wait_queue_head_t vblank_queue; |
807 | wait_queue_head_t vblank_queue; |
807 | bool hpd[RADEON_MAX_HPD_PINS]; |
808 | bool hpd[RADEON_MAX_HPD_PINS]; |
808 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
809 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
809 | union radeon_irq_stat_regs stat_regs; |
810 | union radeon_irq_stat_regs stat_regs; |
810 | bool dpm_thermal; |
811 | bool dpm_thermal; |
811 | }; |
812 | }; |
812 | 813 | ||
813 | int radeon_irq_kms_init(struct radeon_device *rdev); |
814 | int radeon_irq_kms_init(struct radeon_device *rdev); |
814 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
815 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
815 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
816 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
816 | bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); |
817 | bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); |
817 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
818 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
818 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
819 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
819 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
820 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
820 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
821 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
821 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
822 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
822 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
823 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
823 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
824 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
824 | 825 | ||
825 | /* |
826 | /* |
826 | * CP & rings. |
827 | * CP & rings. |
827 | */ |
828 | */ |
828 | 829 | ||
829 | struct radeon_ib { |
830 | struct radeon_ib { |
830 | struct radeon_sa_bo *sa_bo; |
831 | struct radeon_sa_bo *sa_bo; |
831 | uint32_t length_dw; |
832 | uint32_t length_dw; |
832 | uint64_t gpu_addr; |
833 | uint64_t gpu_addr; |
833 | uint32_t *ptr; |
834 | uint32_t *ptr; |
834 | int ring; |
835 | int ring; |
835 | struct radeon_fence *fence; |
836 | struct radeon_fence *fence; |
836 | struct radeon_vm *vm; |
837 | struct radeon_vm *vm; |
837 | bool is_const_ib; |
838 | bool is_const_ib; |
838 | struct radeon_sync sync; |
839 | struct radeon_sync sync; |
839 | }; |
840 | }; |
840 | 841 | ||
841 | struct radeon_ring { |
842 | struct radeon_ring { |
842 | struct radeon_bo *ring_obj; |
843 | struct radeon_bo *ring_obj; |
843 | volatile uint32_t *ring; |
844 | volatile uint32_t *ring; |
844 | unsigned rptr_offs; |
845 | unsigned rptr_offs; |
845 | unsigned rptr_save_reg; |
846 | unsigned rptr_save_reg; |
846 | u64 next_rptr_gpu_addr; |
847 | u64 next_rptr_gpu_addr; |
847 | volatile u32 *next_rptr_cpu_addr; |
848 | volatile u32 *next_rptr_cpu_addr; |
848 | unsigned wptr; |
849 | unsigned wptr; |
849 | unsigned wptr_old; |
850 | unsigned wptr_old; |
850 | unsigned ring_size; |
851 | unsigned ring_size; |
851 | unsigned ring_free_dw; |
852 | unsigned ring_free_dw; |
852 | int count_dw; |
853 | int count_dw; |
853 | atomic_t last_rptr; |
854 | atomic_t last_rptr; |
854 | atomic64_t last_activity; |
855 | atomic64_t last_activity; |
855 | uint64_t gpu_addr; |
856 | uint64_t gpu_addr; |
856 | uint32_t align_mask; |
857 | uint32_t align_mask; |
857 | uint32_t ptr_mask; |
858 | uint32_t ptr_mask; |
858 | bool ready; |
859 | bool ready; |
859 | u32 nop; |
860 | u32 nop; |
860 | u32 idx; |
861 | u32 idx; |
861 | u64 last_semaphore_signal_addr; |
862 | u64 last_semaphore_signal_addr; |
862 | u64 last_semaphore_wait_addr; |
863 | u64 last_semaphore_wait_addr; |
863 | /* for CIK queues */ |
864 | /* for CIK queues */ |
864 | u32 me; |
865 | u32 me; |
865 | u32 pipe; |
866 | u32 pipe; |
866 | u32 queue; |
867 | u32 queue; |
867 | struct radeon_bo *mqd_obj; |
868 | struct radeon_bo *mqd_obj; |
868 | u32 doorbell_index; |
869 | u32 doorbell_index; |
869 | unsigned wptr_offs; |
870 | unsigned wptr_offs; |
870 | }; |
871 | }; |
871 | 872 | ||
872 | struct radeon_mec { |
873 | struct radeon_mec { |
873 | struct radeon_bo *hpd_eop_obj; |
874 | struct radeon_bo *hpd_eop_obj; |
874 | u64 hpd_eop_gpu_addr; |
875 | u64 hpd_eop_gpu_addr; |
875 | u32 num_pipe; |
876 | u32 num_pipe; |
876 | u32 num_mec; |
877 | u32 num_mec; |
877 | u32 num_queue; |
878 | u32 num_queue; |
878 | }; |
879 | }; |
879 | 880 | ||
880 | /* |
881 | /* |
881 | * VM |
882 | * VM |
882 | */ |
883 | */ |
883 | 884 | ||
884 | /* maximum number of VMIDs */ |
885 | /* maximum number of VMIDs */ |
885 | #define RADEON_NUM_VM 16 |
886 | #define RADEON_NUM_VM 16 |
886 | 887 | ||
887 | /* number of entries in page table */ |
888 | /* number of entries in page table */ |
888 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
889 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
889 | 890 | ||
890 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
891 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
891 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
892 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
892 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) |
893 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) |
893 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) |
894 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) |
894 | 895 | ||
895 | #define R600_PTE_VALID (1 << 0) |
896 | #define R600_PTE_VALID (1 << 0) |
896 | #define R600_PTE_SYSTEM (1 << 1) |
897 | #define R600_PTE_SYSTEM (1 << 1) |
897 | #define R600_PTE_SNOOPED (1 << 2) |
898 | #define R600_PTE_SNOOPED (1 << 2) |
898 | #define R600_PTE_READABLE (1 << 5) |
899 | #define R600_PTE_READABLE (1 << 5) |
899 | #define R600_PTE_WRITEABLE (1 << 6) |
900 | #define R600_PTE_WRITEABLE (1 << 6) |
900 | 901 | ||
901 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
902 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
902 | #define R600_PTE_FRAG_4KB (0 << 7) |
903 | #define R600_PTE_FRAG_4KB (0 << 7) |
903 | #define R600_PTE_FRAG_64KB (4 << 7) |
904 | #define R600_PTE_FRAG_64KB (4 << 7) |
904 | #define R600_PTE_FRAG_256KB (6 << 7) |
905 | #define R600_PTE_FRAG_256KB (6 << 7) |
905 | 906 | ||
906 | /* flags needed to be set so we can copy directly from the GART table */ |
907 | /* flags needed to be set so we can copy directly from the GART table */ |
907 | #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ |
908 | #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ |
908 | R600_PTE_SYSTEM | R600_PTE_VALID ) |
909 | R600_PTE_SYSTEM | R600_PTE_VALID ) |
909 | 910 | ||
910 | struct radeon_vm_pt { |
911 | struct radeon_vm_pt { |
911 | struct radeon_bo *bo; |
912 | struct radeon_bo *bo; |
912 | uint64_t addr; |
913 | uint64_t addr; |
913 | }; |
914 | }; |
914 | 915 | ||
915 | struct radeon_vm_id { |
916 | struct radeon_vm_id { |
916 | unsigned id; |
917 | unsigned id; |
917 | uint64_t pd_gpu_addr; |
918 | uint64_t pd_gpu_addr; |
918 | /* last flushed PD/PT update */ |
919 | /* last flushed PD/PT update */ |
919 | struct radeon_fence *flushed_updates; |
920 | struct radeon_fence *flushed_updates; |
920 | /* last use of vmid */ |
921 | /* last use of vmid */ |
921 | struct radeon_fence *last_id_use; |
922 | struct radeon_fence *last_id_use; |
922 | }; |
923 | }; |
923 | 924 | ||
924 | struct radeon_vm { |
925 | struct radeon_vm { |
925 | struct mutex mutex; |
926 | struct mutex mutex; |
926 | 927 | ||
927 | struct rb_root va; |
928 | struct rb_root va; |
928 | 929 | ||
929 | /* protecting invalidated and freed */ |
930 | /* protecting invalidated and freed */ |
930 | spinlock_t status_lock; |
931 | spinlock_t status_lock; |
931 | 932 | ||
932 | /* BOs moved, but not yet updated in the PT */ |
933 | /* BOs moved, but not yet updated in the PT */ |
933 | struct list_head invalidated; |
934 | struct list_head invalidated; |
934 | 935 | ||
935 | /* BOs freed, but not yet updated in the PT */ |
936 | /* BOs freed, but not yet updated in the PT */ |
936 | struct list_head freed; |
937 | struct list_head freed; |
937 | 938 | ||
938 | /* BOs cleared in the PT */ |
939 | /* BOs cleared in the PT */ |
939 | struct list_head cleared; |
940 | struct list_head cleared; |
940 | 941 | ||
941 | /* contains the page directory */ |
942 | /* contains the page directory */ |
942 | struct radeon_bo *page_directory; |
943 | struct radeon_bo *page_directory; |
943 | unsigned max_pde_used; |
944 | unsigned max_pde_used; |
944 | 945 | ||
945 | /* array of page tables, one for each page directory entry */ |
946 | /* array of page tables, one for each page directory entry */ |
946 | struct radeon_vm_pt *page_tables; |
947 | struct radeon_vm_pt *page_tables; |
947 | 948 | ||
948 | struct radeon_bo_va *ib_bo_va; |
949 | struct radeon_bo_va *ib_bo_va; |
949 | 950 | ||
950 | /* for id and flush management per ring */ |
951 | /* for id and flush management per ring */ |
951 | struct radeon_vm_id ids[RADEON_NUM_RINGS]; |
952 | struct radeon_vm_id ids[RADEON_NUM_RINGS]; |
952 | }; |
953 | }; |
953 | 954 | ||
954 | struct radeon_vm_manager { |
955 | struct radeon_vm_manager { |
955 | struct radeon_fence *active[RADEON_NUM_VM]; |
956 | struct radeon_fence *active[RADEON_NUM_VM]; |
956 | uint32_t max_pfn; |
957 | uint32_t max_pfn; |
957 | /* number of VMIDs */ |
958 | /* number of VMIDs */ |
958 | unsigned nvm; |
959 | unsigned nvm; |
959 | /* vram base address for page table entry */ |
960 | /* vram base address for page table entry */ |
960 | u64 vram_base_offset; |
961 | u64 vram_base_offset; |
961 | /* is vm enabled? */ |
962 | /* is vm enabled? */ |
962 | bool enabled; |
963 | bool enabled; |
963 | /* for hw to save the PD addr on suspend/resume */ |
964 | /* for hw to save the PD addr on suspend/resume */ |
964 | uint32_t saved_table_addr[RADEON_NUM_VM]; |
965 | uint32_t saved_table_addr[RADEON_NUM_VM]; |
965 | }; |
966 | }; |
966 | 967 | ||
967 | /* |
968 | /* |
968 | * file private structure |
969 | * file private structure |
969 | */ |
970 | */ |
970 | struct radeon_fpriv { |
971 | struct radeon_fpriv { |
971 | struct radeon_vm vm; |
972 | struct radeon_vm vm; |
972 | }; |
973 | }; |
973 | 974 | ||
974 | /* |
975 | /* |
975 | * R6xx+ IH ring |
976 | * R6xx+ IH ring |
976 | */ |
977 | */ |
977 | struct r600_ih { |
978 | struct r600_ih { |
978 | struct radeon_bo *ring_obj; |
979 | struct radeon_bo *ring_obj; |
979 | volatile uint32_t *ring; |
980 | volatile uint32_t *ring; |
980 | unsigned rptr; |
981 | unsigned rptr; |
981 | unsigned ring_size; |
982 | unsigned ring_size; |
982 | uint64_t gpu_addr; |
983 | uint64_t gpu_addr; |
983 | uint32_t ptr_mask; |
984 | uint32_t ptr_mask; |
984 | atomic_t lock; |
985 | atomic_t lock; |
985 | bool enabled; |
986 | bool enabled; |
986 | }; |
987 | }; |
987 | 988 | ||
988 | /* |
989 | /* |
989 | * RLC stuff |
990 | * RLC stuff |
990 | */ |
991 | */ |
991 | #include "clearstate_defs.h" |
992 | #include "clearstate_defs.h" |
992 | 993 | ||
993 | struct radeon_rlc { |
994 | struct radeon_rlc { |
994 | /* for power gating */ |
995 | /* for power gating */ |
995 | struct radeon_bo *save_restore_obj; |
996 | struct radeon_bo *save_restore_obj; |
996 | uint64_t save_restore_gpu_addr; |
997 | uint64_t save_restore_gpu_addr; |
997 | volatile uint32_t *sr_ptr; |
998 | volatile uint32_t *sr_ptr; |
998 | const u32 *reg_list; |
999 | const u32 *reg_list; |
999 | u32 reg_list_size; |
1000 | u32 reg_list_size; |
1000 | /* for clear state */ |
1001 | /* for clear state */ |
1001 | struct radeon_bo *clear_state_obj; |
1002 | struct radeon_bo *clear_state_obj; |
1002 | uint64_t clear_state_gpu_addr; |
1003 | uint64_t clear_state_gpu_addr; |
1003 | volatile uint32_t *cs_ptr; |
1004 | volatile uint32_t *cs_ptr; |
1004 | const struct cs_section_def *cs_data; |
1005 | const struct cs_section_def *cs_data; |
1005 | u32 clear_state_size; |
1006 | u32 clear_state_size; |
1006 | /* for cp tables */ |
1007 | /* for cp tables */ |
1007 | struct radeon_bo *cp_table_obj; |
1008 | struct radeon_bo *cp_table_obj; |
1008 | uint64_t cp_table_gpu_addr; |
1009 | uint64_t cp_table_gpu_addr; |
1009 | volatile uint32_t *cp_table_ptr; |
1010 | volatile uint32_t *cp_table_ptr; |
1010 | u32 cp_table_size; |
1011 | u32 cp_table_size; |
1011 | }; |
1012 | }; |
1012 | 1013 | ||
1013 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
1014 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
1014 | struct radeon_ib *ib, struct radeon_vm *vm, |
1015 | struct radeon_ib *ib, struct radeon_vm *vm, |
1015 | unsigned size); |
1016 | unsigned size); |
1016 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
1017 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
1017 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
1018 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
1018 | struct radeon_ib *const_ib, bool hdp_flush); |
1019 | struct radeon_ib *const_ib, bool hdp_flush); |
1019 | int radeon_ib_pool_init(struct radeon_device *rdev); |
1020 | int radeon_ib_pool_init(struct radeon_device *rdev); |
1020 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
1021 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
1021 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
1022 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
1022 | /* Ring access between begin & end cannot sleep */ |
1023 | /* Ring access between begin & end cannot sleep */ |
1023 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
1024 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
1024 | struct radeon_ring *ring); |
1025 | struct radeon_ring *ring); |
1025 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
1026 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
1026 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1027 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1027 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1028 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1028 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1029 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1029 | bool hdp_flush); |
1030 | bool hdp_flush); |
1030 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1031 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1031 | bool hdp_flush); |
1032 | bool hdp_flush); |
1032 | void radeon_ring_undo(struct radeon_ring *ring); |
1033 | void radeon_ring_undo(struct radeon_ring *ring); |
1033 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
1034 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
1034 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
1035 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
1035 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
1036 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
1036 | struct radeon_ring *ring); |
1037 | struct radeon_ring *ring); |
1037 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
1038 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
1038 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
1039 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
1039 | uint32_t **data); |
1040 | uint32_t **data); |
1040 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
1041 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
1041 | unsigned size, uint32_t *data); |
1042 | unsigned size, uint32_t *data); |
1042 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
1043 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
1043 | unsigned rptr_offs, u32 nop); |
1044 | unsigned rptr_offs, u32 nop); |
1044 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
1045 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
1045 | 1046 | ||
1046 | 1047 | ||
1047 | /* r600 async dma */ |
1048 | /* r600 async dma */ |
1048 | void r600_dma_stop(struct radeon_device *rdev); |
1049 | void r600_dma_stop(struct radeon_device *rdev); |
1049 | int r600_dma_resume(struct radeon_device *rdev); |
1050 | int r600_dma_resume(struct radeon_device *rdev); |
1050 | void r600_dma_fini(struct radeon_device *rdev); |
1051 | void r600_dma_fini(struct radeon_device *rdev); |
1051 | 1052 | ||
1052 | void cayman_dma_stop(struct radeon_device *rdev); |
1053 | void cayman_dma_stop(struct radeon_device *rdev); |
1053 | int cayman_dma_resume(struct radeon_device *rdev); |
1054 | int cayman_dma_resume(struct radeon_device *rdev); |
1054 | void cayman_dma_fini(struct radeon_device *rdev); |
1055 | void cayman_dma_fini(struct radeon_device *rdev); |
1055 | 1056 | ||
1056 | /* |
1057 | /* |
1057 | * CS. |
1058 | * CS. |
1058 | */ |
1059 | */ |
1059 | struct radeon_cs_chunk { |
1060 | struct radeon_cs_chunk { |
1060 | uint32_t length_dw; |
1061 | uint32_t length_dw; |
1061 | uint32_t *kdata; |
1062 | uint32_t *kdata; |
1062 | void __user *user_ptr; |
1063 | void __user *user_ptr; |
1063 | }; |
1064 | }; |
1064 | 1065 | ||
1065 | struct radeon_cs_parser { |
1066 | struct radeon_cs_parser { |
1066 | struct device *dev; |
1067 | struct device *dev; |
1067 | struct radeon_device *rdev; |
1068 | struct radeon_device *rdev; |
1068 | struct drm_file *filp; |
1069 | struct drm_file *filp; |
1069 | /* chunks */ |
1070 | /* chunks */ |
1070 | unsigned nchunks; |
1071 | unsigned nchunks; |
1071 | struct radeon_cs_chunk *chunks; |
1072 | struct radeon_cs_chunk *chunks; |
1072 | uint64_t *chunks_array; |
1073 | uint64_t *chunks_array; |
1073 | /* IB */ |
1074 | /* IB */ |
1074 | unsigned idx; |
1075 | unsigned idx; |
1075 | /* relocations */ |
1076 | /* relocations */ |
1076 | unsigned nrelocs; |
1077 | unsigned nrelocs; |
1077 | struct radeon_bo_list *relocs; |
1078 | struct radeon_bo_list *relocs; |
1078 | struct radeon_bo_list *vm_bos; |
1079 | struct radeon_bo_list *vm_bos; |
1079 | struct list_head validated; |
1080 | struct list_head validated; |
1080 | unsigned dma_reloc_idx; |
1081 | unsigned dma_reloc_idx; |
1081 | /* indices of various chunks */ |
1082 | /* indices of various chunks */ |
1082 | struct radeon_cs_chunk *chunk_ib; |
1083 | struct radeon_cs_chunk *chunk_ib; |
1083 | struct radeon_cs_chunk *chunk_relocs; |
1084 | struct radeon_cs_chunk *chunk_relocs; |
1084 | struct radeon_cs_chunk *chunk_flags; |
1085 | struct radeon_cs_chunk *chunk_flags; |
1085 | struct radeon_cs_chunk *chunk_const_ib; |
1086 | struct radeon_cs_chunk *chunk_const_ib; |
1086 | struct radeon_ib ib; |
1087 | struct radeon_ib ib; |
1087 | struct radeon_ib const_ib; |
1088 | struct radeon_ib const_ib; |
1088 | void *track; |
1089 | void *track; |
1089 | unsigned family; |
1090 | unsigned family; |
1090 | int parser_error; |
1091 | int parser_error; |
1091 | u32 cs_flags; |
1092 | u32 cs_flags; |
1092 | u32 ring; |
1093 | u32 ring; |
1093 | s32 priority; |
1094 | s32 priority; |
1094 | struct ww_acquire_ctx ticket; |
1095 | struct ww_acquire_ctx ticket; |
1095 | }; |
1096 | }; |
1096 | 1097 | ||
1097 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
1098 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
1098 | { |
1099 | { |
1099 | struct radeon_cs_chunk *ibc = p->chunk_ib; |
1100 | struct radeon_cs_chunk *ibc = p->chunk_ib; |
1100 | 1101 | ||
1101 | if (ibc->kdata) |
1102 | if (ibc->kdata) |
1102 | return ibc->kdata[idx]; |
1103 | return ibc->kdata[idx]; |
1103 | return p->ib.ptr[idx]; |
1104 | return p->ib.ptr[idx]; |
1104 | } |
1105 | } |
1105 | 1106 | ||
1106 | 1107 | ||
1107 | struct radeon_cs_packet { |
1108 | struct radeon_cs_packet { |
1108 | unsigned idx; |
1109 | unsigned idx; |
1109 | unsigned type; |
1110 | unsigned type; |
1110 | unsigned reg; |
1111 | unsigned reg; |
1111 | unsigned opcode; |
1112 | unsigned opcode; |
1112 | int count; |
1113 | int count; |
1113 | unsigned one_reg_wr; |
1114 | unsigned one_reg_wr; |
1114 | }; |
1115 | }; |
1115 | 1116 | ||
1116 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
1117 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
1117 | struct radeon_cs_packet *pkt, |
1118 | struct radeon_cs_packet *pkt, |
1118 | unsigned idx, unsigned reg); |
1119 | unsigned idx, unsigned reg); |
1119 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
1120 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
1120 | struct radeon_cs_packet *pkt); |
1121 | struct radeon_cs_packet *pkt); |
1121 | 1122 | ||
1122 | 1123 | ||
1123 | /* |
1124 | /* |
1124 | * AGP |
1125 | * AGP |
1125 | */ |
1126 | */ |
1126 | int radeon_agp_init(struct radeon_device *rdev); |
1127 | int radeon_agp_init(struct radeon_device *rdev); |
1127 | void radeon_agp_resume(struct radeon_device *rdev); |
1128 | void radeon_agp_resume(struct radeon_device *rdev); |
1128 | void radeon_agp_suspend(struct radeon_device *rdev); |
1129 | void radeon_agp_suspend(struct radeon_device *rdev); |
1129 | void radeon_agp_fini(struct radeon_device *rdev); |
1130 | void radeon_agp_fini(struct radeon_device *rdev); |
1130 | 1131 | ||
1131 | 1132 | ||
1132 | /* |
1133 | /* |
1133 | * Writeback |
1134 | * Writeback |
1134 | */ |
1135 | */ |
1135 | struct radeon_wb { |
1136 | struct radeon_wb { |
1136 | struct radeon_bo *wb_obj; |
1137 | struct radeon_bo *wb_obj; |
1137 | volatile uint32_t *wb; |
1138 | volatile uint32_t *wb; |
1138 | uint64_t gpu_addr; |
1139 | uint64_t gpu_addr; |
1139 | bool enabled; |
1140 | bool enabled; |
1140 | bool use_event; |
1141 | bool use_event; |
1141 | }; |
1142 | }; |
1142 | 1143 | ||
1143 | #define RADEON_WB_SCRATCH_OFFSET 0 |
1144 | #define RADEON_WB_SCRATCH_OFFSET 0 |
1144 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1145 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1145 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
1146 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
1146 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1147 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1147 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
1148 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
1148 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
1149 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
1149 | #define R600_WB_IH_WPTR_OFFSET 2048 |
1150 | #define R600_WB_IH_WPTR_OFFSET 2048 |
1150 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
1151 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
1151 | #define R600_WB_EVENT_OFFSET 3072 |
1152 | #define R600_WB_EVENT_OFFSET 3072 |
1152 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1153 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1153 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
1154 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
1154 | #define R600_WB_DMA_RING_TEST_OFFSET 3588 |
1155 | #define R600_WB_DMA_RING_TEST_OFFSET 3588 |
1155 | #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 |
1156 | #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 |
1156 | 1157 | ||
1157 | /** |
1158 | /** |
1158 | * struct radeon_pm - power management datas |
1159 | * struct radeon_pm - power management datas |
1159 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
1160 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
1160 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
1161 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
1161 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
1162 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
1162 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
1163 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
1163 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
1164 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
1164 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
1165 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
1165 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
1166 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
1166 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
1167 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
1167 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
1168 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
1168 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1169 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1169 | * @needed_bandwidth: current bandwidth needs |
1170 | * @needed_bandwidth: current bandwidth needs |
1170 | * |
1171 | * |
1171 | * It keeps track of various data needed to take powermanagement decision. |
1172 | * It keeps track of various data needed to take powermanagement decision. |
1172 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1173 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1173 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1174 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1174 | * (type of memory, bus size, efficiency, ...) |
1175 | * (type of memory, bus size, efficiency, ...) |
1175 | */ |
1176 | */ |
1176 | 1177 | ||
1177 | enum radeon_pm_method { |
1178 | enum radeon_pm_method { |
1178 | PM_METHOD_PROFILE, |
1179 | PM_METHOD_PROFILE, |
1179 | PM_METHOD_DYNPM, |
1180 | PM_METHOD_DYNPM, |
1180 | PM_METHOD_DPM, |
1181 | PM_METHOD_DPM, |
1181 | }; |
1182 | }; |
1182 | 1183 | ||
1183 | enum radeon_dynpm_state { |
1184 | enum radeon_dynpm_state { |
1184 | DYNPM_STATE_DISABLED, |
1185 | DYNPM_STATE_DISABLED, |
1185 | DYNPM_STATE_MINIMUM, |
1186 | DYNPM_STATE_MINIMUM, |
1186 | DYNPM_STATE_PAUSED, |
1187 | DYNPM_STATE_PAUSED, |
1187 | DYNPM_STATE_ACTIVE, |
1188 | DYNPM_STATE_ACTIVE, |
1188 | DYNPM_STATE_SUSPENDED, |
1189 | DYNPM_STATE_SUSPENDED, |
1189 | }; |
1190 | }; |
1190 | enum radeon_dynpm_action { |
1191 | enum radeon_dynpm_action { |
1191 | DYNPM_ACTION_NONE, |
1192 | DYNPM_ACTION_NONE, |
1192 | DYNPM_ACTION_MINIMUM, |
1193 | DYNPM_ACTION_MINIMUM, |
1193 | DYNPM_ACTION_DOWNCLOCK, |
1194 | DYNPM_ACTION_DOWNCLOCK, |
1194 | DYNPM_ACTION_UPCLOCK, |
1195 | DYNPM_ACTION_UPCLOCK, |
1195 | DYNPM_ACTION_DEFAULT |
1196 | DYNPM_ACTION_DEFAULT |
1196 | }; |
1197 | }; |
1197 | 1198 | ||
1198 | enum radeon_voltage_type { |
1199 | enum radeon_voltage_type { |
1199 | VOLTAGE_NONE = 0, |
1200 | VOLTAGE_NONE = 0, |
1200 | VOLTAGE_GPIO, |
1201 | VOLTAGE_GPIO, |
1201 | VOLTAGE_VDDC, |
1202 | VOLTAGE_VDDC, |
1202 | VOLTAGE_SW |
1203 | VOLTAGE_SW |
1203 | }; |
1204 | }; |
1204 | 1205 | ||
1205 | enum radeon_pm_state_type { |
1206 | enum radeon_pm_state_type { |
1206 | /* not used for dpm */ |
1207 | /* not used for dpm */ |
1207 | POWER_STATE_TYPE_DEFAULT, |
1208 | POWER_STATE_TYPE_DEFAULT, |
1208 | POWER_STATE_TYPE_POWERSAVE, |
1209 | POWER_STATE_TYPE_POWERSAVE, |
1209 | /* user selectable states */ |
1210 | /* user selectable states */ |
1210 | POWER_STATE_TYPE_BATTERY, |
1211 | POWER_STATE_TYPE_BATTERY, |
1211 | POWER_STATE_TYPE_BALANCED, |
1212 | POWER_STATE_TYPE_BALANCED, |
1212 | POWER_STATE_TYPE_PERFORMANCE, |
1213 | POWER_STATE_TYPE_PERFORMANCE, |
1213 | /* internal states */ |
1214 | /* internal states */ |
1214 | POWER_STATE_TYPE_INTERNAL_UVD, |
1215 | POWER_STATE_TYPE_INTERNAL_UVD, |
1215 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
1216 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
1216 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
1217 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
1217 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
1218 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
1218 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
1219 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
1219 | POWER_STATE_TYPE_INTERNAL_BOOT, |
1220 | POWER_STATE_TYPE_INTERNAL_BOOT, |
1220 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
1221 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
1221 | POWER_STATE_TYPE_INTERNAL_ACPI, |
1222 | POWER_STATE_TYPE_INTERNAL_ACPI, |
1222 | POWER_STATE_TYPE_INTERNAL_ULV, |
1223 | POWER_STATE_TYPE_INTERNAL_ULV, |
1223 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
1224 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
1224 | }; |
1225 | }; |
1225 | 1226 | ||
1226 | enum radeon_pm_profile_type { |
1227 | enum radeon_pm_profile_type { |
1227 | PM_PROFILE_DEFAULT, |
1228 | PM_PROFILE_DEFAULT, |
1228 | PM_PROFILE_AUTO, |
1229 | PM_PROFILE_AUTO, |
1229 | PM_PROFILE_LOW, |
1230 | PM_PROFILE_LOW, |
1230 | PM_PROFILE_MID, |
1231 | PM_PROFILE_MID, |
1231 | PM_PROFILE_HIGH, |
1232 | PM_PROFILE_HIGH, |
1232 | }; |
1233 | }; |
1233 | 1234 | ||
1234 | #define PM_PROFILE_DEFAULT_IDX 0 |
1235 | #define PM_PROFILE_DEFAULT_IDX 0 |
1235 | #define PM_PROFILE_LOW_SH_IDX 1 |
1236 | #define PM_PROFILE_LOW_SH_IDX 1 |
1236 | #define PM_PROFILE_MID_SH_IDX 2 |
1237 | #define PM_PROFILE_MID_SH_IDX 2 |
1237 | #define PM_PROFILE_HIGH_SH_IDX 3 |
1238 | #define PM_PROFILE_HIGH_SH_IDX 3 |
1238 | #define PM_PROFILE_LOW_MH_IDX 4 |
1239 | #define PM_PROFILE_LOW_MH_IDX 4 |
1239 | #define PM_PROFILE_MID_MH_IDX 5 |
1240 | #define PM_PROFILE_MID_MH_IDX 5 |
1240 | #define PM_PROFILE_HIGH_MH_IDX 6 |
1241 | #define PM_PROFILE_HIGH_MH_IDX 6 |
1241 | #define PM_PROFILE_MAX 7 |
1242 | #define PM_PROFILE_MAX 7 |
1242 | 1243 | ||
1243 | struct radeon_pm_profile { |
1244 | struct radeon_pm_profile { |
1244 | int dpms_off_ps_idx; |
1245 | int dpms_off_ps_idx; |
1245 | int dpms_on_ps_idx; |
1246 | int dpms_on_ps_idx; |
1246 | int dpms_off_cm_idx; |
1247 | int dpms_off_cm_idx; |
1247 | int dpms_on_cm_idx; |
1248 | int dpms_on_cm_idx; |
1248 | }; |
1249 | }; |
1249 | 1250 | ||
1250 | enum radeon_int_thermal_type { |
1251 | enum radeon_int_thermal_type { |
1251 | THERMAL_TYPE_NONE, |
1252 | THERMAL_TYPE_NONE, |
1252 | THERMAL_TYPE_EXTERNAL, |
1253 | THERMAL_TYPE_EXTERNAL, |
1253 | THERMAL_TYPE_EXTERNAL_GPIO, |
1254 | THERMAL_TYPE_EXTERNAL_GPIO, |
1254 | THERMAL_TYPE_RV6XX, |
1255 | THERMAL_TYPE_RV6XX, |
1255 | THERMAL_TYPE_RV770, |
1256 | THERMAL_TYPE_RV770, |
1256 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
1257 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
1257 | THERMAL_TYPE_EVERGREEN, |
1258 | THERMAL_TYPE_EVERGREEN, |
1258 | THERMAL_TYPE_SUMO, |
1259 | THERMAL_TYPE_SUMO, |
1259 | THERMAL_TYPE_NI, |
1260 | THERMAL_TYPE_NI, |
1260 | THERMAL_TYPE_SI, |
1261 | THERMAL_TYPE_SI, |
1261 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
1262 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
1262 | THERMAL_TYPE_CI, |
1263 | THERMAL_TYPE_CI, |
1263 | THERMAL_TYPE_KV, |
1264 | THERMAL_TYPE_KV, |
1264 | }; |
1265 | }; |
1265 | 1266 | ||
1266 | struct radeon_voltage { |
1267 | struct radeon_voltage { |
1267 | enum radeon_voltage_type type; |
1268 | enum radeon_voltage_type type; |
1268 | /* gpio voltage */ |
1269 | /* gpio voltage */ |
1269 | struct radeon_gpio_rec gpio; |
1270 | struct radeon_gpio_rec gpio; |
1270 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
1271 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
1271 | bool active_high; /* voltage drop is active when bit is high */ |
1272 | bool active_high; /* voltage drop is active when bit is high */ |
1272 | /* VDDC voltage */ |
1273 | /* VDDC voltage */ |
1273 | u8 vddc_id; /* index into vddc voltage table */ |
1274 | u8 vddc_id; /* index into vddc voltage table */ |
1274 | u8 vddci_id; /* index into vddci voltage table */ |
1275 | u8 vddci_id; /* index into vddci voltage table */ |
1275 | bool vddci_enabled; |
1276 | bool vddci_enabled; |
1276 | /* r6xx+ sw */ |
1277 | /* r6xx+ sw */ |
1277 | u16 voltage; |
1278 | u16 voltage; |
1278 | /* evergreen+ vddci */ |
1279 | /* evergreen+ vddci */ |
1279 | u16 vddci; |
1280 | u16 vddci; |
1280 | }; |
1281 | }; |
1281 | 1282 | ||
1282 | /* clock mode flags */ |
1283 | /* clock mode flags */ |
1283 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
1284 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
1284 | 1285 | ||
1285 | struct radeon_pm_clock_info { |
1286 | struct radeon_pm_clock_info { |
1286 | /* memory clock */ |
1287 | /* memory clock */ |
1287 | u32 mclk; |
1288 | u32 mclk; |
1288 | /* engine clock */ |
1289 | /* engine clock */ |
1289 | u32 sclk; |
1290 | u32 sclk; |
1290 | /* voltage info */ |
1291 | /* voltage info */ |
1291 | struct radeon_voltage voltage; |
1292 | struct radeon_voltage voltage; |
1292 | /* standardized clock flags */ |
1293 | /* standardized clock flags */ |
1293 | u32 flags; |
1294 | u32 flags; |
1294 | }; |
1295 | }; |
1295 | 1296 | ||
1296 | /* state flags */ |
1297 | /* state flags */ |
1297 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
1298 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
1298 | 1299 | ||
1299 | struct radeon_power_state { |
1300 | struct radeon_power_state { |
1300 | enum radeon_pm_state_type type; |
1301 | enum radeon_pm_state_type type; |
1301 | struct radeon_pm_clock_info *clock_info; |
1302 | struct radeon_pm_clock_info *clock_info; |
1302 | /* number of valid clock modes in this power state */ |
1303 | /* number of valid clock modes in this power state */ |
1303 | int num_clock_modes; |
1304 | int num_clock_modes; |
1304 | struct radeon_pm_clock_info *default_clock_mode; |
1305 | struct radeon_pm_clock_info *default_clock_mode; |
1305 | /* standardized state flags */ |
1306 | /* standardized state flags */ |
1306 | u32 flags; |
1307 | u32 flags; |
1307 | u32 misc; /* vbios specific flags */ |
1308 | u32 misc; /* vbios specific flags */ |
1308 | u32 misc2; /* vbios specific flags */ |
1309 | u32 misc2; /* vbios specific flags */ |
1309 | int pcie_lanes; /* pcie lanes */ |
1310 | int pcie_lanes; /* pcie lanes */ |
1310 | }; |
1311 | }; |
1311 | 1312 | ||
1312 | /* |
1313 | /* |
1313 | * Some modes are overclocked by very low value, accept them |
1314 | * Some modes are overclocked by very low value, accept them |
1314 | */ |
1315 | */ |
1315 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
1316 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
1316 | 1317 | ||
1317 | enum radeon_dpm_auto_throttle_src { |
1318 | enum radeon_dpm_auto_throttle_src { |
1318 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, |
1319 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, |
1319 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
1320 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
1320 | }; |
1321 | }; |
1321 | 1322 | ||
1322 | enum radeon_dpm_event_src { |
1323 | enum radeon_dpm_event_src { |
1323 | RADEON_DPM_EVENT_SRC_ANALOG = 0, |
1324 | RADEON_DPM_EVENT_SRC_ANALOG = 0, |
1324 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, |
1325 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, |
1325 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, |
1326 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, |
1326 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
1327 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
1327 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
1328 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
1328 | }; |
1329 | }; |
1329 | 1330 | ||
1330 | #define RADEON_MAX_VCE_LEVELS 6 |
1331 | #define RADEON_MAX_VCE_LEVELS 6 |
1331 | 1332 | ||
1332 | enum radeon_vce_level { |
1333 | enum radeon_vce_level { |
1333 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
1334 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
1334 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
1335 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
1335 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
1336 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
1336 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
1337 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
1337 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
1338 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
1338 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
1339 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
1339 | }; |
1340 | }; |
1340 | 1341 | ||
1341 | struct radeon_ps { |
1342 | struct radeon_ps { |
1342 | u32 caps; /* vbios flags */ |
1343 | u32 caps; /* vbios flags */ |
1343 | u32 class; /* vbios flags */ |
1344 | u32 class; /* vbios flags */ |
1344 | u32 class2; /* vbios flags */ |
1345 | u32 class2; /* vbios flags */ |
1345 | /* UVD clocks */ |
1346 | /* UVD clocks */ |
1346 | u32 vclk; |
1347 | u32 vclk; |
1347 | u32 dclk; |
1348 | u32 dclk; |
1348 | /* VCE clocks */ |
1349 | /* VCE clocks */ |
1349 | u32 evclk; |
1350 | u32 evclk; |
1350 | u32 ecclk; |
1351 | u32 ecclk; |
1351 | bool vce_active; |
1352 | bool vce_active; |
1352 | enum radeon_vce_level vce_level; |
1353 | enum radeon_vce_level vce_level; |
1353 | /* asic priv */ |
1354 | /* asic priv */ |
1354 | void *ps_priv; |
1355 | void *ps_priv; |
1355 | }; |
1356 | }; |
1356 | 1357 | ||
1357 | struct radeon_dpm_thermal { |
1358 | struct radeon_dpm_thermal { |
1358 | /* thermal interrupt work */ |
1359 | /* thermal interrupt work */ |
1359 | struct work_struct work; |
1360 | struct work_struct work; |
1360 | /* low temperature threshold */ |
1361 | /* low temperature threshold */ |
1361 | int min_temp; |
1362 | int min_temp; |
1362 | /* high temperature threshold */ |
1363 | /* high temperature threshold */ |
1363 | int max_temp; |
1364 | int max_temp; |
1364 | /* was interrupt low to high or high to low */ |
1365 | /* was interrupt low to high or high to low */ |
1365 | bool high_to_low; |
1366 | bool high_to_low; |
1366 | }; |
1367 | }; |
1367 | 1368 | ||
1368 | enum radeon_clk_action |
1369 | enum radeon_clk_action |
1369 | { |
1370 | { |
1370 | RADEON_SCLK_UP = 1, |
1371 | RADEON_SCLK_UP = 1, |
1371 | RADEON_SCLK_DOWN |
1372 | RADEON_SCLK_DOWN |
1372 | }; |
1373 | }; |
1373 | 1374 | ||
1374 | struct radeon_blacklist_clocks |
1375 | struct radeon_blacklist_clocks |
1375 | { |
1376 | { |
1376 | u32 sclk; |
1377 | u32 sclk; |
1377 | u32 mclk; |
1378 | u32 mclk; |
1378 | enum radeon_clk_action action; |
1379 | enum radeon_clk_action action; |
1379 | }; |
1380 | }; |
1380 | 1381 | ||
1381 | struct radeon_clock_and_voltage_limits { |
1382 | struct radeon_clock_and_voltage_limits { |
1382 | u32 sclk; |
1383 | u32 sclk; |
1383 | u32 mclk; |
1384 | u32 mclk; |
1384 | u16 vddc; |
1385 | u16 vddc; |
1385 | u16 vddci; |
1386 | u16 vddci; |
1386 | }; |
1387 | }; |
1387 | 1388 | ||
1388 | struct radeon_clock_array { |
1389 | struct radeon_clock_array { |
1389 | u32 count; |
1390 | u32 count; |
1390 | u32 *values; |
1391 | u32 *values; |
1391 | }; |
1392 | }; |
1392 | 1393 | ||
1393 | struct radeon_clock_voltage_dependency_entry { |
1394 | struct radeon_clock_voltage_dependency_entry { |
1394 | u32 clk; |
1395 | u32 clk; |
1395 | u16 v; |
1396 | u16 v; |
1396 | }; |
1397 | }; |
1397 | 1398 | ||
1398 | struct radeon_clock_voltage_dependency_table { |
1399 | struct radeon_clock_voltage_dependency_table { |
1399 | u32 count; |
1400 | u32 count; |
1400 | struct radeon_clock_voltage_dependency_entry *entries; |
1401 | struct radeon_clock_voltage_dependency_entry *entries; |
1401 | }; |
1402 | }; |
1402 | 1403 | ||
1403 | union radeon_cac_leakage_entry { |
1404 | union radeon_cac_leakage_entry { |
1404 | struct { |
1405 | struct { |
1405 | u16 vddc; |
1406 | u16 vddc; |
1406 | u32 leakage; |
1407 | u32 leakage; |
1407 | }; |
1408 | }; |
1408 | struct { |
1409 | struct { |
1409 | u16 vddc1; |
1410 | u16 vddc1; |
1410 | u16 vddc2; |
1411 | u16 vddc2; |
1411 | u16 vddc3; |
1412 | u16 vddc3; |
1412 | }; |
1413 | }; |
1413 | }; |
1414 | }; |
1414 | 1415 | ||
1415 | struct radeon_cac_leakage_table { |
1416 | struct radeon_cac_leakage_table { |
1416 | u32 count; |
1417 | u32 count; |
1417 | union radeon_cac_leakage_entry *entries; |
1418 | union radeon_cac_leakage_entry *entries; |
1418 | }; |
1419 | }; |
1419 | 1420 | ||
1420 | struct radeon_phase_shedding_limits_entry { |
1421 | struct radeon_phase_shedding_limits_entry { |
1421 | u16 voltage; |
1422 | u16 voltage; |
1422 | u32 sclk; |
1423 | u32 sclk; |
1423 | u32 mclk; |
1424 | u32 mclk; |
1424 | }; |
1425 | }; |
1425 | 1426 | ||
1426 | struct radeon_phase_shedding_limits_table { |
1427 | struct radeon_phase_shedding_limits_table { |
1427 | u32 count; |
1428 | u32 count; |
1428 | struct radeon_phase_shedding_limits_entry *entries; |
1429 | struct radeon_phase_shedding_limits_entry *entries; |
1429 | }; |
1430 | }; |
1430 | 1431 | ||
1431 | struct radeon_uvd_clock_voltage_dependency_entry { |
1432 | struct radeon_uvd_clock_voltage_dependency_entry { |
1432 | u32 vclk; |
1433 | u32 vclk; |
1433 | u32 dclk; |
1434 | u32 dclk; |
1434 | u16 v; |
1435 | u16 v; |
1435 | }; |
1436 | }; |
1436 | 1437 | ||
1437 | struct radeon_uvd_clock_voltage_dependency_table { |
1438 | struct radeon_uvd_clock_voltage_dependency_table { |
1438 | u8 count; |
1439 | u8 count; |
1439 | struct radeon_uvd_clock_voltage_dependency_entry *entries; |
1440 | struct radeon_uvd_clock_voltage_dependency_entry *entries; |
1440 | }; |
1441 | }; |
1441 | 1442 | ||
1442 | struct radeon_vce_clock_voltage_dependency_entry { |
1443 | struct radeon_vce_clock_voltage_dependency_entry { |
1443 | u32 ecclk; |
1444 | u32 ecclk; |
1444 | u32 evclk; |
1445 | u32 evclk; |
1445 | u16 v; |
1446 | u16 v; |
1446 | }; |
1447 | }; |
1447 | 1448 | ||
1448 | struct radeon_vce_clock_voltage_dependency_table { |
1449 | struct radeon_vce_clock_voltage_dependency_table { |
1449 | u8 count; |
1450 | u8 count; |
1450 | struct radeon_vce_clock_voltage_dependency_entry *entries; |
1451 | struct radeon_vce_clock_voltage_dependency_entry *entries; |
1451 | }; |
1452 | }; |
1452 | 1453 | ||
1453 | struct radeon_ppm_table { |
1454 | struct radeon_ppm_table { |
1454 | u8 ppm_design; |
1455 | u8 ppm_design; |
1455 | u16 cpu_core_number; |
1456 | u16 cpu_core_number; |
1456 | u32 platform_tdp; |
1457 | u32 platform_tdp; |
1457 | u32 small_ac_platform_tdp; |
1458 | u32 small_ac_platform_tdp; |
1458 | u32 platform_tdc; |
1459 | u32 platform_tdc; |
1459 | u32 small_ac_platform_tdc; |
1460 | u32 small_ac_platform_tdc; |
1460 | u32 apu_tdp; |
1461 | u32 apu_tdp; |
1461 | u32 dgpu_tdp; |
1462 | u32 dgpu_tdp; |
1462 | u32 dgpu_ulv_power; |
1463 | u32 dgpu_ulv_power; |
1463 | u32 tj_max; |
1464 | u32 tj_max; |
1464 | }; |
1465 | }; |
1465 | 1466 | ||
1466 | struct radeon_cac_tdp_table { |
1467 | struct radeon_cac_tdp_table { |
1467 | u16 tdp; |
1468 | u16 tdp; |
1468 | u16 configurable_tdp; |
1469 | u16 configurable_tdp; |
1469 | u16 tdc; |
1470 | u16 tdc; |
1470 | u16 battery_power_limit; |
1471 | u16 battery_power_limit; |
1471 | u16 small_power_limit; |
1472 | u16 small_power_limit; |
1472 | u16 low_cac_leakage; |
1473 | u16 low_cac_leakage; |
1473 | u16 high_cac_leakage; |
1474 | u16 high_cac_leakage; |
1474 | u16 maximum_power_delivery_limit; |
1475 | u16 maximum_power_delivery_limit; |
1475 | }; |
1476 | }; |
1476 | 1477 | ||
1477 | struct radeon_dpm_dynamic_state { |
1478 | struct radeon_dpm_dynamic_state { |
1478 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; |
1479 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; |
1479 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; |
1480 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; |
1480 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; |
1481 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; |
1481 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
1482 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
1482 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
1483 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
1483 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
1484 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
1484 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
1485 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
1485 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
1486 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
1486 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
1487 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
1487 | struct radeon_clock_array valid_sclk_values; |
1488 | struct radeon_clock_array valid_sclk_values; |
1488 | struct radeon_clock_array valid_mclk_values; |
1489 | struct radeon_clock_array valid_mclk_values; |
1489 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; |
1490 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; |
1490 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; |
1491 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; |
1491 | u32 mclk_sclk_ratio; |
1492 | u32 mclk_sclk_ratio; |
1492 | u32 sclk_mclk_delta; |
1493 | u32 sclk_mclk_delta; |
1493 | u16 vddc_vddci_delta; |
1494 | u16 vddc_vddci_delta; |
1494 | u16 min_vddc_for_pcie_gen2; |
1495 | u16 min_vddc_for_pcie_gen2; |
1495 | struct radeon_cac_leakage_table cac_leakage_table; |
1496 | struct radeon_cac_leakage_table cac_leakage_table; |
1496 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
1497 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
1497 | struct radeon_ppm_table *ppm_table; |
1498 | struct radeon_ppm_table *ppm_table; |
1498 | struct radeon_cac_tdp_table *cac_tdp_table; |
1499 | struct radeon_cac_tdp_table *cac_tdp_table; |
1499 | }; |
1500 | }; |
1500 | 1501 | ||
1501 | struct radeon_dpm_fan { |
1502 | struct radeon_dpm_fan { |
1502 | u16 t_min; |
1503 | u16 t_min; |
1503 | u16 t_med; |
1504 | u16 t_med; |
1504 | u16 t_high; |
1505 | u16 t_high; |
1505 | u16 pwm_min; |
1506 | u16 pwm_min; |
1506 | u16 pwm_med; |
1507 | u16 pwm_med; |
1507 | u16 pwm_high; |
1508 | u16 pwm_high; |
1508 | u8 t_hyst; |
1509 | u8 t_hyst; |
1509 | u32 cycle_delay; |
1510 | u32 cycle_delay; |
1510 | u16 t_max; |
1511 | u16 t_max; |
1511 | u8 control_mode; |
1512 | u8 control_mode; |
1512 | u16 default_max_fan_pwm; |
1513 | u16 default_max_fan_pwm; |
1513 | u16 default_fan_output_sensitivity; |
1514 | u16 default_fan_output_sensitivity; |
1514 | u16 fan_output_sensitivity; |
1515 | u16 fan_output_sensitivity; |
1515 | bool ucode_fan_control; |
1516 | bool ucode_fan_control; |
1516 | }; |
1517 | }; |
1517 | 1518 | ||
1518 | enum radeon_pcie_gen { |
1519 | enum radeon_pcie_gen { |
1519 | RADEON_PCIE_GEN1 = 0, |
1520 | RADEON_PCIE_GEN1 = 0, |
1520 | RADEON_PCIE_GEN2 = 1, |
1521 | RADEON_PCIE_GEN2 = 1, |
1521 | RADEON_PCIE_GEN3 = 2, |
1522 | RADEON_PCIE_GEN3 = 2, |
1522 | RADEON_PCIE_GEN_INVALID = 0xffff |
1523 | RADEON_PCIE_GEN_INVALID = 0xffff |
1523 | }; |
1524 | }; |
1524 | 1525 | ||
1525 | enum radeon_dpm_forced_level { |
1526 | enum radeon_dpm_forced_level { |
1526 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, |
1527 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, |
1527 | RADEON_DPM_FORCED_LEVEL_LOW = 1, |
1528 | RADEON_DPM_FORCED_LEVEL_LOW = 1, |
1528 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, |
1529 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, |
1529 | }; |
1530 | }; |
1530 | 1531 | ||
1531 | struct radeon_vce_state { |
1532 | struct radeon_vce_state { |
1532 | /* vce clocks */ |
1533 | /* vce clocks */ |
1533 | u32 evclk; |
1534 | u32 evclk; |
1534 | u32 ecclk; |
1535 | u32 ecclk; |
1535 | /* gpu clocks */ |
1536 | /* gpu clocks */ |
1536 | u32 sclk; |
1537 | u32 sclk; |
1537 | u32 mclk; |
1538 | u32 mclk; |
1538 | u8 clk_idx; |
1539 | u8 clk_idx; |
1539 | u8 pstate; |
1540 | u8 pstate; |
1540 | }; |
1541 | }; |
1541 | 1542 | ||
1542 | struct radeon_dpm { |
1543 | struct radeon_dpm { |
1543 | struct radeon_ps *ps; |
1544 | struct radeon_ps *ps; |
1544 | /* number of valid power states */ |
1545 | /* number of valid power states */ |
1545 | int num_ps; |
1546 | int num_ps; |
1546 | /* current power state that is active */ |
1547 | /* current power state that is active */ |
1547 | struct radeon_ps *current_ps; |
1548 | struct radeon_ps *current_ps; |
1548 | /* requested power state */ |
1549 | /* requested power state */ |
1549 | struct radeon_ps *requested_ps; |
1550 | struct radeon_ps *requested_ps; |
1550 | /* boot up power state */ |
1551 | /* boot up power state */ |
1551 | struct radeon_ps *boot_ps; |
1552 | struct radeon_ps *boot_ps; |
1552 | /* default uvd power state */ |
1553 | /* default uvd power state */ |
1553 | struct radeon_ps *uvd_ps; |
1554 | struct radeon_ps *uvd_ps; |
1554 | /* vce requirements */ |
1555 | /* vce requirements */ |
1555 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; |
1556 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; |
1556 | enum radeon_vce_level vce_level; |
1557 | enum radeon_vce_level vce_level; |
1557 | enum radeon_pm_state_type state; |
1558 | enum radeon_pm_state_type state; |
1558 | enum radeon_pm_state_type user_state; |
1559 | enum radeon_pm_state_type user_state; |
1559 | u32 platform_caps; |
1560 | u32 platform_caps; |
1560 | u32 voltage_response_time; |
1561 | u32 voltage_response_time; |
1561 | u32 backbias_response_time; |
1562 | u32 backbias_response_time; |
1562 | void *priv; |
1563 | void *priv; |
1563 | u32 new_active_crtcs; |
1564 | u32 new_active_crtcs; |
1564 | int new_active_crtc_count; |
1565 | int new_active_crtc_count; |
1565 | u32 current_active_crtcs; |
1566 | u32 current_active_crtcs; |
1566 | int current_active_crtc_count; |
1567 | int current_active_crtc_count; |
1567 | bool single_display; |
1568 | bool single_display; |
1568 | struct radeon_dpm_dynamic_state dyn_state; |
1569 | struct radeon_dpm_dynamic_state dyn_state; |
1569 | struct radeon_dpm_fan fan; |
1570 | struct radeon_dpm_fan fan; |
1570 | u32 tdp_limit; |
1571 | u32 tdp_limit; |
1571 | u32 near_tdp_limit; |
1572 | u32 near_tdp_limit; |
1572 | u32 near_tdp_limit_adjusted; |
1573 | u32 near_tdp_limit_adjusted; |
1573 | u32 sq_ramping_threshold; |
1574 | u32 sq_ramping_threshold; |
1574 | u32 cac_leakage; |
1575 | u32 cac_leakage; |
1575 | u16 tdp_od_limit; |
1576 | u16 tdp_od_limit; |
1576 | u32 tdp_adjustment; |
1577 | u32 tdp_adjustment; |
1577 | u16 load_line_slope; |
1578 | u16 load_line_slope; |
1578 | bool power_control; |
1579 | bool power_control; |
1579 | bool ac_power; |
1580 | bool ac_power; |
1580 | /* special states active */ |
1581 | /* special states active */ |
1581 | bool thermal_active; |
1582 | bool thermal_active; |
1582 | bool uvd_active; |
1583 | bool uvd_active; |
1583 | bool vce_active; |
1584 | bool vce_active; |
1584 | /* thermal handling */ |
1585 | /* thermal handling */ |
1585 | struct radeon_dpm_thermal thermal; |
1586 | struct radeon_dpm_thermal thermal; |
1586 | /* forced levels */ |
1587 | /* forced levels */ |
1587 | enum radeon_dpm_forced_level forced_level; |
1588 | enum radeon_dpm_forced_level forced_level; |
1588 | /* track UVD streams */ |
1589 | /* track UVD streams */ |
1589 | unsigned sd; |
1590 | unsigned sd; |
1590 | unsigned hd; |
1591 | unsigned hd; |
1591 | }; |
1592 | }; |
1592 | 1593 | ||
1593 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
1594 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
1594 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
1595 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
1595 | 1596 | ||
1596 | struct radeon_pm { |
1597 | struct radeon_pm { |
1597 | struct mutex mutex; |
1598 | struct mutex mutex; |
1598 | /* write locked while reprogramming mclk */ |
1599 | /* write locked while reprogramming mclk */ |
1599 | struct rw_semaphore mclk_lock; |
1600 | struct rw_semaphore mclk_lock; |
1600 | u32 active_crtcs; |
1601 | u32 active_crtcs; |
1601 | int active_crtc_count; |
1602 | int active_crtc_count; |
1602 | int req_vblank; |
1603 | int req_vblank; |
1603 | bool vblank_sync; |
1604 | bool vblank_sync; |
1604 | fixed20_12 max_bandwidth; |
1605 | fixed20_12 max_bandwidth; |
1605 | fixed20_12 igp_sideport_mclk; |
1606 | fixed20_12 igp_sideport_mclk; |
1606 | fixed20_12 igp_system_mclk; |
1607 | fixed20_12 igp_system_mclk; |
1607 | fixed20_12 igp_ht_link_clk; |
1608 | fixed20_12 igp_ht_link_clk; |
1608 | fixed20_12 igp_ht_link_width; |
1609 | fixed20_12 igp_ht_link_width; |
1609 | fixed20_12 k8_bandwidth; |
1610 | fixed20_12 k8_bandwidth; |
1610 | fixed20_12 sideport_bandwidth; |
1611 | fixed20_12 sideport_bandwidth; |
1611 | fixed20_12 ht_bandwidth; |
1612 | fixed20_12 ht_bandwidth; |
1612 | fixed20_12 core_bandwidth; |
1613 | fixed20_12 core_bandwidth; |
1613 | fixed20_12 sclk; |
1614 | fixed20_12 sclk; |
1614 | fixed20_12 mclk; |
1615 | fixed20_12 mclk; |
1615 | fixed20_12 needed_bandwidth; |
1616 | fixed20_12 needed_bandwidth; |
1616 | struct radeon_power_state *power_state; |
1617 | struct radeon_power_state *power_state; |
1617 | /* number of valid power states */ |
1618 | /* number of valid power states */ |
1618 | int num_power_states; |
1619 | int num_power_states; |
1619 | int current_power_state_index; |
1620 | int current_power_state_index; |
1620 | int current_clock_mode_index; |
1621 | int current_clock_mode_index; |
1621 | int requested_power_state_index; |
1622 | int requested_power_state_index; |
1622 | int requested_clock_mode_index; |
1623 | int requested_clock_mode_index; |
1623 | int default_power_state_index; |
1624 | int default_power_state_index; |
1624 | u32 current_sclk; |
1625 | u32 current_sclk; |
1625 | u32 current_mclk; |
1626 | u32 current_mclk; |
1626 | u16 current_vddc; |
1627 | u16 current_vddc; |
1627 | u16 current_vddci; |
1628 | u16 current_vddci; |
1628 | u32 default_sclk; |
1629 | u32 default_sclk; |
1629 | u32 default_mclk; |
1630 | u32 default_mclk; |
1630 | u16 default_vddc; |
1631 | u16 default_vddc; |
1631 | u16 default_vddci; |
1632 | u16 default_vddci; |
1632 | struct radeon_i2c_chan *i2c_bus; |
1633 | struct radeon_i2c_chan *i2c_bus; |
1633 | /* selected pm method */ |
1634 | /* selected pm method */ |
1634 | enum radeon_pm_method pm_method; |
1635 | enum radeon_pm_method pm_method; |
1635 | /* dynpm power management */ |
1636 | /* dynpm power management */ |
1636 | struct delayed_work dynpm_idle_work; |
1637 | struct delayed_work dynpm_idle_work; |
1637 | enum radeon_dynpm_state dynpm_state; |
1638 | enum radeon_dynpm_state dynpm_state; |
1638 | enum radeon_dynpm_action dynpm_planned_action; |
1639 | enum radeon_dynpm_action dynpm_planned_action; |
1639 | unsigned long dynpm_action_timeout; |
1640 | unsigned long dynpm_action_timeout; |
1640 | bool dynpm_can_upclock; |
1641 | bool dynpm_can_upclock; |
1641 | bool dynpm_can_downclock; |
1642 | bool dynpm_can_downclock; |
1642 | /* profile-based power management */ |
1643 | /* profile-based power management */ |
1643 | enum radeon_pm_profile_type profile; |
1644 | enum radeon_pm_profile_type profile; |
1644 | int profile_index; |
1645 | int profile_index; |
1645 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
1646 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
1646 | /* internal thermal controller on rv6xx+ */ |
1647 | /* internal thermal controller on rv6xx+ */ |
1647 | enum radeon_int_thermal_type int_thermal_type; |
1648 | enum radeon_int_thermal_type int_thermal_type; |
1648 | struct device *int_hwmon_dev; |
1649 | struct device *int_hwmon_dev; |
1649 | /* fan control parameters */ |
1650 | /* fan control parameters */ |
1650 | bool no_fan; |
1651 | bool no_fan; |
1651 | u8 fan_pulses_per_revolution; |
1652 | u8 fan_pulses_per_revolution; |
1652 | u8 fan_min_rpm; |
1653 | u8 fan_min_rpm; |
1653 | u8 fan_max_rpm; |
1654 | u8 fan_max_rpm; |
1654 | /* dpm */ |
1655 | /* dpm */ |
1655 | bool dpm_enabled; |
1656 | bool dpm_enabled; |
1656 | bool sysfs_initialized; |
1657 | bool sysfs_initialized; |
1657 | struct radeon_dpm dpm; |
1658 | struct radeon_dpm dpm; |
1658 | }; |
1659 | }; |
1659 | 1660 | ||
1660 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1661 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1661 | enum radeon_pm_state_type ps_type, |
1662 | enum radeon_pm_state_type ps_type, |
1662 | int instance); |
1663 | int instance); |
1663 | /* |
1664 | /* |
1664 | * UVD |
1665 | * UVD |
1665 | */ |
1666 | */ |
1666 | #define RADEON_MAX_UVD_HANDLES 10 |
1667 | #define RADEON_MAX_UVD_HANDLES 10 |
1667 | #define RADEON_UVD_STACK_SIZE (1024*1024) |
1668 | #define RADEON_UVD_STACK_SIZE (1024*1024) |
1668 | #define RADEON_UVD_HEAP_SIZE (1024*1024) |
1669 | #define RADEON_UVD_HEAP_SIZE (1024*1024) |
1669 | 1670 | ||
1670 | struct radeon_uvd { |
1671 | struct radeon_uvd { |
1671 | struct radeon_bo *vcpu_bo; |
1672 | struct radeon_bo *vcpu_bo; |
1672 | void *cpu_addr; |
1673 | void *cpu_addr; |
1673 | uint64_t gpu_addr; |
1674 | uint64_t gpu_addr; |
1674 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
1675 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
1675 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
1676 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
1676 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
1677 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
1677 | struct delayed_work idle_work; |
1678 | struct delayed_work idle_work; |
1678 | }; |
1679 | }; |
1679 | 1680 | ||
1680 | int radeon_uvd_init(struct radeon_device *rdev); |
1681 | int radeon_uvd_init(struct radeon_device *rdev); |
1681 | void radeon_uvd_fini(struct radeon_device *rdev); |
1682 | void radeon_uvd_fini(struct radeon_device *rdev); |
1682 | int radeon_uvd_suspend(struct radeon_device *rdev); |
1683 | int radeon_uvd_suspend(struct radeon_device *rdev); |
1683 | int radeon_uvd_resume(struct radeon_device *rdev); |
1684 | int radeon_uvd_resume(struct radeon_device *rdev); |
1684 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
1685 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
1685 | uint32_t handle, struct radeon_fence **fence); |
1686 | uint32_t handle, struct radeon_fence **fence); |
1686 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
1687 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
1687 | uint32_t handle, struct radeon_fence **fence); |
1688 | uint32_t handle, struct radeon_fence **fence); |
1688 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, |
1689 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, |
1689 | uint32_t allowed_domains); |
1690 | uint32_t allowed_domains); |
1690 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
1691 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
1691 | struct drm_file *filp); |
1692 | struct drm_file *filp); |
1692 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
1693 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
1693 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
1694 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
1694 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1695 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1695 | unsigned vclk, unsigned dclk, |
1696 | unsigned vclk, unsigned dclk, |
1696 | unsigned vco_min, unsigned vco_max, |
1697 | unsigned vco_min, unsigned vco_max, |
1697 | unsigned fb_factor, unsigned fb_mask, |
1698 | unsigned fb_factor, unsigned fb_mask, |
1698 | unsigned pd_min, unsigned pd_max, |
1699 | unsigned pd_min, unsigned pd_max, |
1699 | unsigned pd_even, |
1700 | unsigned pd_even, |
1700 | unsigned *optimal_fb_div, |
1701 | unsigned *optimal_fb_div, |
1701 | unsigned *optimal_vclk_div, |
1702 | unsigned *optimal_vclk_div, |
1702 | unsigned *optimal_dclk_div); |
1703 | unsigned *optimal_dclk_div); |
1703 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
1704 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
1704 | unsigned cg_upll_func_cntl); |
1705 | unsigned cg_upll_func_cntl); |
1705 | 1706 | ||
1706 | /* |
1707 | /* |
1707 | * VCE |
1708 | * VCE |
1708 | */ |
1709 | */ |
1709 | #define RADEON_MAX_VCE_HANDLES 16 |
1710 | #define RADEON_MAX_VCE_HANDLES 16 |
1710 | 1711 | ||
1711 | struct radeon_vce { |
1712 | struct radeon_vce { |
1712 | struct radeon_bo *vcpu_bo; |
1713 | struct radeon_bo *vcpu_bo; |
1713 | uint64_t gpu_addr; |
1714 | uint64_t gpu_addr; |
1714 | unsigned fw_version; |
1715 | unsigned fw_version; |
1715 | unsigned fb_version; |
1716 | unsigned fb_version; |
1716 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
1717 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
1717 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; |
1718 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; |
1718 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
1719 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
1719 | struct delayed_work idle_work; |
1720 | struct delayed_work idle_work; |
1720 | uint32_t keyselect; |
1721 | uint32_t keyselect; |
1721 | }; |
1722 | }; |
1722 | 1723 | ||
1723 | int radeon_vce_init(struct radeon_device *rdev); |
1724 | int radeon_vce_init(struct radeon_device *rdev); |
1724 | void radeon_vce_fini(struct radeon_device *rdev); |
1725 | void radeon_vce_fini(struct radeon_device *rdev); |
1725 | int radeon_vce_suspend(struct radeon_device *rdev); |
1726 | int radeon_vce_suspend(struct radeon_device *rdev); |
1726 | int radeon_vce_resume(struct radeon_device *rdev); |
1727 | int radeon_vce_resume(struct radeon_device *rdev); |
1727 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, |
1728 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, |
1728 | uint32_t handle, struct radeon_fence **fence); |
1729 | uint32_t handle, struct radeon_fence **fence); |
1729 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, |
1730 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, |
1730 | uint32_t handle, struct radeon_fence **fence); |
1731 | uint32_t handle, struct radeon_fence **fence); |
1731 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); |
1732 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); |
1732 | void radeon_vce_note_usage(struct radeon_device *rdev); |
1733 | void radeon_vce_note_usage(struct radeon_device *rdev); |
1733 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
1734 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
1734 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
1735 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
1735 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, |
1736 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, |
1736 | struct radeon_ring *ring, |
1737 | struct radeon_ring *ring, |
1737 | struct radeon_semaphore *semaphore, |
1738 | struct radeon_semaphore *semaphore, |
1738 | bool emit_wait); |
1739 | bool emit_wait); |
1739 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
1740 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
1740 | void radeon_vce_fence_emit(struct radeon_device *rdev, |
1741 | void radeon_vce_fence_emit(struct radeon_device *rdev, |
1741 | struct radeon_fence *fence); |
1742 | struct radeon_fence *fence); |
1742 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1743 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1743 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1744 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1744 | 1745 | ||
1745 | struct r600_audio_pin { |
1746 | struct r600_audio_pin { |
1746 | int channels; |
1747 | int channels; |
1747 | int rate; |
1748 | int rate; |
1748 | int bits_per_sample; |
1749 | int bits_per_sample; |
1749 | u8 status_bits; |
1750 | u8 status_bits; |
1750 | u8 category_code; |
1751 | u8 category_code; |
1751 | u32 offset; |
1752 | u32 offset; |
1752 | bool connected; |
1753 | bool connected; |
1753 | u32 id; |
1754 | u32 id; |
1754 | }; |
1755 | }; |
1755 | 1756 | ||
1756 | struct r600_audio { |
1757 | struct r600_audio { |
1757 | bool enabled; |
1758 | bool enabled; |
1758 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; |
1759 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; |
1759 | int num_pins; |
1760 | int num_pins; |
1760 | struct radeon_audio_funcs *hdmi_funcs; |
1761 | struct radeon_audio_funcs *hdmi_funcs; |
1761 | struct radeon_audio_funcs *dp_funcs; |
1762 | struct radeon_audio_funcs *dp_funcs; |
1762 | struct radeon_audio_basic_funcs *funcs; |
1763 | struct radeon_audio_basic_funcs *funcs; |
1763 | }; |
1764 | }; |
1764 | 1765 | ||
1765 | /* |
1766 | /* |
1766 | * Benchmarking |
1767 | * Benchmarking |
1767 | */ |
1768 | */ |
1768 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
1769 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
1769 | 1770 | ||
1770 | 1771 | ||
1771 | /* |
1772 | /* |
1772 | * Testing |
1773 | * Testing |
1773 | */ |
1774 | */ |
1774 | void radeon_test_moves(struct radeon_device *rdev); |
1775 | void radeon_test_moves(struct radeon_device *rdev); |
1775 | void radeon_test_ring_sync(struct radeon_device *rdev, |
1776 | void radeon_test_ring_sync(struct radeon_device *rdev, |
1776 | struct radeon_ring *cpA, |
1777 | struct radeon_ring *cpA, |
1777 | struct radeon_ring *cpB); |
1778 | struct radeon_ring *cpB); |
1778 | void radeon_test_syncing(struct radeon_device *rdev); |
1779 | void radeon_test_syncing(struct radeon_device *rdev); |
1779 | 1780 | ||
1780 | /* |
1781 | /* |
1781 | * MMU Notifier |
1782 | * MMU Notifier |
1782 | */ |
1783 | */ |
1783 | #if defined(CONFIG_MMU_NOTIFIER) |
1784 | #if defined(CONFIG_MMU_NOTIFIER) |
1784 | int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); |
1785 | int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); |
1785 | void radeon_mn_unregister(struct radeon_bo *bo); |
1786 | void radeon_mn_unregister(struct radeon_bo *bo); |
1786 | #else |
1787 | #else |
1787 | static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) |
1788 | static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) |
1788 | { |
1789 | { |
1789 | return -ENODEV; |
1790 | return -ENODEV; |
1790 | } |
1791 | } |
1791 | static inline void radeon_mn_unregister(struct radeon_bo *bo) {} |
1792 | static inline void radeon_mn_unregister(struct radeon_bo *bo) {} |
1792 | #endif |
1793 | #endif |
1793 | 1794 | ||
1794 | /* |
1795 | /* |
1795 | * Debugfs |
1796 | * Debugfs |
1796 | */ |
1797 | */ |
1797 | struct radeon_debugfs { |
1798 | struct radeon_debugfs { |
1798 | struct drm_info_list *files; |
1799 | struct drm_info_list *files; |
1799 | unsigned num_files; |
1800 | unsigned num_files; |
1800 | }; |
1801 | }; |
1801 | 1802 | ||
1802 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1803 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1803 | struct drm_info_list *files, |
1804 | struct drm_info_list *files, |
1804 | unsigned nfiles); |
1805 | unsigned nfiles); |
1805 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
1806 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
1806 | 1807 | ||
1807 | /* |
1808 | /* |
1808 | * ASIC ring specific functions. |
1809 | * ASIC ring specific functions. |
1809 | */ |
1810 | */ |
1810 | struct radeon_asic_ring { |
1811 | struct radeon_asic_ring { |
1811 | /* ring read/write ptr handling */ |
1812 | /* ring read/write ptr handling */ |
1812 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1813 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1813 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1814 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1814 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1815 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1815 | 1816 | ||
1816 | /* validating and patching of IBs */ |
1817 | /* validating and patching of IBs */ |
1817 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
1818 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
1818 | int (*cs_parse)(struct radeon_cs_parser *p); |
1819 | int (*cs_parse)(struct radeon_cs_parser *p); |
1819 | 1820 | ||
1820 | /* command emmit functions */ |
1821 | /* command emmit functions */ |
1821 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
1822 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
1822 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
1823 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
1823 | void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); |
1824 | void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); |
1824 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
1825 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
1825 | struct radeon_semaphore *semaphore, bool emit_wait); |
1826 | struct radeon_semaphore *semaphore, bool emit_wait); |
1826 | void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, |
1827 | void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, |
1827 | unsigned vm_id, uint64_t pd_addr); |
1828 | unsigned vm_id, uint64_t pd_addr); |
1828 | 1829 | ||
1829 | /* testing functions */ |
1830 | /* testing functions */ |
1830 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1831 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1831 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1832 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1832 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
1833 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
1833 | 1834 | ||
1834 | /* deprecated */ |
1835 | /* deprecated */ |
1835 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1836 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1836 | }; |
1837 | }; |
1837 | 1838 | ||
1838 | /* |
1839 | /* |
1839 | * ASIC specific functions. |
1840 | * ASIC specific functions. |
1840 | */ |
1841 | */ |
1841 | struct radeon_asic { |
1842 | struct radeon_asic { |
1842 | int (*init)(struct radeon_device *rdev); |
1843 | int (*init)(struct radeon_device *rdev); |
1843 | void (*fini)(struct radeon_device *rdev); |
1844 | void (*fini)(struct radeon_device *rdev); |
1844 | int (*resume)(struct radeon_device *rdev); |
1845 | int (*resume)(struct radeon_device *rdev); |
1845 | int (*suspend)(struct radeon_device *rdev); |
1846 | int (*suspend)(struct radeon_device *rdev); |
1846 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
1847 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
1847 | int (*asic_reset)(struct radeon_device *rdev); |
1848 | int (*asic_reset)(struct radeon_device *rdev); |
1848 | /* Flush the HDP cache via MMIO */ |
1849 | /* Flush the HDP cache via MMIO */ |
1849 | void (*mmio_hdp_flush)(struct radeon_device *rdev); |
1850 | void (*mmio_hdp_flush)(struct radeon_device *rdev); |
1850 | /* check if 3D engine is idle */ |
1851 | /* check if 3D engine is idle */ |
1851 | bool (*gui_idle)(struct radeon_device *rdev); |
1852 | bool (*gui_idle)(struct radeon_device *rdev); |
1852 | /* wait for mc_idle */ |
1853 | /* wait for mc_idle */ |
1853 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
1854 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
1854 | /* get the reference clock */ |
1855 | /* get the reference clock */ |
1855 | u32 (*get_xclk)(struct radeon_device *rdev); |
1856 | u32 (*get_xclk)(struct radeon_device *rdev); |
1856 | /* get the gpu clock counter */ |
1857 | /* get the gpu clock counter */ |
1857 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
1858 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
1858 | /* get register for info ioctl */ |
1859 | /* get register for info ioctl */ |
1859 | int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); |
1860 | int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); |
1860 | /* gart */ |
1861 | /* gart */ |
1861 | struct { |
1862 | struct { |
1862 | void (*tlb_flush)(struct radeon_device *rdev); |
1863 | void (*tlb_flush)(struct radeon_device *rdev); |
1863 | uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); |
1864 | uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); |
1864 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
1865 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
1865 | uint64_t entry); |
1866 | uint64_t entry); |
1866 | } gart; |
1867 | } gart; |
1867 | struct { |
1868 | struct { |
1868 | int (*init)(struct radeon_device *rdev); |
1869 | int (*init)(struct radeon_device *rdev); |
1869 | void (*fini)(struct radeon_device *rdev); |
1870 | void (*fini)(struct radeon_device *rdev); |
1870 | void (*copy_pages)(struct radeon_device *rdev, |
1871 | void (*copy_pages)(struct radeon_device *rdev, |
1871 | struct radeon_ib *ib, |
1872 | struct radeon_ib *ib, |
1872 | uint64_t pe, uint64_t src, |
1873 | uint64_t pe, uint64_t src, |
1873 | unsigned count); |
1874 | unsigned count); |
1874 | void (*write_pages)(struct radeon_device *rdev, |
1875 | void (*write_pages)(struct radeon_device *rdev, |
1875 | struct radeon_ib *ib, |
1876 | struct radeon_ib *ib, |
1876 | uint64_t pe, |
1877 | uint64_t pe, |
1877 | uint64_t addr, unsigned count, |
1878 | uint64_t addr, unsigned count, |
1878 | uint32_t incr, uint32_t flags); |
1879 | uint32_t incr, uint32_t flags); |
1879 | void (*set_pages)(struct radeon_device *rdev, |
1880 | void (*set_pages)(struct radeon_device *rdev, |
1880 | struct radeon_ib *ib, |
1881 | struct radeon_ib *ib, |
1881 | uint64_t pe, |
1882 | uint64_t pe, |
1882 | uint64_t addr, unsigned count, |
1883 | uint64_t addr, unsigned count, |
1883 | uint32_t incr, uint32_t flags); |
1884 | uint32_t incr, uint32_t flags); |
1884 | void (*pad_ib)(struct radeon_ib *ib); |
1885 | void (*pad_ib)(struct radeon_ib *ib); |
1885 | } vm; |
1886 | } vm; |
1886 | /* ring specific callbacks */ |
1887 | /* ring specific callbacks */ |
1887 | const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
1888 | const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
1888 | /* irqs */ |
1889 | /* irqs */ |
1889 | struct { |
1890 | struct { |
1890 | int (*set)(struct radeon_device *rdev); |
1891 | int (*set)(struct radeon_device *rdev); |
1891 | int (*process)(struct radeon_device *rdev); |
1892 | int (*process)(struct radeon_device *rdev); |
1892 | } irq; |
1893 | } irq; |
1893 | /* displays */ |
1894 | /* displays */ |
1894 | struct { |
1895 | struct { |
1895 | /* display watermarks */ |
1896 | /* display watermarks */ |
1896 | void (*bandwidth_update)(struct radeon_device *rdev); |
1897 | void (*bandwidth_update)(struct radeon_device *rdev); |
1897 | /* get frame count */ |
1898 | /* get frame count */ |
1898 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1899 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1899 | /* wait for vblank */ |
1900 | /* wait for vblank */ |
1900 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
1901 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
1901 | /* set backlight level */ |
1902 | /* set backlight level */ |
1902 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
1903 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
1903 | /* get backlight level */ |
1904 | /* get backlight level */ |
1904 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
1905 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
1905 | /* audio callbacks */ |
1906 | /* audio callbacks */ |
1906 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
1907 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
1907 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1908 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1908 | } display; |
1909 | } display; |
1909 | /* copy functions for bo handling */ |
1910 | /* copy functions for bo handling */ |
1910 | struct { |
1911 | struct { |
1911 | struct radeon_fence *(*blit)(struct radeon_device *rdev, |
1912 | struct radeon_fence *(*blit)(struct radeon_device *rdev, |
1912 | uint64_t src_offset, |
1913 | uint64_t src_offset, |
1913 | uint64_t dst_offset, |
1914 | uint64_t dst_offset, |
1914 | unsigned num_gpu_pages, |
1915 | unsigned num_gpu_pages, |
1915 | struct reservation_object *resv); |
1916 | struct reservation_object *resv); |
1916 | u32 blit_ring_index; |
1917 | u32 blit_ring_index; |
1917 | struct radeon_fence *(*dma)(struct radeon_device *rdev, |
1918 | struct radeon_fence *(*dma)(struct radeon_device *rdev, |
1918 | uint64_t src_offset, |
1919 | uint64_t src_offset, |
1919 | uint64_t dst_offset, |
1920 | uint64_t dst_offset, |
1920 | unsigned num_gpu_pages, |
1921 | unsigned num_gpu_pages, |
1921 | struct reservation_object *resv); |
1922 | struct reservation_object *resv); |
1922 | u32 dma_ring_index; |
1923 | u32 dma_ring_index; |
1923 | /* method used for bo copy */ |
1924 | /* method used for bo copy */ |
1924 | struct radeon_fence *(*copy)(struct radeon_device *rdev, |
1925 | struct radeon_fence *(*copy)(struct radeon_device *rdev, |
1925 | uint64_t src_offset, |
1926 | uint64_t src_offset, |
1926 | uint64_t dst_offset, |
1927 | uint64_t dst_offset, |
1927 | unsigned num_gpu_pages, |
1928 | unsigned num_gpu_pages, |
1928 | struct reservation_object *resv); |
1929 | struct reservation_object *resv); |
1929 | /* ring used for bo copies */ |
1930 | /* ring used for bo copies */ |
1930 | u32 copy_ring_index; |
1931 | u32 copy_ring_index; |
1931 | } copy; |
1932 | } copy; |
1932 | /* surfaces */ |
1933 | /* surfaces */ |
1933 | struct { |
1934 | struct { |
1934 | int (*set_reg)(struct radeon_device *rdev, int reg, |
1935 | int (*set_reg)(struct radeon_device *rdev, int reg, |
1935 | uint32_t tiling_flags, uint32_t pitch, |
1936 | uint32_t tiling_flags, uint32_t pitch, |
1936 | uint32_t offset, uint32_t obj_size); |
1937 | uint32_t offset, uint32_t obj_size); |
1937 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
1938 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
1938 | } surface; |
1939 | } surface; |
1939 | /* hotplug detect */ |
1940 | /* hotplug detect */ |
1940 | struct { |
1941 | struct { |
1941 | void (*init)(struct radeon_device *rdev); |
1942 | void (*init)(struct radeon_device *rdev); |
1942 | void (*fini)(struct radeon_device *rdev); |
1943 | void (*fini)(struct radeon_device *rdev); |
1943 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1944 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1944 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1945 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1945 | } hpd; |
1946 | } hpd; |
1946 | /* static power management */ |
1947 | /* static power management */ |
1947 | struct { |
1948 | struct { |
1948 | void (*misc)(struct radeon_device *rdev); |
1949 | void (*misc)(struct radeon_device *rdev); |
1949 | void (*prepare)(struct radeon_device *rdev); |
1950 | void (*prepare)(struct radeon_device *rdev); |
1950 | void (*finish)(struct radeon_device *rdev); |
1951 | void (*finish)(struct radeon_device *rdev); |
1951 | void (*init_profile)(struct radeon_device *rdev); |
1952 | void (*init_profile)(struct radeon_device *rdev); |
1952 | void (*get_dynpm_state)(struct radeon_device *rdev); |
1953 | void (*get_dynpm_state)(struct radeon_device *rdev); |
1953 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1954 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1954 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1955 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1955 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1956 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1956 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1957 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1957 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1958 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1958 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1959 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1959 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
1960 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
1960 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
1961 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
1961 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
1962 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
1962 | int (*get_temperature)(struct radeon_device *rdev); |
1963 | int (*get_temperature)(struct radeon_device *rdev); |
1963 | } pm; |
1964 | } pm; |
1964 | /* dynamic power management */ |
1965 | /* dynamic power management */ |
1965 | struct { |
1966 | struct { |
1966 | int (*init)(struct radeon_device *rdev); |
1967 | int (*init)(struct radeon_device *rdev); |
1967 | void (*setup_asic)(struct radeon_device *rdev); |
1968 | void (*setup_asic)(struct radeon_device *rdev); |
1968 | int (*enable)(struct radeon_device *rdev); |
1969 | int (*enable)(struct radeon_device *rdev); |
1969 | int (*late_enable)(struct radeon_device *rdev); |
1970 | int (*late_enable)(struct radeon_device *rdev); |
1970 | void (*disable)(struct radeon_device *rdev); |
1971 | void (*disable)(struct radeon_device *rdev); |
1971 | int (*pre_set_power_state)(struct radeon_device *rdev); |
1972 | int (*pre_set_power_state)(struct radeon_device *rdev); |
1972 | int (*set_power_state)(struct radeon_device *rdev); |
1973 | int (*set_power_state)(struct radeon_device *rdev); |
1973 | void (*post_set_power_state)(struct radeon_device *rdev); |
1974 | void (*post_set_power_state)(struct radeon_device *rdev); |
1974 | void (*display_configuration_changed)(struct radeon_device *rdev); |
1975 | void (*display_configuration_changed)(struct radeon_device *rdev); |
1975 | void (*fini)(struct radeon_device *rdev); |
1976 | void (*fini)(struct radeon_device *rdev); |
1976 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); |
1977 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); |
1977 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); |
1978 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); |
1978 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); |
1979 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); |
1979 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
1980 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
1980 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
1981 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
1981 | bool (*vblank_too_short)(struct radeon_device *rdev); |
1982 | bool (*vblank_too_short)(struct radeon_device *rdev); |
1982 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
1983 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
1983 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
1984 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
1984 | void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); |
1985 | void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); |
1985 | u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); |
1986 | u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); |
1986 | int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); |
1987 | int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); |
1987 | int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); |
1988 | int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); |
1988 | u32 (*get_current_sclk)(struct radeon_device *rdev); |
1989 | u32 (*get_current_sclk)(struct radeon_device *rdev); |
1989 | u32 (*get_current_mclk)(struct radeon_device *rdev); |
1990 | u32 (*get_current_mclk)(struct radeon_device *rdev); |
1990 | } dpm; |
1991 | } dpm; |
1991 | /* pageflipping */ |
1992 | /* pageflipping */ |
1992 | struct { |
1993 | struct { |
1993 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
1994 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
1994 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); |
1995 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); |
1995 | } pflip; |
1996 | } pflip; |
1996 | }; |
1997 | }; |
1997 | 1998 | ||
1998 | /* |
1999 | /* |
1999 | * Asic structures |
2000 | * Asic structures |
2000 | */ |
2001 | */ |
2001 | struct r100_asic { |
2002 | struct r100_asic { |
2002 | const unsigned *reg_safe_bm; |
2003 | const unsigned *reg_safe_bm; |
2003 | unsigned reg_safe_bm_size; |
2004 | unsigned reg_safe_bm_size; |
2004 | u32 hdp_cntl; |
2005 | u32 hdp_cntl; |
2005 | }; |
2006 | }; |
2006 | 2007 | ||
2007 | struct r300_asic { |
2008 | struct r300_asic { |
2008 | const unsigned *reg_safe_bm; |
2009 | const unsigned *reg_safe_bm; |
2009 | unsigned reg_safe_bm_size; |
2010 | unsigned reg_safe_bm_size; |
2010 | u32 resync_scratch; |
2011 | u32 resync_scratch; |
2011 | u32 hdp_cntl; |
2012 | u32 hdp_cntl; |
2012 | }; |
2013 | }; |
2013 | 2014 | ||
2014 | struct r600_asic { |
2015 | struct r600_asic { |
2015 | unsigned max_pipes; |
2016 | unsigned max_pipes; |
2016 | unsigned max_tile_pipes; |
2017 | unsigned max_tile_pipes; |
2017 | unsigned max_simds; |
2018 | unsigned max_simds; |
2018 | unsigned max_backends; |
2019 | unsigned max_backends; |
2019 | unsigned max_gprs; |
2020 | unsigned max_gprs; |
2020 | unsigned max_threads; |
2021 | unsigned max_threads; |
2021 | unsigned max_stack_entries; |
2022 | unsigned max_stack_entries; |
2022 | unsigned max_hw_contexts; |
2023 | unsigned max_hw_contexts; |
2023 | unsigned max_gs_threads; |
2024 | unsigned max_gs_threads; |
2024 | unsigned sx_max_export_size; |
2025 | unsigned sx_max_export_size; |
2025 | unsigned sx_max_export_pos_size; |
2026 | unsigned sx_max_export_pos_size; |
2026 | unsigned sx_max_export_smx_size; |
2027 | unsigned sx_max_export_smx_size; |
2027 | unsigned sq_num_cf_insts; |
2028 | unsigned sq_num_cf_insts; |
2028 | unsigned tiling_nbanks; |
2029 | unsigned tiling_nbanks; |
2029 | unsigned tiling_npipes; |
2030 | unsigned tiling_npipes; |
2030 | unsigned tiling_group_size; |
2031 | unsigned tiling_group_size; |
2031 | unsigned tile_config; |
2032 | unsigned tile_config; |
2032 | unsigned backend_map; |
2033 | unsigned backend_map; |
2033 | unsigned active_simds; |
2034 | unsigned active_simds; |
2034 | }; |
2035 | }; |
2035 | 2036 | ||
2036 | struct rv770_asic { |
2037 | struct rv770_asic { |
2037 | unsigned max_pipes; |
2038 | unsigned max_pipes; |
2038 | unsigned max_tile_pipes; |
2039 | unsigned max_tile_pipes; |
2039 | unsigned max_simds; |
2040 | unsigned max_simds; |
2040 | unsigned max_backends; |
2041 | unsigned max_backends; |
2041 | unsigned max_gprs; |
2042 | unsigned max_gprs; |
2042 | unsigned max_threads; |
2043 | unsigned max_threads; |
2043 | unsigned max_stack_entries; |
2044 | unsigned max_stack_entries; |
2044 | unsigned max_hw_contexts; |
2045 | unsigned max_hw_contexts; |
2045 | unsigned max_gs_threads; |
2046 | unsigned max_gs_threads; |
2046 | unsigned sx_max_export_size; |
2047 | unsigned sx_max_export_size; |
2047 | unsigned sx_max_export_pos_size; |
2048 | unsigned sx_max_export_pos_size; |
2048 | unsigned sx_max_export_smx_size; |
2049 | unsigned sx_max_export_smx_size; |
2049 | unsigned sq_num_cf_insts; |
2050 | unsigned sq_num_cf_insts; |
2050 | unsigned sx_num_of_sets; |
2051 | unsigned sx_num_of_sets; |
2051 | unsigned sc_prim_fifo_size; |
2052 | unsigned sc_prim_fifo_size; |
2052 | unsigned sc_hiz_tile_fifo_size; |
2053 | unsigned sc_hiz_tile_fifo_size; |
2053 | unsigned sc_earlyz_tile_fifo_fize; |
2054 | unsigned sc_earlyz_tile_fifo_fize; |
2054 | unsigned tiling_nbanks; |
2055 | unsigned tiling_nbanks; |
2055 | unsigned tiling_npipes; |
2056 | unsigned tiling_npipes; |
2056 | unsigned tiling_group_size; |
2057 | unsigned tiling_group_size; |
2057 | unsigned tile_config; |
2058 | unsigned tile_config; |
2058 | unsigned backend_map; |
2059 | unsigned backend_map; |
2059 | unsigned active_simds; |
2060 | unsigned active_simds; |
2060 | }; |
2061 | }; |
2061 | 2062 | ||
2062 | struct evergreen_asic { |
2063 | struct evergreen_asic { |
2063 | unsigned num_ses; |
2064 | unsigned num_ses; |
2064 | unsigned max_pipes; |
2065 | unsigned max_pipes; |
2065 | unsigned max_tile_pipes; |
2066 | unsigned max_tile_pipes; |
2066 | unsigned max_simds; |
2067 | unsigned max_simds; |
2067 | unsigned max_backends; |
2068 | unsigned max_backends; |
2068 | unsigned max_gprs; |
2069 | unsigned max_gprs; |
2069 | unsigned max_threads; |
2070 | unsigned max_threads; |
2070 | unsigned max_stack_entries; |
2071 | unsigned max_stack_entries; |
2071 | unsigned max_hw_contexts; |
2072 | unsigned max_hw_contexts; |
2072 | unsigned max_gs_threads; |
2073 | unsigned max_gs_threads; |
2073 | unsigned sx_max_export_size; |
2074 | unsigned sx_max_export_size; |
2074 | unsigned sx_max_export_pos_size; |
2075 | unsigned sx_max_export_pos_size; |
2075 | unsigned sx_max_export_smx_size; |
2076 | unsigned sx_max_export_smx_size; |
2076 | unsigned sq_num_cf_insts; |
2077 | unsigned sq_num_cf_insts; |
2077 | unsigned sx_num_of_sets; |
2078 | unsigned sx_num_of_sets; |
2078 | unsigned sc_prim_fifo_size; |
2079 | unsigned sc_prim_fifo_size; |
2079 | unsigned sc_hiz_tile_fifo_size; |
2080 | unsigned sc_hiz_tile_fifo_size; |
2080 | unsigned sc_earlyz_tile_fifo_size; |
2081 | unsigned sc_earlyz_tile_fifo_size; |
2081 | unsigned tiling_nbanks; |
2082 | unsigned tiling_nbanks; |
2082 | unsigned tiling_npipes; |
2083 | unsigned tiling_npipes; |
2083 | unsigned tiling_group_size; |
2084 | unsigned tiling_group_size; |
2084 | unsigned tile_config; |
2085 | unsigned tile_config; |
2085 | unsigned backend_map; |
2086 | unsigned backend_map; |
2086 | unsigned active_simds; |
2087 | unsigned active_simds; |
2087 | }; |
2088 | }; |
2088 | 2089 | ||
2089 | struct cayman_asic { |
2090 | struct cayman_asic { |
2090 | unsigned max_shader_engines; |
2091 | unsigned max_shader_engines; |
2091 | unsigned max_pipes_per_simd; |
2092 | unsigned max_pipes_per_simd; |
2092 | unsigned max_tile_pipes; |
2093 | unsigned max_tile_pipes; |
2093 | unsigned max_simds_per_se; |
2094 | unsigned max_simds_per_se; |
2094 | unsigned max_backends_per_se; |
2095 | unsigned max_backends_per_se; |
2095 | unsigned max_texture_channel_caches; |
2096 | unsigned max_texture_channel_caches; |
2096 | unsigned max_gprs; |
2097 | unsigned max_gprs; |
2097 | unsigned max_threads; |
2098 | unsigned max_threads; |
2098 | unsigned max_gs_threads; |
2099 | unsigned max_gs_threads; |
2099 | unsigned max_stack_entries; |
2100 | unsigned max_stack_entries; |
2100 | unsigned sx_num_of_sets; |
2101 | unsigned sx_num_of_sets; |
2101 | unsigned sx_max_export_size; |
2102 | unsigned sx_max_export_size; |
2102 | unsigned sx_max_export_pos_size; |
2103 | unsigned sx_max_export_pos_size; |
2103 | unsigned sx_max_export_smx_size; |
2104 | unsigned sx_max_export_smx_size; |
2104 | unsigned max_hw_contexts; |
2105 | unsigned max_hw_contexts; |
2105 | unsigned sq_num_cf_insts; |
2106 | unsigned sq_num_cf_insts; |
2106 | unsigned sc_prim_fifo_size; |
2107 | unsigned sc_prim_fifo_size; |
2107 | unsigned sc_hiz_tile_fifo_size; |
2108 | unsigned sc_hiz_tile_fifo_size; |
2108 | unsigned sc_earlyz_tile_fifo_size; |
2109 | unsigned sc_earlyz_tile_fifo_size; |
2109 | 2110 | ||
2110 | unsigned num_shader_engines; |
2111 | unsigned num_shader_engines; |
2111 | unsigned num_shader_pipes_per_simd; |
2112 | unsigned num_shader_pipes_per_simd; |
2112 | unsigned num_tile_pipes; |
2113 | unsigned num_tile_pipes; |
2113 | unsigned num_simds_per_se; |
2114 | unsigned num_simds_per_se; |
2114 | unsigned num_backends_per_se; |
2115 | unsigned num_backends_per_se; |
2115 | unsigned backend_disable_mask_per_asic; |
2116 | unsigned backend_disable_mask_per_asic; |
2116 | unsigned backend_map; |
2117 | unsigned backend_map; |
2117 | unsigned num_texture_channel_caches; |
2118 | unsigned num_texture_channel_caches; |
2118 | unsigned mem_max_burst_length_bytes; |
2119 | unsigned mem_max_burst_length_bytes; |
2119 | unsigned mem_row_size_in_kb; |
2120 | unsigned mem_row_size_in_kb; |
2120 | unsigned shader_engine_tile_size; |
2121 | unsigned shader_engine_tile_size; |
2121 | unsigned num_gpus; |
2122 | unsigned num_gpus; |
2122 | unsigned multi_gpu_tile_size; |
2123 | unsigned multi_gpu_tile_size; |
2123 | 2124 | ||
2124 | unsigned tile_config; |
2125 | unsigned tile_config; |
2125 | unsigned active_simds; |
2126 | unsigned active_simds; |
2126 | }; |
2127 | }; |
2127 | 2128 | ||
2128 | struct si_asic { |
2129 | struct si_asic { |
2129 | unsigned max_shader_engines; |
2130 | unsigned max_shader_engines; |
2130 | unsigned max_tile_pipes; |
2131 | unsigned max_tile_pipes; |
2131 | unsigned max_cu_per_sh; |
2132 | unsigned max_cu_per_sh; |
2132 | unsigned max_sh_per_se; |
2133 | unsigned max_sh_per_se; |
2133 | unsigned max_backends_per_se; |
2134 | unsigned max_backends_per_se; |
2134 | unsigned max_texture_channel_caches; |
2135 | unsigned max_texture_channel_caches; |
2135 | unsigned max_gprs; |
2136 | unsigned max_gprs; |
2136 | unsigned max_gs_threads; |
2137 | unsigned max_gs_threads; |
2137 | unsigned max_hw_contexts; |
2138 | unsigned max_hw_contexts; |
2138 | unsigned sc_prim_fifo_size_frontend; |
2139 | unsigned sc_prim_fifo_size_frontend; |
2139 | unsigned sc_prim_fifo_size_backend; |
2140 | unsigned sc_prim_fifo_size_backend; |
2140 | unsigned sc_hiz_tile_fifo_size; |
2141 | unsigned sc_hiz_tile_fifo_size; |
2141 | unsigned sc_earlyz_tile_fifo_size; |
2142 | unsigned sc_earlyz_tile_fifo_size; |
2142 | 2143 | ||
2143 | unsigned num_tile_pipes; |
2144 | unsigned num_tile_pipes; |
2144 | unsigned backend_enable_mask; |
2145 | unsigned backend_enable_mask; |
2145 | unsigned backend_disable_mask_per_asic; |
2146 | unsigned backend_disable_mask_per_asic; |
2146 | unsigned backend_map; |
2147 | unsigned backend_map; |
2147 | unsigned num_texture_channel_caches; |
2148 | unsigned num_texture_channel_caches; |
2148 | unsigned mem_max_burst_length_bytes; |
2149 | unsigned mem_max_burst_length_bytes; |
2149 | unsigned mem_row_size_in_kb; |
2150 | unsigned mem_row_size_in_kb; |
2150 | unsigned shader_engine_tile_size; |
2151 | unsigned shader_engine_tile_size; |
2151 | unsigned num_gpus; |
2152 | unsigned num_gpus; |
2152 | unsigned multi_gpu_tile_size; |
2153 | unsigned multi_gpu_tile_size; |
2153 | 2154 | ||
2154 | unsigned tile_config; |
2155 | unsigned tile_config; |
2155 | uint32_t tile_mode_array[32]; |
2156 | uint32_t tile_mode_array[32]; |
2156 | uint32_t active_cus; |
2157 | uint32_t active_cus; |
2157 | }; |
2158 | }; |
2158 | 2159 | ||
2159 | struct cik_asic { |
2160 | struct cik_asic { |
2160 | unsigned max_shader_engines; |
2161 | unsigned max_shader_engines; |
2161 | unsigned max_tile_pipes; |
2162 | unsigned max_tile_pipes; |
2162 | unsigned max_cu_per_sh; |
2163 | unsigned max_cu_per_sh; |
2163 | unsigned max_sh_per_se; |
2164 | unsigned max_sh_per_se; |
2164 | unsigned max_backends_per_se; |
2165 | unsigned max_backends_per_se; |
2165 | unsigned max_texture_channel_caches; |
2166 | unsigned max_texture_channel_caches; |
2166 | unsigned max_gprs; |
2167 | unsigned max_gprs; |
2167 | unsigned max_gs_threads; |
2168 | unsigned max_gs_threads; |
2168 | unsigned max_hw_contexts; |
2169 | unsigned max_hw_contexts; |
2169 | unsigned sc_prim_fifo_size_frontend; |
2170 | unsigned sc_prim_fifo_size_frontend; |
2170 | unsigned sc_prim_fifo_size_backend; |
2171 | unsigned sc_prim_fifo_size_backend; |
2171 | unsigned sc_hiz_tile_fifo_size; |
2172 | unsigned sc_hiz_tile_fifo_size; |
2172 | unsigned sc_earlyz_tile_fifo_size; |
2173 | unsigned sc_earlyz_tile_fifo_size; |
2173 | 2174 | ||
2174 | unsigned num_tile_pipes; |
2175 | unsigned num_tile_pipes; |
2175 | unsigned backend_enable_mask; |
2176 | unsigned backend_enable_mask; |
2176 | unsigned backend_disable_mask_per_asic; |
2177 | unsigned backend_disable_mask_per_asic; |
2177 | unsigned backend_map; |
2178 | unsigned backend_map; |
2178 | unsigned num_texture_channel_caches; |
2179 | unsigned num_texture_channel_caches; |
2179 | unsigned mem_max_burst_length_bytes; |
2180 | unsigned mem_max_burst_length_bytes; |
2180 | unsigned mem_row_size_in_kb; |
2181 | unsigned mem_row_size_in_kb; |
2181 | unsigned shader_engine_tile_size; |
2182 | unsigned shader_engine_tile_size; |
2182 | unsigned num_gpus; |
2183 | unsigned num_gpus; |
2183 | unsigned multi_gpu_tile_size; |
2184 | unsigned multi_gpu_tile_size; |
2184 | 2185 | ||
2185 | unsigned tile_config; |
2186 | unsigned tile_config; |
2186 | uint32_t tile_mode_array[32]; |
2187 | uint32_t tile_mode_array[32]; |
2187 | uint32_t macrotile_mode_array[16]; |
2188 | uint32_t macrotile_mode_array[16]; |
2188 | uint32_t active_cus; |
2189 | uint32_t active_cus; |
2189 | }; |
2190 | }; |
2190 | 2191 | ||
2191 | union radeon_asic_config { |
2192 | union radeon_asic_config { |
2192 | struct r300_asic r300; |
2193 | struct r300_asic r300; |
2193 | struct r100_asic r100; |
2194 | struct r100_asic r100; |
2194 | struct r600_asic r600; |
2195 | struct r600_asic r600; |
2195 | struct rv770_asic rv770; |
2196 | struct rv770_asic rv770; |
2196 | struct evergreen_asic evergreen; |
2197 | struct evergreen_asic evergreen; |
2197 | struct cayman_asic cayman; |
2198 | struct cayman_asic cayman; |
2198 | struct si_asic si; |
2199 | struct si_asic si; |
2199 | struct cik_asic cik; |
2200 | struct cik_asic cik; |
2200 | }; |
2201 | }; |
2201 | 2202 | ||
2202 | /* |
2203 | /* |
2203 | * asic initizalization from radeon_asic.c |
2204 | * asic initizalization from radeon_asic.c |
2204 | */ |
2205 | */ |
2205 | void radeon_agp_disable(struct radeon_device *rdev); |
2206 | void radeon_agp_disable(struct radeon_device *rdev); |
2206 | int radeon_asic_init(struct radeon_device *rdev); |
2207 | int radeon_asic_init(struct radeon_device *rdev); |
2207 | 2208 | ||
2208 | 2209 | ||
2209 | 2210 | ||
2210 | /* VRAM scratch page for HDP bug, default vram page */ |
2211 | /* VRAM scratch page for HDP bug, default vram page */ |
2211 | struct r600_vram_scratch { |
2212 | struct r600_vram_scratch { |
2212 | struct radeon_bo *robj; |
2213 | struct radeon_bo *robj; |
2213 | volatile uint32_t *ptr; |
2214 | volatile uint32_t *ptr; |
2214 | u64 gpu_addr; |
2215 | u64 gpu_addr; |
2215 | }; |
2216 | }; |
2216 | 2217 | ||
2217 | /* |
2218 | /* |
2218 | * ACPI |
2219 | * ACPI |
2219 | */ |
2220 | */ |
2220 | struct radeon_atif_notification_cfg { |
2221 | struct radeon_atif_notification_cfg { |
2221 | bool enabled; |
2222 | bool enabled; |
2222 | int command_code; |
2223 | int command_code; |
2223 | }; |
2224 | }; |
2224 | 2225 | ||
2225 | struct radeon_atif_notifications { |
2226 | struct radeon_atif_notifications { |
2226 | bool display_switch; |
2227 | bool display_switch; |
2227 | bool expansion_mode_change; |
2228 | bool expansion_mode_change; |
2228 | bool thermal_state; |
2229 | bool thermal_state; |
2229 | bool forced_power_state; |
2230 | bool forced_power_state; |
2230 | bool system_power_state; |
2231 | bool system_power_state; |
2231 | bool display_conf_change; |
2232 | bool display_conf_change; |
2232 | bool px_gfx_switch; |
2233 | bool px_gfx_switch; |
2233 | bool brightness_change; |
2234 | bool brightness_change; |
2234 | bool dgpu_display_event; |
2235 | bool dgpu_display_event; |
2235 | }; |
2236 | }; |
2236 | 2237 | ||
2237 | struct radeon_atif_functions { |
2238 | struct radeon_atif_functions { |
2238 | bool system_params; |
2239 | bool system_params; |
2239 | bool sbios_requests; |
2240 | bool sbios_requests; |
2240 | bool select_active_disp; |
2241 | bool select_active_disp; |
2241 | bool lid_state; |
2242 | bool lid_state; |
2242 | bool get_tv_standard; |
2243 | bool get_tv_standard; |
2243 | bool set_tv_standard; |
2244 | bool set_tv_standard; |
2244 | bool get_panel_expansion_mode; |
2245 | bool get_panel_expansion_mode; |
2245 | bool set_panel_expansion_mode; |
2246 | bool set_panel_expansion_mode; |
2246 | bool temperature_change; |
2247 | bool temperature_change; |
2247 | bool graphics_device_types; |
2248 | bool graphics_device_types; |
2248 | }; |
2249 | }; |
2249 | 2250 | ||
2250 | struct radeon_atif { |
2251 | struct radeon_atif { |
2251 | struct radeon_atif_notifications notifications; |
2252 | struct radeon_atif_notifications notifications; |
2252 | struct radeon_atif_functions functions; |
2253 | struct radeon_atif_functions functions; |
2253 | struct radeon_atif_notification_cfg notification_cfg; |
2254 | struct radeon_atif_notification_cfg notification_cfg; |
2254 | struct radeon_encoder *encoder_for_bl; |
2255 | struct radeon_encoder *encoder_for_bl; |
2255 | }; |
2256 | }; |
2256 | 2257 | ||
2257 | struct radeon_atcs_functions { |
2258 | struct radeon_atcs_functions { |
2258 | bool get_ext_state; |
2259 | bool get_ext_state; |
2259 | bool pcie_perf_req; |
2260 | bool pcie_perf_req; |
2260 | bool pcie_dev_rdy; |
2261 | bool pcie_dev_rdy; |
2261 | bool pcie_bus_width; |
2262 | bool pcie_bus_width; |
2262 | }; |
2263 | }; |
2263 | 2264 | ||
2264 | struct radeon_atcs { |
2265 | struct radeon_atcs { |
2265 | struct radeon_atcs_functions functions; |
2266 | struct radeon_atcs_functions functions; |
2266 | }; |
2267 | }; |
2267 | 2268 | ||
2268 | /* |
2269 | /* |
2269 | * Core structure, functions and helpers. |
2270 | * Core structure, functions and helpers. |
2270 | */ |
2271 | */ |
2271 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
2272 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
2272 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
2273 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
2273 | 2274 | ||
2274 | struct radeon_device { |
2275 | struct radeon_device { |
2275 | struct device *dev; |
2276 | struct device *dev; |
2276 | struct drm_device *ddev; |
2277 | struct drm_device *ddev; |
2277 | struct pci_dev *pdev; |
2278 | struct pci_dev *pdev; |
2278 | struct rw_semaphore exclusive_lock; |
2279 | struct rw_semaphore exclusive_lock; |
2279 | /* ASIC */ |
2280 | /* ASIC */ |
2280 | union radeon_asic_config config; |
2281 | union radeon_asic_config config; |
2281 | enum radeon_family family; |
2282 | enum radeon_family family; |
2282 | unsigned long flags; |
2283 | unsigned long flags; |
2283 | int usec_timeout; |
2284 | int usec_timeout; |
2284 | enum radeon_pll_errata pll_errata; |
2285 | enum radeon_pll_errata pll_errata; |
2285 | int num_gb_pipes; |
2286 | int num_gb_pipes; |
2286 | int num_z_pipes; |
2287 | int num_z_pipes; |
2287 | int disp_priority; |
2288 | int disp_priority; |
2288 | /* BIOS */ |
2289 | /* BIOS */ |
2289 | uint8_t *bios; |
2290 | uint8_t *bios; |
2290 | bool is_atom_bios; |
2291 | bool is_atom_bios; |
2291 | uint16_t bios_header_start; |
2292 | uint16_t bios_header_start; |
2292 | struct radeon_bo *stollen_vga_memory; |
2293 | struct radeon_bo *stollen_vga_memory; |
2293 | /* Register mmio */ |
2294 | /* Register mmio */ |
2294 | resource_size_t rmmio_base; |
2295 | resource_size_t rmmio_base; |
2295 | resource_size_t rmmio_size; |
2296 | resource_size_t rmmio_size; |
2296 | /* protects concurrent MM_INDEX/DATA based register access */ |
2297 | /* protects concurrent MM_INDEX/DATA based register access */ |
2297 | spinlock_t mmio_idx_lock; |
2298 | spinlock_t mmio_idx_lock; |
2298 | /* protects concurrent SMC based register access */ |
2299 | /* protects concurrent SMC based register access */ |
2299 | spinlock_t smc_idx_lock; |
2300 | spinlock_t smc_idx_lock; |
2300 | /* protects concurrent PLL register access */ |
2301 | /* protects concurrent PLL register access */ |
2301 | spinlock_t pll_idx_lock; |
2302 | spinlock_t pll_idx_lock; |
2302 | /* protects concurrent MC register access */ |
2303 | /* protects concurrent MC register access */ |
2303 | spinlock_t mc_idx_lock; |
2304 | spinlock_t mc_idx_lock; |
2304 | /* protects concurrent PCIE register access */ |
2305 | /* protects concurrent PCIE register access */ |
2305 | spinlock_t pcie_idx_lock; |
2306 | spinlock_t pcie_idx_lock; |
2306 | /* protects concurrent PCIE_PORT register access */ |
2307 | /* protects concurrent PCIE_PORT register access */ |
2307 | spinlock_t pciep_idx_lock; |
2308 | spinlock_t pciep_idx_lock; |
2308 | /* protects concurrent PIF register access */ |
2309 | /* protects concurrent PIF register access */ |
2309 | spinlock_t pif_idx_lock; |
2310 | spinlock_t pif_idx_lock; |
2310 | /* protects concurrent CG register access */ |
2311 | /* protects concurrent CG register access */ |
2311 | spinlock_t cg_idx_lock; |
2312 | spinlock_t cg_idx_lock; |
2312 | /* protects concurrent UVD register access */ |
2313 | /* protects concurrent UVD register access */ |
2313 | spinlock_t uvd_idx_lock; |
2314 | spinlock_t uvd_idx_lock; |
2314 | /* protects concurrent RCU register access */ |
2315 | /* protects concurrent RCU register access */ |
2315 | spinlock_t rcu_idx_lock; |
2316 | spinlock_t rcu_idx_lock; |
2316 | /* protects concurrent DIDT register access */ |
2317 | /* protects concurrent DIDT register access */ |
2317 | spinlock_t didt_idx_lock; |
2318 | spinlock_t didt_idx_lock; |
2318 | /* protects concurrent ENDPOINT (audio) register access */ |
2319 | /* protects concurrent ENDPOINT (audio) register access */ |
2319 | spinlock_t end_idx_lock; |
2320 | spinlock_t end_idx_lock; |
2320 | void __iomem *rmmio; |
2321 | void __iomem *rmmio; |
2321 | radeon_rreg_t mc_rreg; |
2322 | radeon_rreg_t mc_rreg; |
2322 | radeon_wreg_t mc_wreg; |
2323 | radeon_wreg_t mc_wreg; |
2323 | radeon_rreg_t pll_rreg; |
2324 | radeon_rreg_t pll_rreg; |
2324 | radeon_wreg_t pll_wreg; |
2325 | radeon_wreg_t pll_wreg; |
2325 | uint32_t pcie_reg_mask; |
2326 | uint32_t pcie_reg_mask; |
2326 | radeon_rreg_t pciep_rreg; |
2327 | radeon_rreg_t pciep_rreg; |
2327 | radeon_wreg_t pciep_wreg; |
2328 | radeon_wreg_t pciep_wreg; |
2328 | /* io port */ |
2329 | /* io port */ |
2329 | void __iomem *rio_mem; |
2330 | void __iomem *rio_mem; |
2330 | resource_size_t rio_mem_size; |
2331 | resource_size_t rio_mem_size; |
2331 | struct radeon_clock clock; |
2332 | struct radeon_clock clock; |
2332 | struct radeon_mc mc; |
2333 | struct radeon_mc mc; |
2333 | struct radeon_gart gart; |
2334 | struct radeon_gart gart; |
2334 | struct radeon_mode_info mode_info; |
2335 | struct radeon_mode_info mode_info; |
2335 | struct radeon_scratch scratch; |
2336 | struct radeon_scratch scratch; |
2336 | struct radeon_doorbell doorbell; |
2337 | struct radeon_doorbell doorbell; |
2337 | struct radeon_mman mman; |
2338 | struct radeon_mman mman; |
2338 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
2339 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
2339 | wait_queue_head_t fence_queue; |
2340 | wait_queue_head_t fence_queue; |
2340 | unsigned fence_context; |
2341 | unsigned fence_context; |
2341 | struct mutex ring_lock; |
2342 | struct mutex ring_lock; |
2342 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
2343 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
2343 | bool ib_pool_ready; |
2344 | bool ib_pool_ready; |
2344 | struct radeon_sa_manager ring_tmp_bo; |
2345 | struct radeon_sa_manager ring_tmp_bo; |
2345 | struct radeon_irq irq; |
2346 | struct radeon_irq irq; |
2346 | struct radeon_asic *asic; |
2347 | struct radeon_asic *asic; |
2347 | struct radeon_gem gem; |
2348 | struct radeon_gem gem; |
2348 | struct radeon_pm pm; |
2349 | struct radeon_pm pm; |
2349 | struct radeon_uvd uvd; |
2350 | struct radeon_uvd uvd; |
2350 | struct radeon_vce vce; |
2351 | struct radeon_vce vce; |
2351 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
2352 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
2352 | struct radeon_wb wb; |
2353 | struct radeon_wb wb; |
2353 | struct radeon_dummy_page dummy_page; |
2354 | struct radeon_dummy_page dummy_page; |
2354 | bool shutdown; |
2355 | bool shutdown; |
2355 | bool suspend; |
2356 | bool suspend; |
2356 | bool need_dma32; |
2357 | bool need_dma32; |
2357 | bool accel_working; |
2358 | bool accel_working; |
2358 | bool fastfb_working; /* IGP feature*/ |
2359 | bool fastfb_working; /* IGP feature*/ |
2359 | bool needs_reset, in_reset; |
2360 | bool needs_reset, in_reset; |
2360 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
2361 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
2361 | const struct firmware *me_fw; /* all family ME firmware */ |
2362 | const struct firmware *me_fw; /* all family ME firmware */ |
2362 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
2363 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
2363 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
2364 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
2364 | const struct firmware *mc_fw; /* NI MC firmware */ |
2365 | const struct firmware *mc_fw; /* NI MC firmware */ |
2365 | const struct firmware *ce_fw; /* SI CE firmware */ |
2366 | const struct firmware *ce_fw; /* SI CE firmware */ |
2366 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
2367 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
2367 | const struct firmware *mec2_fw; /* KV MEC2 firmware */ |
2368 | const struct firmware *mec2_fw; /* KV MEC2 firmware */ |
2368 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
2369 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
2369 | const struct firmware *smc_fw; /* SMC firmware */ |
2370 | const struct firmware *smc_fw; /* SMC firmware */ |
2370 | const struct firmware *uvd_fw; /* UVD firmware */ |
2371 | const struct firmware *uvd_fw; /* UVD firmware */ |
2371 | const struct firmware *vce_fw; /* VCE firmware */ |
2372 | const struct firmware *vce_fw; /* VCE firmware */ |
2372 | bool new_fw; |
2373 | bool new_fw; |
2373 | struct r600_vram_scratch vram_scratch; |
2374 | struct r600_vram_scratch vram_scratch; |
2374 | int msi_enabled; /* msi enabled */ |
2375 | int msi_enabled; /* msi enabled */ |
2375 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2376 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2376 | struct radeon_rlc rlc; |
2377 | struct radeon_rlc rlc; |
2377 | struct radeon_mec mec; |
2378 | struct radeon_mec mec; |
2378 | struct delayed_work hotplug_work; |
2379 | struct delayed_work hotplug_work; |
2379 | struct work_struct dp_work; |
2380 | struct work_struct dp_work; |
2380 | struct work_struct audio_work; |
2381 | struct work_struct audio_work; |
2381 | int num_crtc; /* number of crtcs */ |
2382 | int num_crtc; /* number of crtcs */ |
2382 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
2383 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
2383 | bool has_uvd; |
2384 | bool has_uvd; |
2384 | struct r600_audio audio; /* audio stuff */ |
2385 | struct r600_audio audio; /* audio stuff */ |
2385 | struct notifier_block acpi_nb; |
2386 | struct notifier_block acpi_nb; |
2386 | /* only one userspace can use Hyperz features or CMASK at a time */ |
2387 | /* only one userspace can use Hyperz features or CMASK at a time */ |
2387 | struct drm_file *hyperz_filp; |
2388 | struct drm_file *hyperz_filp; |
2388 | struct drm_file *cmask_filp; |
2389 | struct drm_file *cmask_filp; |
2389 | /* i2c buses */ |
2390 | /* i2c buses */ |
2390 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
2391 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
2391 | /* debugfs */ |
2392 | /* debugfs */ |
2392 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
2393 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
2393 | unsigned debugfs_count; |
2394 | unsigned debugfs_count; |
2394 | /* virtual memory */ |
2395 | /* virtual memory */ |
2395 | struct radeon_vm_manager vm_manager; |
2396 | struct radeon_vm_manager vm_manager; |
2396 | struct mutex gpu_clock_mutex; |
2397 | struct mutex gpu_clock_mutex; |
2397 | /* memory stats */ |
2398 | /* memory stats */ |
2398 | atomic64_t vram_usage; |
2399 | atomic64_t vram_usage; |
2399 | atomic64_t gtt_usage; |
2400 | atomic64_t gtt_usage; |
2400 | atomic64_t num_bytes_moved; |
2401 | atomic64_t num_bytes_moved; |
2401 | atomic_t gpu_reset_counter; |
2402 | atomic_t gpu_reset_counter; |
2402 | /* ACPI interface */ |
2403 | /* ACPI interface */ |
2403 | struct radeon_atif atif; |
2404 | struct radeon_atif atif; |
2404 | struct radeon_atcs atcs; |
2405 | struct radeon_atcs atcs; |
2405 | /* srbm instance registers */ |
2406 | /* srbm instance registers */ |
2406 | struct mutex srbm_mutex; |
2407 | struct mutex srbm_mutex; |
2407 | /* GRBM index mutex. Protects concurrents access to GRBM index */ |
2408 | /* GRBM index mutex. Protects concurrents access to GRBM index */ |
2408 | struct mutex grbm_idx_mutex; |
2409 | struct mutex grbm_idx_mutex; |
2409 | /* clock, powergating flags */ |
2410 | /* clock, powergating flags */ |
2410 | u32 cg_flags; |
2411 | u32 cg_flags; |
2411 | u32 pg_flags; |
2412 | u32 pg_flags; |
2412 | 2413 | ||
2413 | // struct dev_pm_domain vga_pm_domain; |
2414 | // struct dev_pm_domain vga_pm_domain; |
2414 | bool have_disp_power_ref; |
2415 | bool have_disp_power_ref; |
2415 | u32 px_quirk_flags; |
2416 | u32 px_quirk_flags; |
2416 | 2417 | ||
2417 | /* tracking pinned memory */ |
2418 | /* tracking pinned memory */ |
2418 | u64 vram_pin_size; |
2419 | u64 vram_pin_size; |
2419 | u64 gart_pin_size; |
2420 | u64 gart_pin_size; |
2420 | struct mutex mn_lock; |
2421 | struct mutex mn_lock; |
2421 | }; |
2422 | }; |
2422 | 2423 | ||
2423 | bool radeon_is_px(struct drm_device *dev); |
2424 | bool radeon_is_px(struct drm_device *dev); |
2424 | int radeon_device_init(struct radeon_device *rdev, |
2425 | int radeon_device_init(struct radeon_device *rdev, |
2425 | struct drm_device *ddev, |
2426 | struct drm_device *ddev, |
2426 | struct pci_dev *pdev, |
2427 | struct pci_dev *pdev, |
2427 | uint32_t flags); |
2428 | uint32_t flags); |
2428 | void radeon_device_fini(struct radeon_device *rdev); |
2429 | void radeon_device_fini(struct radeon_device *rdev); |
2429 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
2430 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
2430 | 2431 | ||
2431 | #define RADEON_MIN_MMIO_SIZE 0x10000 |
2432 | #define RADEON_MIN_MMIO_SIZE 0x10000 |
2432 | 2433 | ||
2433 | uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); |
2434 | uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); |
2434 | void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
2435 | void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
2435 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
2436 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
2436 | bool always_indirect) |
2437 | bool always_indirect) |
2437 | { |
2438 | { |
2438 | /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ |
2439 | /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ |
2439 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2440 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2440 | return readl(((void __iomem *)rdev->rmmio) + reg); |
2441 | return readl(((void __iomem *)rdev->rmmio) + reg); |
2441 | else |
2442 | else |
2442 | return r100_mm_rreg_slow(rdev, reg); |
2443 | return r100_mm_rreg_slow(rdev, reg); |
2443 | } |
2444 | } |
2444 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
2445 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
2445 | bool always_indirect) |
2446 | bool always_indirect) |
2446 | { |
2447 | { |
2447 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2448 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2448 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
2449 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
2449 | else |
2450 | else |
2450 | r100_mm_wreg_slow(rdev, reg, v); |
2451 | r100_mm_wreg_slow(rdev, reg, v); |
2451 | } |
2452 | } |
2452 | 2453 | ||
2453 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
2454 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
2454 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2455 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2455 | 2456 | ||
2456 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
2457 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
2457 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); |
2458 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); |
2458 | 2459 | ||
2459 | /* |
2460 | /* |
2460 | * Cast helper |
2461 | * Cast helper |
2461 | */ |
2462 | */ |
2462 | extern const struct fence_ops radeon_fence_ops; |
2463 | extern const struct fence_ops radeon_fence_ops; |
2463 | 2464 | ||
2464 | static inline struct radeon_fence *to_radeon_fence(struct fence *f) |
2465 | static inline struct radeon_fence *to_radeon_fence(struct fence *f) |
2465 | { |
2466 | { |
2466 | struct radeon_fence *__f = container_of(f, struct radeon_fence, base); |
2467 | struct radeon_fence *__f = container_of(f, struct radeon_fence, base); |
2467 | 2468 | ||
2468 | if (__f->base.ops == &radeon_fence_ops) |
2469 | if (__f->base.ops == &radeon_fence_ops) |
2469 | return __f; |
2470 | return __f; |
2470 | 2471 | ||
2471 | return NULL; |
2472 | return NULL; |
2472 | } |
2473 | } |
2473 | 2474 | ||
2474 | /* |
2475 | /* |
2475 | * Registers read & write functions. |
2476 | * Registers read & write functions. |
2476 | */ |
2477 | */ |
2477 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
2478 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
2478 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
2479 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
2479 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
2480 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
2480 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
2481 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
2481 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
2482 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
2482 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
2483 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
2483 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
2484 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
2484 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
2485 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
2485 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
2486 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
2486 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2487 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2487 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2488 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2488 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
2489 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
2489 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
2490 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
2490 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
2491 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
2491 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
2492 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
2492 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
2493 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
2493 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
2494 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
2494 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
2495 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
2495 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
2496 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
2496 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
2497 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
2497 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) |
2498 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) |
2498 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
2499 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
2499 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) |
2500 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) |
2500 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
2501 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
2501 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) |
2502 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) |
2502 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
2503 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
2503 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) |
2504 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) |
2504 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) |
2505 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) |
2505 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) |
2506 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) |
2506 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
2507 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
2507 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) |
2508 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) |
2508 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
2509 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
2509 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) |
2510 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) |
2510 | #define WREG32_P(reg, val, mask) \ |
2511 | #define WREG32_P(reg, val, mask) \ |
2511 | do { \ |
2512 | do { \ |
2512 | uint32_t tmp_ = RREG32(reg); \ |
2513 | uint32_t tmp_ = RREG32(reg); \ |
2513 | tmp_ &= (mask); \ |
2514 | tmp_ &= (mask); \ |
2514 | tmp_ |= ((val) & ~(mask)); \ |
2515 | tmp_ |= ((val) & ~(mask)); \ |
2515 | WREG32(reg, tmp_); \ |
2516 | WREG32(reg, tmp_); \ |
2516 | } while (0) |
2517 | } while (0) |
2517 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
2518 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
2518 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
2519 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
2519 | #define WREG32_PLL_P(reg, val, mask) \ |
2520 | #define WREG32_PLL_P(reg, val, mask) \ |
2520 | do { \ |
2521 | do { \ |
2521 | uint32_t tmp_ = RREG32_PLL(reg); \ |
2522 | uint32_t tmp_ = RREG32_PLL(reg); \ |
2522 | tmp_ &= (mask); \ |
2523 | tmp_ &= (mask); \ |
2523 | tmp_ |= ((val) & ~(mask)); \ |
2524 | tmp_ |= ((val) & ~(mask)); \ |
2524 | WREG32_PLL(reg, tmp_); \ |
2525 | WREG32_PLL(reg, tmp_); \ |
2525 | } while (0) |
2526 | } while (0) |
2526 | #define WREG32_SMC_P(reg, val, mask) \ |
2527 | #define WREG32_SMC_P(reg, val, mask) \ |
2527 | do { \ |
2528 | do { \ |
2528 | uint32_t tmp_ = RREG32_SMC(reg); \ |
2529 | uint32_t tmp_ = RREG32_SMC(reg); \ |
2529 | tmp_ &= (mask); \ |
2530 | tmp_ &= (mask); \ |
2530 | tmp_ |= ((val) & ~(mask)); \ |
2531 | tmp_ |= ((val) & ~(mask)); \ |
2531 | WREG32_SMC(reg, tmp_); \ |
2532 | WREG32_SMC(reg, tmp_); \ |
2532 | } while (0) |
2533 | } while (0) |
2533 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
2534 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
2534 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
2535 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
2535 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
2536 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
2536 | 2537 | ||
2537 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
2538 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
2538 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) |
2539 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) |
2539 | 2540 | ||
2540 | /* |
2541 | /* |
2541 | * Indirect registers accessors. |
2542 | * Indirect registers accessors. |
2542 | * They used to be inlined, but this increases code size by ~65 kbytes. |
2543 | * They used to be inlined, but this increases code size by ~65 kbytes. |
2543 | * Since each performs a pair of MMIO ops |
2544 | * Since each performs a pair of MMIO ops |
2544 | * within a spin_lock_irqsave/spin_unlock_irqrestore region, |
2545 | * within a spin_lock_irqsave/spin_unlock_irqrestore region, |
2545 | * the cost of call+ret is almost negligible. MMIO and locking |
2546 | * the cost of call+ret is almost negligible. MMIO and locking |
2546 | * costs several dozens of cycles each at best, call+ret is ~5 cycles. |
2547 | * costs several dozens of cycles each at best, call+ret is ~5 cycles. |
2547 | */ |
2548 | */ |
2548 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
2549 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
2549 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
2550 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
2550 | u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); |
2551 | u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); |
2551 | void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2552 | void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2552 | u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); |
2553 | u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); |
2553 | void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2554 | void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2554 | u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); |
2555 | u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); |
2555 | void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2556 | void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2556 | u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); |
2557 | u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); |
2557 | void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2558 | void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2558 | u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); |
2559 | u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); |
2559 | void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2560 | void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2560 | u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); |
2561 | u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); |
2561 | void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2562 | void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2562 | u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); |
2563 | u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); |
2563 | void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2564 | void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2564 | 2565 | ||
2565 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
2566 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
2566 | 2567 | ||
2567 | 2568 | ||
2568 | /* |
2569 | /* |
2569 | * ASICs helpers. |
2570 | * ASICs helpers. |
2570 | */ |
2571 | */ |
2571 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
2572 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
2572 | (rdev->pdev->device == 0x5969)) |
2573 | (rdev->pdev->device == 0x5969)) |
2573 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
2574 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
2574 | (rdev->family == CHIP_RV200) || \ |
2575 | (rdev->family == CHIP_RV200) || \ |
2575 | (rdev->family == CHIP_RS100) || \ |
2576 | (rdev->family == CHIP_RS100) || \ |
2576 | (rdev->family == CHIP_RS200) || \ |
2577 | (rdev->family == CHIP_RS200) || \ |
2577 | (rdev->family == CHIP_RV250) || \ |
2578 | (rdev->family == CHIP_RV250) || \ |
2578 | (rdev->family == CHIP_RV280) || \ |
2579 | (rdev->family == CHIP_RV280) || \ |
2579 | (rdev->family == CHIP_RS300)) |
2580 | (rdev->family == CHIP_RS300)) |
2580 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
2581 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
2581 | (rdev->family == CHIP_RV350) || \ |
2582 | (rdev->family == CHIP_RV350) || \ |
2582 | (rdev->family == CHIP_R350) || \ |
2583 | (rdev->family == CHIP_R350) || \ |
2583 | (rdev->family == CHIP_RV380) || \ |
2584 | (rdev->family == CHIP_RV380) || \ |
2584 | (rdev->family == CHIP_R420) || \ |
2585 | (rdev->family == CHIP_R420) || \ |
2585 | (rdev->family == CHIP_R423) || \ |
2586 | (rdev->family == CHIP_R423) || \ |
2586 | (rdev->family == CHIP_RV410) || \ |
2587 | (rdev->family == CHIP_RV410) || \ |
2587 | (rdev->family == CHIP_RS400) || \ |
2588 | (rdev->family == CHIP_RS400) || \ |
2588 | (rdev->family == CHIP_RS480)) |
2589 | (rdev->family == CHIP_RS480)) |
2589 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2590 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2590 | (rdev->ddev->pdev->device == 0x9443) || \ |
2591 | (rdev->ddev->pdev->device == 0x9443) || \ |
2591 | (rdev->ddev->pdev->device == 0x944B) || \ |
2592 | (rdev->ddev->pdev->device == 0x944B) || \ |
2592 | (rdev->ddev->pdev->device == 0x9506) || \ |
2593 | (rdev->ddev->pdev->device == 0x9506) || \ |
2593 | (rdev->ddev->pdev->device == 0x9509) || \ |
2594 | (rdev->ddev->pdev->device == 0x9509) || \ |
2594 | (rdev->ddev->pdev->device == 0x950F) || \ |
2595 | (rdev->ddev->pdev->device == 0x950F) || \ |
2595 | (rdev->ddev->pdev->device == 0x689C) || \ |
2596 | (rdev->ddev->pdev->device == 0x689C) || \ |
2596 | (rdev->ddev->pdev->device == 0x689D)) |
2597 | (rdev->ddev->pdev->device == 0x689D)) |
2597 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
2598 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
2598 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2599 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2599 | (rdev->family == CHIP_RS690) || \ |
2600 | (rdev->family == CHIP_RS690) || \ |
2600 | (rdev->family == CHIP_RS740) || \ |
2601 | (rdev->family == CHIP_RS740) || \ |
2601 | (rdev->family >= CHIP_R600)) |
2602 | (rdev->family >= CHIP_R600)) |
2602 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2603 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2603 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
2604 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
2604 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
2605 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
2605 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2606 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2606 | (rdev->flags & RADEON_IS_IGP)) |
2607 | (rdev->flags & RADEON_IS_IGP)) |
2607 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
2608 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
2608 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2609 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2609 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
2610 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
2610 | (rdev->flags & RADEON_IS_IGP)) |
2611 | (rdev->flags & RADEON_IS_IGP)) |
2611 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
2612 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
2612 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
2613 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
2613 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
2614 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
2614 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
2615 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
2615 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) |
2616 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) |
2616 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
2617 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
2617 | (rdev->family == CHIP_MULLINS)) |
2618 | (rdev->family == CHIP_MULLINS)) |
2618 | 2619 | ||
2619 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
2620 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
2620 | (rdev->ddev->pdev->device == 0x6850) || \ |
2621 | (rdev->ddev->pdev->device == 0x6850) || \ |
2621 | (rdev->ddev->pdev->device == 0x6858) || \ |
2622 | (rdev->ddev->pdev->device == 0x6858) || \ |
2622 | (rdev->ddev->pdev->device == 0x6859) || \ |
2623 | (rdev->ddev->pdev->device == 0x6859) || \ |
2623 | (rdev->ddev->pdev->device == 0x6840) || \ |
2624 | (rdev->ddev->pdev->device == 0x6840) || \ |
2624 | (rdev->ddev->pdev->device == 0x6841) || \ |
2625 | (rdev->ddev->pdev->device == 0x6841) || \ |
2625 | (rdev->ddev->pdev->device == 0x6842) || \ |
2626 | (rdev->ddev->pdev->device == 0x6842) || \ |
2626 | (rdev->ddev->pdev->device == 0x6843)) |
2627 | (rdev->ddev->pdev->device == 0x6843)) |
2627 | 2628 | ||
2628 | /* |
2629 | /* |
2629 | * BIOS helpers. |
2630 | * BIOS helpers. |
2630 | */ |
2631 | */ |
2631 | #define RBIOS8(i) (rdev->bios[i]) |
2632 | #define RBIOS8(i) (rdev->bios[i]) |
2632 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
2633 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
2633 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
2634 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
2634 | 2635 | ||
2635 | int radeon_combios_init(struct radeon_device *rdev); |
2636 | int radeon_combios_init(struct radeon_device *rdev); |
2636 | void radeon_combios_fini(struct radeon_device *rdev); |
2637 | void radeon_combios_fini(struct radeon_device *rdev); |
2637 | int radeon_atombios_init(struct radeon_device *rdev); |
2638 | int radeon_atombios_init(struct radeon_device *rdev); |
2638 | void radeon_atombios_fini(struct radeon_device *rdev); |
2639 | void radeon_atombios_fini(struct radeon_device *rdev); |
2639 | 2640 | ||
2640 | 2641 | ||
2641 | /* |
2642 | /* |
2642 | * RING helpers. |
2643 | * RING helpers. |
2643 | */ |
2644 | */ |
2644 | 2645 | ||
2645 | /** |
2646 | /** |
2646 | * radeon_ring_write - write a value to the ring |
2647 | * radeon_ring_write - write a value to the ring |
2647 | * |
2648 | * |
2648 | * @ring: radeon_ring structure holding ring information |
2649 | * @ring: radeon_ring structure holding ring information |
2649 | * @v: dword (dw) value to write |
2650 | * @v: dword (dw) value to write |
2650 | * |
2651 | * |
2651 | * Write a value to the requested ring buffer (all asics). |
2652 | * Write a value to the requested ring buffer (all asics). |
2652 | */ |
2653 | */ |
2653 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
2654 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
2654 | { |
2655 | { |
2655 | if (ring->count_dw <= 0) |
2656 | if (ring->count_dw <= 0) |
2656 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
2657 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
2657 | 2658 | ||
2658 | ring->ring[ring->wptr++] = v; |
2659 | ring->ring[ring->wptr++] = v; |
2659 | ring->wptr &= ring->ptr_mask; |
2660 | ring->wptr &= ring->ptr_mask; |
2660 | ring->count_dw--; |
2661 | ring->count_dw--; |
2661 | ring->ring_free_dw--; |
2662 | ring->ring_free_dw--; |
2662 | } |
2663 | } |
2663 | 2664 | ||
2664 | /* |
2665 | /* |
2665 | * ASICs macro. |
2666 | * ASICs macro. |
2666 | */ |
2667 | */ |
2667 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
2668 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
2668 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2669 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2669 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
2670 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
2670 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
2671 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
2671 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
2672 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
2672 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
2673 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
2673 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
2674 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
2674 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
2675 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
2675 | #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) |
2676 | #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) |
2676 | #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) |
2677 | #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) |
2677 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2678 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2678 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
2679 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
2679 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) |
2680 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) |
2680 | #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2681 | #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2681 | #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2682 | #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2682 | #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) |
2683 | #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) |
2683 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
2684 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
2684 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) |
2685 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) |
2685 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) |
2686 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) |
2686 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) |
2687 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) |
2687 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) |
2688 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) |
2688 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) |
2689 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) |
2689 | #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) |
2690 | #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) |
2690 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
2691 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
2691 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) |
2692 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) |
2692 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) |
2693 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) |
2693 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2694 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2694 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
2695 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
2695 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
2696 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
2696 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
2697 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
2697 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
2698 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
2698 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2699 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2699 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
2700 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
2700 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
2701 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
2701 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
2702 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
2702 | #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) |
2703 | #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) |
2703 | #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) |
2704 | #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) |
2704 | #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) |
2705 | #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) |
2705 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
2706 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
2706 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
2707 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
2707 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
2708 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
2708 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2709 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2709 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
2710 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
2710 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
2711 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
2711 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
2712 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
2712 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
2713 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
2713 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
2714 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
2714 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
2715 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
2715 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
2716 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
2716 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
2717 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
2717 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
2718 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
2718 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2719 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2719 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
2720 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
2720 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
2721 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
2721 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2722 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2722 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
2723 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
2723 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
2724 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
2724 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
2725 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
2725 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2726 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2726 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2727 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2727 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
2728 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
2728 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
2729 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
2729 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
2730 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
2730 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
2731 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
2731 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
2732 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
2732 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
2733 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
2733 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
2734 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
2734 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
2735 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
2735 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
2736 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
2736 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
2737 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
2737 | #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) |
2738 | #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) |
2738 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
2739 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
2739 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) |
2740 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) |
2740 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) |
2741 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) |
2741 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
2742 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
2742 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
2743 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
2743 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
2744 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
2744 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
2745 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
2745 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
2746 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
2746 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
2747 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
2747 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) |
2748 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) |
2748 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) |
2749 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) |
2749 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) |
2750 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) |
2750 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) |
2751 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) |
2751 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
2752 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
2752 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
2753 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
2753 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
2754 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
2754 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
2755 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
2755 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
2756 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
2756 | #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) |
2757 | #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) |
2757 | #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) |
2758 | #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) |
2758 | 2759 | ||
2759 | /* Common functions */ |
2760 | /* Common functions */ |
2760 | /* AGP */ |
2761 | /* AGP */ |
2761 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
2762 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
2762 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
2763 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
2763 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
2764 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
2764 | extern void radeon_agp_disable(struct radeon_device *rdev); |
2765 | extern void radeon_agp_disable(struct radeon_device *rdev); |
2765 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2766 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2766 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
2767 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
2767 | extern bool radeon_card_posted(struct radeon_device *rdev); |
2768 | extern bool radeon_card_posted(struct radeon_device *rdev); |
2768 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
2769 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
2769 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
2770 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
2770 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
2771 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
2771 | extern void radeon_scratch_init(struct radeon_device *rdev); |
2772 | extern void radeon_scratch_init(struct radeon_device *rdev); |
2772 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2773 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2773 | extern int radeon_wb_init(struct radeon_device *rdev); |
2774 | extern int radeon_wb_init(struct radeon_device *rdev); |
2774 | extern void radeon_wb_disable(struct radeon_device *rdev); |
2775 | extern void radeon_wb_disable(struct radeon_device *rdev); |
2775 | extern void radeon_surface_init(struct radeon_device *rdev); |
2776 | extern void radeon_surface_init(struct radeon_device *rdev); |
2776 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
2777 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
2777 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
2778 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
2778 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
2779 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
2779 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
2780 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
2780 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
2781 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
2781 | extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
2782 | extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
2782 | uint32_t flags); |
2783 | uint32_t flags); |
2783 | extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); |
2784 | extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); |
2784 | extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); |
2785 | extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); |
2785 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2786 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2786 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
2787 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
2787 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
2788 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
2788 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); |
2789 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); |
2789 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2790 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2790 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2791 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2791 | const u32 *registers, |
2792 | const u32 *registers, |
2792 | const u32 array_size); |
2793 | const u32 array_size); |
2793 | 2794 | ||
2794 | /* |
2795 | /* |
2795 | * vm |
2796 | * vm |
2796 | */ |
2797 | */ |
2797 | int radeon_vm_manager_init(struct radeon_device *rdev); |
2798 | int radeon_vm_manager_init(struct radeon_device *rdev); |
2798 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
2799 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
2799 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
2800 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
2800 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
2801 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
2801 | struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, |
2802 | struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, |
2802 | struct radeon_vm *vm, |
2803 | struct radeon_vm *vm, |
2803 | struct list_head *head); |
2804 | struct list_head *head); |
2804 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2805 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2805 | struct radeon_vm *vm, int ring); |
2806 | struct radeon_vm *vm, int ring); |
2806 | void radeon_vm_flush(struct radeon_device *rdev, |
2807 | void radeon_vm_flush(struct radeon_device *rdev, |
2807 | struct radeon_vm *vm, |
2808 | struct radeon_vm *vm, |
2808 | int ring, struct radeon_fence *fence); |
2809 | int ring, struct radeon_fence *fence); |
2809 | void radeon_vm_fence(struct radeon_device *rdev, |
2810 | void radeon_vm_fence(struct radeon_device *rdev, |
2810 | struct radeon_vm *vm, |
2811 | struct radeon_vm *vm, |
2811 | struct radeon_fence *fence); |
2812 | struct radeon_fence *fence); |
2812 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
2813 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
2813 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
2814 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
2814 | struct radeon_vm *vm); |
2815 | struct radeon_vm *vm); |
2815 | int radeon_vm_clear_freed(struct radeon_device *rdev, |
2816 | int radeon_vm_clear_freed(struct radeon_device *rdev, |
2816 | struct radeon_vm *vm); |
2817 | struct radeon_vm *vm); |
2817 | int radeon_vm_clear_invalids(struct radeon_device *rdev, |
2818 | int radeon_vm_clear_invalids(struct radeon_device *rdev, |
2818 | struct radeon_vm *vm); |
2819 | struct radeon_vm *vm); |
2819 | int radeon_vm_bo_update(struct radeon_device *rdev, |
2820 | int radeon_vm_bo_update(struct radeon_device *rdev, |
2820 | struct radeon_bo_va *bo_va, |
2821 | struct radeon_bo_va *bo_va, |
2821 | struct ttm_mem_reg *mem); |
2822 | struct ttm_mem_reg *mem); |
2822 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
2823 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
2823 | struct radeon_bo *bo); |
2824 | struct radeon_bo *bo); |
2824 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2825 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2825 | struct radeon_bo *bo); |
2826 | struct radeon_bo *bo); |
2826 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2827 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2827 | struct radeon_vm *vm, |
2828 | struct radeon_vm *vm, |
2828 | struct radeon_bo *bo); |
2829 | struct radeon_bo *bo); |
2829 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
2830 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
2830 | struct radeon_bo_va *bo_va, |
2831 | struct radeon_bo_va *bo_va, |
2831 | uint64_t offset, |
2832 | uint64_t offset, |
2832 | uint32_t flags); |
2833 | uint32_t flags); |
2833 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
2834 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
2834 | struct radeon_bo_va *bo_va); |
2835 | struct radeon_bo_va *bo_va); |
2835 | 2836 | ||
2836 | /* audio */ |
2837 | /* audio */ |
2837 | void r600_audio_update_hdmi(struct work_struct *work); |
2838 | void r600_audio_update_hdmi(struct work_struct *work); |
2838 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2839 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2839 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
2840 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
2840 | void r600_audio_enable(struct radeon_device *rdev, |
2841 | void r600_audio_enable(struct radeon_device *rdev, |
2841 | struct r600_audio_pin *pin, |
2842 | struct r600_audio_pin *pin, |
2842 | u8 enable_mask); |
2843 | u8 enable_mask); |
2843 | void dce6_audio_enable(struct radeon_device *rdev, |
2844 | void dce6_audio_enable(struct radeon_device *rdev, |
2844 | struct r600_audio_pin *pin, |
2845 | struct r600_audio_pin *pin, |
2845 | u8 enable_mask); |
2846 | u8 enable_mask); |
2846 | 2847 | ||
2847 | /* |
2848 | /* |
2848 | * R600 vram scratch functions |
2849 | * R600 vram scratch functions |
2849 | */ |
2850 | */ |
2850 | int r600_vram_scratch_init(struct radeon_device *rdev); |
2851 | int r600_vram_scratch_init(struct radeon_device *rdev); |
2851 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
2852 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
2852 | 2853 | ||
2853 | /* |
2854 | /* |
2854 | * r600 cs checking helper |
2855 | * r600 cs checking helper |
2855 | */ |
2856 | */ |
2856 | unsigned r600_mip_minify(unsigned size, unsigned level); |
2857 | unsigned r600_mip_minify(unsigned size, unsigned level); |
2857 | bool r600_fmt_is_valid_color(u32 format); |
2858 | bool r600_fmt_is_valid_color(u32 format); |
2858 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
2859 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
2859 | int r600_fmt_get_blocksize(u32 format); |
2860 | int r600_fmt_get_blocksize(u32 format); |
2860 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
2861 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
2861 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
2862 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
2862 | 2863 | ||
2863 | /* |
2864 | /* |
2864 | * r600 functions used by radeon_encoder.c |
2865 | * r600 functions used by radeon_encoder.c |
2865 | */ |
2866 | */ |
2866 | struct radeon_hdmi_acr { |
2867 | struct radeon_hdmi_acr { |
2867 | u32 clock; |
2868 | u32 clock; |
2868 | 2869 | ||
2869 | int n_32khz; |
2870 | int n_32khz; |
2870 | int cts_32khz; |
2871 | int cts_32khz; |
2871 | 2872 | ||
2872 | int n_44_1khz; |
2873 | int n_44_1khz; |
2873 | int cts_44_1khz; |
2874 | int cts_44_1khz; |
2874 | 2875 | ||
2875 | int n_48khz; |
2876 | int n_48khz; |
2876 | int cts_48khz; |
2877 | int cts_48khz; |
2877 | 2878 | ||
2878 | }; |
2879 | }; |
2879 | 2880 | ||
2880 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2881 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2881 | 2882 | ||
2882 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2883 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2883 | u32 tiling_pipe_num, |
2884 | u32 tiling_pipe_num, |
2884 | u32 max_rb_num, |
2885 | u32 max_rb_num, |
2885 | u32 total_max_rb_num, |
2886 | u32 total_max_rb_num, |
2886 | u32 enabled_rb_mask); |
2887 | u32 enabled_rb_mask); |
2887 | 2888 | ||
2888 | /* |
2889 | /* |
2889 | * evergreen functions used by radeon_encoder.c |
2890 | * evergreen functions used by radeon_encoder.c |
2890 | */ |
2891 | */ |
2891 | 2892 | ||
2892 | extern int ni_init_microcode(struct radeon_device *rdev); |
2893 | extern int ni_init_microcode(struct radeon_device *rdev); |
2893 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
2894 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
2894 | 2895 | ||
2895 | /* radeon_acpi.c */ |
2896 | /* radeon_acpi.c */ |
2896 | #if defined(CONFIG_ACPI) |
2897 | #if defined(CONFIG_ACPI) |
2897 | extern int radeon_acpi_init(struct radeon_device *rdev); |
2898 | extern int radeon_acpi_init(struct radeon_device *rdev); |
2898 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
2899 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
2899 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
2900 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
2900 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, |
2901 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, |
2901 | u8 perf_req, bool advertise); |
2902 | u8 perf_req, bool advertise); |
2902 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
2903 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
2903 | #else |
2904 | #else |
2904 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
2905 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
2905 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
2906 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
2906 | #endif |
2907 | #endif |
2907 | 2908 | ||
2908 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2909 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2909 | struct radeon_cs_packet *pkt, |
2910 | struct radeon_cs_packet *pkt, |
2910 | unsigned idx); |
2911 | unsigned idx); |
2911 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
2912 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
2912 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2913 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2913 | struct radeon_cs_packet *pkt); |
2914 | struct radeon_cs_packet *pkt); |
2914 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2915 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2915 | struct radeon_bo_list **cs_reloc, |
2916 | struct radeon_bo_list **cs_reloc, |
2916 | int nomm); |
2917 | int nomm); |
2917 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
2918 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
2918 | uint32_t *vline_start_end, |
2919 | uint32_t *vline_start_end, |
2919 | uint32_t *vline_status); |
2920 | uint32_t *vline_status); |
2920 | 2921 | ||
2921 | #include "radeon_object.h" |
2922 | #include "radeon_object.h" |
2922 | 2923 | ||
2923 | #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 |
2924 | #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 |
2924 | #define PCI_VENDOR_ID_ATI 0x1002 |
2925 | #define PCI_VENDOR_ID_ATI 0x1002 |
2925 | 2926 | ||
2926 | resource_size_t |
2927 | resource_size_t |
2927 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
2928 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
2928 | resource_size_t |
2929 | resource_size_t |
2929 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
2930 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
2930 | 2931 | ||
2931 | #endif=>><>><>><>><>>>>>=>=>><>><>><>><>><>><>><>><>><>><>><>=>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
2932 | #endif=>><>><>><>><>>>>>=>=>><>><>><>><>><>><>><>><>><>><>><>=>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |