WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon.h


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RADEON_H__
#define __RADEON_H__
 
/* TODO: Here are things that needs to be done :
 *	- surface allocator & initializer : (bit like scratch reg) should
 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
 *	  related to surface
 *	- WB : write back stuff (do it bit like scratch reg things)
 *	- Vblank : look at Jesse's rework and what we should do
 *	- r600/r700: gart & cp
 *	- cs : clean cs ioctl use bitmap & things like that.
 *	- power management stuff
 *	- Barrier in gart code
 *	- Unmappabled vram ?
 *	- TESTING, TESTING, TESTING
 */
 
/* Initialization path:
 *  We expect that acceleration initialization might fail for various
 *  reasons even thought we work hard to make it works on most
 *  configurations. In order to still have a working userspace in such
 *  situation the init path must succeed up to the memory controller
 *  initialization point. Failure before this point are considered as
 *  fatal error. Here is the init callchain :
 *      radeon_device_init  perform common structure, mutex initialization
 *      asic_init           setup the GPU memory layout and perform all
 *                          one time initialization (failure in this
 *                          function are considered fatal)
 *      asic_startup        setup the GPU acceleration, in order to
 *                          follow guideline the first thing this
 *                          function should do is setting the GPU
 *                          memory controller (only MC setup failure
 *                          are considered as fatal)
 */
 
#include 
#include 
#include 
#include 
#include 
 
#include 
#include 
#include 
#include 
 
#include 
#include 
 
#include 
 
#include "radeon_family.h"
#include "radeon_mode.h"
#include "radeon_reg.h"
 
#include 
 
/*
 * Modules parameters.
 */
extern int radeon_no_wb;
extern int radeon_modeset;
extern int radeon_dynclks;
extern int radeon_r4xx_atom;
extern int radeon_agpmode;
extern int radeon_vram_limit;
extern int radeon_gart_size;
extern int radeon_benchmarking;
extern int radeon_testing;
extern int radeon_connector_table;
extern int radeon_tv;
extern int radeon_audio;
extern int radeon_disp_priority;
extern int radeon_hw_i2c;
extern int radeon_pcie_gen2;
extern int radeon_msi;
extern int radeon_lockup_timeout;
 
extern int radeon_fastfb;
 
 
typedef struct pm_message {
    int event;
} pm_message_t;
 
typedef struct
{
  int width;
  int height;
  int bpp;
  int freq;
}videomode_t;
 
 
 
static inline u32 ioread32(const volatile void __iomem *addr)
{
    return in32((u32)addr);
}
 
//static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
//{
//    out32((u32)addr, b);
//}
 
 
/*
 * Copy from radeon_drv.h so we don't have to include both and have conflicting
 * symbol;
 */
#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
#define RADEON_FENCE_JIFFIES_TIMEOUT	(HZ / 2)
/* RADEON_IB_POOL_SIZE must be a power of 2 */
#define RADEON_IB_POOL_SIZE             16
#define RADEON_DEBUGFS_MAX_COMPONENTS	32
#define RADEONFB_CONN_LIMIT             4
#define RADEON_BIOS_NUM_SCRATCH		8
 
/* max number of rings */
#define RADEON_NUM_RINGS			6
 
/* fence seq are set to this number when signaled */
#define RADEON_FENCE_SIGNALED_SEQ		0LL
 
/* internal ring indices */
/* r1xx+ has gfx CP ring */
#define RADEON_RING_TYPE_GFX_INDEX  0
 
/* cayman has 2 compute CP rings */
#define CAYMAN_RING_TYPE_CP1_INDEX 1
#define CAYMAN_RING_TYPE_CP2_INDEX 2
 
/* R600+ has an async dma ring */
#define R600_RING_TYPE_DMA_INDEX		3
/* cayman add a second async dma ring */
#define CAYMAN_RING_TYPE_DMA1_INDEX		4
 
/* R600+ */
#define R600_RING_TYPE_UVD_INDEX	5
 
/* hardcode those limit for now */
#define RADEON_VA_IB_OFFSET			(1 << 20)
#define RADEON_VA_RESERVED_SIZE		(8 << 20)
#define RADEON_IB_VM_MAX_SIZE		(64 << 10)
 
/* reset flags */
#define RADEON_RESET_GFX			(1 << 0)
#define RADEON_RESET_COMPUTE			(1 << 1)
#define RADEON_RESET_DMA			(1 << 2)
#define RADEON_RESET_CP				(1 << 3)
#define RADEON_RESET_GRBM			(1 << 4)
#define RADEON_RESET_DMA1			(1 << 5)
#define RADEON_RESET_RLC			(1 << 6)
#define RADEON_RESET_SEM			(1 << 7)
#define RADEON_RESET_IH				(1 << 8)
#define RADEON_RESET_VMC			(1 << 9)
#define RADEON_RESET_MC				(1 << 10)
#define RADEON_RESET_DISPLAY			(1 << 11)
 
/*
 * Errata workarounds.
 */
enum radeon_pll_errata {
    CHIP_ERRATA_R300_CG             = 0x00000001,
    CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
    CHIP_ERRATA_PLL_DELAY           = 0x00000004
};
 
 
struct radeon_device;
 
 
/*
 * BIOS.
 */
bool radeon_get_bios(struct radeon_device *rdev);
 
/*
 * Dummy page
 */
struct radeon_dummy_page {
	struct page	*page;
	dma_addr_t	addr;
};
int radeon_dummy_page_init(struct radeon_device *rdev);
void radeon_dummy_page_fini(struct radeon_device *rdev);
 
 
/*
 * Clocks
 */
struct radeon_clock {
	struct radeon_pll p1pll;
	struct radeon_pll p2pll;
	struct radeon_pll dcpll;
	struct radeon_pll spll;
	struct radeon_pll mpll;
	/* 10 Khz units */
	uint32_t default_mclk;
	uint32_t default_sclk;
	uint32_t default_dispclk;
	uint32_t dp_extclk;
	uint32_t max_pixel_clock;
};
 
/*
 * Power management
 */
int radeon_pm_init(struct radeon_device *rdev);
void radeon_pm_fini(struct radeon_device *rdev);
void radeon_pm_compute_clocks(struct radeon_device *rdev);
void radeon_pm_suspend(struct radeon_device *rdev);
void radeon_pm_resume(struct radeon_device *rdev);
void radeon_combios_get_power_modes(struct radeon_device *rdev);
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
				   u8 clock_type,
				   u32 clock,
				   bool strobe_mode,
				   struct atom_clock_dividers *dividers);
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
void rs690_pm_info(struct radeon_device *rdev);
extern int rv6xx_get_temp(struct radeon_device *rdev);
extern int rv770_get_temp(struct radeon_device *rdev);
extern int evergreen_get_temp(struct radeon_device *rdev);
extern int sumo_get_temp(struct radeon_device *rdev);
extern int si_get_temp(struct radeon_device *rdev);
extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
				    unsigned *bankh, unsigned *mtaspect,
				    unsigned *tile_split);
 
/*
 * Fences.
 */
struct radeon_fence_driver {
	uint32_t			scratch_reg;
	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
	/* sync_seq is protected by ring emission lock */
	uint64_t			sync_seq[RADEON_NUM_RINGS];
	atomic64_t			last_seq;
	unsigned long			last_activity;
	bool				initialized;
};
 
struct radeon_fence {
    struct radeon_device   *rdev;
    struct kref             kref;
	/* protected by radeon_fence.lock */
	uint64_t			seq;
	/* RB, DMA, etc. */
	unsigned			ring;
};
 
int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
int radeon_fence_driver_init(struct radeon_device *rdev);
void radeon_fence_driver_fini(struct radeon_device *rdev);
void radeon_fence_driver_force_completion(struct radeon_device *rdev);
int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
void radeon_fence_process(struct radeon_device *rdev, int ring);
bool radeon_fence_signaled(struct radeon_fence *fence);
int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
int radeon_fence_wait_any(struct radeon_device *rdev,
			  struct radeon_fence **fences,
			  bool intr);
struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
void radeon_fence_unref(struct radeon_fence **fence);
unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
						      struct radeon_fence *b)
{
	if (!a) {
		return b;
	}
 
	if (!b) {
		return a;
	}
 
	BUG_ON(a->ring != b->ring);
 
	if (a->seq > b->seq) {
		return a;
	} else {
		return b;
	}
}
 
static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
					   struct radeon_fence *b)
{
	if (!a) {
		return false;
	}
 
	if (!b) {
		return true;
	}
 
	BUG_ON(a->ring != b->ring);
 
	return a->seq < b->seq;
}
 
/*
 * Tiling registers
 */
struct radeon_surface_reg {
	struct radeon_bo *bo;
};
 
#define RADEON_GEM_MAX_SURFACES 8
 
/*
 * TTM.
 */
struct radeon_mman {
	struct ttm_bo_global_ref        bo_global_ref;
	struct drm_global_reference	mem_global_ref;
	struct ttm_bo_device		bdev;
	bool				mem_global_referenced;
	bool				initialized;
};
 
/* bo virtual address in a specific vm */
struct radeon_bo_va {
	/* protected by bo being reserved */
	struct list_head		bo_list;
	uint64_t			soffset;
	uint64_t			eoffset;
	uint32_t			flags;
	bool				valid;
	unsigned			ref_count;
 
	/* protected by vm mutex */
	struct list_head		vm_list;
 
	/* constant after initialization */
	struct radeon_vm		*vm;
	struct radeon_bo		*bo;
};
 
struct radeon_bo {
	/* Protected by gem.mutex */
	struct list_head		list;
	/* Protected by tbo.reserved */
	u32				placements[3];
    u32             domain;
	struct ttm_placement		placement;
	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
    unsigned                    pin_count;
    void                       *kptr;
    void                       *uptr;
    u32                         cpu_addr;
    u32                         tiling_flags;
    u32                         pitch;
    int                         surface_reg;
	/* list of all virtual address to which this bo
	 * is associated to
	 */
	struct list_head		va;
	/* Constant after initialization */
	struct radeon_device		*rdev;
	struct drm_gem_object		gem_base;
 
 
	struct ttm_bo_kmap_obj dma_buf_vmap;
};
#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 
struct radeon_bo_list {
	struct radeon_bo	*bo;
	uint64_t		gpu_offset;
	unsigned		rdomain;
	unsigned		wdomain;
	u32			tiling_flags;
};
 
int radeon_gem_debugfs_init(struct radeon_device *rdev);
 
/* sub-allocation manager, it has to be protected by another lock.
 * By conception this is an helper for other part of the driver
 * like the indirect buffer or semaphore, which both have their
 * locking.
 *
 * Principe is simple, we keep a list of sub allocation in offset
 * order (first entry has offset == 0, last entry has the highest
 * offset).
 *
 * When allocating new object we first check if there is room at
 * the end total_size - (last_object_offset + last_object_size) >=
 * alloc_size. If so we allocate new object there.
 *
 * When there is not enough room at the end, we start waiting for
 * each sub object until we reach object_offset+object_size >=
 * alloc_size, this object then become the sub object we return.
 *
 * Alignment can't be bigger than page size.
 *
 * Hole are not considered for allocation to keep things simple.
 * Assumption is that there won't be hole (all object on same
 * alignment).
 */
struct radeon_sa_manager {
	wait_queue_head_t	wq;
	struct radeon_bo	*bo;
	struct list_head	*hole;
	struct list_head	flist[RADEON_NUM_RINGS];
	struct list_head	olist;
	unsigned		size;
	uint64_t		gpu_addr;
	void			*cpu_ptr;
	uint32_t		domain;
};
 
struct radeon_sa_bo;
 
/* sub-allocation buffer */
struct radeon_sa_bo {
	struct list_head		olist;
	struct list_head		flist;
	struct radeon_sa_manager	*manager;
	unsigned			soffset;
	unsigned			eoffset;
	struct radeon_fence		*fence;
};
 
/*
 * GEM objects.
 */
struct radeon_gem {
	struct mutex		mutex;
	struct list_head	objects;
};
 
int radeon_gem_init(struct radeon_device *rdev);
void radeon_gem_fini(struct radeon_device *rdev);
int radeon_gem_object_create(struct radeon_device *rdev, int size,
			     int alignment, int initial_domain,
			     bool discardable, bool kernel,
			     struct drm_gem_object **obj);
 
int radeon_mode_dumb_create(struct drm_file *file_priv,
			    struct drm_device *dev,
			    struct drm_mode_create_dumb *args);
int radeon_mode_dumb_mmap(struct drm_file *filp,
			  struct drm_device *dev,
			  uint32_t handle, uint64_t *offset_p);
int radeon_mode_dumb_destroy(struct drm_file *file_priv,
			     struct drm_device *dev,
			     uint32_t handle);
 
/*
 * Semaphores.
 */
/* everything here is constant */
struct radeon_semaphore {
	struct radeon_sa_bo		*sa_bo;
	signed				waiters;
	uint64_t			gpu_addr;
};
 
int radeon_semaphore_create(struct radeon_device *rdev,
			    struct radeon_semaphore **semaphore);
void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
				  struct radeon_semaphore *semaphore);
void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
				struct radeon_semaphore *semaphore);
int radeon_semaphore_sync_rings(struct radeon_device *rdev,
				struct radeon_semaphore *semaphore,
				int signaler, int waiter);
void radeon_semaphore_free(struct radeon_device *rdev,
			   struct radeon_semaphore **semaphore,
			   struct radeon_fence *fence);
 
/*
 * GART structures, functions & helpers
 */
struct radeon_mc;
 
#define RADEON_GPU_PAGE_SIZE 4096
#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
#define RADEON_GPU_PAGE_SHIFT 12
#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 
struct radeon_gart {
    dma_addr_t          table_addr;
	struct radeon_bo		*robj;
	void				*ptr;
    unsigned            num_gpu_pages;
    unsigned            num_cpu_pages;
    unsigned            table_size;
    struct page         **pages;
    dma_addr_t          *pages_addr;
    bool                ready;
};
 
int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
void radeon_gart_table_ram_free(struct radeon_device *rdev);
int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
void radeon_gart_table_vram_free(struct radeon_device *rdev);
int radeon_gart_table_vram_pin(struct radeon_device *rdev);
void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
int radeon_gart_init(struct radeon_device *rdev);
void radeon_gart_fini(struct radeon_device *rdev);
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages);
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
             int pages, u32 *pagelist,
		     dma_addr_t *dma_addr);
void radeon_gart_restore(struct radeon_device *rdev);
 
 
/*
 * GPU MC structures, functions & helpers
 */
struct radeon_mc {
    resource_size_t     aper_size;
    resource_size_t     aper_base;
    resource_size_t     agp_base;
	/* for some chips with <= 32MB we need to lie
	 * about vram size near mc fb location */
	u64			mc_vram_size;
	u64			visible_vram_size;
	u64			gtt_size;
	u64			gtt_start;
	u64			gtt_end;
	u64			vram_start;
	u64			vram_end;
    unsigned            vram_width;
	u64			real_vram_size;
    int                 vram_mtrr;
    bool                vram_is_ddr;
	bool                    igp_sideport_enabled;
	u64                     gtt_base_align;
	u64                     mc_mask;
};
 
bool radeon_combios_sideport_present(struct radeon_device *rdev);
bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 
/*
 * GPU scratch registers structures, functions & helpers
 */
struct radeon_scratch {
    unsigned        num_reg;
	uint32_t                reg_base;
    bool            free[32];
    uint32_t        reg[32];
};
 
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 
 
/*
 * IRQS.
 */
struct r500_irq_stat_regs {
	u32 disp_int;
	u32 hdmi0_status;
};
 
struct r600_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 d1grph_int;
	u32 d2grph_int;
	u32 hdmi0_status;
	u32 hdmi1_status;
};
 
struct evergreen_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 disp_int_cont3;
	u32 disp_int_cont4;
	u32 disp_int_cont5;
	u32 d1grph_int;
	u32 d2grph_int;
	u32 d3grph_int;
	u32 d4grph_int;
	u32 d5grph_int;
	u32 d6grph_int;
	u32 afmt_status1;
	u32 afmt_status2;
	u32 afmt_status3;
	u32 afmt_status4;
	u32 afmt_status5;
	u32 afmt_status6;
};
 
union radeon_irq_stat_regs {
	struct r500_irq_stat_regs r500;
	struct r600_irq_stat_regs r600;
	struct evergreen_irq_stat_regs evergreen;
};
 
#define RADEON_MAX_HPD_PINS 6
#define RADEON_MAX_CRTCS 6
#define RADEON_MAX_AFMT_BLOCKS 6
 
struct radeon_irq {
	bool		installed;
	spinlock_t			lock;
	atomic_t			ring_int[RADEON_NUM_RINGS];
	bool				crtc_vblank_int[RADEON_MAX_CRTCS];
	atomic_t			pflip[RADEON_MAX_CRTCS];
    wait_queue_head_t   vblank_queue;
	bool				hpd[RADEON_MAX_HPD_PINS];
	bool				afmt[RADEON_MAX_AFMT_BLOCKS];
	union radeon_irq_stat_regs stat_regs;
};
 
int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 
/*
 * CP & rings.
 */
 
struct radeon_ib {
	struct radeon_sa_bo		*sa_bo;
	uint32_t		length_dw;
    uint64_t            gpu_addr;
	uint32_t		*ptr;
	int				ring;
	struct radeon_fence	*fence;
	struct radeon_vm		*vm;
	bool			is_const_ib;
	struct radeon_fence		*sync_to[RADEON_NUM_RINGS];
	struct radeon_semaphore		*semaphore;
};
 
struct radeon_ring {
	struct radeon_bo	*ring_obj;
	volatile uint32_t	*ring;
    unsigned            rptr;
	unsigned		rptr_offs;
	unsigned		rptr_reg;
	unsigned		rptr_save_reg;
	u64			next_rptr_gpu_addr;
	volatile u32		*next_rptr_cpu_addr;
    unsigned            wptr;
    unsigned            wptr_old;
	unsigned		wptr_reg;
    unsigned            ring_size;
    unsigned            ring_free_dw;
    int                 count_dw;
	unsigned long		last_activity;
	unsigned		last_rptr;
    uint64_t            gpu_addr;
    uint32_t            align_mask;
    uint32_t            ptr_mask;
    bool                ready;
	u32			ptr_reg_shift;
	u32			ptr_reg_mask;
	u32			nop;
	u32			idx;
	u64			last_semaphore_signal_addr;
	u64			last_semaphore_wait_addr;
};
 
/*
 * VM
 */
 
/* maximum number of VMIDs */
#define RADEON_NUM_VM	16
 
/* defines number of bits in page table versus page directory,
 * a page is 4KB so we have 12 bits offset, 9 bits in the page
 * table and the remaining 19 bits are in the page directory */
#define RADEON_VM_BLOCK_SIZE   9
 
/* number of entries in page table */
#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
 
struct radeon_vm {
	struct list_head		list;
	struct list_head		va;
	unsigned			id;
 
	/* contains the page directory */
	struct radeon_sa_bo		*page_directory;
	uint64_t			pd_gpu_addr;
 
	/* array of page tables, one for each page directory entry */
	struct radeon_sa_bo		**page_tables;
 
	struct mutex			mutex;
	/* last fence for cs using this vm */
	struct radeon_fence		*fence;
	/* last flush or NULL if we still need to flush */
	struct radeon_fence		*last_flush;
};
 
struct radeon_vm_manager {
	struct mutex			lock;
	struct list_head		lru_vm;
	struct radeon_fence		*active[RADEON_NUM_VM];
	struct radeon_sa_manager	sa_manager;
	uint32_t			max_pfn;
	/* number of VMIDs */
	unsigned			nvm;
	/* vram base address for page table entry  */
	u64				vram_base_offset;
	/* is vm enabled? */
	bool				enabled;
};
 
/*
 * file private structure
 */
struct radeon_fpriv {
	struct radeon_vm		vm;
};
 
/*
 * R6xx+ IH ring
 */
struct r600_ih {
	struct radeon_bo	*ring_obj;
	volatile uint32_t	*ring;
    unsigned            rptr;
    unsigned            ring_size;
    uint64_t            gpu_addr;
    uint32_t            ptr_mask;
	atomic_t		lock;
    bool                enabled;
};
 
struct r600_blit_cp_primitives {
	void (*set_render_target)(struct radeon_device *rdev, int format,
				  int w, int h, u64 gpu_addr);
	void (*cp_set_surface_sync)(struct radeon_device *rdev,
				    u32 sync_type, u32 size,
				    u64 mc_addr);
	void (*set_shaders)(struct radeon_device *rdev);
	void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
	void (*set_tex_resource)(struct radeon_device *rdev,
				 int format, int w, int h, int pitch,
				 u64 gpu_addr, u32 size);
	void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
			     int x2, int y2);
	void (*draw_auto)(struct radeon_device *rdev);
	void (*set_default_state)(struct radeon_device *rdev);
};
 
struct r600_blit {
	struct radeon_bo	*shader_obj;
	struct r600_blit_cp_primitives primitives;
	int max_dim;
	int ring_size_common;
	int ring_size_per_loop;
	u64 shader_gpu_addr;
	u32 vs_offset, ps_offset;
	u32 state_offset;
	u32 state_len;
};
 
/*
 * SI RLC stuff
 */
struct si_rlc {
	/* for power gating */
	struct radeon_bo	*save_restore_obj;
	uint64_t		save_restore_gpu_addr;
	/* for clear state */
	struct radeon_bo	*clear_state_obj;
	uint64_t		clear_state_gpu_addr;
};
 
int radeon_ib_get(struct radeon_device *rdev, int ring,
		  struct radeon_ib *ib, struct radeon_vm *vm,
		  unsigned size);
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
		       struct radeon_ib *const_ib);
int radeon_ib_pool_init(struct radeon_device *rdev);
void radeon_ib_pool_fini(struct radeon_device *rdev);
int radeon_ib_ring_tests(struct radeon_device *rdev);
/* Ring access between begin & end cannot sleep */
bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
				      struct radeon_ring *ring);
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
void radeon_ring_undo(struct radeon_ring *ring);
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
void radeon_ring_lockup_update(struct radeon_ring *ring);
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
			    uint32_t **data);
int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
			unsigned size, uint32_t *data);
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
		     unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
		     u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 
 
/* r600 async dma */
void r600_dma_stop(struct radeon_device *rdev);
int r600_dma_resume(struct radeon_device *rdev);
void r600_dma_fini(struct radeon_device *rdev);
 
void cayman_dma_stop(struct radeon_device *rdev);
int cayman_dma_resume(struct radeon_device *rdev);
void cayman_dma_fini(struct radeon_device *rdev);
 
/*
 * CS.
 */
struct radeon_cs_reloc {
//	struct drm_gem_object		*gobj;
	struct radeon_bo		*robj;
	struct radeon_bo_list		lobj;
    uint32_t                handle;
    uint32_t                flags;
};
 
struct radeon_cs_chunk {
	uint32_t		chunk_id;
	uint32_t		length_dw;
	int kpage_idx[2];
	uint32_t                *kpage[2];
	uint32_t		*kdata;
	void __user *user_ptr;
	int last_copied_page;
	int last_page_index;
};
 
struct radeon_cs_parser {
	struct device		*dev;
	struct radeon_device	*rdev;
	struct drm_file		*filp;
	/* chunks */
	unsigned		nchunks;
	struct radeon_cs_chunk	*chunks;
	uint64_t		*chunks_array;
	/* IB */
	unsigned		idx;
	/* relocations */
	unsigned		nrelocs;
	struct radeon_cs_reloc	*relocs;
	struct radeon_cs_reloc	**relocs_ptr;
	struct list_head	validated;
	unsigned		dma_reloc_idx;
	/* indices of various chunks */
	int			chunk_ib_idx;
	int			chunk_relocs_idx;
	int			chunk_flags_idx;
	int			chunk_const_ib_idx;
	struct radeon_ib	ib;
	struct radeon_ib	const_ib;
	void			*track;
	unsigned		family;
	int parser_error;
	u32			cs_flags;
	u32			ring;
	s32			priority;
};
 
extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
 
struct radeon_cs_packet {
	unsigned	idx;
	unsigned	type;
	unsigned	reg;
	unsigned	opcode;
	int		count;
	unsigned	one_reg_wr;
};
 
typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt,
				      unsigned idx, unsigned reg);
typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt);
 
 
/*
 * AGP
 */
int radeon_agp_init(struct radeon_device *rdev);
void radeon_agp_resume(struct radeon_device *rdev);
void radeon_agp_suspend(struct radeon_device *rdev);
void radeon_agp_fini(struct radeon_device *rdev);
 
 
/*
 * Writeback
 */
struct radeon_wb {
	struct radeon_bo	*wb_obj;
	volatile uint32_t	*wb;
	uint64_t		gpu_addr;
	bool                    enabled;
	bool                    use_event;
};
 
#define RADEON_WB_SCRATCH_OFFSET 0
#define RADEON_WB_RING0_NEXT_RPTR 256
#define RADEON_WB_CP_RPTR_OFFSET 1024
#define RADEON_WB_CP1_RPTR_OFFSET 1280
#define RADEON_WB_CP2_RPTR_OFFSET 1536
#define R600_WB_DMA_RPTR_OFFSET   1792
#define R600_WB_IH_WPTR_OFFSET   2048
#define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
#define R600_WB_UVD_RPTR_OFFSET  2560
#define R600_WB_EVENT_OFFSET     3072
 
/**
 * struct radeon_pm - power management datas
 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)
 * @needed_bandwidth:   current bandwidth needs
 *
 * It keeps track of various data needed to take powermanagement decision.
 * Bandwidth need is used to determine minimun clock of the GPU and memory.
 * Equation between gpu/memory clock and available bandwidth is hw dependent
 * (type of memory, bus size, efficiency, ...)
 */
 
enum radeon_pm_method {
	PM_METHOD_PROFILE,
	PM_METHOD_DYNPM,
};
 
enum radeon_dynpm_state {
	DYNPM_STATE_DISABLED,
	DYNPM_STATE_MINIMUM,
	DYNPM_STATE_PAUSED,
	DYNPM_STATE_ACTIVE,
	DYNPM_STATE_SUSPENDED,
};
enum radeon_dynpm_action {
	DYNPM_ACTION_NONE,
	DYNPM_ACTION_MINIMUM,
	DYNPM_ACTION_DOWNCLOCK,
	DYNPM_ACTION_UPCLOCK,
	DYNPM_ACTION_DEFAULT
};
 
enum radeon_voltage_type {
	VOLTAGE_NONE = 0,
	VOLTAGE_GPIO,
	VOLTAGE_VDDC,
	VOLTAGE_SW
};
 
enum radeon_pm_state_type {
	POWER_STATE_TYPE_DEFAULT,
	POWER_STATE_TYPE_POWERSAVE,
	POWER_STATE_TYPE_BATTERY,
	POWER_STATE_TYPE_BALANCED,
	POWER_STATE_TYPE_PERFORMANCE,
};
 
enum radeon_pm_profile_type {
	PM_PROFILE_DEFAULT,
	PM_PROFILE_AUTO,
	PM_PROFILE_LOW,
	PM_PROFILE_MID,
	PM_PROFILE_HIGH,
};
 
#define PM_PROFILE_DEFAULT_IDX 0
#define PM_PROFILE_LOW_SH_IDX  1
#define PM_PROFILE_MID_SH_IDX  2
#define PM_PROFILE_HIGH_SH_IDX 3
#define PM_PROFILE_LOW_MH_IDX  4
#define PM_PROFILE_MID_MH_IDX  5
#define PM_PROFILE_HIGH_MH_IDX 6
#define PM_PROFILE_MAX         7
 
struct radeon_pm_profile {
	int dpms_off_ps_idx;
	int dpms_on_ps_idx;
	int dpms_off_cm_idx;
	int dpms_on_cm_idx;
};
 
enum radeon_int_thermal_type {
	THERMAL_TYPE_NONE,
	THERMAL_TYPE_RV6XX,
	THERMAL_TYPE_RV770,
	THERMAL_TYPE_EVERGREEN,
	THERMAL_TYPE_SUMO,
	THERMAL_TYPE_NI,
	THERMAL_TYPE_SI,
};
 
struct radeon_voltage {
	enum radeon_voltage_type type;
	/* gpio voltage */
	struct radeon_gpio_rec gpio;
	u32 delay; /* delay in usec from voltage drop to sclk change */
	bool active_high; /* voltage drop is active when bit is high */
	/* VDDC voltage */
	u8 vddc_id; /* index into vddc voltage table */
	u8 vddci_id; /* index into vddci voltage table */
	bool vddci_enabled;
	/* r6xx+ sw */
	u16 voltage;
	/* evergreen+ vddci */
	u16 vddci;
};
 
/* clock mode flags */
#define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 
struct radeon_pm_clock_info {
	/* memory clock */
	u32 mclk;
	/* engine clock */
	u32 sclk;
	/* voltage info */
	struct radeon_voltage voltage;
	/* standardized clock flags */
	u32 flags;
};
 
/* state flags */
#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
 
struct radeon_power_state {
	enum radeon_pm_state_type type;
	struct radeon_pm_clock_info *clock_info;
	/* number of valid clock modes in this power state */
	int num_clock_modes;
	struct radeon_pm_clock_info *default_clock_mode;
	/* standardized state flags */
	u32 flags;
	u32 misc; /* vbios specific flags */
	u32 misc2; /* vbios specific flags */
	int pcie_lanes; /* pcie lanes */
};
 
/*
 * Some modes are overclocked by very low value, accept them
 */
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 
struct radeon_pm {
	struct mutex		mutex;
	/* write locked while reprogramming mclk */
	struct rw_semaphore	mclk_lock;
	u32			active_crtcs;
	int			active_crtc_count;
	int			req_vblank;
	bool			vblank_sync;
	fixed20_12		max_bandwidth;
	fixed20_12		igp_sideport_mclk;
	fixed20_12		igp_system_mclk;
	fixed20_12		igp_ht_link_clk;
	fixed20_12		igp_ht_link_width;
	fixed20_12		k8_bandwidth;
	fixed20_12		sideport_bandwidth;
	fixed20_12		ht_bandwidth;
	fixed20_12		core_bandwidth;
	fixed20_12		sclk;
	fixed20_12		mclk;
	fixed20_12		needed_bandwidth;
	struct radeon_power_state *power_state;
	/* number of valid power states */
	int                     num_power_states;
	int                     current_power_state_index;
	int                     current_clock_mode_index;
	int                     requested_power_state_index;
	int                     requested_clock_mode_index;
	int                     default_power_state_index;
	u32                     current_sclk;
	u32                     current_mclk;
	u16                     current_vddc;
	u16                     current_vddci;
	u32                     default_sclk;
	u32                     default_mclk;
	u16                     default_vddc;
	u16                     default_vddci;
	struct radeon_i2c_chan *i2c_bus;
	/* selected pm method */
	enum radeon_pm_method     pm_method;
	/* dynpm power management */
//   struct delayed_work dynpm_idle_work;
	enum radeon_dynpm_state	dynpm_state;
	enum radeon_dynpm_action	dynpm_planned_action;
	unsigned long		dynpm_action_timeout;
	bool                    dynpm_can_upclock;
	bool                    dynpm_can_downclock;
	/* profile-based power management */
	enum radeon_pm_profile_type profile;
	int                     profile_index;
	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
	/* internal thermal controller on rv6xx+ */
	enum radeon_int_thermal_type int_thermal_type;
	struct device	        *int_hwmon_dev;
};
 
int radeon_pm_get_type_index(struct radeon_device *rdev,
			     enum radeon_pm_state_type ps_type,
			     int instance);
/*
 * UVD
 */
#define RADEON_MAX_UVD_HANDLES	10
#define RADEON_UVD_STACK_SIZE	(1024*1024)
#define RADEON_UVD_HEAP_SIZE	(1024*1024)
 
struct radeon_uvd {
	struct radeon_bo	*vcpu_bo;
	void			*cpu_addr;
	uint64_t		gpu_addr;
	atomic_t		handles[RADEON_MAX_UVD_HANDLES];
	struct drm_file		*filp[RADEON_MAX_UVD_HANDLES];
	struct delayed_work	idle_work;
};
 
int radeon_uvd_init(struct radeon_device *rdev);
void radeon_uvd_fini(struct radeon_device *rdev);
int radeon_uvd_suspend(struct radeon_device *rdev);
int radeon_uvd_resume(struct radeon_device *rdev);
int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
			      uint32_t handle, struct radeon_fence **fence);
int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
			       uint32_t handle, struct radeon_fence **fence);
void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
void radeon_uvd_free_handles(struct radeon_device *rdev,
			     struct drm_file *filp);
int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
void radeon_uvd_note_usage(struct radeon_device *rdev);
int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
				  unsigned vclk, unsigned dclk,
				  unsigned vco_min, unsigned vco_max,
				  unsigned fb_factor, unsigned fb_mask,
				  unsigned pd_min, unsigned pd_max,
				  unsigned pd_even,
				  unsigned *optimal_fb_div,
				  unsigned *optimal_vclk_div,
				  unsigned *optimal_dclk_div);
int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
                                unsigned cg_upll_func_cntl);
 
struct r600_audio {
	int			channels;
	int			rate;
	int			bits_per_sample;
	u8			status_bits;
	u8			category_code;
};
/*
 * ASIC specific functions.
 */
struct radeon_asic {
	int (*init)(struct radeon_device *rdev);
	void (*fini)(struct radeon_device *rdev);
	int (*resume)(struct radeon_device *rdev);
	int (*suspend)(struct radeon_device *rdev);
	void (*vga_set_state)(struct radeon_device *rdev, bool state);
	int (*asic_reset)(struct radeon_device *rdev);
	/* ioctl hw specific callback. Some hw might want to perform special
	 * operation on specific ioctl. For instance on wait idle some hw
	 * might want to perform and HDP flush through MMIO as it seems that
	 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
	 * through ring.
	 */
	void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
	/* check if 3D engine is idle */
	bool (*gui_idle)(struct radeon_device *rdev);
	/* wait for mc_idle */
	int (*mc_wait_for_idle)(struct radeon_device *rdev);
	/* get the reference clock */
	u32 (*get_xclk)(struct radeon_device *rdev);
	/* get the gpu clock counter */
	uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
	/* gart */
	struct {
		void (*tlb_flush)(struct radeon_device *rdev);
		int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
	} gart;
	struct {
		int (*init)(struct radeon_device *rdev);
		void (*fini)(struct radeon_device *rdev);
 
		u32 pt_ring_index;
		void (*set_page)(struct radeon_device *rdev,
				 struct radeon_ib *ib,
				 uint64_t pe,
				 uint64_t addr, unsigned count,
				 uint32_t incr, uint32_t flags);
	} vm;
	/* ring specific callbacks */
	struct {
		void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
		int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
		void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
		void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
				       struct radeon_semaphore *semaphore, bool emit_wait);
		int (*cs_parse)(struct radeon_cs_parser *p);
		void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
		int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
		int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
		bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
		void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
	} ring[RADEON_NUM_RINGS];
	/* irqs */
	struct {
		int (*set)(struct radeon_device *rdev);
		int (*process)(struct radeon_device *rdev);
	} irq;
	/* displays */
	struct {
		/* display watermarks */
		void (*bandwidth_update)(struct radeon_device *rdev);
		/* get frame count */
	u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
		/* wait for vblank */
		void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
		/* set backlight level */
		void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
		/* get backlight level */
		u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
		/* audio callbacks */
		void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
		void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
	} display;
	/* copy functions for bo handling */
	struct {
		int (*blit)(struct radeon_device *rdev,
			 uint64_t src_offset,
			 uint64_t dst_offset,
			 unsigned num_gpu_pages,
			    struct radeon_fence **fence);
		u32 blit_ring_index;
		int (*dma)(struct radeon_device *rdev,
			uint64_t src_offset,
			uint64_t dst_offset,
			unsigned num_gpu_pages,
			   struct radeon_fence **fence);
		u32 dma_ring_index;
		/* method used for bo copy */
	int (*copy)(struct radeon_device *rdev,
		    uint64_t src_offset,
		    uint64_t dst_offset,
		    unsigned num_gpu_pages,
			    struct radeon_fence **fence);
		/* ring used for bo copies */
		u32 copy_ring_index;
	} copy;
	/* surfaces */
	struct {
		int (*set_reg)(struct radeon_device *rdev, int reg,
				       uint32_t tiling_flags, uint32_t pitch,
				       uint32_t offset, uint32_t obj_size);
		void (*clear_reg)(struct radeon_device *rdev, int reg);
	} surface;
	/* hotplug detect */
	struct {
		void (*init)(struct radeon_device *rdev);
		void (*fini)(struct radeon_device *rdev);
		bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
		void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	} hpd;
	/* power management */
	struct {
		void (*misc)(struct radeon_device *rdev);
		void (*prepare)(struct radeon_device *rdev);
		void (*finish)(struct radeon_device *rdev);
		void (*init_profile)(struct radeon_device *rdev);
		void (*get_dynpm_state)(struct radeon_device *rdev);
	uint32_t (*get_engine_clock)(struct radeon_device *rdev);
	void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
	uint32_t (*get_memory_clock)(struct radeon_device *rdev);
	void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
	int (*get_pcie_lanes)(struct radeon_device *rdev);
	void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
	void (*set_clock_gating)(struct radeon_device *rdev, int enable);
		int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
	} pm;
	/* pageflipping */
	struct {
	void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
	u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
	void (*post_page_flip)(struct radeon_device *rdev, int crtc);
	} pflip;
};
 
/*
 * Asic structures
 */
struct r100_asic {
	const unsigned	*reg_safe_bm;
	unsigned	reg_safe_bm_size;
	u32		hdp_cntl;
};
 
struct r300_asic {
	const unsigned	*reg_safe_bm;
	unsigned	reg_safe_bm_size;
	u32		resync_scratch;
	u32		hdp_cntl;
};
 
struct r600_asic {
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
	unsigned		tile_config;
	unsigned		backend_map;
};
 
struct rv770_asic {
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned sx_num_of_sets;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_fize;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
	unsigned		tile_config;
	unsigned		backend_map;
};
 
struct evergreen_asic {
	unsigned num_ses;
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned sx_num_of_sets;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
	unsigned tile_config;
	unsigned backend_map;
};
 
struct cayman_asic {
	unsigned max_shader_engines;
	unsigned max_pipes_per_simd;
	unsigned max_tile_pipes;
	unsigned max_simds_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_gs_threads;
	unsigned max_stack_entries;
	unsigned sx_num_of_sets;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned max_hw_contexts;
	unsigned sq_num_cf_insts;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;
 
	unsigned num_shader_engines;
	unsigned num_shader_pipes_per_simd;
	unsigned num_tile_pipes;
	unsigned num_simds_per_se;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;
 
	unsigned tile_config;
};
 
struct si_asic {
	unsigned max_shader_engines;
	unsigned max_tile_pipes;
	unsigned max_cu_per_sh;
	unsigned max_sh_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_gs_threads;
	unsigned max_hw_contexts;
	unsigned sc_prim_fifo_size_frontend;
	unsigned sc_prim_fifo_size_backend;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;
 
	unsigned num_tile_pipes;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;
 
	unsigned tile_config;
	uint32_t tile_mode_array[32];
};
 
union radeon_asic_config {
	struct r300_asic	r300;
	struct r100_asic	r100;
	struct r600_asic	r600;
	struct rv770_asic	rv770;
	struct evergreen_asic	evergreen;
	struct cayman_asic	cayman;
	struct si_asic		si;
};
 
/*
 * asic initizalization from radeon_asic.c
 */
void radeon_agp_disable(struct radeon_device *rdev);
int radeon_asic_init(struct radeon_device *rdev);
 
 
 
/* VRAM scratch page for HDP bug, default vram page */
struct r600_vram_scratch {
	struct radeon_bo		*robj;
	volatile uint32_t		*ptr;
	u64				gpu_addr;
};
 
 
/*
 * Core structure, functions and helpers.
 */
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 
struct radeon_device {
    struct device              *dev;
    struct drm_device          *ddev;
    struct pci_dev             *pdev;
	struct rw_semaphore		exclusive_lock;
    /* ASIC */
    union radeon_asic_config    config;
    enum radeon_family          family;
    unsigned long               flags;
    int                         usec_timeout;
    enum radeon_pll_errata      pll_errata;
    int                         num_gb_pipes;
	int				            num_z_pipes;
    int                         disp_priority;
    /* BIOS */
    uint8_t                     *bios;
    bool                        is_atom_bios;
    uint16_t                    bios_header_start;
	struct radeon_bo		    *stollen_vga_memory;
    /* Register mmio */
	resource_size_t			rmmio_base;
	resource_size_t			rmmio_size;
	/* protects concurrent MM_INDEX/DATA based register access */
	spinlock_t mmio_idx_lock;
	void __iomem			*rmmio;
    radeon_rreg_t               mc_rreg;
    radeon_wreg_t               mc_wreg;
    radeon_rreg_t               pll_rreg;
    radeon_wreg_t               pll_wreg;
	uint32_t                        pcie_reg_mask;
    radeon_rreg_t               pciep_rreg;
    radeon_wreg_t               pciep_wreg;
	/* io port */
	void __iomem                    *rio_mem;
	resource_size_t			rio_mem_size;
    struct radeon_clock         clock;
    struct radeon_mc            mc;
    struct radeon_gart          gart;
	struct radeon_mode_info		mode_info;
    struct radeon_scratch       scratch;
    struct radeon_mman          mman;
	struct radeon_fence_driver	fence_drv[RADEON_NUM_RINGS];
	wait_queue_head_t		fence_queue;
	struct mutex			ring_lock;
	struct radeon_ring		ring[RADEON_NUM_RINGS];
	bool				ib_pool_ready;
	struct radeon_sa_manager	ring_tmp_bo;
    struct radeon_irq       irq;
    struct radeon_asic         *asic;
    struct radeon_gem       gem;
	struct radeon_pm		pm;
	struct radeon_uvd		uvd;
	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
    struct radeon_wb        wb;
	struct radeon_dummy_page	dummy_page;
    bool                shutdown;
    bool                suspend;
	bool				need_dma32;
	bool				accel_working;
	bool				fastfb_working; /* IGP feature*/
	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
	const struct firmware *me_fw;	/* all family ME firmware */
	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
	const struct firmware *mc_fw;	/* NI MC firmware */
	const struct firmware *ce_fw;	/* SI CE firmware */
	const struct firmware *uvd_fw;	/* UVD firmware */
	struct r600_blit r600_blit;
	struct r600_vram_scratch vram_scratch;
	int msi_enabled; /* msi enabled */
	struct r600_ih ih; /* r6/700 interrupt ring */
	struct si_rlc rlc;
//	struct work_struct hotplug_work;
//	struct work_struct audio_work;
	int num_crtc; /* number of crtcs */
	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
	bool			audio_enabled;
	bool has_uvd;
//   struct r600_audio audio_status; /* audio stuff */
//   struct notifier_block acpi_nb;
	/* only one userspace can use Hyperz features or CMASK at a time */
//	struct drm_file *hyperz_filp;
//	struct drm_file *cmask_filp;
	/* i2c buses */
	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
	/* debugfs */
//	struct radeon_debugfs	debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
	unsigned 		debugfs_count;
	/* virtual memory */
	struct radeon_vm_manager	vm_manager;
	struct mutex			gpu_clock_mutex;
	/* ACPI interface */
//	struct radeon_atif		atif;
//	struct radeon_atcs		atcs;
};
 
int radeon_device_init(struct radeon_device *rdev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags);
void radeon_device_fini(struct radeon_device *rdev);
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		      bool always_indirect);
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		  bool always_indirect);
u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 
/*
 * Cast helper
 */
#define to_radeon_fence(p) ((struct radeon_fence *)(p))
 
/*
 * Registers read & write functions.
 */
#define RREG8(reg) readb((rdev->rmmio) + (reg))
#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
#define RREG16(reg) readw((rdev->rmmio) + (reg))
#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
#define WREG32_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32(reg);			\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32(reg, tmp_);				\
	} while (0)
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
#define WREG32_PLL_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32_PLL(reg);		\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32_PLL(reg, tmp_);				\
	} while (0)
#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
 
/*
 * Indirect registers accessor
 */
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;
 
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	r = RREG32(RADEON_PCIE_DATA);
	return r;
}
 
static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	WREG32(RADEON_PCIE_DATA, (v));
}
 
void r100_pll_errata_after_index(struct radeon_device *rdev);
 
 
/*
 * ASICs helpers.
 */
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
			    (rdev->pdev->device == 0x5969))
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
        (rdev->family == CHIP_RV200) || \
        (rdev->family == CHIP_RS100) || \
        (rdev->family == CHIP_RS200) || \
        (rdev->family == CHIP_RV250) || \
        (rdev->family == CHIP_RV280) || \
        (rdev->family == CHIP_RS300))
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
        (rdev->family == CHIP_RV350) ||         \
        (rdev->family == CHIP_R350)  ||         \
        (rdev->family == CHIP_RV380) ||         \
        (rdev->family == CHIP_R420)  ||         \
        (rdev->family == CHIP_R423)  ||         \
        (rdev->family == CHIP_RV410) ||         \
        (rdev->family == CHIP_RS400) ||         \
        (rdev->family == CHIP_RS480))
#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
		(rdev->ddev->pdev->device == 0x9443) || \
		(rdev->ddev->pdev->device == 0x944B) || \
		(rdev->ddev->pdev->device == 0x9506) || \
		(rdev->ddev->pdev->device == 0x9509) || \
		(rdev->ddev->pdev->device == 0x950F) || \
		(rdev->ddev->pdev->device == 0x689C) || \
		(rdev->ddev->pdev->device == 0x689D))
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
			    (rdev->family == CHIP_RS690)  ||	\
			    (rdev->family == CHIP_RS740)  ||	\
			    (rdev->family >= CHIP_R600))
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
			     (rdev->flags & RADEON_IS_IGP))
#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
			     (rdev->flags & RADEON_IS_IGP))
#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
 
/*
 * BIOS helpers.
 */
#define RBIOS8(i) (rdev->bios[i])
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 
int radeon_combios_init(struct radeon_device *rdev);
void radeon_combios_fini(struct radeon_device *rdev);
int radeon_atombios_init(struct radeon_device *rdev);
void radeon_atombios_fini(struct radeon_device *rdev);
 
 
/*
 * RING helpers.
 */
#if DRM_DEBUG_CODE == 0
static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
{
	ring->ring[ring->wptr++] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
	ring->ring_free_dw--;
}
#else
/* With debugging this is just too big to inline */
void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
#endif
 
/*
 * ASICs macro.
 */
#define radeon_init(rdev) (rdev)->asic->init((rdev))
#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
 
/* Common functions */
/* AGP */
extern int radeon_gpu_reset(struct radeon_device *rdev);
extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
extern void radeon_agp_disable(struct radeon_device *rdev);
extern int radeon_modeset_init(struct radeon_device *rdev);
extern void radeon_modeset_fini(struct radeon_device *rdev);
extern bool radeon_card_posted(struct radeon_device *rdev);
extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
extern void radeon_update_display_priority(struct radeon_device *rdev);
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
extern void radeon_scratch_init(struct radeon_device *rdev);
extern void radeon_wb_fini(struct radeon_device *rdev);
extern int radeon_wb_init(struct radeon_device *rdev);
extern void radeon_wb_disable(struct radeon_device *rdev);
extern void radeon_surface_init(struct radeon_device *rdev);
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
extern int radeon_resume_kms(struct drm_device *dev);
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
extern void radeon_program_register_sequence(struct radeon_device *rdev,
					     const u32 *registers,
					     const u32 array_size);
 
/*
 * vm
 */
int radeon_vm_manager_init(struct radeon_device *rdev);
void radeon_vm_manager_fini(struct radeon_device *rdev);
void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
				       struct radeon_vm *vm, int ring);
void radeon_vm_fence(struct radeon_device *rdev,
		     struct radeon_vm *vm,
		     struct radeon_fence *fence);
uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
int radeon_vm_bo_update_pte(struct radeon_device *rdev,
			    struct radeon_vm *vm,
			    struct radeon_bo *bo,
			    struct ttm_mem_reg *mem);
void radeon_vm_bo_invalidate(struct radeon_device *rdev,
			     struct radeon_bo *bo);
struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
				       struct radeon_bo *bo);
struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
				      struct radeon_vm *vm,
				      struct radeon_bo *bo);
int radeon_vm_bo_set_addr(struct radeon_device *rdev,
			  struct radeon_bo_va *bo_va,
			  uint64_t offset,
			  uint32_t flags);
int radeon_vm_bo_rmv(struct radeon_device *rdev,
		     struct radeon_bo_va *bo_va);
 
/* audio */
void r600_audio_update_hdmi(struct work_struct *work);
 
/*
 * R600 vram scratch functions
 */
int r600_vram_scratch_init(struct radeon_device *rdev);
void r600_vram_scratch_fini(struct radeon_device *rdev);
 
/*
 * r600 cs checking helper
 */
unsigned r600_mip_minify(unsigned size, unsigned level);
bool r600_fmt_is_valid_color(u32 format);
bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
int r600_fmt_get_blocksize(u32 format);
int r600_fmt_get_nblocksx(u32 format, u32 w);
int r600_fmt_get_nblocksy(u32 format, u32 h);
 
/*
 * r600 functions used by radeon_encoder.c
 */
struct radeon_hdmi_acr {
	u32 clock;
 
	int n_32khz;
	int cts_32khz;
 
	int n_44_1khz;
	int cts_44_1khz;
 
	int n_48khz;
	int cts_48khz;
 
};
 
extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
 
 
 
 
extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
				     u32 tiling_pipe_num,
				     u32 max_rb_num,
				     u32 total_max_rb_num,
				     u32 enabled_rb_mask);
 
/*
 * evergreen functions used by radeon_encoder.c
 */
 
 
 
extern int ni_init_microcode(struct radeon_device *rdev);
extern int ni_mc_load_microcode(struct radeon_device *rdev);
 
/* radeon_acpi.c */
#if defined(CONFIG_ACPI)
extern int radeon_acpi_init(struct radeon_device *rdev);
extern void radeon_acpi_fini(struct radeon_device *rdev);
#else
static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
#endif
 
#include "radeon_object.h"
 
#define DRM_UDELAY(d)           udelay(d)
 
resource_size_t
drm_get_resource_start(struct drm_device *dev, unsigned int resource);
resource_size_t
drm_get_resource_len(struct drm_device *dev, unsigned int resource);
 
bool set_mode(struct drm_device *dev, struct drm_connector *connector,
              videomode_t *mode, bool strict);
 
 
#ifndef __TTM__
#define radeon_ttm_set_active_vram_size(a, b)
#endif
 
#endif

Rev 3192	Rev 3764
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#ifndef __RADEON_H__	28	#ifndef __RADEON_H__
29	#define __RADEON_H__	29	#define __RADEON_H__
30		30
31	/* TODO: Here are things that needs to be done :	31	/* TODO: Here are things that needs to be done :
32	* - surface allocator & initializer : (bit like scratch reg) should	32	* - surface allocator & initializer : (bit like scratch reg) should
33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings	33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34	* related to surface	34	* related to surface
35	* - WB : write back stuff (do it bit like scratch reg things)	35	* - WB : write back stuff (do it bit like scratch reg things)
36	* - Vblank : look at Jesse's rework and what we should do	36	* - Vblank : look at Jesse's rework and what we should do
37	* - r600/r700: gart & cp	37	* - r600/r700: gart & cp
38	* - cs : clean cs ioctl use bitmap & things like that.	38	* - cs : clean cs ioctl use bitmap & things like that.
39	* - power management stuff	39	* - power management stuff
40	* - Barrier in gart code	40	* - Barrier in gart code
41	* - Unmappabled vram ?	41	* - Unmappabled vram ?
42	* - TESTING, TESTING, TESTING	42	* - TESTING, TESTING, TESTING
43	*/	43	*/
44		44
45	/* Initialization path:	45	/* Initialization path:
46	* We expect that acceleration initialization might fail for various	46	* We expect that acceleration initialization might fail for various
47	* reasons even thought we work hard to make it works on most	47	* reasons even thought we work hard to make it works on most
48	* configurations. In order to still have a working userspace in such	48	* configurations. In order to still have a working userspace in such
49	* situation the init path must succeed up to the memory controller	49	* situation the init path must succeed up to the memory controller
50	* initialization point. Failure before this point are considered as	50	* initialization point. Failure before this point are considered as
51	* fatal error. Here is the init callchain :	51	* fatal error. Here is the init callchain :
52	* radeon_device_init perform common structure, mutex initialization	52	* radeon_device_init perform common structure, mutex initialization
53	* asic_init setup the GPU memory layout and perform all	53	* asic_init setup the GPU memory layout and perform all
54	* one time initialization (failure in this	54	* one time initialization (failure in this
55	* function are considered fatal)	55	* function are considered fatal)
56	* asic_startup setup the GPU acceleration, in order to	56	* asic_startup setup the GPU acceleration, in order to
57	* follow guideline the first thing this	57	* follow guideline the first thing this
58	* function should do is setting the GPU	58	* function should do is setting the GPU
59	* memory controller (only MC setup failure	59	* memory controller (only MC setup failure
60	* are considered as fatal)	60	* are considered as fatal)
61	*/	61	*/
62		62
63	#include	63	#include
64	#include	64	#include
65	#include	65	#include
66	#include	66	#include
67	#include	67	#include
68		68
69	#include	69	#include
70	#include	70	#include
71	#include	71	#include
72	#include	72	#include
73		73
74	#include	74	#include
75	#include	75	#include
76		76
77	#include	77	#include
78		78
79	#include "radeon_family.h"	79	#include "radeon_family.h"
80	#include "radeon_mode.h"	80	#include "radeon_mode.h"
81	#include "radeon_reg.h"	81	#include "radeon_reg.h"
82		82
83	#include	83	#include
84		84
85	/*	85	/*
86	* Modules parameters.	86	* Modules parameters.
87	*/	87	*/
88	extern int radeon_no_wb;	88	extern int radeon_no_wb;
89	extern int radeon_modeset;	89	extern int radeon_modeset;
90	extern int radeon_dynclks;	90	extern int radeon_dynclks;
91	extern int radeon_r4xx_atom;	91	extern int radeon_r4xx_atom;
92	extern int radeon_agpmode;	92	extern int radeon_agpmode;
93	extern int radeon_vram_limit;	93	extern int radeon_vram_limit;
94	extern int radeon_gart_size;	94	extern int radeon_gart_size;
95	extern int radeon_benchmarking;	95	extern int radeon_benchmarking;
96	extern int radeon_testing;	96	extern int radeon_testing;
97	extern int radeon_connector_table;	97	extern int radeon_connector_table;
98	extern int radeon_tv;	98	extern int radeon_tv;
99	extern int radeon_audio;	99	extern int radeon_audio;
100	extern int radeon_disp_priority;	100	extern int radeon_disp_priority;
101	extern int radeon_hw_i2c;	101	extern int radeon_hw_i2c;
102	extern int radeon_pcie_gen2;	102	extern int radeon_pcie_gen2;
103	extern int radeon_msi;	103	extern int radeon_msi;
104	extern int radeon_lockup_timeout;	104	extern int radeon_lockup_timeout;
105		-
-		105	extern int radeon_fastfb;
106		106
107		107
108	typedef struct pm_message {	108	typedef struct pm_message {
109	int event;	109	int event;
110	} pm_message_t;	110	} pm_message_t;
111		111
112	typedef struct	112	typedef struct
113	{	113	{
114	int width;	114	int width;
115	int height;	115	int height;
116	int bpp;	116	int bpp;
117	int freq;	117	int freq;
118	}videomode_t;	118	}videomode_t;
119		119
120		120
121		121
122	static inline u32 ioread32(const volatile void __iomem *addr)	122	static inline u32 ioread32(const volatile void __iomem *addr)
123	{	123	{
124	return in32((u32)addr);	124	return in32((u32)addr);
125	}	125	}
126		126
127	static inline void iowrite32(uint32_t b, volatile void __iomem *addr)	127	//static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
128	{	128	//{
129	out32((u32)addr, b);	129	// out32((u32)addr, b);
130	}	130	//}
131		131
132		132
133	/*	133	/*
134	* Copy from radeon_drv.h so we don't have to include both and have conflicting	134	* Copy from radeon_drv.h so we don't have to include both and have conflicting
135	* symbol;	135	* symbol;
136	*/	136	*/
137	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */	137	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
138	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)	138	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
139	/* RADEON_IB_POOL_SIZE must be a power of 2 */	139	/* RADEON_IB_POOL_SIZE must be a power of 2 */
140	#define RADEON_IB_POOL_SIZE 16	140	#define RADEON_IB_POOL_SIZE 16
141	#define RADEON_DEBUGFS_MAX_COMPONENTS 32	141	#define RADEON_DEBUGFS_MAX_COMPONENTS 32
142	#define RADEONFB_CONN_LIMIT 4	142	#define RADEONFB_CONN_LIMIT 4
143	#define RADEON_BIOS_NUM_SCRATCH 8	143	#define RADEON_BIOS_NUM_SCRATCH 8
144		144
145	/* max number of rings */	145	/* max number of rings */
146	#define RADEON_NUM_RINGS 5	146	#define RADEON_NUM_RINGS 6
147		147
148	/* fence seq are set to this number when signaled */	148	/* fence seq are set to this number when signaled */
149	#define RADEON_FENCE_SIGNALED_SEQ 0LL	149	#define RADEON_FENCE_SIGNALED_SEQ 0LL
150		150
151	/* internal ring indices */	151	/* internal ring indices */
152	/* r1xx+ has gfx CP ring */	152	/* r1xx+ has gfx CP ring */
153	#define RADEON_RING_TYPE_GFX_INDEX 0	153	#define RADEON_RING_TYPE_GFX_INDEX 0
154		154
155	/* cayman has 2 compute CP rings */	155	/* cayman has 2 compute CP rings */
156	#define CAYMAN_RING_TYPE_CP1_INDEX 1	156	#define CAYMAN_RING_TYPE_CP1_INDEX 1
157	#define CAYMAN_RING_TYPE_CP2_INDEX 2	157	#define CAYMAN_RING_TYPE_CP2_INDEX 2
158		158
159	/* R600+ has an async dma ring */	159	/* R600+ has an async dma ring */
160	#define R600_RING_TYPE_DMA_INDEX 3	160	#define R600_RING_TYPE_DMA_INDEX 3
161	/* cayman add a second async dma ring */	161	/* cayman add a second async dma ring */
162	#define CAYMAN_RING_TYPE_DMA1_INDEX 4	162	#define CAYMAN_RING_TYPE_DMA1_INDEX 4
-		163
-		164	/* R600+ */
-		165	#define R600_RING_TYPE_UVD_INDEX 5
163		166
164	/* hardcode those limit for now */	167	/* hardcode those limit for now */
165	#define RADEON_VA_IB_OFFSET (1 << 20)	168	#define RADEON_VA_IB_OFFSET (1 << 20)
166	#define RADEON_VA_RESERVED_SIZE (8 << 20)	169	#define RADEON_VA_RESERVED_SIZE (8 << 20)
167	#define RADEON_IB_VM_MAX_SIZE (64 << 10)	170	#define RADEON_IB_VM_MAX_SIZE (64 << 10)
168		171
169	/* reset flags */	172	/* reset flags */
170	#define RADEON_RESET_GFX (1 << 0)	173	#define RADEON_RESET_GFX (1 << 0)
171	#define RADEON_RESET_COMPUTE (1 << 1)	174	#define RADEON_RESET_COMPUTE (1 << 1)
172	#define RADEON_RESET_DMA (1 << 2)	175	#define RADEON_RESET_DMA (1 << 2)
-		176	#define RADEON_RESET_CP (1 << 3)
-		177	#define RADEON_RESET_GRBM (1 << 4)
-		178	#define RADEON_RESET_DMA1 (1 << 5)
-		179	#define RADEON_RESET_RLC (1 << 6)
-		180	#define RADEON_RESET_SEM (1 << 7)
-		181	#define RADEON_RESET_IH (1 << 8)
-		182	#define RADEON_RESET_VMC (1 << 9)
-		183	#define RADEON_RESET_MC (1 << 10)
-		184	#define RADEON_RESET_DISPLAY (1 << 11)
173		185
174	/*	186	/*
175	* Errata workarounds.	187	* Errata workarounds.
176	*/	188	*/
177	enum radeon_pll_errata {	189	enum radeon_pll_errata {
178	CHIP_ERRATA_R300_CG = 0x00000001,	190	CHIP_ERRATA_R300_CG = 0x00000001,
179	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,	191	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
180	CHIP_ERRATA_PLL_DELAY = 0x00000004	192	CHIP_ERRATA_PLL_DELAY = 0x00000004
181	};	193	};
182		194
183		195
184	struct radeon_device;	196	struct radeon_device;
185		197
186		198
187	/*	199	/*
188	* BIOS.	200	* BIOS.
189	*/	201	*/
190	bool radeon_get_bios(struct radeon_device *rdev);	202	bool radeon_get_bios(struct radeon_device *rdev);
191		203
192	/*	204	/*
193	* Dummy page	205	* Dummy page
194	*/	206	*/
195	struct radeon_dummy_page {	207	struct radeon_dummy_page {
196	struct page *page;	208	struct page *page;
197	dma_addr_t addr;	209	dma_addr_t addr;
198	};	210	};
199	int radeon_dummy_page_init(struct radeon_device *rdev);	211	int radeon_dummy_page_init(struct radeon_device *rdev);
200	void radeon_dummy_page_fini(struct radeon_device *rdev);	212	void radeon_dummy_page_fini(struct radeon_device *rdev);
201		213
202		214
203	/*	215	/*
204	* Clocks	216	* Clocks
205	*/	217	*/
206	struct radeon_clock {	218	struct radeon_clock {
207	struct radeon_pll p1pll;	219	struct radeon_pll p1pll;
208	struct radeon_pll p2pll;	220	struct radeon_pll p2pll;
209	struct radeon_pll dcpll;	221	struct radeon_pll dcpll;
210	struct radeon_pll spll;	222	struct radeon_pll spll;
211	struct radeon_pll mpll;	223	struct radeon_pll mpll;
212	/* 10 Khz units */	224	/* 10 Khz units */
213	uint32_t default_mclk;	225	uint32_t default_mclk;
214	uint32_t default_sclk;	226	uint32_t default_sclk;
215	uint32_t default_dispclk;	227	uint32_t default_dispclk;
216	uint32_t dp_extclk;	228	uint32_t dp_extclk;
217	uint32_t max_pixel_clock;	229	uint32_t max_pixel_clock;
218	};	230	};
219		231
220	/*	232	/*
221	* Power management	233	* Power management
222	*/	234	*/
223	int radeon_pm_init(struct radeon_device *rdev);	235	int radeon_pm_init(struct radeon_device *rdev);
224	void radeon_pm_fini(struct radeon_device *rdev);	236	void radeon_pm_fini(struct radeon_device *rdev);
225	void radeon_pm_compute_clocks(struct radeon_device *rdev);	237	void radeon_pm_compute_clocks(struct radeon_device *rdev);
226	void radeon_pm_suspend(struct radeon_device *rdev);	238	void radeon_pm_suspend(struct radeon_device *rdev);
227	void radeon_pm_resume(struct radeon_device *rdev);	239	void radeon_pm_resume(struct radeon_device *rdev);
228	void radeon_combios_get_power_modes(struct radeon_device *rdev);	240	void radeon_combios_get_power_modes(struct radeon_device *rdev);
229	void radeon_atombios_get_power_modes(struct radeon_device *rdev);	241	void radeon_atombios_get_power_modes(struct radeon_device *rdev);
-		242	int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
-		243	u8 clock_type,
-		244	u32 clock,
-		245	bool strobe_mode,
-		246	struct atom_clock_dividers *dividers);
230	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);	247	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
231	void rs690_pm_info(struct radeon_device *rdev);	248	void rs690_pm_info(struct radeon_device *rdev);
232	extern int rv6xx_get_temp(struct radeon_device *rdev);	249	extern int rv6xx_get_temp(struct radeon_device *rdev);
233	extern int rv770_get_temp(struct radeon_device *rdev);	250	extern int rv770_get_temp(struct radeon_device *rdev);
234	extern int evergreen_get_temp(struct radeon_device *rdev);	251	extern int evergreen_get_temp(struct radeon_device *rdev);
235	extern int sumo_get_temp(struct radeon_device *rdev);	252	extern int sumo_get_temp(struct radeon_device *rdev);
236	extern int si_get_temp(struct radeon_device *rdev);	253	extern int si_get_temp(struct radeon_device *rdev);
237	extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,	254	extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
238	unsigned bankh, unsigned mtaspect,	255	unsigned bankh, unsigned mtaspect,
239	unsigned *tile_split);	256	unsigned *tile_split);
240		257
241	/*	258	/*
242	* Fences.	259	* Fences.
243	*/	260	*/
244	struct radeon_fence_driver {	261	struct radeon_fence_driver {
245	uint32_t scratch_reg;	262	uint32_t scratch_reg;
246	uint64_t gpu_addr;	263	uint64_t gpu_addr;
247	volatile uint32_t *cpu_addr;	264	volatile uint32_t *cpu_addr;
248	/* sync_seq is protected by ring emission lock */	265	/* sync_seq is protected by ring emission lock */
249	uint64_t sync_seq[RADEON_NUM_RINGS];	266	uint64_t sync_seq[RADEON_NUM_RINGS];
250	atomic64_t last_seq;	267	atomic64_t last_seq;
251	unsigned long last_activity;	268	unsigned long last_activity;
252	bool initialized;	269	bool initialized;
253	};	270	};
254		271
255	struct radeon_fence {	272	struct radeon_fence {
256	struct radeon_device *rdev;	273	struct radeon_device *rdev;
257	struct kref kref;	274	struct kref kref;
258	/* protected by radeon_fence.lock */	275	/* protected by radeon_fence.lock */
259	uint64_t seq;	276	uint64_t seq;
260	/* RB, DMA, etc. */	277	/* RB, DMA, etc. */
261	unsigned ring;	278	unsigned ring;
262	};	279	};
263		280
264	int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);	281	int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
265	int radeon_fence_driver_init(struct radeon_device *rdev);	282	int radeon_fence_driver_init(struct radeon_device *rdev);
266	void radeon_fence_driver_fini(struct radeon_device *rdev);	283	void radeon_fence_driver_fini(struct radeon_device *rdev);
267	void radeon_fence_driver_force_completion(struct radeon_device *rdev);	284	void radeon_fence_driver_force_completion(struct radeon_device *rdev);
268	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence *fence, int ring);	285	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence *fence, int ring);
269	void radeon_fence_process(struct radeon_device *rdev, int ring);	286	void radeon_fence_process(struct radeon_device *rdev, int ring);
270	bool radeon_fence_signaled(struct radeon_fence *fence);	287	bool radeon_fence_signaled(struct radeon_fence *fence);
271	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);	288	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
272	int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);	289	int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
273	int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);	290	int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
274	int radeon_fence_wait_any(struct radeon_device *rdev,	291	int radeon_fence_wait_any(struct radeon_device *rdev,
275	struct radeon_fence **fences,	292	struct radeon_fence **fences,
276	bool intr);	293	bool intr);
277	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);	294	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
278	void radeon_fence_unref(struct radeon_fence **fence);	295	void radeon_fence_unref(struct radeon_fence **fence);
279	unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);	296	unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
280	bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);	297	bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
281	void radeon_fence_note_sync(struct radeon_fence *fence, int ring);	298	void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
282	static inline struct radeon_fence radeon_fence_later(struct radeon_fence a,	299	static inline struct radeon_fence radeon_fence_later(struct radeon_fence a,
283	struct radeon_fence *b)	300	struct radeon_fence *b)
284	{	301	{
285	if (!a) {	302	if (!a) {
286	return b;	303	return b;
287	}	304	}
288		305
289	if (!b) {	306	if (!b) {
290	return a;	307	return a;
291	}	308	}
292		309
293	BUG_ON(a->ring != b->ring);	310	BUG_ON(a->ring != b->ring);
294		311
295	if (a->seq > b->seq) {	312	if (a->seq > b->seq) {
296	return a;	313	return a;
297	} else {	314	} else {
298	return b;	315	return b;
299	}	316	}
300	}	317	}
301		318
302	static inline bool radeon_fence_is_earlier(struct radeon_fence *a,	319	static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
303	struct radeon_fence *b)	320	struct radeon_fence *b)
304	{	321	{
305	if (!a) {	322	if (!a) {
306	return false;	323	return false;
307	}	324	}
308		325
309	if (!b) {	326	if (!b) {
310	return true;	327	return true;
311	}	328	}
312		329
313	BUG_ON(a->ring != b->ring);	330	BUG_ON(a->ring != b->ring);
314		331
315	return a->seq < b->seq;	332	return a->seq < b->seq;
316	}	333	}
317		334
318	/*	335	/*
319	* Tiling registers	336	* Tiling registers
320	*/	337	*/
321	struct radeon_surface_reg {	338	struct radeon_surface_reg {
322	struct radeon_bo *bo;	339	struct radeon_bo *bo;
323	};	340	};
324		341
325	#define RADEON_GEM_MAX_SURFACES 8	342	#define RADEON_GEM_MAX_SURFACES 8
326		343
327	/*	344	/*
328	* TTM.	345	* TTM.
329	*/	346	*/
330	struct radeon_mman {	347	struct radeon_mman {
331	struct ttm_bo_global_ref bo_global_ref;	348	struct ttm_bo_global_ref bo_global_ref;
332	// struct drm_global_reference mem_global_ref;	349	struct drm_global_reference mem_global_ref;
333	struct ttm_bo_device bdev;	350	struct ttm_bo_device bdev;
334	bool mem_global_referenced;	351	bool mem_global_referenced;
335	bool initialized;	352	bool initialized;
336	};	353	};
337		354
338	/* bo virtual address in a specific vm */	355	/* bo virtual address in a specific vm */
339	struct radeon_bo_va {	356	struct radeon_bo_va {
340	/* protected by bo being reserved */	357	/* protected by bo being reserved */
341	struct list_head bo_list;	358	struct list_head bo_list;
342	uint64_t soffset;	359	uint64_t soffset;
343	uint64_t eoffset;	360	uint64_t eoffset;
344	uint32_t flags;	361	uint32_t flags;
345	bool valid;	362	bool valid;
346	unsigned ref_count;	363	unsigned ref_count;
347		364
348	/* protected by vm mutex */	365	/* protected by vm mutex */
349	struct list_head vm_list;	366	struct list_head vm_list;
350		367
351	/* constant after initialization */	368	/* constant after initialization */
352	struct radeon_vm *vm;	369	struct radeon_vm *vm;
353	struct radeon_bo *bo;	370	struct radeon_bo *bo;
354	};	371	};
355		372
356	struct radeon_bo {	373	struct radeon_bo {
357	/* Protected by gem.mutex */	374	/* Protected by gem.mutex */
358	struct list_head list;	375	struct list_head list;
359	/* Protected by tbo.reserved */	376	/* Protected by tbo.reserved */
360	u32 placements[3];	377	u32 placements[3];
361	u32 busy_placements[3];	378	u32 domain;
362	struct ttm_placement placement;	379	struct ttm_placement placement;
363	struct ttm_buffer_object tbo;	380	struct ttm_buffer_object tbo;
364	struct ttm_bo_kmap_obj kmap;	381	struct ttm_bo_kmap_obj kmap;
365	unsigned pin_count;	382	unsigned pin_count;
366	void *kptr;	383	void *kptr;
367	void *uptr;	384	void *uptr;
368	u32 cpu_addr;	385	u32 cpu_addr;
369	u32 tiling_flags;	386	u32 tiling_flags;
370	u32 pitch;	387	u32 pitch;
371	int surface_reg;	388	int surface_reg;
372	/* list of all virtual address to which this bo	389	/* list of all virtual address to which this bo
373	* is associated to	390	* is associated to
374	*/	391	*/
375	struct list_head va;	392	struct list_head va;
376	/* Constant after initialization */	393	/* Constant after initialization */
377	struct radeon_device *rdev;	394	struct radeon_device *rdev;
378	struct drm_gem_object gem_base;	395	struct drm_gem_object gem_base;
379		396
380	u32 domain;	-
381	int vmapping_count;	397	struct ttm_bo_kmap_obj dma_buf_vmap;
382	};	398	};
383	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)	399	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
384		400
385	struct radeon_bo_list {	401	struct radeon_bo_list {
386	struct radeon_bo *bo;	402	struct radeon_bo *bo;
387	uint64_t gpu_offset;	403	uint64_t gpu_offset;
388	unsigned rdomain;	404	unsigned rdomain;
389	unsigned wdomain;	405	unsigned wdomain;
390	u32 tiling_flags;	406	u32 tiling_flags;
391	};	407	};
-		408
-		409	int radeon_gem_debugfs_init(struct radeon_device *rdev);
392		410
393	/* sub-allocation manager, it has to be protected by another lock.	411	/* sub-allocation manager, it has to be protected by another lock.
394	* By conception this is an helper for other part of the driver	412	* By conception this is an helper for other part of the driver
395	* like the indirect buffer or semaphore, which both have their	413	* like the indirect buffer or semaphore, which both have their
396	* locking.	414	* locking.
397	*	415	*
398	* Principe is simple, we keep a list of sub allocation in offset	416	* Principe is simple, we keep a list of sub allocation in offset
399	* order (first entry has offset == 0, last entry has the highest	417	* order (first entry has offset == 0, last entry has the highest
400	* offset).	418	* offset).
401	*	419	*
402	* When allocating new object we first check if there is room at	420	* When allocating new object we first check if there is room at
403	* the end total_size - (last_object_offset + last_object_size) >=	421	* the end total_size - (last_object_offset + last_object_size) >=
404	* alloc_size. If so we allocate new object there.	422	* alloc_size. If so we allocate new object there.
405	*	423	*
406	* When there is not enough room at the end, we start waiting for	424	* When there is not enough room at the end, we start waiting for
407	* each sub object until we reach object_offset+object_size >=	425	* each sub object until we reach object_offset+object_size >=
408	* alloc_size, this object then become the sub object we return.	426	* alloc_size, this object then become the sub object we return.
409	*	427	*
410	* Alignment can't be bigger than page size.	428	* Alignment can't be bigger than page size.
411	*	429	*
412	* Hole are not considered for allocation to keep things simple.	430	* Hole are not considered for allocation to keep things simple.
413	* Assumption is that there won't be hole (all object on same	431	* Assumption is that there won't be hole (all object on same
414	* alignment).	432	* alignment).
415	*/	433	*/
416	struct radeon_sa_manager {	434	struct radeon_sa_manager {
417	wait_queue_head_t wq;	435	wait_queue_head_t wq;
418	struct radeon_bo *bo;	436	struct radeon_bo *bo;
419	struct list_head *hole;	437	struct list_head *hole;
420	struct list_head flist[RADEON_NUM_RINGS];	438	struct list_head flist[RADEON_NUM_RINGS];
421	struct list_head olist;	439	struct list_head olist;
422	unsigned size;	440	unsigned size;
423	uint64_t gpu_addr;	441	uint64_t gpu_addr;
424	void *cpu_ptr;	442	void *cpu_ptr;
425	uint32_t domain;	443	uint32_t domain;
426	};	444	};
427		445
428	struct radeon_sa_bo;	446	struct radeon_sa_bo;
429		447
430	/* sub-allocation buffer */	448	/* sub-allocation buffer */
431	struct radeon_sa_bo {	449	struct radeon_sa_bo {
432	struct list_head olist;	450	struct list_head olist;
433	struct list_head flist;	451	struct list_head flist;
434	struct radeon_sa_manager *manager;	452	struct radeon_sa_manager *manager;
435	unsigned soffset;	453	unsigned soffset;
436	unsigned eoffset;	454	unsigned eoffset;
437	struct radeon_fence *fence;	455	struct radeon_fence *fence;
438	};	456	};
439		457
440	/*	458	/*
441	* GEM objects.	459	* GEM objects.
442	*/	460	*/
443	struct radeon_gem {	461	struct radeon_gem {
444	struct mutex mutex;	462	struct mutex mutex;
445	struct list_head objects;	463	struct list_head objects;
446	};	464	};
447		465
448	int radeon_gem_init(struct radeon_device *rdev);	466	int radeon_gem_init(struct radeon_device *rdev);
449	void radeon_gem_fini(struct radeon_device *rdev);	467	void radeon_gem_fini(struct radeon_device *rdev);
450	int radeon_gem_object_create(struct radeon_device *rdev, int size,	468	int radeon_gem_object_create(struct radeon_device *rdev, int size,
451	int alignment, int initial_domain,	469	int alignment, int initial_domain,
452	bool discardable, bool kernel,	470	bool discardable, bool kernel,
453	struct drm_gem_object **obj);	471	struct drm_gem_object **obj);
454		472
455	int radeon_mode_dumb_create(struct drm_file *file_priv,	473	int radeon_mode_dumb_create(struct drm_file *file_priv,
456	struct drm_device *dev,	474	struct drm_device *dev,
457	struct drm_mode_create_dumb *args);	475	struct drm_mode_create_dumb *args);
458	int radeon_mode_dumb_mmap(struct drm_file *filp,	476	int radeon_mode_dumb_mmap(struct drm_file *filp,
459	struct drm_device *dev,	477	struct drm_device *dev,
460	uint32_t handle, uint64_t *offset_p);	478	uint32_t handle, uint64_t *offset_p);
461	int radeon_mode_dumb_destroy(struct drm_file *file_priv,	479	int radeon_mode_dumb_destroy(struct drm_file *file_priv,
462	struct drm_device *dev,	480	struct drm_device *dev,
463	uint32_t handle);	481	uint32_t handle);
464		482
465	/*	483	/*
466	* Semaphores.	484	* Semaphores.
467	*/	485	*/
468	/* everything here is constant */	486	/* everything here is constant */
469	struct radeon_semaphore {	487	struct radeon_semaphore {
470	struct radeon_sa_bo *sa_bo;	488	struct radeon_sa_bo *sa_bo;
471	signed waiters;	489	signed waiters;
472	uint64_t gpu_addr;	490	uint64_t gpu_addr;
473	};	491	};
474		492
475	int radeon_semaphore_create(struct radeon_device *rdev,	493	int radeon_semaphore_create(struct radeon_device *rdev,
476	struct radeon_semaphore **semaphore);	494	struct radeon_semaphore **semaphore);
477	void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,	495	void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
478	struct radeon_semaphore *semaphore);	496	struct radeon_semaphore *semaphore);
479	void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,	497	void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
480	struct radeon_semaphore *semaphore);	498	struct radeon_semaphore *semaphore);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon.h – Rev 3192 → 3764