WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon.h


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RADEON_H__
#define __RADEON_H__
 
/* TODO: Here are things that needs to be done :
 *	- surface allocator & initializer : (bit like scratch reg) should
 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
 *	  related to surface
 *	- WB : write back stuff (do it bit like scratch reg things)
 *	- Vblank : look at Jesse's rework and what we should do
 *	- r600/r700: gart & cp
 *	- cs : clean cs ioctl use bitmap & things like that.
 *	- power management stuff
 *	- Barrier in gart code
 *	- Unmappabled vram ?
 *	- TESTING, TESTING, TESTING
 */
 
/* Initialization path:
 *  We expect that acceleration initialization might fail for various
 *  reasons even thought we work hard to make it works on most
 *  configurations. In order to still have a working userspace in such
 *  situation the init path must succeed up to the memory controller
 *  initialization point. Failure before this point are considered as
 *  fatal error. Here is the init callchain :
 *      radeon_device_init  perform common structure, mutex initialization
 *      asic_init           setup the GPU memory layout and perform all
 *                          one time initialization (failure in this
 *                          function are considered fatal)
 *      asic_startup        setup the GPU acceleration, in order to
 *                          follow guideline the first thing this
 *                          function should do is setting the GPU
 *                          memory controller (only MC setup failure
 *                          are considered as fatal)
 */
 
#include 
 
#include 
#include 
 
#include 
#include 
#include 
#include 
 
#include 
#include 
 
#include 
#include "drm_edid.h"
 
#include "radeon_family.h"
#include "radeon_mode.h"
#include "radeon_reg.h"
 
#include 
 
extern unsigned long volatile jiffies;
 
/*
 * Modules parameters.
 */
extern int radeon_no_wb;
extern int radeon_modeset;
extern int radeon_dynclks;
extern int radeon_r4xx_atom;
extern int radeon_agpmode;
extern int radeon_vram_limit;
extern int radeon_gart_size;
extern int radeon_benchmarking;
extern int radeon_testing;
extern int radeon_connector_table;
extern int radeon_tv;
extern int radeon_audio;
extern int radeon_disp_priority;
extern int radeon_hw_i2c;
extern int radeon_pcie_gen2;
typedef struct pm_message {
    int event;
} pm_message_t;
 
typedef struct
{
  int width;
  int height;
  int bpp;
  int freq;
}videomode_t;
 
static inline uint8_t __raw_readb(const volatile void __iomem *addr)
{
    return *(const volatile uint8_t __force *) addr;
}
 
static inline uint16_t __raw_readw(const volatile void __iomem *addr)
{
    return *(const volatile uint16_t __force *) addr;
}
 
static inline uint32_t __raw_readl(const volatile void __iomem *addr)
{
    return *(const volatile uint32_t __force *) addr;
}
 
#define readb __raw_readb
#define readw __raw_readw
#define readl __raw_readl
 
 
 
static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
{
    *(volatile uint8_t __force *) addr = b;
}
 
static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
{
    *(volatile uint16_t __force *) addr = b;
}
 
static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
{
    *(volatile uint32_t __force *) addr = b;
}
 
static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
{
        *(volatile __u64 *)addr = b;
}
 
#define writeb __raw_writeb
#define writew __raw_writew
#define writel __raw_writel
#define writeq __raw_writeq
 
 
static inline u32 ioread32(const volatile void __iomem *addr)
{
    return in32((u32)addr);
}
 
static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
{
    out32((u32)addr, b);
}
 
struct __wait_queue_head {
        spinlock_t lock;
        struct list_head task_list;
};
typedef struct __wait_queue_head wait_queue_head_t;
 
 
/*
 * Copy from radeon_drv.h so we don't have to include both and have conflicting
 * symbol;
 */
#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
#define RADEON_FENCE_JIFFIES_TIMEOUT	(HZ / 2)
/* RADEON_IB_POOL_SIZE must be a power of 2 */
#define RADEON_IB_POOL_SIZE             16
#define RADEON_DEBUGFS_MAX_NUM_FILES	32
#define RADEONFB_CONN_LIMIT             4
#define RADEON_BIOS_NUM_SCRATCH		8
 
/*
 * Errata workarounds.
 */
enum radeon_pll_errata {
    CHIP_ERRATA_R300_CG             = 0x00000001,
    CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
    CHIP_ERRATA_PLL_DELAY           = 0x00000004
};
 
 
struct radeon_device;
 
 
/*
 * BIOS.
 */
#define ATRM_BIOS_PAGE 4096
 
#if defined(CONFIG_VGA_SWITCHEROO)
bool radeon_atrm_supported(struct pci_dev *pdev);
int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
#else
static inline bool radeon_atrm_supported(struct pci_dev *pdev)
{
	return false;
}
 
static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
	return -EINVAL;
}
#endif
bool radeon_get_bios(struct radeon_device *rdev);
 
 
/*
 * Dummy page
 */
struct radeon_dummy_page {
	struct page	*page;
	dma_addr_t	addr;
};
int radeon_dummy_page_init(struct radeon_device *rdev);
void radeon_dummy_page_fini(struct radeon_device *rdev);
 
 
/*
 * Clocks
 */
struct radeon_clock {
	struct radeon_pll p1pll;
	struct radeon_pll p2pll;
	struct radeon_pll dcpll;
	struct radeon_pll spll;
	struct radeon_pll mpll;
	/* 10 Khz units */
	uint32_t default_mclk;
	uint32_t default_sclk;
	uint32_t default_dispclk;
	uint32_t dp_extclk;
	uint32_t max_pixel_clock;
};
 
/*
 * Power management
 */
int radeon_pm_init(struct radeon_device *rdev);
void radeon_pm_fini(struct radeon_device *rdev);
void radeon_pm_compute_clocks(struct radeon_device *rdev);
void radeon_pm_suspend(struct radeon_device *rdev);
void radeon_pm_resume(struct radeon_device *rdev);
void radeon_combios_get_power_modes(struct radeon_device *rdev);
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
void rs690_pm_info(struct radeon_device *rdev);
extern int rv6xx_get_temp(struct radeon_device *rdev);
extern int rv770_get_temp(struct radeon_device *rdev);
extern int evergreen_get_temp(struct radeon_device *rdev);
extern int sumo_get_temp(struct radeon_device *rdev);
 
/*
 * Fences.
 */
struct radeon_fence_driver {
	uint32_t			scratch_reg;
	atomic_t			seq;
	uint32_t			last_seq;
	unsigned long			last_jiffies;
	unsigned long			last_timeout;
	wait_queue_head_t		queue;
	rwlock_t			lock;
	struct list_head		created;
	struct list_head		emited;
	struct list_head		signaled;
	bool				initialized;
};
 
struct radeon_fence {
	struct radeon_device		*rdev;
	struct kref			kref;
	struct list_head		list;
	/* protected by radeon_fence.lock */
	uint32_t			seq;
	bool				emited;
	bool				signaled;
    evhandle_t              evnt;
};
 
int radeon_fence_driver_init(struct radeon_device *rdev);
void radeon_fence_driver_fini(struct radeon_device *rdev);
int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
void radeon_fence_process(struct radeon_device *rdev);
bool radeon_fence_signaled(struct radeon_fence *fence);
int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
int radeon_fence_wait_next(struct radeon_device *rdev);
int radeon_fence_wait_last(struct radeon_device *rdev);
struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
void radeon_fence_unref(struct radeon_fence **fence);
 
/*
 * Tiling registers
 */
struct radeon_surface_reg {
	struct radeon_bo *bo;
};
 
#define RADEON_GEM_MAX_SURFACES 8
 
/*
 * TTM.
 */
struct radeon_mman {
	struct ttm_bo_global_ref        bo_global_ref;
//	struct drm_global_reference	mem_global_ref;
	struct ttm_bo_device		bdev;
	bool				mem_global_referenced;
	bool				initialized;
};
 
struct radeon_bo {
	/* Protected by gem.mutex */
	struct list_head		list;
	/* Protected by tbo.reserved */
	u32				placements[3];
	struct ttm_placement		placement;
	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
    unsigned                    pin_count;
    void                       *kptr;
    void                       *uptr;
    u32                         cpu_addr;
    u32                         tiling_flags;
    u32                         pitch;
    int                         surface_reg;
	/* Constant after initialization */
	struct radeon_device		*rdev;
	struct drm_gem_object		gem_base;
    u32                          domain;
};
#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 
struct radeon_bo_list {
	struct radeon_bo	*bo;
	uint64_t		gpu_offset;
	unsigned		rdomain;
	unsigned		wdomain;
	u32			tiling_flags;
};
 
/*
 * GEM objects.
 */
struct radeon_gem {
	struct mutex		mutex;
	struct list_head	objects;
};
 
int radeon_gem_init(struct radeon_device *rdev);
void radeon_gem_fini(struct radeon_device *rdev);
int radeon_gem_object_create(struct radeon_device *rdev, int size,
			     int alignment, int initial_domain,
			     bool discardable, bool kernel,
			     struct drm_gem_object **obj);
int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
			  uint64_t *gpu_addr);
void radeon_gem_object_unpin(struct drm_gem_object *obj);
 
int radeon_mode_dumb_create(struct drm_file *file_priv,
			    struct drm_device *dev,
			    struct drm_mode_create_dumb *args);
int radeon_mode_dumb_mmap(struct drm_file *filp,
			  struct drm_device *dev,
			  uint32_t handle, uint64_t *offset_p);
int radeon_mode_dumb_destroy(struct drm_file *file_priv,
			     struct drm_device *dev,
			     uint32_t handle);
 
/*
 * GART structures, functions & helpers
 */
struct radeon_mc;
 
struct radeon_gart_table_ram {
    volatile uint32_t       *ptr;
};
 
struct radeon_gart_table_vram {
	struct radeon_bo		*robj;
    volatile uint32_t       *ptr;
};
 
union radeon_gart_table {
    struct radeon_gart_table_ram    ram;
    struct radeon_gart_table_vram   vram;
};
 
#define RADEON_GPU_PAGE_SIZE 4096
#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 
struct radeon_gart {
    dma_addr_t          table_addr;
    unsigned            num_gpu_pages;
    unsigned            num_cpu_pages;
    unsigned            table_size;
    union radeon_gart_table     table;
    struct page         **pages;
    dma_addr_t          *pages_addr;
	bool				*ttm_alloced;
    bool                ready;
};
 
int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
void radeon_gart_table_ram_free(struct radeon_device *rdev);
int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
void radeon_gart_table_vram_free(struct radeon_device *rdev);
int radeon_gart_init(struct radeon_device *rdev);
void radeon_gart_fini(struct radeon_device *rdev);
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages);
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
            int pages, u32_t *pagelist);
 
 
/*
 * GPU MC structures, functions & helpers
 */
struct radeon_mc {
    resource_size_t     aper_size;
    resource_size_t     aper_base;
    resource_size_t     agp_base;
	/* for some chips with <= 32MB we need to lie
	 * about vram size near mc fb location */
	u64			mc_vram_size;
	u64			visible_vram_size;
	u64			gtt_size;
	u64			gtt_start;
	u64			gtt_end;
	u64			vram_start;
	u64			vram_end;
    unsigned            vram_width;
	u64			real_vram_size;
    int                 vram_mtrr;
    bool                vram_is_ddr;
	bool                    igp_sideport_enabled;
	u64                     gtt_base_align;
};
 
bool radeon_combios_sideport_present(struct radeon_device *rdev);
bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 
/*
 * GPU scratch registers structures, functions & helpers
 */
struct radeon_scratch {
    unsigned        num_reg;
	uint32_t                reg_base;
    bool            free[32];
    uint32_t        reg[32];
};
 
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 
 
/*
 * IRQS.
 */
struct r500_irq_stat_regs {
	u32 disp_int;
};
 
struct r600_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 d1grph_int;
	u32 d2grph_int;
};
 
struct evergreen_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 disp_int_cont3;
	u32 disp_int_cont4;
	u32 disp_int_cont5;
	u32 d1grph_int;
	u32 d2grph_int;
	u32 d3grph_int;
	u32 d4grph_int;
	u32 d5grph_int;
	u32 d6grph_int;
};
 
union radeon_irq_stat_regs {
	struct r500_irq_stat_regs r500;
	struct r600_irq_stat_regs r600;
	struct evergreen_irq_stat_regs evergreen;
};
 
struct radeon_irq {
	bool		installed;
	bool		sw_int;
	/* FIXME: use a define max crtc rather than hardcode it */
	bool		crtc_vblank_int[6];
	bool		pflip[6];
    wait_queue_head_t   vblank_queue;
	/* FIXME: use defines for max hpd/dacs */
	bool            hpd[6];
	bool            gui_idle;
	bool            gui_idle_acked;
   wait_queue_head_t   idle_queue;
	/* FIXME: use defines for max HDMI blocks */
	bool		hdmi[2];
    spinlock_t  sw_lock;
	int sw_refcount;
	union radeon_irq_stat_regs stat_regs;
	spinlock_t pflip_lock[6];
	int pflip_refcount[6];
};
 
int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 
/*
 * CP & ring.
 */
struct radeon_ib {
    struct list_head    list;
	unsigned		idx;
    uint64_t            gpu_addr;
	struct radeon_fence	*fence;
    uint32_t            *ptr;
    uint32_t            length_dw;
	bool			free;
};
 
/*
 * locking -
 * mutex protects scheduled_ibs, ready, alloc_bm
 */
struct radeon_ib_pool {
	struct mutex		mutex;
	struct radeon_bo	*robj;
	struct list_head	bogus_ib;
	struct radeon_ib	ibs[RADEON_IB_POOL_SIZE];
    bool                ready;
	unsigned		head_id;
};
 
struct radeon_cp {
	struct radeon_bo	*ring_obj;
	volatile uint32_t	*ring;
    unsigned            rptr;
    unsigned            wptr;
    unsigned            wptr_old;
    unsigned            ring_size;
    unsigned            ring_free_dw;
    int                 count_dw;
    uint64_t            gpu_addr;
    uint32_t            align_mask;
    uint32_t            ptr_mask;
	struct mutex		mutex;
    bool                ready;
};
 
/*
 * R6xx+ IH ring
 */
struct r600_ih {
	struct radeon_bo	*ring_obj;
	volatile uint32_t	*ring;
    unsigned            rptr;
    unsigned            wptr;
    unsigned            wptr_old;
    unsigned            ring_size;
    uint64_t            gpu_addr;
    uint32_t            ptr_mask;
    spinlock_t              lock;
    bool                enabled;
};
 
struct r600_blit {
	struct mutex		mutex;
	struct radeon_bo	*shader_obj;
	u64 shader_gpu_addr;
	u32 vs_offset, ps_offset;
	u32 state_offset;
	u32 state_len;
	u32 vb_used, vb_total;
	struct radeon_ib *vb_ib;
};
 
int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
int radeon_ib_pool_init(struct radeon_device *rdev);
void radeon_ib_pool_fini(struct radeon_device *rdev);
int radeon_ib_test(struct radeon_device *rdev);
extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
/* Ring access between begin & end cannot sleep */
void radeon_ring_free_size(struct radeon_device *rdev);
int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
void radeon_ring_commit(struct radeon_device *rdev);
void radeon_ring_unlock_commit(struct radeon_device *rdev);
void radeon_ring_unlock_undo(struct radeon_device *rdev);
int radeon_ring_test(struct radeon_device *rdev);
int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
void radeon_ring_fini(struct radeon_device *rdev);
 
 
/*
 * CS.
 */
struct radeon_cs_reloc {
//	struct drm_gem_object		*gobj;
	struct radeon_bo		*robj;
	struct radeon_bo_list		lobj;
    uint32_t                handle;
    uint32_t                flags;
};
 
struct radeon_cs_chunk {
	uint32_t		chunk_id;
	uint32_t		length_dw;
	int kpage_idx[2];
	uint32_t                *kpage[2];
	uint32_t		*kdata;
	void __user *user_ptr;
	int last_copied_page;
	int last_page_index;
};
 
struct radeon_cs_parser {
	struct device		*dev;
	struct radeon_device	*rdev;
	struct drm_file		*filp;
	/* chunks */
	unsigned		nchunks;
	struct radeon_cs_chunk	*chunks;
	uint64_t		*chunks_array;
	/* IB */
	unsigned		idx;
	/* relocations */
	unsigned		nrelocs;
	struct radeon_cs_reloc	*relocs;
	struct radeon_cs_reloc	**relocs_ptr;
	struct list_head	validated;
	/* indices of various chunks */
	int			chunk_ib_idx;
	int			chunk_relocs_idx;
	struct radeon_ib	*ib;
	void			*track;
	unsigned		family;
	int parser_error;
};
 
extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 
 
static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	u32 pg_idx, pg_offset;
	u32 idx_value = 0;
	int new_page;
 
	pg_idx = (idx * 4) / PAGE_SIZE;
	pg_offset = (idx * 4) % PAGE_SIZE;
 
	if (ibc->kpage_idx[0] == pg_idx)
		return ibc->kpage[0][pg_offset/4];
	if (ibc->kpage_idx[1] == pg_idx)
		return ibc->kpage[1][pg_offset/4];
 
	new_page = radeon_cs_update_pages(p, pg_idx);
	if (new_page < 0) {
		p->parser_error = new_page;
		return 0;
	}
 
	idx_value = ibc->kpage[new_page][pg_offset/4];
	return idx_value;
}
 
struct radeon_cs_packet {
	unsigned	idx;
	unsigned	type;
	unsigned	reg;
	unsigned	opcode;
	int		count;
	unsigned	one_reg_wr;
};
 
typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt,
				      unsigned idx, unsigned reg);
typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt);
 
 
/*
 * AGP
 */
int radeon_agp_init(struct radeon_device *rdev);
void radeon_agp_resume(struct radeon_device *rdev);
void radeon_agp_suspend(struct radeon_device *rdev);
void radeon_agp_fini(struct radeon_device *rdev);
 
 
/*
 * Writeback
 */
struct radeon_wb {
	struct radeon_bo	*wb_obj;
	volatile uint32_t	*wb;
	uint64_t		gpu_addr;
	bool                    enabled;
	bool                    use_event;
};
 
#define RADEON_WB_SCRATCH_OFFSET 0
#define RADEON_WB_CP_RPTR_OFFSET 1024
#define RADEON_WB_CP1_RPTR_OFFSET 1280
#define RADEON_WB_CP2_RPTR_OFFSET 1536
#define R600_WB_IH_WPTR_OFFSET   2048
#define R600_WB_EVENT_OFFSET     3072
 
/**
 * struct radeon_pm - power management datas
 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)
 * @needed_bandwidth:   current bandwidth needs
 *
 * It keeps track of various data needed to take powermanagement decision.
 * Bandwidth need is used to determine minimun clock of the GPU and memory.
 * Equation between gpu/memory clock and available bandwidth is hw dependent
 * (type of memory, bus size, efficiency, ...)
 */
 
enum radeon_pm_method {
	PM_METHOD_PROFILE,
	PM_METHOD_DYNPM,
};
 
enum radeon_dynpm_state {
	DYNPM_STATE_DISABLED,
	DYNPM_STATE_MINIMUM,
	DYNPM_STATE_PAUSED,
	DYNPM_STATE_ACTIVE,
	DYNPM_STATE_SUSPENDED,
};
enum radeon_dynpm_action {
	DYNPM_ACTION_NONE,
	DYNPM_ACTION_MINIMUM,
	DYNPM_ACTION_DOWNCLOCK,
	DYNPM_ACTION_UPCLOCK,
	DYNPM_ACTION_DEFAULT
};
 
enum radeon_voltage_type {
	VOLTAGE_NONE = 0,
	VOLTAGE_GPIO,
	VOLTAGE_VDDC,
	VOLTAGE_SW
};
 
enum radeon_pm_state_type {
	POWER_STATE_TYPE_DEFAULT,
	POWER_STATE_TYPE_POWERSAVE,
	POWER_STATE_TYPE_BATTERY,
	POWER_STATE_TYPE_BALANCED,
	POWER_STATE_TYPE_PERFORMANCE,
};
 
enum radeon_pm_profile_type {
	PM_PROFILE_DEFAULT,
	PM_PROFILE_AUTO,
	PM_PROFILE_LOW,
	PM_PROFILE_MID,
	PM_PROFILE_HIGH,
};
 
#define PM_PROFILE_DEFAULT_IDX 0
#define PM_PROFILE_LOW_SH_IDX  1
#define PM_PROFILE_MID_SH_IDX  2
#define PM_PROFILE_HIGH_SH_IDX 3
#define PM_PROFILE_LOW_MH_IDX  4
#define PM_PROFILE_MID_MH_IDX  5
#define PM_PROFILE_HIGH_MH_IDX 6
#define PM_PROFILE_MAX         7
 
struct radeon_pm_profile {
	int dpms_off_ps_idx;
	int dpms_on_ps_idx;
	int dpms_off_cm_idx;
	int dpms_on_cm_idx;
};
 
enum radeon_int_thermal_type {
	THERMAL_TYPE_NONE,
	THERMAL_TYPE_RV6XX,
	THERMAL_TYPE_RV770,
	THERMAL_TYPE_EVERGREEN,
	THERMAL_TYPE_SUMO,
	THERMAL_TYPE_NI,
};
 
struct radeon_voltage {
	enum radeon_voltage_type type;
	/* gpio voltage */
	struct radeon_gpio_rec gpio;
	u32 delay; /* delay in usec from voltage drop to sclk change */
	bool active_high; /* voltage drop is active when bit is high */
	/* VDDC voltage */
	u8 vddc_id; /* index into vddc voltage table */
	u8 vddci_id; /* index into vddci voltage table */
	bool vddci_enabled;
	/* r6xx+ sw */
	u16 voltage;
	/* evergreen+ vddci */
	u16 vddci;
};
 
/* clock mode flags */
#define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 
struct radeon_pm_clock_info {
	/* memory clock */
	u32 mclk;
	/* engine clock */
	u32 sclk;
	/* voltage info */
	struct radeon_voltage voltage;
	/* standardized clock flags */
	u32 flags;
};
 
/* state flags */
#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
 
struct radeon_power_state {
	enum radeon_pm_state_type type;
	/* XXX: use a define for num clock modes */
	struct radeon_pm_clock_info clock_info[8];
	/* number of valid clock modes in this power state */
	int num_clock_modes;
	struct radeon_pm_clock_info *default_clock_mode;
	/* standardized state flags */
	u32 flags;
	u32 misc; /* vbios specific flags */
	u32 misc2; /* vbios specific flags */
	int pcie_lanes; /* pcie lanes */
};
 
/*
 * Some modes are overclocked by very low value, accept them
 */
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 
struct radeon_pm {
	struct mutex		mutex;
	u32			active_crtcs;
	int			active_crtc_count;
	int			req_vblank;
	bool			vblank_sync;
	bool			gui_idle;
	fixed20_12		max_bandwidth;
	fixed20_12		igp_sideport_mclk;
	fixed20_12		igp_system_mclk;
	fixed20_12		igp_ht_link_clk;
	fixed20_12		igp_ht_link_width;
	fixed20_12		k8_bandwidth;
	fixed20_12		sideport_bandwidth;
	fixed20_12		ht_bandwidth;
	fixed20_12		core_bandwidth;
	fixed20_12		sclk;
	fixed20_12		mclk;
	fixed20_12		needed_bandwidth;
	struct radeon_power_state *power_state;
	/* number of valid power states */
	int                     num_power_states;
	int                     current_power_state_index;
	int                     current_clock_mode_index;
	int                     requested_power_state_index;
	int                     requested_clock_mode_index;
	int                     default_power_state_index;
	u32                     current_sclk;
	u32                     current_mclk;
	u16                     current_vddc;
	u16                     current_vddci;
	u32                     default_sclk;
	u32                     default_mclk;
	u16                     default_vddc;
	u16                     default_vddci;
	struct radeon_i2c_chan *i2c_bus;
	/* selected pm method */
	enum radeon_pm_method     pm_method;
	/* dynpm power management */
//   struct delayed_work dynpm_idle_work;
	enum radeon_dynpm_state	dynpm_state;
	enum radeon_dynpm_action	dynpm_planned_action;
	unsigned long		dynpm_action_timeout;
	bool                    dynpm_can_upclock;
	bool                    dynpm_can_downclock;
	/* profile-based power management */
	enum radeon_pm_profile_type profile;
	int                     profile_index;
	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
	/* internal thermal controller on rv6xx+ */
	enum radeon_int_thermal_type int_thermal_type;
	struct device	        *int_hwmon_dev;
};
 
/*
 * ASIC specific functions.
 */
struct radeon_asic {
	int (*init)(struct radeon_device *rdev);
	void (*fini)(struct radeon_device *rdev);
	int (*resume)(struct radeon_device *rdev);
	int (*suspend)(struct radeon_device *rdev);
	void (*vga_set_state)(struct radeon_device *rdev, bool state);
	bool (*gpu_is_lockup)(struct radeon_device *rdev);
	int (*asic_reset)(struct radeon_device *rdev);
	void (*gart_tlb_flush)(struct radeon_device *rdev);
	int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
	int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
	void (*cp_fini)(struct radeon_device *rdev);
	void (*cp_disable)(struct radeon_device *rdev);
	void (*cp_commit)(struct radeon_device *rdev);
	void (*ring_start)(struct radeon_device *rdev);
	int (*ring_test)(struct radeon_device *rdev);
	void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
	int (*irq_set)(struct radeon_device *rdev);
	int (*irq_process)(struct radeon_device *rdev);
	u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
	void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
	int (*cs_parse)(struct radeon_cs_parser *p);
	int (*copy_blit)(struct radeon_device *rdev,
			 uint64_t src_offset,
			 uint64_t dst_offset,
			 unsigned num_pages,
			 struct radeon_fence *fence);
	int (*copy_dma)(struct radeon_device *rdev,
			uint64_t src_offset,
			uint64_t dst_offset,
			unsigned num_pages,
			struct radeon_fence *fence);
	int (*copy)(struct radeon_device *rdev,
		    uint64_t src_offset,
		    uint64_t dst_offset,
		    unsigned num_pages,
		    struct radeon_fence *fence);
	uint32_t (*get_engine_clock)(struct radeon_device *rdev);
	void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
	uint32_t (*get_memory_clock)(struct radeon_device *rdev);
	void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
	int (*get_pcie_lanes)(struct radeon_device *rdev);
	void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
	void (*set_clock_gating)(struct radeon_device *rdev, int enable);
	int (*set_surface_reg)(struct radeon_device *rdev, int reg,
			       uint32_t tiling_flags, uint32_t pitch,
			       uint32_t offset, uint32_t obj_size);
	void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
	void (*bandwidth_update)(struct radeon_device *rdev);
	void (*hpd_init)(struct radeon_device *rdev);
	void (*hpd_fini)(struct radeon_device *rdev);
	bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	/* ioctl hw specific callback. Some hw might want to perform special
	 * operation on specific ioctl. For instance on wait idle some hw
	 * might want to perform and HDP flush through MMIO as it seems that
	 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
	 * through ring.
	 */
	void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
	bool (*gui_idle)(struct radeon_device *rdev);
	/* power management */
	void (*pm_misc)(struct radeon_device *rdev);
	void (*pm_prepare)(struct radeon_device *rdev);
	void (*pm_finish)(struct radeon_device *rdev);
	void (*pm_init_profile)(struct radeon_device *rdev);
	void (*pm_get_dynpm_state)(struct radeon_device *rdev);
	/* pageflipping */
	void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
	u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
	void (*post_page_flip)(struct radeon_device *rdev, int crtc);
};
 
/*
 * Asic structures
 */
struct r100_gpu_lockup {
	unsigned long	last_jiffies;
	u32		last_cp_rptr;
};
 
struct r100_asic {
	const unsigned	*reg_safe_bm;
	unsigned	reg_safe_bm_size;
	u32		hdp_cntl;
	struct r100_gpu_lockup	lockup;
};
 
struct r300_asic {
	const unsigned	*reg_safe_bm;
	unsigned	reg_safe_bm_size;
	u32		resync_scratch;
	u32		hdp_cntl;
	struct r100_gpu_lockup	lockup;
};
 
struct r600_asic {
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
	unsigned		tile_config;
	unsigned		backend_map;
	struct r100_gpu_lockup	lockup;
};
 
struct rv770_asic {
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned sx_num_of_sets;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_fize;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
	unsigned		tile_config;
	unsigned		backend_map;
	struct r100_gpu_lockup	lockup;
};
 
struct evergreen_asic {
	unsigned num_ses;
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned sx_num_of_sets;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
	unsigned tile_config;
	unsigned backend_map;
	struct r100_gpu_lockup	lockup;
};
 
struct cayman_asic {
	unsigned max_shader_engines;
	unsigned max_pipes_per_simd;
	unsigned max_tile_pipes;
	unsigned max_simds_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_gs_threads;
	unsigned max_stack_entries;
	unsigned sx_num_of_sets;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned max_hw_contexts;
	unsigned sq_num_cf_insts;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;
 
	unsigned num_shader_engines;
	unsigned num_shader_pipes_per_simd;
	unsigned num_tile_pipes;
	unsigned num_simds_per_se;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;
 
	unsigned tile_config;
	struct r100_gpu_lockup	lockup;
};
 
union radeon_asic_config {
	struct r300_asic	r300;
	struct r100_asic	r100;
	struct r600_asic	r600;
	struct rv770_asic	rv770;
	struct evergreen_asic	evergreen;
	struct cayman_asic	cayman;
};
 
/*
 * asic initizalization from radeon_asic.c
 */
void radeon_agp_disable(struct radeon_device *rdev);
int radeon_asic_init(struct radeon_device *rdev);
 
 
 
/* VRAM scratch page for HDP bug */
struct r700_vram_scratch {
	struct radeon_bo		*robj;
	volatile uint32_t		*ptr;
};
 
/*
 * Core structure, functions and helpers.
 */
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 
struct radeon_device {
	struct device			*dev;
    struct drm_device          *ddev;
    struct pci_dev             *pdev;
    /* ASIC */
    union radeon_asic_config    config;
    enum radeon_family          family;
    unsigned long               flags;
    int                         usec_timeout;
    enum radeon_pll_errata      pll_errata;
    int                         num_gb_pipes;
	int				            num_z_pipes;
    int                         disp_priority;
    /* BIOS */
    uint8_t                     *bios;
    bool                        is_atom_bios;
    uint16_t                    bios_header_start;
	struct radeon_bo		    *stollen_vga_memory;
    /* Register mmio */
	resource_size_t			rmmio_base;
	resource_size_t			rmmio_size;
    void                       *rmmio;
    radeon_rreg_t               mc_rreg;
    radeon_wreg_t               mc_wreg;
    radeon_rreg_t               pll_rreg;
    radeon_wreg_t               pll_wreg;
	uint32_t                        pcie_reg_mask;
    radeon_rreg_t               pciep_rreg;
    radeon_wreg_t               pciep_wreg;
	/* io port */
	void __iomem                    *rio_mem;
	resource_size_t			rio_mem_size;
    struct radeon_clock         clock;
    struct radeon_mc            mc;
    struct radeon_gart          gart;
	struct radeon_mode_info		mode_info;
    struct radeon_scratch       scratch;
    struct radeon_mman          mman;
	struct radeon_fence_driver	fence_drv;
    struct radeon_cp            cp;
	/* cayman compute rings */
	struct radeon_cp		cp1;
	struct radeon_cp		cp2;
    struct radeon_ib_pool       ib_pool;
    struct radeon_irq       irq;
    struct radeon_asic         *asic;
    struct radeon_gem       gem;
	struct radeon_pm		pm;
	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
	struct mutex			cs_mutex;
    struct radeon_wb        wb;
	struct radeon_dummy_page	dummy_page;
    bool                gpu_lockup;
    bool                shutdown;
    bool                suspend;
	bool				need_dma32;
	bool				accel_working;
	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
	const struct firmware *me_fw;	/* all family ME firmware */
	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
	const struct firmware *mc_fw;	/* NI MC firmware */
	struct r600_blit r600_blit;
    struct r600_blit r600_video;
	struct r700_vram_scratch vram_scratch;
	int msi_enabled; /* msi enabled */
	struct r600_ih ih; /* r6/700 interrupt ring */
//	struct work_struct hotplug_work;
	int num_crtc; /* number of crtcs */
	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
	struct mutex vram_mutex;
 
	/* audio stuff */
	bool			audio_enabled;
//	struct timer_list	audio_timer;
	int			audio_channels;
	int			audio_rate;
	int			audio_bits_per_sample;
	uint8_t			audio_status_bits;
	uint8_t			audio_category_code;
 
 
	/* i2c buses */
	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
};
 
int radeon_device_init(struct radeon_device *rdev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags);
void radeon_device_fini(struct radeon_device *rdev);
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
{
	if (reg < rdev->rmmio_size)
		return readl(((void __iomem *)rdev->rmmio) + reg);
	else {
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
	}
}
 
static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	if (reg < rdev->rmmio_size)
		writel(v, ((void __iomem *)rdev->rmmio) + reg);
	else {
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
	}
}
 
static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
{
	if (reg < rdev->rio_mem_size)
		return ioread32(rdev->rio_mem + reg);
	else {
		iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		return ioread32(rdev->rio_mem + RADEON_MM_DATA);
	}
}
 
static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
{
	if (reg < rdev->rio_mem_size)
		iowrite32(v, rdev->rio_mem + reg);
	else {
		iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
	}
}
 
/*
 * Cast helper
 */
#define to_radeon_fence(p) ((struct radeon_fence *)(p))
 
/*
 * Registers read & write functions.
 */
#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
#define RREG32(reg) r100_mm_rreg(rdev, (reg))
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
#define WREG32_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32(reg);			\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32(reg, tmp_);				\
	} while (0)
#define WREG32_PLL_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32_PLL(reg);		\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32_PLL(reg, tmp_);				\
	} while (0)
#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
 
/*
 * Indirect registers accessor
 */
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;
 
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	r = RREG32(RADEON_PCIE_DATA);
	return r;
}
 
static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	WREG32(RADEON_PCIE_DATA, (v));
}
 
void r100_pll_errata_after_index(struct radeon_device *rdev);
 
 
/*
 * ASICs helpers.
 */
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
			    (rdev->pdev->device == 0x5969))
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
        (rdev->family == CHIP_RV200) || \
        (rdev->family == CHIP_RS100) || \
        (rdev->family == CHIP_RS200) || \
        (rdev->family == CHIP_RV250) || \
        (rdev->family == CHIP_RV280) || \
        (rdev->family == CHIP_RS300))
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
        (rdev->family == CHIP_RV350) ||         \
        (rdev->family == CHIP_R350)  ||         \
        (rdev->family == CHIP_RV380) ||         \
        (rdev->family == CHIP_R420)  ||         \
        (rdev->family == CHIP_R423)  ||         \
        (rdev->family == CHIP_RV410) ||         \
        (rdev->family == CHIP_RS400) ||         \
        (rdev->family == CHIP_RS480))
#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
		(rdev->ddev->pdev->device == 0x9443) || \
		(rdev->ddev->pdev->device == 0x944B) || \
		(rdev->ddev->pdev->device == 0x9506) || \
		(rdev->ddev->pdev->device == 0x9509) || \
		(rdev->ddev->pdev->device == 0x950F) || \
		(rdev->ddev->pdev->device == 0x689C) || \
		(rdev->ddev->pdev->device == 0x689D))
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
			    (rdev->family == CHIP_RS690)  ||	\
			    (rdev->family == CHIP_RS740)  ||	\
			    (rdev->family >= CHIP_R600))
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
			     (rdev->flags & RADEON_IS_IGP))
#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
 
/*
 * BIOS helpers.
 */
#define RBIOS8(i) (rdev->bios[i])
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 
int radeon_combios_init(struct radeon_device *rdev);
void radeon_combios_fini(struct radeon_device *rdev);
int radeon_atombios_init(struct radeon_device *rdev);
void radeon_atombios_fini(struct radeon_device *rdev);
 
 
/*
 * RING helpers.
 */
static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
{
#if DRM_DEBUG_CODE
	if (rdev->cp.count_dw <= 0) {
		DRM_ERROR("radeon: writting more dword to ring than expected !\n");
	}
#endif
	rdev->cp.ring[rdev->cp.wptr++] = v;
	rdev->cp.wptr &= rdev->cp.ptr_mask;
	rdev->cp.count_dw--;
	rdev->cp.ring_free_dw--;
}
 
 
/*
 * ASICs macro.
 */
#define radeon_init(rdev) (rdev)->asic->init((rdev))
#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
 
/* Common functions */
/* AGP */
extern int radeon_gpu_reset(struct radeon_device *rdev);
extern void radeon_agp_disable(struct radeon_device *rdev);
extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
extern void radeon_gart_restore(struct radeon_device *rdev);
extern int radeon_modeset_init(struct radeon_device *rdev);
extern void radeon_modeset_fini(struct radeon_device *rdev);
extern bool radeon_card_posted(struct radeon_device *rdev);
extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
extern void radeon_update_display_priority(struct radeon_device *rdev);
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
extern void radeon_scratch_init(struct radeon_device *rdev);
extern void radeon_wb_fini(struct radeon_device *rdev);
extern int radeon_wb_init(struct radeon_device *rdev);
extern void radeon_wb_disable(struct radeon_device *rdev);
extern void radeon_surface_init(struct radeon_device *rdev);
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
extern int radeon_resume_kms(struct drm_device *dev);
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
 
/*
 * r600 functions used by radeon_encoder.c
 */
extern void r600_hdmi_enable(struct drm_encoder *encoder);
extern void r600_hdmi_disable(struct drm_encoder *encoder);
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
 
extern int ni_init_microcode(struct radeon_device *rdev);
extern int ni_mc_load_microcode(struct radeon_device *rdev);
 
/* radeon_acpi.c */
#if defined(CONFIG_ACPI)
extern int radeon_acpi_init(struct radeon_device *rdev);
#else
static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
#endif
 
#include "radeon_object.h"
 
#define DRM_UDELAY(d)           udelay(d)
 
resource_size_t
drm_get_resource_start(struct drm_device *dev, unsigned int resource);
resource_size_t
drm_get_resource_len(struct drm_device *dev, unsigned int resource);
 
bool set_mode(struct drm_device *dev, struct drm_connector *connector,
              videomode_t *mode, bool strict);
 
 
 
struct work_struct;
typedef void (*work_func_t)(struct work_struct *work);
 
/*
 * The first word is the work queue pointer and the flags rolled into
 * one
 */
#define work_data_bits(work) ((unsigned long *)(&(work)->data))
 
struct work_struct {
        atomic_long_t data;
#define WORK_STRUCT_PENDING 0           /* T if work item pending execution */
#define WORK_STRUCT_FLAG_MASK (3UL)
#define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK)
        struct list_head entry;
        work_func_t func;
};
 
#endif

Rev 2160	Rev 2175
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#ifndef __RADEON_H__	28	#ifndef __RADEON_H__
29	#define __RADEON_H__	29	#define __RADEON_H__
30		30
31	/* TODO: Here are things that needs to be done :	31	/* TODO: Here are things that needs to be done :
32	* - surface allocator & initializer : (bit like scratch reg) should	32	* - surface allocator & initializer : (bit like scratch reg) should
33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings	33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34	* related to surface	34	* related to surface
35	* - WB : write back stuff (do it bit like scratch reg things)	35	* - WB : write back stuff (do it bit like scratch reg things)
36	* - Vblank : look at Jesse's rework and what we should do	36	* - Vblank : look at Jesse's rework and what we should do
37	* - r600/r700: gart & cp	37	* - r600/r700: gart & cp
38	* - cs : clean cs ioctl use bitmap & things like that.	38	* - cs : clean cs ioctl use bitmap & things like that.
39	* - power management stuff	39	* - power management stuff
40	* - Barrier in gart code	40	* - Barrier in gart code
41	* - Unmappabled vram ?	41	* - Unmappabled vram ?
42	* - TESTING, TESTING, TESTING	42	* - TESTING, TESTING, TESTING
43	*/	43	*/
44		44
45	/* Initialization path:	45	/* Initialization path:
46	* We expect that acceleration initialization might fail for various	46	* We expect that acceleration initialization might fail for various
47	* reasons even thought we work hard to make it works on most	47	* reasons even thought we work hard to make it works on most
48	* configurations. In order to still have a working userspace in such	48	* configurations. In order to still have a working userspace in such
49	* situation the init path must succeed up to the memory controller	49	* situation the init path must succeed up to the memory controller
50	* initialization point. Failure before this point are considered as	50	* initialization point. Failure before this point are considered as
51	* fatal error. Here is the init callchain :	51	* fatal error. Here is the init callchain :
52	* radeon_device_init perform common structure, mutex initialization	52	* radeon_device_init perform common structure, mutex initialization
53	* asic_init setup the GPU memory layout and perform all	53	* asic_init setup the GPU memory layout and perform all
54	* one time initialization (failure in this	54	* one time initialization (failure in this
55	* function are considered fatal)	55	* function are considered fatal)
56	* asic_startup setup the GPU acceleration, in order to	56	* asic_startup setup the GPU acceleration, in order to
57	* follow guideline the first thing this	57	* follow guideline the first thing this
58	* function should do is setting the GPU	58	* function should do is setting the GPU
59	* memory controller (only MC setup failure	59	* memory controller (only MC setup failure
60	* are considered as fatal)	60	* are considered as fatal)
61	*/	61	*/
62		62
63	#include	63	#include
64		64
65	#include	65	#include
66	#include	66	#include
67		67
68	#include	68	#include
69	#include	69	#include
70	#include	70	#include
71	#include	71	#include
72		72
73	#include	73	#include
74	#include	74	#include
75		75
76	#include	76	#include
77	#include "drm_edid.h"	77	#include "drm_edid.h"
78		78
79	#include "radeon_family.h"	79	#include "radeon_family.h"
80	#include "radeon_mode.h"	80	#include "radeon_mode.h"
81	#include "radeon_reg.h"	81	#include "radeon_reg.h"
82		82
83	#include	83	#include
84		84
85	extern unsigned long volatile jiffies;	85	extern unsigned long volatile jiffies;
86		86
87	/*	87	/*
88	* Modules parameters.	88	* Modules parameters.
89	*/	89	*/
90	extern int radeon_no_wb;	90	extern int radeon_no_wb;
91	extern int radeon_modeset;	91	extern int radeon_modeset;
92	extern int radeon_dynclks;	92	extern int radeon_dynclks;
93	extern int radeon_r4xx_atom;	93	extern int radeon_r4xx_atom;
94	extern int radeon_agpmode;	94	extern int radeon_agpmode;
95	extern int radeon_vram_limit;	95	extern int radeon_vram_limit;
96	extern int radeon_gart_size;	96	extern int radeon_gart_size;
97	extern int radeon_benchmarking;	97	extern int radeon_benchmarking;
98	extern int radeon_testing;	98	extern int radeon_testing;
99	extern int radeon_connector_table;	99	extern int radeon_connector_table;
100	extern int radeon_tv;	100	extern int radeon_tv;
101	extern int radeon_audio;	101	extern int radeon_audio;
102	extern int radeon_disp_priority;	102	extern int radeon_disp_priority;
103	extern int radeon_hw_i2c;	103	extern int radeon_hw_i2c;
104	extern int radeon_pcie_gen2;	104	extern int radeon_pcie_gen2;
105	typedef struct pm_message {	105	typedef struct pm_message {
106	int event;	106	int event;
107	} pm_message_t;	107	} pm_message_t;
108		108
109	typedef struct	109	typedef struct
110	{	110	{
111	int width;	111	int width;
112	int height;	112	int height;
113	int bpp;	113	int bpp;
114	int freq;	114	int freq;
115	}videomode_t;	115	}videomode_t;
116		116
117	static inline uint8_t __raw_readb(const volatile void __iomem *addr)	117	static inline uint8_t __raw_readb(const volatile void __iomem *addr)
118	{	118	{
119	return (const volatile uint8_t __force ) addr;	119	return (const volatile uint8_t __force ) addr;
120	}	120	}
121		121
122	static inline uint16_t __raw_readw(const volatile void __iomem *addr)	122	static inline uint16_t __raw_readw(const volatile void __iomem *addr)
123	{	123	{
124	return (const volatile uint16_t __force ) addr;	124	return (const volatile uint16_t __force ) addr;
125	}	125	}
126		126
127	static inline uint32_t __raw_readl(const volatile void __iomem *addr)	127	static inline uint32_t __raw_readl(const volatile void __iomem *addr)
128	{	128	{
129	return (const volatile uint32_t __force ) addr;	129	return (const volatile uint32_t __force ) addr;
130	}	130	}
131		131
132	#define readb __raw_readb	132	#define readb __raw_readb
133	#define readw __raw_readw	133	#define readw __raw_readw
134	#define readl __raw_readl	134	#define readl __raw_readl
135		135
136		136
137		137
138	static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)	138	static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
139	{	139	{
140	(volatile uint8_t __force ) addr = b;	140	(volatile uint8_t __force ) addr = b;
141	}	141	}
142		142
143	static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)	143	static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
144	{	144	{
145	(volatile uint16_t __force ) addr = b;	145	(volatile uint16_t __force ) addr = b;
146	}	146	}
147		147
148	static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)	148	static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
149	{	149	{
150	(volatile uint32_t __force ) addr = b;	150	(volatile uint32_t __force ) addr = b;
151	}	151	}
152		152
153	static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)	153	static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
154	{	154	{
155	(volatile __u64 )addr = b;	155	(volatile __u64 )addr = b;
156	}	156	}
157		157
158	#define writeb __raw_writeb	158	#define writeb __raw_writeb
159	#define writew __raw_writew	159	#define writew __raw_writew
160	#define writel __raw_writel	160	#define writel __raw_writel
161	#define writeq __raw_writeq	161	#define writeq __raw_writeq
162		162
163		163
164	static inline u32 ioread32(const volatile void __iomem *addr)	164	static inline u32 ioread32(const volatile void __iomem *addr)
165	{	165	{
166	return in32((u32)addr);	166	return in32((u32)addr);
167	}	167	}
168		168
169	static inline void iowrite32(uint32_t b, volatile void __iomem *addr)	169	static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
170	{	170	{
171	out32((u32)addr, b);	171	out32((u32)addr, b);
172	}	172	}
173		173
174	struct __wait_queue_head {	174	struct __wait_queue_head {
175	spinlock_t lock;	175	spinlock_t lock;
176	struct list_head task_list;	176	struct list_head task_list;
177	};	177	};
178	typedef struct __wait_queue_head wait_queue_head_t;	178	typedef struct __wait_queue_head wait_queue_head_t;
179		179
180		180
181	/*	181	/*
182	* Copy from radeon_drv.h so we don't have to include both and have conflicting	182	* Copy from radeon_drv.h so we don't have to include both and have conflicting
183	* symbol;	183	* symbol;
184	*/	184	*/
185	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */	185	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
186	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)	186	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
187	/* RADEON_IB_POOL_SIZE must be a power of 2 */	187	/* RADEON_IB_POOL_SIZE must be a power of 2 */
188	#define RADEON_IB_POOL_SIZE 16	188	#define RADEON_IB_POOL_SIZE 16
189	#define RADEON_DEBUGFS_MAX_NUM_FILES 32	189	#define RADEON_DEBUGFS_MAX_NUM_FILES 32
190	#define RADEONFB_CONN_LIMIT 4	190	#define RADEONFB_CONN_LIMIT 4
191	#define RADEON_BIOS_NUM_SCRATCH 8	191	#define RADEON_BIOS_NUM_SCRATCH 8
192		192
193	/*	193	/*
194	* Errata workarounds.	194	* Errata workarounds.
195	*/	195	*/
196	enum radeon_pll_errata {	196	enum radeon_pll_errata {
197	CHIP_ERRATA_R300_CG = 0x00000001,	197	CHIP_ERRATA_R300_CG = 0x00000001,
198	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,	198	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
199	CHIP_ERRATA_PLL_DELAY = 0x00000004	199	CHIP_ERRATA_PLL_DELAY = 0x00000004
200	};	200	};
201		201
202		202
203	struct radeon_device;	203	struct radeon_device;
204		204
205		205
206	/*	206	/*
207	* BIOS.	207	* BIOS.
208	*/	208	*/
209	#define ATRM_BIOS_PAGE 4096	209	#define ATRM_BIOS_PAGE 4096
210		210
211	#if defined(CONFIG_VGA_SWITCHEROO)	211	#if defined(CONFIG_VGA_SWITCHEROO)
212	bool radeon_atrm_supported(struct pci_dev *pdev);	212	bool radeon_atrm_supported(struct pci_dev *pdev);
213	int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);	213	int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
214	#else	214	#else
215	static inline bool radeon_atrm_supported(struct pci_dev *pdev)	215	static inline bool radeon_atrm_supported(struct pci_dev *pdev)
216	{	216	{
217	return false;	217	return false;
218	}	218	}
219		219
220	static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){	220	static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
221	return -EINVAL;	221	return -EINVAL;
222	}	222	}
223	#endif	223	#endif
224	bool radeon_get_bios(struct radeon_device *rdev);	224	bool radeon_get_bios(struct radeon_device *rdev);
225		225
226		226
227	/*	227	/*
228	* Dummy page	228	* Dummy page
229	*/	229	*/
230	struct radeon_dummy_page {	230	struct radeon_dummy_page {
231	struct page *page;	231	struct page *page;
232	dma_addr_t addr;	232	dma_addr_t addr;
233	};	233	};
234	int radeon_dummy_page_init(struct radeon_device *rdev);	234	int radeon_dummy_page_init(struct radeon_device *rdev);
235	void radeon_dummy_page_fini(struct radeon_device *rdev);	235	void radeon_dummy_page_fini(struct radeon_device *rdev);
236		236
237		237
238	/*	238	/*
239	* Clocks	239	* Clocks
240	*/	240	*/
241	struct radeon_clock {	241	struct radeon_clock {
242	struct radeon_pll p1pll;	242	struct radeon_pll p1pll;
243	struct radeon_pll p2pll;	243	struct radeon_pll p2pll;
244	struct radeon_pll dcpll;	244	struct radeon_pll dcpll;
245	struct radeon_pll spll;	245	struct radeon_pll spll;
246	struct radeon_pll mpll;	246	struct radeon_pll mpll;
247	/* 10 Khz units */	247	/* 10 Khz units */
248	uint32_t default_mclk;	248	uint32_t default_mclk;
249	uint32_t default_sclk;	249	uint32_t default_sclk;
250	uint32_t default_dispclk;	250	uint32_t default_dispclk;
251	uint32_t dp_extclk;	251	uint32_t dp_extclk;
252	uint32_t max_pixel_clock;	252	uint32_t max_pixel_clock;
253	};	253	};
254		254
255	/*	255	/*
256	* Power management	256	* Power management
257	*/	257	*/
258	int radeon_pm_init(struct radeon_device *rdev);	258	int radeon_pm_init(struct radeon_device *rdev);
259	void radeon_pm_fini(struct radeon_device *rdev);	259	void radeon_pm_fini(struct radeon_device *rdev);
260	void radeon_pm_compute_clocks(struct radeon_device *rdev);	260	void radeon_pm_compute_clocks(struct radeon_device *rdev);
261	void radeon_pm_suspend(struct radeon_device *rdev);	261	void radeon_pm_suspend(struct radeon_device *rdev);
262	void radeon_pm_resume(struct radeon_device *rdev);	262	void radeon_pm_resume(struct radeon_device *rdev);
263	void radeon_combios_get_power_modes(struct radeon_device *rdev);	263	void radeon_combios_get_power_modes(struct radeon_device *rdev);
264	void radeon_atombios_get_power_modes(struct radeon_device *rdev);	264	void radeon_atombios_get_power_modes(struct radeon_device *rdev);
265	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);	265	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
266	int radeon_atom_get_max_vddc(struct radeon_device rdev, u16 voltage);	266	int radeon_atom_get_max_vddc(struct radeon_device rdev, u16 voltage);
267	void rs690_pm_info(struct radeon_device *rdev);	267	void rs690_pm_info(struct radeon_device *rdev);
268	extern int rv6xx_get_temp(struct radeon_device *rdev);	268	extern int rv6xx_get_temp(struct radeon_device *rdev);
269	extern int rv770_get_temp(struct radeon_device *rdev);	269	extern int rv770_get_temp(struct radeon_device *rdev);
270	extern int evergreen_get_temp(struct radeon_device *rdev);	270	extern int evergreen_get_temp(struct radeon_device *rdev);
271	extern int sumo_get_temp(struct radeon_device *rdev);	271	extern int sumo_get_temp(struct radeon_device *rdev);
272		272
273	/*	273	/*
274	* Fences.	274	* Fences.
275	*/	275	*/
276	struct radeon_fence_driver {	276	struct radeon_fence_driver {
277	uint32_t scratch_reg;	277	uint32_t scratch_reg;
278	atomic_t seq;	278	atomic_t seq;
279	uint32_t last_seq;	279	uint32_t last_seq;
280	unsigned long last_jiffies;	280	unsigned long last_jiffies;
281	unsigned long last_timeout;	281	unsigned long last_timeout;
282	wait_queue_head_t queue;	282	wait_queue_head_t queue;
283	rwlock_t lock;	283	rwlock_t lock;
284	struct list_head created;	284	struct list_head created;
285	struct list_head emited;	285	struct list_head emited;
286	struct list_head signaled;	286	struct list_head signaled;
287	bool initialized;	287	bool initialized;
288	};	288	};
289		289
290	struct radeon_fence {	290	struct radeon_fence {
291	struct radeon_device *rdev;	291	struct radeon_device *rdev;
292	struct kref kref;	292	struct kref kref;
293	struct list_head list;	293	struct list_head list;
294	/* protected by radeon_fence.lock */	294	/* protected by radeon_fence.lock */
295	uint32_t seq;	295	uint32_t seq;
296	bool emited;	296	bool emited;
297	bool signaled;	297	bool signaled;
298	evhandle_t evnt;	298	evhandle_t evnt;
299	};	299	};
300		300
301	int radeon_fence_driver_init(struct radeon_device *rdev);	301	int radeon_fence_driver_init(struct radeon_device *rdev);
302	void radeon_fence_driver_fini(struct radeon_device *rdev);	302	void radeon_fence_driver_fini(struct radeon_device *rdev);
303	int radeon_fence_create(struct radeon_device rdev, struct radeon_fence *fence);	303	int radeon_fence_create(struct radeon_device rdev, struct radeon_fence *fence);
304	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence fence);	304	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence fence);
305	void radeon_fence_process(struct radeon_device *rdev);	305	void radeon_fence_process(struct radeon_device *rdev);
306	bool radeon_fence_signaled(struct radeon_fence *fence);	306	bool radeon_fence_signaled(struct radeon_fence *fence);
307	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);	307	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
308	int radeon_fence_wait_next(struct radeon_device *rdev);	308	int radeon_fence_wait_next(struct radeon_device *rdev);
309	int radeon_fence_wait_last(struct radeon_device *rdev);	309	int radeon_fence_wait_last(struct radeon_device *rdev);
310	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);	310	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
311	void radeon_fence_unref(struct radeon_fence **fence);	311	void radeon_fence_unref(struct radeon_fence **fence);
312		312
313	/*	313	/*
314	* Tiling registers	314	* Tiling registers
315	*/	315	*/
316	struct radeon_surface_reg {	316	struct radeon_surface_reg {
317	struct radeon_bo *bo;	317	struct radeon_bo *bo;
318	};	318	};
319		319
320	#define RADEON_GEM_MAX_SURFACES 8	320	#define RADEON_GEM_MAX_SURFACES 8
321		321
322	/*	322	/*
323	* TTM.	323	* TTM.
324	*/	324	*/
325	struct radeon_mman {	325	struct radeon_mman {
326	struct ttm_bo_global_ref bo_global_ref;	326	struct ttm_bo_global_ref bo_global_ref;
327	// struct drm_global_reference mem_global_ref;	327	// struct drm_global_reference mem_global_ref;
328	struct ttm_bo_device bdev;	328	struct ttm_bo_device bdev;
329	bool mem_global_referenced;	329	bool mem_global_referenced;
330	bool initialized;	330	bool initialized;
331	};	331	};
332		332
333	struct radeon_bo {	333	struct radeon_bo {
334	/* Protected by gem.mutex */	334	/* Protected by gem.mutex */
335	struct list_head list;	335	struct list_head list;
336	/* Protected by tbo.reserved */	336	/* Protected by tbo.reserved */
337	u32 placements[3];	337	u32 placements[3];
338	struct ttm_placement placement;	338	struct ttm_placement placement;
339	struct ttm_buffer_object tbo;	339	struct ttm_buffer_object tbo;
340	struct ttm_bo_kmap_obj kmap;	340	struct ttm_bo_kmap_obj kmap;
341	unsigned pin_count;	341	unsigned pin_count;
342	void *kptr;	342	void *kptr;
343	void *uptr;	343	void *uptr;
344	u32 cpu_addr;	344	u32 cpu_addr;
345	u32 tiling_flags;	345	u32 tiling_flags;
346	u32 pitch;	346	u32 pitch;
347	int surface_reg;	347	int surface_reg;
348	/* Constant after initialization */	348	/* Constant after initialization */
349	struct radeon_device *rdev;	349	struct radeon_device *rdev;
350	struct drm_gem_object gem_base;	350	struct drm_gem_object gem_base;
351	u32 domain;	351	u32 domain;
352	};	352	};
353	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)	353	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
354		354
355	struct radeon_bo_list {	355	struct radeon_bo_list {
356	struct radeon_bo *bo;	356	struct radeon_bo *bo;
357	uint64_t gpu_offset;	357	uint64_t gpu_offset;
358	unsigned rdomain;	358	unsigned rdomain;
359	unsigned wdomain;	359	unsigned wdomain;
360	u32 tiling_flags;	360	u32 tiling_flags;
361	};	361	};
362		362
363	/*	363	/*
364	* GEM objects.	364	* GEM objects.
365	*/	365	*/
366	struct radeon_gem {	366	struct radeon_gem {
367	struct mutex mutex;	367	struct mutex mutex;
368	struct list_head objects;	368	struct list_head objects;
369	};	369	};
370		370
371	int radeon_gem_init(struct radeon_device *rdev);	371	int radeon_gem_init(struct radeon_device *rdev);
372	void radeon_gem_fini(struct radeon_device *rdev);	372	void radeon_gem_fini(struct radeon_device *rdev);
373	int radeon_gem_object_create(struct radeon_device *rdev, int size,	373	int radeon_gem_object_create(struct radeon_device *rdev, int size,
374	int alignment, int initial_domain,	374	int alignment, int initial_domain,
375	bool discardable, bool kernel,	375	bool discardable, bool kernel,
376	struct drm_gem_object **obj);	376	struct drm_gem_object **obj);
377	int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,	377	int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
378	uint64_t *gpu_addr);	378	uint64_t *gpu_addr);
379	void radeon_gem_object_unpin(struct drm_gem_object *obj);	379	void radeon_gem_object_unpin(struct drm_gem_object *obj);
380		380
381	int radeon_mode_dumb_create(struct drm_file *file_priv,	381	int radeon_mode_dumb_create(struct drm_file *file_priv,
382	struct drm_device *dev,	382	struct drm_device *dev,
383	struct drm_mode_create_dumb *args);	383	struct drm_mode_create_dumb *args);
384	int radeon_mode_dumb_mmap(struct drm_file *filp,	384	int radeon_mode_dumb_mmap(struct drm_file *filp,
385	struct drm_device *dev,	385	struct drm_device *dev,
386	uint32_t handle, uint64_t *offset_p);	386	uint32_t handle, uint64_t *offset_p);
387	int radeon_mode_dumb_destroy(struct drm_file *file_priv,	387	int radeon_mode_dumb_destroy(struct drm_file *file_priv,
388	struct drm_device *dev,	388	struct drm_device *dev,
389	uint32_t handle);	389	uint32_t handle);
390		390
391	/*	391	/*
392	* GART structures, functions & helpers	392	* GART structures, functions & helpers
393	*/	393	*/
394	struct radeon_mc;	394	struct radeon_mc;
395		395
396	struct radeon_gart_table_ram {	396	struct radeon_gart_table_ram {
397	volatile uint32_t *ptr;	397	volatile uint32_t *ptr;
398	};	398	};
399		399
400	struct radeon_gart_table_vram {	400	struct radeon_gart_table_vram {
401	struct radeon_bo *robj;	401	struct radeon_bo *robj;
402	volatile uint32_t *ptr;	402	volatile uint32_t *ptr;
403	};	403	};
404		404
405	union radeon_gart_table {	405	union radeon_gart_table {
406	struct radeon_gart_table_ram ram;	406	struct radeon_gart_table_ram ram;
407	struct radeon_gart_table_vram vram;	407	struct radeon_gart_table_vram vram;
408	};	408	};
409		409
410	#define RADEON_GPU_PAGE_SIZE 4096	410	#define RADEON_GPU_PAGE_SIZE 4096
411	#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)	411	#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
412		412
413	struct radeon_gart {	413	struct radeon_gart {
414	dma_addr_t table_addr;	414	dma_addr_t table_addr;
415	unsigned num_gpu_pages;	415	unsigned num_gpu_pages;
416	unsigned num_cpu_pages;	416	unsigned num_cpu_pages;
417	unsigned table_size;	417	unsigned table_size;
418	union radeon_gart_table table;	418	union radeon_gart_table table;
419	struct page **pages;	419	struct page **pages;
420	dma_addr_t *pages_addr;	420	dma_addr_t *pages_addr;
421	bool *ttm_alloced;	421	bool *ttm_alloced;
422	bool ready;	422	bool ready;
423	};	423	};
424		424
425	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);	425	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
426	void radeon_gart_table_ram_free(struct radeon_device *rdev);	426	void radeon_gart_table_ram_free(struct radeon_device *rdev);
427	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);	427	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
428	void radeon_gart_table_vram_free(struct radeon_device *rdev);	428	void radeon_gart_table_vram_free(struct radeon_device *rdev);
429	int radeon_gart_init(struct radeon_device *rdev);	429	int radeon_gart_init(struct radeon_device *rdev);
430	void radeon_gart_fini(struct radeon_device *rdev);	430	void radeon_gart_fini(struct radeon_device *rdev);
431	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,	431	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
432	int pages);	432	int pages);
433	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,	433	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
434	int pages, u32_t *pagelist);	434	int pages, u32_t *pagelist);
435		435
436		436
437	/*	437	/*
438	* GPU MC structures, functions & helpers	438	* GPU MC structures, functions & helpers
439	*/	439	*/
440	struct radeon_mc {	440	struct radeon_mc {
441	resource_size_t aper_size;	441	resource_size_t aper_size;
442	resource_size_t aper_base;	442	resource_size_t aper_base;
443	resource_size_t agp_base;	443	resource_size_t agp_base;
444	/* for some chips with <= 32MB we need to lie	444	/* for some chips with <= 32MB we need to lie
445	* about vram size near mc fb location */	445	* about vram size near mc fb location */
446	u64 mc_vram_size;	446	u64 mc_vram_size;
447	u64 visible_vram_size;	447	u64 visible_vram_size;
448	u64 gtt_size;	448	u64 gtt_size;
449	u64 gtt_start;	449	u64 gtt_start;
450	u64 gtt_end;	450	u64 gtt_end;
451	u64 vram_start;	451	u64 vram_start;
452	u64 vram_end;	452	u64 vram_end;
453	unsigned vram_width;	453	unsigned vram_width;
454	u64 real_vram_size;	454	u64 real_vram_size;
455	int vram_mtrr;	455	int vram_mtrr;
456	bool vram_is_ddr;	456	bool vram_is_ddr;
457	bool igp_sideport_enabled;	457	bool igp_sideport_enabled;
458	u64 gtt_base_align;	458	u64 gtt_base_align;
459	};	459	};
460		460
461	bool radeon_combios_sideport_present(struct radeon_device *rdev);	461	bool radeon_combios_sideport_present(struct radeon_device *rdev);
462	bool radeon_atombios_sideport_present(struct radeon_device *rdev);	462	bool radeon_atombios_sideport_present(struct radeon_device *rdev);
463		463
464	/*	464	/*
465	* GPU scratch registers structures, functions & helpers	465	* GPU scratch registers structures, functions & helpers
466	*/	466	*/
467	struct radeon_scratch {	467	struct radeon_scratch {
468	unsigned num_reg;	468	unsigned num_reg;
469	uint32_t reg_base;	469	uint32_t reg_base;
470	bool free[32];	470	bool free[32];
471	uint32_t reg[32];	471	uint32_t reg[32];
472	};	472	};
473		473
474	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);	474	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);
475	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);	475	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
476		476
477		477
478	/*	478	/*
479	* IRQS.	479	* IRQS.
480	*/	480	*/
481	struct r500_irq_stat_regs {	481	struct r500_irq_stat_regs {
482	u32 disp_int;	482	u32 disp_int;
483	};	483	};
484		484
485	struct r600_irq_stat_regs {	485	struct r600_irq_stat_regs {
486	u32 disp_int;	486	u32 disp_int;
487	u32 disp_int_cont;	487	u32 disp_int_cont;
488	u32 disp_int_cont2;	488	u32 disp_int_cont2;
489	u32 d1grph_int;	489	u32 d1grph_int;
490	u32 d2grph_int;	490	u32 d2grph_int;
491	};	491	};
492		492
493	struct evergreen_irq_stat_regs {	493	struct evergreen_irq_stat_regs {
494	u32 disp_int;	494	u32 disp_int;
495	u32 disp_int_cont;	495	u32 disp_int_cont;
496	u32 disp_int_cont2;	496	u32 disp_int_cont2;
497	u32 disp_int_cont3;	497	u32 disp_int_cont3;
498	u32 disp_int_cont4;	498	u32 disp_int_cont4;
499	u32 disp_int_cont5;	499	u32 disp_int_cont5;
500	u32 d1grph_int;	500	u32 d1grph_int;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon.h – Rev 2160 → 2175