Rev 1630 | Rev 2004 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1630 | Rev 1963 | ||
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Line 58... | Line 58... | ||
58 | * function should do is setting the GPU |
58 | * function should do is setting the GPU |
59 | * memory controller (only MC setup failure |
59 | * memory controller (only MC setup failure |
60 | * are considered as fatal) |
60 | * are considered as fatal) |
61 | */ |
61 | */ |
Line 62... | Line -... | ||
62 | - | ||
63 | #include |
62 | |
Line 64... | Line 63... | ||
64 | #include |
63 | #include |
65 | 64 | ||
Line 81... | Line 80... | ||
81 | #include "radeon_mode.h" |
80 | #include "radeon_mode.h" |
82 | #include "radeon_reg.h" |
81 | #include "radeon_reg.h" |
Line 83... | Line 82... | ||
83 | 82 | ||
Line -... | Line 83... | ||
- | 83 | #include |
|
- | 84 | ||
84 | #include |
85 | extern unsigned long volatile jiffies; |
85 | 86 | ||
86 | /* |
87 | /* |
87 | * Modules parameters. |
88 | * Modules parameters. |
88 | */ |
89 | */ |
Line 95... | Line 96... | ||
95 | extern int radeon_gart_size; |
96 | extern int radeon_gart_size; |
96 | extern int radeon_benchmarking; |
97 | extern int radeon_benchmarking; |
97 | extern int radeon_testing; |
98 | extern int radeon_testing; |
98 | extern int radeon_connector_table; |
99 | extern int radeon_connector_table; |
99 | extern int radeon_tv; |
100 | extern int radeon_tv; |
100 | extern int radeon_new_pll; |
- | |
101 | extern int radeon_dynpm; |
- | |
102 | extern int radeon_audio; |
101 | extern int radeon_audio; |
103 | - | ||
- | 102 | extern int radeon_disp_priority; |
|
- | 103 | extern int radeon_hw_i2c; |
|
- | 104 | extern int radeon_pcie_gen2; |
|
104 | typedef struct pm_message { |
105 | typedef struct pm_message { |
105 | int event; |
106 | int event; |
106 | } pm_message_t; |
107 | } pm_message_t; |
Line 107... | Line 108... | ||
107 | 108 | ||
Line 158... | Line 159... | ||
158 | #define writew __raw_writew |
159 | #define writew __raw_writew |
159 | #define writel __raw_writel |
160 | #define writel __raw_writel |
160 | #define writeq __raw_writeq |
161 | #define writeq __raw_writeq |
Line -... | Line 162... | ||
- | 162 | ||
- | 163 | ||
- | 164 | static inline u32 ioread32(const volatile void __iomem *addr) |
|
- | 165 | { |
|
- | 166 | return in32((u32)addr); |
|
- | 167 | } |
|
- | 168 | ||
- | 169 | static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
|
- | 170 | { |
|
- | 171 | out32((u32)addr, b); |
|
- | 172 | } |
|
- | 173 | ||
- | 174 | struct __wait_queue_head { |
|
- | 175 | spinlock_t lock; |
|
- | 176 | struct list_head task_list; |
|
- | 177 | }; |
|
- | 178 | typedef struct __wait_queue_head wait_queue_head_t; |
|
161 | 179 | ||
162 | 180 | ||
163 | /* |
181 | /* |
164 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
182 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
165 | * symbol; |
183 | * symbol; |
- | 184 | */ |
|
166 | */ |
185 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
167 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
186 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
168 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
187 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
169 | #define RADEON_IB_POOL_SIZE 16 |
188 | #define RADEON_IB_POOL_SIZE 16 |
170 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
189 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
Line 228... | Line 247... | ||
228 | /* 10 Khz units */ |
247 | /* 10 Khz units */ |
229 | uint32_t default_mclk; |
248 | uint32_t default_mclk; |
230 | uint32_t default_sclk; |
249 | uint32_t default_sclk; |
231 | uint32_t default_dispclk; |
250 | uint32_t default_dispclk; |
232 | uint32_t dp_extclk; |
251 | uint32_t dp_extclk; |
- | 252 | uint32_t max_pixel_clock; |
|
233 | }; |
253 | }; |
Line 234... | Line 254... | ||
234 | 254 | ||
235 | /* |
255 | /* |
236 | * Power management |
256 | * Power management |
237 | */ |
257 | */ |
- | 258 | int radeon_pm_init(struct radeon_device *rdev); |
|
238 | int radeon_pm_init(struct radeon_device *rdev); |
259 | void radeon_pm_fini(struct radeon_device *rdev); |
- | 260 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
|
- | 261 | void radeon_pm_suspend(struct radeon_device *rdev); |
|
239 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
262 | void radeon_pm_resume(struct radeon_device *rdev); |
240 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
263 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
- | 264 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
|
- | 265 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
|
- | 266 | void rs690_pm_info(struct radeon_device *rdev); |
|
- | 267 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
|
- | 268 | extern int rv770_get_temp(struct radeon_device *rdev); |
|
- | 269 | extern int evergreen_get_temp(struct radeon_device *rdev); |
|
Line 241... | Line 270... | ||
241 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
270 | extern int sumo_get_temp(struct radeon_device *rdev); |
242 | 271 | ||
243 | /* |
272 | /* |
244 | * Fences. |
273 | * Fences. |
245 | */ |
274 | */ |
246 | struct radeon_fence_driver { |
275 | struct radeon_fence_driver { |
247 | uint32_t scratch_reg; |
276 | uint32_t scratch_reg; |
- | 277 | atomic_t seq; |
|
248 | atomic_t seq; |
278 | uint32_t last_seq; |
249 | uint32_t last_seq; |
279 | unsigned long last_jiffies; |
250 | unsigned long count_timeout; |
280 | unsigned long last_timeout; |
251 | // wait_queue_head_t queue; |
281 | wait_queue_head_t queue; |
252 | rwlock_t lock; |
282 | rwlock_t lock; |
253 | struct list_head created; |
283 | struct list_head created; |
254 | struct list_head emited; |
284 | struct list_head emited; |
Line 260... | Line 290... | ||
260 | struct radeon_device *rdev; |
290 | struct radeon_device *rdev; |
261 | struct kref kref; |
291 | struct kref kref; |
262 | struct list_head list; |
292 | struct list_head list; |
263 | /* protected by radeon_fence.lock */ |
293 | /* protected by radeon_fence.lock */ |
264 | uint32_t seq; |
294 | uint32_t seq; |
265 | unsigned long timeout; |
- | |
266 | bool emited; |
295 | bool emited; |
267 | bool signaled; |
296 | bool signaled; |
268 | }; |
297 | }; |
Line 269... | Line 298... | ||
269 | 298 | ||
Line 291... | Line 320... | ||
291 | /* |
320 | /* |
292 | * TTM. |
321 | * TTM. |
293 | */ |
322 | */ |
294 | struct radeon_mman { |
323 | struct radeon_mman { |
295 | struct ttm_bo_global_ref bo_global_ref; |
324 | struct ttm_bo_global_ref bo_global_ref; |
296 | struct ttm_global_reference mem_global_ref; |
325 | // struct drm_global_reference mem_global_ref; |
297 | struct ttm_bo_device bdev; |
326 | struct ttm_bo_device bdev; |
298 | bool mem_global_referenced; |
327 | bool mem_global_referenced; |
299 | bool initialized; |
328 | bool initialized; |
300 | }; |
329 | }; |
Line 313... | Line 342... | ||
313 | u32 tiling_flags; |
342 | u32 tiling_flags; |
314 | u32 pitch; |
343 | u32 pitch; |
315 | int surface_reg; |
344 | int surface_reg; |
316 | /* Constant after initialization */ |
345 | /* Constant after initialization */ |
317 | struct radeon_device *rdev; |
346 | struct radeon_device *rdev; |
318 | struct drm_gem_object *gobj; |
347 | struct drm_gem_object gem_base; |
319 | u32 domain; |
348 | u32 domain; |
320 | }; |
349 | }; |
- | 350 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
|
Line 321... | Line 351... | ||
321 | 351 | ||
322 | struct radeon_bo_list { |
- | |
323 | struct list_head list; |
352 | struct radeon_bo_list { |
324 | struct radeon_bo *bo; |
353 | struct radeon_bo *bo; |
325 | uint64_t gpu_offset; |
354 | uint64_t gpu_offset; |
326 | unsigned rdomain; |
355 | unsigned rdomain; |
327 | unsigned wdomain; |
356 | unsigned wdomain; |
Line 375... | Line 404... | ||
375 | unsigned num_cpu_pages; |
404 | unsigned num_cpu_pages; |
376 | unsigned table_size; |
405 | unsigned table_size; |
377 | union radeon_gart_table table; |
406 | union radeon_gart_table table; |
378 | struct page **pages; |
407 | struct page **pages; |
379 | dma_addr_t *pages_addr; |
408 | dma_addr_t *pages_addr; |
- | 409 | bool *ttm_alloced; |
|
380 | bool ready; |
410 | bool ready; |
381 | }; |
411 | }; |
Line 382... | Line 412... | ||
382 | 412 | ||
383 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
413 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
Line 411... | Line 441... | ||
411 | unsigned vram_width; |
441 | unsigned vram_width; |
412 | u64 real_vram_size; |
442 | u64 real_vram_size; |
413 | int vram_mtrr; |
443 | int vram_mtrr; |
414 | bool vram_is_ddr; |
444 | bool vram_is_ddr; |
415 | bool igp_sideport_enabled; |
445 | bool igp_sideport_enabled; |
- | 446 | u64 gtt_base_align; |
|
416 | }; |
447 | }; |
Line 417... | Line 448... | ||
417 | 448 | ||
418 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
449 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
Line 419... | Line 450... | ||
419 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
450 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
420 | 451 | ||
421 | /* |
452 | /* |
422 | * GPU scratch registers structures, functions & helpers |
453 | * GPU scratch registers structures, functions & helpers |
423 | */ |
454 | */ |
- | 455 | struct radeon_scratch { |
|
424 | struct radeon_scratch { |
456 | unsigned num_reg; |
425 | unsigned num_reg; |
457 | uint32_t reg_base; |
426 | bool free[32]; |
458 | bool free[32]; |
Line 427... | Line 459... | ||
427 | uint32_t reg[32]; |
459 | uint32_t reg[32]; |
Line 432... | Line 464... | ||
432 | 464 | ||
433 | 465 | ||
434 | /* |
466 | /* |
- | 467 | * IRQS. |
|
- | 468 | */ |
|
- | 469 | struct r500_irq_stat_regs { |
|
- | 470 | u32 disp_int; |
|
- | 471 | }; |
|
- | 472 | ||
- | 473 | struct r600_irq_stat_regs { |
|
- | 474 | u32 disp_int; |
|
- | 475 | u32 disp_int_cont; |
|
- | 476 | u32 disp_int_cont2; |
|
- | 477 | u32 d1grph_int; |
|
- | 478 | u32 d2grph_int; |
|
- | 479 | }; |
|
- | 480 | ||
- | 481 | struct evergreen_irq_stat_regs { |
|
- | 482 | u32 disp_int; |
|
- | 483 | u32 disp_int_cont; |
|
- | 484 | u32 disp_int_cont2; |
|
- | 485 | u32 disp_int_cont3; |
|
- | 486 | u32 disp_int_cont4; |
|
- | 487 | u32 disp_int_cont5; |
|
- | 488 | u32 d1grph_int; |
|
- | 489 | u32 d2grph_int; |
|
- | 490 | u32 d3grph_int; |
|
- | 491 | u32 d4grph_int; |
|
- | 492 | u32 d5grph_int; |
|
- | 493 | u32 d6grph_int; |
|
- | 494 | }; |
|
- | 495 | ||
- | 496 | union radeon_irq_stat_regs { |
|
- | 497 | struct r500_irq_stat_regs r500; |
|
- | 498 | struct r600_irq_stat_regs r600; |
|
- | 499 | struct evergreen_irq_stat_regs evergreen; |
|
435 | * IRQS. |
500 | }; |
436 | */ |
501 | |
437 | struct radeon_irq { |
502 | struct radeon_irq { |
438 | bool installed; |
503 | bool installed; |
439 | bool sw_int; |
504 | bool sw_int; |
- | 505 | /* FIXME: use a define max crtc rather than hardcode it */ |
|
- | 506 | bool crtc_vblank_int[6]; |
|
440 | /* FIXME: use a define max crtc rather than hardcode it */ |
507 | bool pflip[6]; |
441 | bool crtc_vblank_int[2]; |
508 | wait_queue_head_t vblank_queue; |
- | 509 | /* FIXME: use defines for max hpd/dacs */ |
|
- | 510 | bool hpd[6]; |
|
- | 511 | bool gui_idle; |
|
- | 512 | bool gui_idle_acked; |
|
- | 513 | wait_queue_head_t idle_queue; |
|
442 | /* FIXME: use defines for max hpd/dacs */ |
514 | /* FIXME: use defines for max HDMI blocks */ |
443 | bool hpd[6]; |
515 | bool hdmi[2]; |
- | 516 | spinlock_t sw_lock; |
|
- | 517 | int sw_refcount; |
|
- | 518 | union radeon_irq_stat_regs stat_regs; |
|
444 | spinlock_t sw_lock; |
519 | spinlock_t pflip_lock[6]; |
Line 445... | Line 520... | ||
445 | int sw_refcount; |
520 | int pflip_refcount[6]; |
446 | }; |
521 | }; |
447 | 522 | ||
Line 526... | Line 601... | ||
526 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
601 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
527 | int radeon_ib_test(struct radeon_device *rdev); |
602 | int radeon_ib_test(struct radeon_device *rdev); |
528 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
603 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
529 | /* Ring access between begin & end cannot sleep */ |
604 | /* Ring access between begin & end cannot sleep */ |
530 | void radeon_ring_free_size(struct radeon_device *rdev); |
605 | void radeon_ring_free_size(struct radeon_device *rdev); |
- | 606 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
|
531 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
607 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
- | 608 | void radeon_ring_commit(struct radeon_device *rdev); |
|
532 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
609 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
533 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
610 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
534 | int radeon_ring_test(struct radeon_device *rdev); |
611 | int radeon_ring_test(struct radeon_device *rdev); |
535 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
612 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
536 | void radeon_ring_fini(struct radeon_device *rdev); |
613 | void radeon_ring_fini(struct radeon_device *rdev); |
Line 630... | Line 707... | ||
630 | /* |
707 | /* |
631 | * AGP |
708 | * AGP |
632 | */ |
709 | */ |
633 | int radeon_agp_init(struct radeon_device *rdev); |
710 | int radeon_agp_init(struct radeon_device *rdev); |
634 | void radeon_agp_resume(struct radeon_device *rdev); |
711 | void radeon_agp_resume(struct radeon_device *rdev); |
- | 712 | void radeon_agp_suspend(struct radeon_device *rdev); |
|
635 | void radeon_agp_fini(struct radeon_device *rdev); |
713 | void radeon_agp_fini(struct radeon_device *rdev); |
Line 636... | Line 714... | ||
636 | 714 | ||
637 | 715 | ||
638 | /* |
716 | /* |
639 | * Writeback |
717 | * Writeback |
640 | */ |
718 | */ |
641 | struct radeon_wb { |
719 | struct radeon_wb { |
642 | struct radeon_bo *wb_obj; |
720 | struct radeon_bo *wb_obj; |
- | 721 | volatile uint32_t *wb; |
|
- | 722 | uint64_t gpu_addr; |
|
643 | volatile uint32_t *wb; |
723 | bool enabled; |
Line -... | Line 724... | ||
- | 724 | bool use_event; |
|
- | 725 | }; |
|
- | 726 | ||
- | 727 | #define RADEON_WB_SCRATCH_OFFSET 0 |
|
- | 728 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
|
- | 729 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
|
- | 730 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
|
644 | uint64_t gpu_addr; |
731 | #define R600_WB_IH_WPTR_OFFSET 2048 |
645 | }; |
732 | #define R600_WB_EVENT_OFFSET 3072 |
646 | 733 | ||
647 | /** |
734 | /** |
648 | * struct radeon_pm - power management datas |
735 | * struct radeon_pm - power management datas |
Line 653... | Line 740... | ||
653 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
740 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
654 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
741 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
655 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
742 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
656 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
743 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
657 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
744 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
658 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
745 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
659 | * @needed_bandwidth: current bandwidth needs |
746 | * @needed_bandwidth: current bandwidth needs |
660 | * |
747 | * |
661 | * It keeps track of various data needed to take powermanagement decision. |
748 | * It keeps track of various data needed to take powermanagement decision. |
662 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
749 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
663 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
750 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
664 | * (type of memory, bus size, efficiency, ...) |
751 | * (type of memory, bus size, efficiency, ...) |
665 | */ |
752 | */ |
- | 753 | ||
- | 754 | enum radeon_pm_method { |
|
- | 755 | PM_METHOD_PROFILE, |
|
- | 756 | PM_METHOD_DYNPM, |
|
- | 757 | }; |
|
- | 758 | ||
666 | enum radeon_pm_state { |
759 | enum radeon_dynpm_state { |
667 | PM_STATE_DISABLED, |
760 | DYNPM_STATE_DISABLED, |
668 | PM_STATE_MINIMUM, |
761 | DYNPM_STATE_MINIMUM, |
669 | PM_STATE_PAUSED, |
762 | DYNPM_STATE_PAUSED, |
670 | PM_STATE_ACTIVE |
763 | DYNPM_STATE_ACTIVE, |
- | 764 | DYNPM_STATE_SUSPENDED, |
|
671 | }; |
765 | }; |
672 | enum radeon_pm_action { |
766 | enum radeon_dynpm_action { |
673 | PM_ACTION_NONE, |
767 | DYNPM_ACTION_NONE, |
674 | PM_ACTION_MINIMUM, |
768 | DYNPM_ACTION_MINIMUM, |
675 | PM_ACTION_DOWNCLOCK, |
769 | DYNPM_ACTION_DOWNCLOCK, |
676 | PM_ACTION_UPCLOCK |
770 | DYNPM_ACTION_UPCLOCK, |
- | 771 | DYNPM_ACTION_DEFAULT |
|
677 | }; |
772 | }; |
Line 678... | Line 773... | ||
678 | 773 | ||
679 | enum radeon_voltage_type { |
774 | enum radeon_voltage_type { |
680 | VOLTAGE_NONE = 0, |
775 | VOLTAGE_NONE = 0, |
Line 689... | Line 784... | ||
689 | POWER_STATE_TYPE_BATTERY, |
784 | POWER_STATE_TYPE_BATTERY, |
690 | POWER_STATE_TYPE_BALANCED, |
785 | POWER_STATE_TYPE_BALANCED, |
691 | POWER_STATE_TYPE_PERFORMANCE, |
786 | POWER_STATE_TYPE_PERFORMANCE, |
692 | }; |
787 | }; |
Line 693... | Line 788... | ||
693 | 788 | ||
694 | enum radeon_pm_clock_mode_type { |
789 | enum radeon_pm_profile_type { |
- | 790 | PM_PROFILE_DEFAULT, |
|
- | 791 | PM_PROFILE_AUTO, |
|
- | 792 | PM_PROFILE_LOW, |
|
- | 793 | PM_PROFILE_MID, |
|
- | 794 | PM_PROFILE_HIGH, |
|
- | 795 | }; |
|
- | 796 | ||
- | 797 | #define PM_PROFILE_DEFAULT_IDX 0 |
|
- | 798 | #define PM_PROFILE_LOW_SH_IDX 1 |
|
- | 799 | #define PM_PROFILE_MID_SH_IDX 2 |
|
- | 800 | #define PM_PROFILE_HIGH_SH_IDX 3 |
|
- | 801 | #define PM_PROFILE_LOW_MH_IDX 4 |
|
- | 802 | #define PM_PROFILE_MID_MH_IDX 5 |
|
- | 803 | #define PM_PROFILE_HIGH_MH_IDX 6 |
|
- | 804 | #define PM_PROFILE_MAX 7 |
|
- | 805 | ||
- | 806 | struct radeon_pm_profile { |
|
- | 807 | int dpms_off_ps_idx; |
|
- | 808 | int dpms_on_ps_idx; |
|
- | 809 | int dpms_off_cm_idx; |
|
- | 810 | int dpms_on_cm_idx; |
|
- | 811 | }; |
|
- | 812 | ||
695 | POWER_MODE_TYPE_DEFAULT, |
813 | enum radeon_int_thermal_type { |
- | 814 | THERMAL_TYPE_NONE, |
|
- | 815 | THERMAL_TYPE_RV6XX, |
|
- | 816 | THERMAL_TYPE_RV770, |
|
696 | POWER_MODE_TYPE_LOW, |
817 | THERMAL_TYPE_EVERGREEN, |
697 | POWER_MODE_TYPE_MID, |
818 | THERMAL_TYPE_SUMO, |
698 | POWER_MODE_TYPE_HIGH, |
819 | THERMAL_TYPE_NI, |
Line 699... | Line 820... | ||
699 | }; |
820 | }; |
700 | 821 | ||
701 | struct radeon_voltage { |
822 | struct radeon_voltage { |
Line 707... | Line 828... | ||
707 | /* VDDC voltage */ |
828 | /* VDDC voltage */ |
708 | u8 vddc_id; /* index into vddc voltage table */ |
829 | u8 vddc_id; /* index into vddc voltage table */ |
709 | u8 vddci_id; /* index into vddci voltage table */ |
830 | u8 vddci_id; /* index into vddci voltage table */ |
710 | bool vddci_enabled; |
831 | bool vddci_enabled; |
711 | /* r6xx+ sw */ |
832 | /* r6xx+ sw */ |
712 | u32 voltage; |
833 | u16 voltage; |
- | 834 | /* evergreen+ vddci */ |
|
- | 835 | u16 vddci; |
|
713 | }; |
836 | }; |
Line 714... | Line -... | ||
714 | - | ||
715 | struct radeon_pm_non_clock_info { |
837 | |
716 | /* pcie lanes */ |
- | |
717 | int pcie_lanes; |
838 | /* clock mode flags */ |
718 | /* standardized non-clock flags */ |
- | |
719 | u32 flags; |
- | |
Line 720... | Line 839... | ||
720 | }; |
839 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
721 | 840 | ||
722 | struct radeon_pm_clock_info { |
841 | struct radeon_pm_clock_info { |
723 | /* memory clock */ |
842 | /* memory clock */ |
724 | u32 mclk; |
843 | u32 mclk; |
725 | /* engine clock */ |
844 | /* engine clock */ |
726 | u32 sclk; |
845 | u32 sclk; |
727 | /* voltage info */ |
846 | /* voltage info */ |
728 | struct radeon_voltage voltage; |
847 | struct radeon_voltage voltage; |
729 | /* standardized clock flags - not sure we'll need these */ |
848 | /* standardized clock flags */ |
Line -... | Line 849... | ||
- | 849 | u32 flags; |
|
- | 850 | }; |
|
- | 851 | ||
730 | u32 flags; |
852 | /* state flags */ |
731 | }; |
853 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
732 | 854 | ||
733 | struct radeon_power_state { |
855 | struct radeon_power_state { |
734 | enum radeon_pm_state_type type; |
856 | enum radeon_pm_state_type type; |
735 | /* XXX: use a define for num clock modes */ |
857 | /* XXX: use a define for num clock modes */ |
736 | struct radeon_pm_clock_info clock_info[8]; |
858 | struct radeon_pm_clock_info clock_info[8]; |
737 | /* number of valid clock modes in this power state */ |
859 | /* number of valid clock modes in this power state */ |
- | 860 | int num_clock_modes; |
|
738 | int num_clock_modes; |
861 | struct radeon_pm_clock_info *default_clock_mode; |
- | 862 | /* standardized state flags */ |
|
739 | struct radeon_pm_clock_info *default_clock_mode; |
863 | u32 flags; |
740 | /* non clock info about this state */ |
864 | u32 misc; /* vbios specific flags */ |
Line 741... | Line 865... | ||
741 | struct radeon_pm_non_clock_info non_clock_info; |
865 | u32 misc2; /* vbios specific flags */ |
742 | bool voltage_drop_active; |
866 | int pcie_lanes; /* pcie lanes */ |
743 | }; |
867 | }; |
744 | 868 | ||
Line 745... | Line 869... | ||
745 | /* |
869 | /* |
746 | * Some modes are overclocked by very low value, accept them |
870 | * Some modes are overclocked by very low value, accept them |
747 | */ |
- | |
748 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
- | |
749 | - | ||
750 | struct radeon_pm { |
- | |
751 | struct mutex mutex; |
871 | */ |
752 | // struct delayed_work idle_work; |
872 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
753 | enum radeon_pm_state state; |
873 | |
- | 874 | struct radeon_pm { |
|
- | 875 | struct mutex mutex; |
|
754 | enum radeon_pm_action planned_action; |
876 | u32 active_crtcs; |
755 | unsigned long action_timeout; |
877 | int active_crtc_count; |
756 | bool downclocked; |
878 | int req_vblank; |
757 | int active_crtcs; |
879 | bool vblank_sync; |
758 | int req_vblank; |
880 | bool gui_idle; |
759 | fixed20_12 max_bandwidth; |
881 | fixed20_12 max_bandwidth; |
760 | fixed20_12 igp_sideport_mclk; |
882 | fixed20_12 igp_sideport_mclk; |
761 | fixed20_12 igp_system_mclk; |
883 | fixed20_12 igp_system_mclk; |
762 | fixed20_12 igp_ht_link_clk; |
884 | fixed20_12 igp_ht_link_clk; |
763 | fixed20_12 igp_ht_link_width; |
885 | fixed20_12 igp_ht_link_width; |
- | 886 | fixed20_12 k8_bandwidth; |
|
764 | fixed20_12 k8_bandwidth; |
887 | fixed20_12 sideport_bandwidth; |
765 | fixed20_12 sideport_bandwidth; |
- | |
766 | fixed20_12 ht_bandwidth; |
888 | fixed20_12 ht_bandwidth; |
767 | fixed20_12 core_bandwidth; |
889 | fixed20_12 core_bandwidth; |
768 | fixed20_12 sclk; |
890 | fixed20_12 sclk; |
769 | fixed20_12 needed_bandwidth; |
891 | fixed20_12 mclk; |
770 | /* XXX: use a define for num power modes */ |
892 | fixed20_12 needed_bandwidth; |
771 | struct radeon_power_state power_state[8]; |
893 | struct radeon_power_state *power_state; |
772 | /* number of valid power states */ |
894 | /* number of valid power states */ |
- | 895 | int num_power_states; |
|
- | 896 | int current_power_state_index; |
|
- | 897 | int current_clock_mode_index; |
|
- | 898 | int requested_power_state_index; |
|
- | 899 | int requested_clock_mode_index; |
|
- | 900 | int default_power_state_index; |
|
- | 901 | u32 current_sclk; |
|
- | 902 | u32 current_mclk; |
|
- | 903 | u16 current_vddc; |
|
- | 904 | u16 current_vddci; |
|
- | 905 | u32 default_sclk; |
|
- | 906 | u32 default_mclk; |
|
- | 907 | u16 default_vddc; |
|
- | 908 | u16 default_vddci; |
|
773 | int num_power_states; |
909 | struct radeon_i2c_chan *i2c_bus; |
- | 910 | /* selected pm method */ |
|
- | 911 | enum radeon_pm_method pm_method; |
|
- | 912 | /* dynpm power management */ |
|
- | 913 | // struct delayed_work dynpm_idle_work; |
|
- | 914 | enum radeon_dynpm_state dynpm_state; |
|
- | 915 | enum radeon_dynpm_action dynpm_planned_action; |
|
- | 916 | unsigned long dynpm_action_timeout; |
|
- | 917 | bool dynpm_can_upclock; |
|
- | 918 | bool dynpm_can_downclock; |
|
- | 919 | /* profile-based power management */ |
|
- | 920 | enum radeon_pm_profile_type profile; |
|
774 | struct radeon_power_state *current_power_state; |
921 | int profile_index; |
Line 775... | Line 922... | ||
775 | struct radeon_pm_clock_info *current_clock_mode; |
922 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
776 | struct radeon_power_state *requested_power_state; |
923 | /* internal thermal controller on rv6xx+ */ |
777 | struct radeon_pm_clock_info *requested_clock_mode; |
924 | enum radeon_int_thermal_type int_thermal_type; |
Line 785... | Line 932... | ||
785 | int (*init)(struct radeon_device *rdev); |
932 | int (*init)(struct radeon_device *rdev); |
786 | void (*fini)(struct radeon_device *rdev); |
933 | void (*fini)(struct radeon_device *rdev); |
787 | int (*resume)(struct radeon_device *rdev); |
934 | int (*resume)(struct radeon_device *rdev); |
788 | int (*suspend)(struct radeon_device *rdev); |
935 | int (*suspend)(struct radeon_device *rdev); |
789 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
936 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
- | 937 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
|
790 | int (*gpu_reset)(struct radeon_device *rdev); |
938 | int (*asic_reset)(struct radeon_device *rdev); |
791 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
939 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
792 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
940 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
793 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
941 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
794 | void (*cp_fini)(struct radeon_device *rdev); |
942 | void (*cp_fini)(struct radeon_device *rdev); |
795 | void (*cp_disable)(struct radeon_device *rdev); |
943 | void (*cp_disable)(struct radeon_device *rdev); |
Line 825... | Line 973... | ||
825 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
973 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
826 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
974 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
827 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
975 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
828 | uint32_t tiling_flags, uint32_t pitch, |
976 | uint32_t tiling_flags, uint32_t pitch, |
829 | uint32_t offset, uint32_t obj_size); |
977 | uint32_t offset, uint32_t obj_size); |
830 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
978 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
831 | void (*bandwidth_update)(struct radeon_device *rdev); |
979 | void (*bandwidth_update)(struct radeon_device *rdev); |
832 | void (*hpd_init)(struct radeon_device *rdev); |
980 | void (*hpd_init)(struct radeon_device *rdev); |
833 | void (*hpd_fini)(struct radeon_device *rdev); |
981 | void (*hpd_fini)(struct radeon_device *rdev); |
834 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
982 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
835 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
983 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
Line 838... | Line 986... | ||
838 | * might want to perform and HDP flush through MMIO as it seems that |
986 | * might want to perform and HDP flush through MMIO as it seems that |
839 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
987 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
840 | * through ring. |
988 | * through ring. |
841 | */ |
989 | */ |
842 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
990 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
- | 991 | bool (*gui_idle)(struct radeon_device *rdev); |
|
- | 992 | /* power management */ |
|
- | 993 | void (*pm_misc)(struct radeon_device *rdev); |
|
- | 994 | void (*pm_prepare)(struct radeon_device *rdev); |
|
- | 995 | void (*pm_finish)(struct radeon_device *rdev); |
|
- | 996 | void (*pm_init_profile)(struct radeon_device *rdev); |
|
- | 997 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); |
|
- | 998 | /* pageflipping */ |
|
- | 999 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
|
- | 1000 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
|
- | 1001 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
|
843 | }; |
1002 | }; |
Line 844... | Line 1003... | ||
844 | 1003 | ||
845 | /* |
1004 | /* |
846 | * Asic structures |
1005 | * Asic structures |
- | 1006 | */ |
|
- | 1007 | struct r100_gpu_lockup { |
|
- | 1008 | unsigned long last_jiffies; |
|
- | 1009 | u32 last_cp_rptr; |
|
- | 1010 | }; |
|
847 | */ |
1011 | |
848 | struct r100_asic { |
1012 | struct r100_asic { |
849 | const unsigned *reg_safe_bm; |
1013 | const unsigned *reg_safe_bm; |
850 | unsigned reg_safe_bm_size; |
1014 | unsigned reg_safe_bm_size; |
- | 1015 | u32 hdp_cntl; |
|
851 | u32 hdp_cntl; |
1016 | struct r100_gpu_lockup lockup; |
Line 852... | Line 1017... | ||
852 | }; |
1017 | }; |
853 | 1018 | ||
854 | struct r300_asic { |
1019 | struct r300_asic { |
855 | const unsigned *reg_safe_bm; |
1020 | const unsigned *reg_safe_bm; |
856 | unsigned reg_safe_bm_size; |
1021 | unsigned reg_safe_bm_size; |
- | 1022 | u32 resync_scratch; |
|
857 | u32 resync_scratch; |
1023 | u32 hdp_cntl; |
Line 858... | Line 1024... | ||
858 | u32 hdp_cntl; |
1024 | struct r100_gpu_lockup lockup; |
859 | }; |
1025 | }; |
860 | 1026 | ||
Line 873... | Line 1039... | ||
873 | unsigned sx_max_export_smx_size; |
1039 | unsigned sx_max_export_smx_size; |
874 | unsigned sq_num_cf_insts; |
1040 | unsigned sq_num_cf_insts; |
875 | unsigned tiling_nbanks; |
1041 | unsigned tiling_nbanks; |
876 | unsigned tiling_npipes; |
1042 | unsigned tiling_npipes; |
877 | unsigned tiling_group_size; |
1043 | unsigned tiling_group_size; |
- | 1044 | unsigned tile_config; |
|
- | 1045 | struct r100_gpu_lockup lockup; |
|
878 | }; |
1046 | }; |
Line 879... | Line 1047... | ||
879 | 1047 | ||
880 | struct rv770_asic { |
1048 | struct rv770_asic { |
881 | unsigned max_pipes; |
1049 | unsigned max_pipes; |
Line 896... | Line 1064... | ||
896 | unsigned sc_hiz_tile_fifo_size; |
1064 | unsigned sc_hiz_tile_fifo_size; |
897 | unsigned sc_earlyz_tile_fifo_fize; |
1065 | unsigned sc_earlyz_tile_fifo_fize; |
898 | unsigned tiling_nbanks; |
1066 | unsigned tiling_nbanks; |
899 | unsigned tiling_npipes; |
1067 | unsigned tiling_npipes; |
900 | unsigned tiling_group_size; |
1068 | unsigned tiling_group_size; |
- | 1069 | unsigned tile_config; |
|
- | 1070 | struct r100_gpu_lockup lockup; |
|
- | 1071 | }; |
|
- | 1072 | ||
- | 1073 | struct evergreen_asic { |
|
- | 1074 | unsigned num_ses; |
|
- | 1075 | unsigned max_pipes; |
|
- | 1076 | unsigned max_tile_pipes; |
|
- | 1077 | unsigned max_simds; |
|
- | 1078 | unsigned max_backends; |
|
- | 1079 | unsigned max_gprs; |
|
- | 1080 | unsigned max_threads; |
|
- | 1081 | unsigned max_stack_entries; |
|
- | 1082 | unsigned max_hw_contexts; |
|
- | 1083 | unsigned max_gs_threads; |
|
- | 1084 | unsigned sx_max_export_size; |
|
- | 1085 | unsigned sx_max_export_pos_size; |
|
- | 1086 | unsigned sx_max_export_smx_size; |
|
- | 1087 | unsigned sq_num_cf_insts; |
|
- | 1088 | unsigned sx_num_of_sets; |
|
- | 1089 | unsigned sc_prim_fifo_size; |
|
- | 1090 | unsigned sc_hiz_tile_fifo_size; |
|
- | 1091 | unsigned sc_earlyz_tile_fifo_size; |
|
- | 1092 | unsigned tiling_nbanks; |
|
- | 1093 | unsigned tiling_npipes; |
|
- | 1094 | unsigned tiling_group_size; |
|
- | 1095 | unsigned tile_config; |
|
- | 1096 | struct r100_gpu_lockup lockup; |
|
- | 1097 | }; |
|
- | 1098 | ||
- | 1099 | struct cayman_asic { |
|
- | 1100 | unsigned max_shader_engines; |
|
- | 1101 | unsigned max_pipes_per_simd; |
|
- | 1102 | unsigned max_tile_pipes; |
|
- | 1103 | unsigned max_simds_per_se; |
|
- | 1104 | unsigned max_backends_per_se; |
|
- | 1105 | unsigned max_texture_channel_caches; |
|
- | 1106 | unsigned max_gprs; |
|
- | 1107 | unsigned max_threads; |
|
- | 1108 | unsigned max_gs_threads; |
|
- | 1109 | unsigned max_stack_entries; |
|
- | 1110 | unsigned sx_num_of_sets; |
|
- | 1111 | unsigned sx_max_export_size; |
|
- | 1112 | unsigned sx_max_export_pos_size; |
|
- | 1113 | unsigned sx_max_export_smx_size; |
|
- | 1114 | unsigned max_hw_contexts; |
|
- | 1115 | unsigned sq_num_cf_insts; |
|
- | 1116 | unsigned sc_prim_fifo_size; |
|
- | 1117 | unsigned sc_hiz_tile_fifo_size; |
|
- | 1118 | unsigned sc_earlyz_tile_fifo_size; |
|
- | 1119 | ||
- | 1120 | unsigned num_shader_engines; |
|
- | 1121 | unsigned num_shader_pipes_per_simd; |
|
- | 1122 | unsigned num_tile_pipes; |
|
- | 1123 | unsigned num_simds_per_se; |
|
- | 1124 | unsigned num_backends_per_se; |
|
- | 1125 | unsigned backend_disable_mask_per_asic; |
|
- | 1126 | unsigned backend_map; |
|
- | 1127 | unsigned num_texture_channel_caches; |
|
- | 1128 | unsigned mem_max_burst_length_bytes; |
|
- | 1129 | unsigned mem_row_size_in_kb; |
|
- | 1130 | unsigned shader_engine_tile_size; |
|
- | 1131 | unsigned num_gpus; |
|
- | 1132 | unsigned multi_gpu_tile_size; |
|
- | 1133 | ||
- | 1134 | unsigned tile_config; |
|
- | 1135 | struct r100_gpu_lockup lockup; |
|
901 | }; |
1136 | }; |
Line 902... | Line 1137... | ||
902 | 1137 | ||
903 | union radeon_asic_config { |
1138 | union radeon_asic_config { |
904 | struct r300_asic r300; |
1139 | struct r300_asic r300; |
905 | struct r100_asic r100; |
1140 | struct r100_asic r100; |
906 | struct r600_asic r600; |
1141 | struct r600_asic r600; |
- | 1142 | struct rv770_asic rv770; |
|
- | 1143 | struct evergreen_asic evergreen; |
|
907 | struct rv770_asic rv770; |
1144 | struct cayman_asic cayman; |
Line 908... | Line -... | ||
908 | }; |
- | |
909 | 1145 | }; |
|
- | 1146 | ||
- | 1147 | /* |
|
- | 1148 | * asic initizalization from radeon_asic.c |
|
- | 1149 | */ |
|
Line -... | Line 1150... | ||
- | 1150 | void radeon_agp_disable(struct radeon_device *rdev); |
|
- | 1151 | int radeon_asic_init(struct radeon_device *rdev); |
|
- | 1152 | ||
- | 1153 | ||
- | 1154 | ||
Line 910... | Line 1155... | ||
910 | 1155 | /* VRAM scratch page for HDP bug */ |
|
911 | /* |
1156 | struct r700_vram_scratch { |
912 | 1157 | struct radeon_bo *robj; |
|
913 | 1158 | volatile uint32_t *ptr; |
|
Line 935... | Line 1180... | ||
935 | /* BIOS */ |
1180 | /* BIOS */ |
936 | uint8_t *bios; |
1181 | uint8_t *bios; |
937 | bool is_atom_bios; |
1182 | bool is_atom_bios; |
938 | uint16_t bios_header_start; |
1183 | uint16_t bios_header_start; |
939 | struct radeon_bo *stollen_vga_memory; |
1184 | struct radeon_bo *stollen_vga_memory; |
940 | struct fb_info *fbdev_info; |
- | |
941 | struct radeon_bo *fbdev_rbo; |
- | |
942 | struct radeon_framebuffer *fbdev_rfb; |
- | |
943 | /* Register mmio */ |
1185 | /* Register mmio */ |
944 | unsigned long rmmio_base; |
1186 | resource_size_t rmmio_base; |
945 | unsigned long rmmio_size; |
1187 | resource_size_t rmmio_size; |
946 | void *rmmio; |
1188 | void *rmmio; |
947 | radeon_rreg_t mc_rreg; |
1189 | radeon_rreg_t mc_rreg; |
948 | radeon_wreg_t mc_wreg; |
1190 | radeon_wreg_t mc_wreg; |
949 | radeon_rreg_t pll_rreg; |
1191 | radeon_rreg_t pll_rreg; |
950 | radeon_wreg_t pll_wreg; |
1192 | radeon_wreg_t pll_wreg; |
951 | uint32_t pcie_reg_mask; |
1193 | uint32_t pcie_reg_mask; |
952 | radeon_rreg_t pciep_rreg; |
1194 | radeon_rreg_t pciep_rreg; |
953 | radeon_wreg_t pciep_wreg; |
1195 | radeon_wreg_t pciep_wreg; |
- | 1196 | /* io port */ |
|
- | 1197 | void __iomem *rio_mem; |
|
- | 1198 | resource_size_t rio_mem_size; |
|
954 | struct radeon_clock clock; |
1199 | struct radeon_clock clock; |
955 | struct radeon_mc mc; |
1200 | struct radeon_mc mc; |
956 | struct radeon_gart gart; |
1201 | struct radeon_gart gart; |
957 | struct radeon_mode_info mode_info; |
1202 | struct radeon_mode_info mode_info; |
958 | struct radeon_scratch scratch; |
1203 | struct radeon_scratch scratch; |
959 | struct radeon_mman mman; |
1204 | struct radeon_mman mman; |
960 | struct radeon_fence_driver fence_drv; |
1205 | struct radeon_fence_driver fence_drv; |
961 | struct radeon_cp cp; |
1206 | struct radeon_cp cp; |
- | 1207 | /* cayman compute rings */ |
|
- | 1208 | struct radeon_cp cp1; |
|
- | 1209 | struct radeon_cp cp2; |
|
962 | struct radeon_ib_pool ib_pool; |
1210 | struct radeon_ib_pool ib_pool; |
963 | // struct radeon_irq irq; |
1211 | struct radeon_irq irq; |
964 | struct radeon_asic *asic; |
1212 | struct radeon_asic *asic; |
965 | struct radeon_gem gem; |
1213 | struct radeon_gem gem; |
966 | struct radeon_pm pm; |
1214 | struct radeon_pm pm; |
967 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
1215 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
968 | struct mutex cs_mutex; |
1216 | struct mutex cs_mutex; |
Line 975... | Line 1223... | ||
975 | bool accel_working; |
1223 | bool accel_working; |
976 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
1224 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
977 | const struct firmware *me_fw; /* all family ME firmware */ |
1225 | const struct firmware *me_fw; /* all family ME firmware */ |
978 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
1226 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
979 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
1227 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
- | 1228 | const struct firmware *mc_fw; /* NI MC firmware */ |
|
980 | struct r600_blit r600_blit; |
1229 | struct r600_blit r600_blit; |
- | 1230 | struct r700_vram_scratch vram_scratch; |
|
981 | int msi_enabled; /* msi enabled */ |
1231 | int msi_enabled; /* msi enabled */ |
- | 1232 | // struct r600_ih ih; /* r6/700 interrupt ring */ |
|
- | 1233 | // struct workqueue_struct *wq; |
|
- | 1234 | // struct work_struct hotplug_work; |
|
982 | int num_crtc; /* number of crtcs */ |
1235 | int num_crtc; /* number of crtcs */ |
983 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
1236 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
- | 1237 | struct mutex vram_mutex; |
|
Line 984... | Line 1238... | ||
984 | 1238 | ||
- | 1239 | /* audio stuff */ |
|
985 | /* audio stuff */ |
1240 | bool audio_enabled; |
986 | // struct timer_list audio_timer; |
1241 | // struct timer_list audio_timer; |
987 | int audio_channels; |
1242 | int audio_channels; |
988 | int audio_rate; |
1243 | int audio_rate; |
989 | int audio_bits_per_sample; |
1244 | int audio_bits_per_sample; |
990 | uint8_t audio_status_bits; |
1245 | uint8_t audio_status_bits; |
Line -... | Line 1246... | ||
- | 1246 | uint8_t audio_category_code; |
|
991 | uint8_t audio_category_code; |
1247 | |
- | 1248 | ||
992 | 1249 | /* i2c buses */ |
|
Line 993... | Line 1250... | ||
993 | bool powered_down; |
1250 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
994 | }; |
1251 | }; |
995 | 1252 | ||
996 | int radeon_device_init(struct radeon_device *rdev, |
1253 | int radeon_device_init(struct radeon_device *rdev, |
997 | struct drm_device *ddev, |
1254 | struct drm_device *ddev, |
998 | struct pci_dev *pdev, |
1255 | struct pci_dev *pdev, |
Line 999... | Line -... | ||
999 | uint32_t flags); |
- | |
1000 | void radeon_device_fini(struct radeon_device *rdev); |
- | |
1001 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
- | |
1002 | - | ||
1003 | /* r600 blit */ |
- | |
1004 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
- | |
1005 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
- | |
1006 | void r600_kms_blit_copy(struct radeon_device *rdev, |
1256 | uint32_t flags); |
1007 | u64 src_gpu_addr, u64 dst_gpu_addr, |
1257 | void radeon_device_fini(struct radeon_device *rdev); |
1008 | int size_bytes); |
1258 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
1009 | 1259 | ||
1010 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1260 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
Line 1025... | Line 1275... | ||
1025 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
1275 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
1026 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
1276 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
1027 | } |
1277 | } |
1028 | } |
1278 | } |
Line -... | Line 1279... | ||
- | 1279 | ||
- | 1280 | static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
|
- | 1281 | { |
|
- | 1282 | if (reg < rdev->rio_mem_size) |
|
- | 1283 | return ioread32(rdev->rio_mem + reg); |
|
- | 1284 | else { |
|
- | 1285 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
|
- | 1286 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
|
- | 1287 | } |
|
- | 1288 | } |
|
- | 1289 | ||
- | 1290 | static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
|
- | 1291 | { |
|
- | 1292 | if (reg < rdev->rio_mem_size) |
|
- | 1293 | iowrite32(v, rdev->rio_mem + reg); |
|
- | 1294 | else { |
|
- | 1295 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
|
- | 1296 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
|
- | 1297 | } |
|
- | 1298 | } |
|
1029 | 1299 | ||
1030 | /* |
1300 | /* |
1031 | * Cast helper |
1301 | * Cast helper |
1032 | */ |
1302 | */ |
Line 1033... | Line 1303... | ||
1033 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
1303 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
1034 | 1304 | ||
1035 | /* |
1305 | /* |
1036 | * Registers read & write functions. |
1306 | * Registers read & write functions. |
1037 | */ |
1307 | */ |
- | 1308 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
|
- | 1309 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
|
1038 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
1310 | #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg)) |
1039 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
1311 | #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg)) |
1040 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
1312 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
1041 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
1313 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
1042 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1314 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
Line 1061... | Line 1333... | ||
1061 | uint32_t tmp_ = RREG32_PLL(reg); \ |
1333 | uint32_t tmp_ = RREG32_PLL(reg); \ |
1062 | tmp_ &= (mask); \ |
1334 | tmp_ &= (mask); \ |
1063 | tmp_ |= ((val) & ~(mask)); \ |
1335 | tmp_ |= ((val) & ~(mask)); \ |
1064 | WREG32_PLL(reg, tmp_); \ |
1336 | WREG32_PLL(reg, tmp_); \ |
1065 | } while (0) |
1337 | } while (0) |
- | 1338 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
|
- | 1339 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
|
Line 1066... | Line 1340... | ||
1066 | 1340 | ||
1067 | /* |
1341 | /* |
1068 | * Indirect registers accessor |
1342 | * Indirect registers accessor |
1069 | */ |
1343 | */ |
Line 1104... | Line 1378... | ||
1104 | (rdev->family == CHIP_R420) || \ |
1378 | (rdev->family == CHIP_R420) || \ |
1105 | (rdev->family == CHIP_R423) || \ |
1379 | (rdev->family == CHIP_R423) || \ |
1106 | (rdev->family == CHIP_RV410) || \ |
1380 | (rdev->family == CHIP_RV410) || \ |
1107 | (rdev->family == CHIP_RS400) || \ |
1381 | (rdev->family == CHIP_RS400) || \ |
1108 | (rdev->family == CHIP_RS480)) |
1382 | (rdev->family == CHIP_RS480)) |
- | 1383 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
|
- | 1384 | (rdev->ddev->pdev->device == 0x9443) || \ |
|
- | 1385 | (rdev->ddev->pdev->device == 0x944B) || \ |
|
- | 1386 | (rdev->ddev->pdev->device == 0x9506) || \ |
|
- | 1387 | (rdev->ddev->pdev->device == 0x9509) || \ |
|
- | 1388 | (rdev->ddev->pdev->device == 0x950F) || \ |
|
- | 1389 | (rdev->ddev->pdev->device == 0x689C) || \ |
|
- | 1390 | (rdev->ddev->pdev->device == 0x689D)) |
|
1109 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1391 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
- | 1392 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
|
- | 1393 | (rdev->family == CHIP_RS690) || \ |
|
- | 1394 | (rdev->family == CHIP_RS740) || \ |
|
- | 1395 | (rdev->family >= CHIP_R600)) |
|
1110 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1396 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1111 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
1397 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
1112 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
1398 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
- | 1399 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
|
- | 1400 | (rdev->flags & RADEON_IS_IGP)) |
|
- | 1401 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
|
Line 1113... | Line 1402... | ||
1113 | 1402 | ||
1114 | /* |
1403 | /* |
1115 | * BIOS helpers. |
1404 | * BIOS helpers. |
1116 | */ |
1405 | */ |
Line 1148... | Line 1437... | ||
1148 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1437 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1149 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
1438 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
1150 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
1439 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
1151 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1440 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1152 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1441 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
- | 1442 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
|
1153 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
1443 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
1154 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1444 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1155 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
1445 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
1156 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1446 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1157 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1447 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1158 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1448 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
Line 1176... | Line 1466... | ||
1176 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
1466 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
1177 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1467 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1178 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
1468 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
1179 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
1469 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
1180 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
1470 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
- | 1471 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
|
- | 1472 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
|
- | 1473 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) |
|
- | 1474 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) |
|
- | 1475 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
|
- | 1476 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) |
|
- | 1477 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
|
- | 1478 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) |
|
- | 1479 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) |
|
Line 1181... | Line 1480... | ||
1181 | 1480 | ||
1182 | /* Common functions */ |
1481 | /* Common functions */ |
- | 1482 | /* AGP */ |
|
1183 | /* AGP */ |
1483 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
1184 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1484 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1185 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
1485 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
1186 | extern void radeon_gart_restore(struct radeon_device *rdev); |
1486 | extern void radeon_gart_restore(struct radeon_device *rdev); |
1187 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1487 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1188 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
1488 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
- | 1489 | extern bool radeon_card_posted(struct radeon_device *rdev); |
|
- | 1490 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
|
1189 | extern bool radeon_card_posted(struct radeon_device *rdev); |
1491 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
1190 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
- | |
1191 | extern int radeon_clocks_init(struct radeon_device *rdev); |
- | |
1192 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
1492 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
- | 1493 | extern void radeon_scratch_init(struct radeon_device *rdev); |
|
- | 1494 | extern void radeon_wb_fini(struct radeon_device *rdev); |
|
- | 1495 | extern int radeon_wb_init(struct radeon_device *rdev); |
|
1193 | extern void radeon_scratch_init(struct radeon_device *rdev); |
1496 | extern void radeon_wb_disable(struct radeon_device *rdev); |
1194 | extern void radeon_surface_init(struct radeon_device *rdev); |
1497 | extern void radeon_surface_init(struct radeon_device *rdev); |
1195 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
1498 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
1196 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1499 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1197 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
1500 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
1198 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1501 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1199 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1502 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1200 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1503 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1201 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
1504 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
1202 | extern int radeon_resume_kms(struct drm_device *dev); |
1505 | extern int radeon_resume_kms(struct drm_device *dev); |
- | 1506 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
|
Line 1203... | Line -... | ||
1203 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
- | |
1204 | - | ||
1205 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
- | |
1206 | struct r100_mc_save { |
- | |
1207 | u32 GENMO_WT; |
- | |
1208 | u32 CRTC_EXT_CNTL; |
- | |
1209 | u32 CRTC_GEN_CNTL; |
- | |
1210 | u32 CRTC2_GEN_CNTL; |
- | |
1211 | u32 CUR_OFFSET; |
1507 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
1212 | u32 CUR2_OFFSET; |
- | |
1213 | }; |
- | |
1214 | extern void r100_cp_disable(struct radeon_device *rdev); |
- | |
1215 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
- | |
1216 | extern void r100_cp_fini(struct radeon_device *rdev); |
- | |
1217 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
- | |
1218 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
- | |
1219 | extern void r100_pci_gart_fini(struct radeon_device *rdev); |
- | |
1220 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
- | |
1221 | extern void r100_pci_gart_disable(struct radeon_device *rdev); |
- | |
1222 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
- | |
1223 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
- | |
1224 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
- | |
1225 | extern void r100_ib_fini(struct radeon_device *rdev); |
- | |
1226 | extern int r100_ib_init(struct radeon_device *rdev); |
- | |
1227 | extern void r100_irq_disable(struct radeon_device *rdev); |
- | |
1228 | extern int r100_irq_set(struct radeon_device *rdev); |
- | |
1229 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
- | |
1230 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
- | |
1231 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
- | |
1232 | extern void r100_wb_disable(struct radeon_device *rdev); |
- | |
1233 | extern void r100_wb_fini(struct radeon_device *rdev); |
- | |
1234 | extern int r100_wb_init(struct radeon_device *rdev); |
- | |
1235 | extern void r100_hdp_reset(struct radeon_device *rdev); |
- | |
1236 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
- | |
1237 | extern int r100_cp_reset(struct radeon_device *rdev); |
- | |
1238 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
- | |
1239 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
- | |
1240 | struct radeon_cs_packet *pkt, |
- | |
1241 | struct radeon_bo *robj); |
- | |
1242 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
- | |
1243 | struct radeon_cs_packet *pkt, |
- | |
1244 | const unsigned *auth, unsigned n, |
- | |
1245 | radeon_packet0_check_t check); |
- | |
1246 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
- | |
1247 | struct radeon_cs_packet *pkt, |
- | |
1248 | unsigned idx); |
- | |
1249 | extern void r100_enable_bm(struct radeon_device *rdev); |
- | |
1250 | extern void r100_set_common_regs(struct radeon_device *rdev); |
- | |
1251 | - | ||
1252 | /* rv200,rv250,rv280 */ |
- | |
1253 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
- | |
1254 | - | ||
1255 | /* r300,r350,rv350,rv370,rv380 */ |
- | |
1256 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1508 | |
1257 | extern void r300_mc_program(struct radeon_device *rdev); |
- | |
1258 | extern void r300_mc_init(struct radeon_device *rdev); |
- | |
1259 | extern void r300_clock_startup(struct radeon_device *rdev); |
- | |
1260 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
- | |
1261 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
- | |
1262 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
- | |
1263 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
- | |
1264 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
- | |
1265 | - | ||
1266 | /* r420,r423,rv410 */ |
- | |
1267 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
- | |
1268 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
- | |
1269 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
- | |
1270 | extern void r420_pipes_init(struct radeon_device *rdev); |
- | |
1271 | - | ||
1272 | /* rv515 */ |
- | |
1273 | struct rv515_mc_save { |
- | |
1274 | u32 d1vga_control; |
- | |
1275 | u32 d2vga_control; |
- | |
1276 | u32 vga_render_control; |
- | |
1277 | u32 vga_hdp_control; |
- | |
1278 | u32 d1crtc_control; |
1509 | /* |
1279 | u32 d2crtc_control; |
- | |
1280 | }; |
- | |
1281 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
- | |
1282 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
- | |
1283 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
- | |
1284 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
- | |
1285 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
- | |
1286 | extern void rv515_clock_startup(struct radeon_device *rdev); |
- | |
1287 | extern void rv515_debugfs(struct radeon_device *rdev); |
- | |
1288 | extern int rv515_suspend(struct radeon_device *rdev); |
- | |
1289 | - | ||
1290 | /* rs400 */ |
- | |
1291 | extern int rs400_gart_init(struct radeon_device *rdev); |
- | |
1292 | extern int rs400_gart_enable(struct radeon_device *rdev); |
- | |
1293 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
- | |
1294 | extern void rs400_gart_disable(struct radeon_device *rdev); |
- | |
1295 | extern void rs400_gart_fini(struct radeon_device *rdev); |
- | |
1296 | - | ||
1297 | /* rs600 */ |
- | |
1298 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
- | |
1299 | extern int rs600_irq_set(struct radeon_device *rdev); |
- | |
1300 | extern void rs600_irq_disable(struct radeon_device *rdev); |
- | |
1301 | - | ||
1302 | /* rs690, rs740 */ |
- | |
1303 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
- | |
1304 | struct drm_display_mode *mode1, |
- | |
1305 | struct drm_display_mode *mode2); |
- | |
1306 | - | ||
1307 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
- | |
1308 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
- | |
1309 | extern bool r600_card_posted(struct radeon_device *rdev); |
- | |
1310 | extern void r600_cp_stop(struct radeon_device *rdev); |
- | |
1311 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
- | |
1312 | extern int r600_cp_resume(struct radeon_device *rdev); |
- | |
1313 | extern void r600_cp_fini(struct radeon_device *rdev); |
- | |
1314 | extern int r600_count_pipe_bits(uint32_t val); |
- | |
1315 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
- | |
1316 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
- | |
1317 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
- | |
1318 | extern int r600_ib_test(struct radeon_device *rdev); |
- | |
1319 | extern int r600_ring_test(struct radeon_device *rdev); |
- | |
1320 | extern void r600_wb_fini(struct radeon_device *rdev); |
- | |
1321 | extern int r600_wb_enable(struct radeon_device *rdev); |
- | |
1322 | extern void r600_wb_disable(struct radeon_device *rdev); |
- | |
1323 | extern void r600_scratch_init(struct radeon_device *rdev); |
- | |
1324 | extern int r600_blit_init(struct radeon_device *rdev); |
- | |
1325 | extern void r600_blit_fini(struct radeon_device *rdev); |
- | |
1326 | extern int r600_init_microcode(struct radeon_device *rdev); |
- | |
1327 | extern int r600_gpu_reset(struct radeon_device *rdev); |
- | |
1328 | /* r600 irq */ |
- | |
1329 | extern int r600_irq_init(struct radeon_device *rdev); |
- | |
1330 | extern void r600_irq_fini(struct radeon_device *rdev); |
- | |
1331 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
- | |
1332 | extern int r600_irq_set(struct radeon_device *rdev); |
- | |
1333 | extern void r600_irq_suspend(struct radeon_device *rdev); |
- | |
1334 | /* r600 audio */ |
- | |
1335 | extern int r600_audio_init(struct radeon_device *rdev); |
- | |
1336 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
- | |
1337 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
1510 | * r600 functions used by radeon_encoder.c |
1338 | extern void r600_audio_fini(struct radeon_device *rdev); |
1511 | */ |
1339 | extern void r600_hdmi_init(struct drm_encoder *encoder); |
1512 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
- | 1513 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
|
1340 | extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); |
1514 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1341 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1515 | |
1342 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
- | |
1343 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, |
- | |
1344 | int channels, |
- | |
1345 | int rate, |
- | |
1346 | int bps, |
- | |
1347 | uint8_t status_bits, |
1516 | extern int ni_init_microcode(struct radeon_device *rdev); |
1348 | uint8_t category_code); |
1517 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
1349 | 1518 | ||
1350 | /* evergreen */ |
1519 | /* radeon_acpi.c */ |
1351 | struct evergreen_mc_save { |
1520 | #if defined(CONFIG_ACPI) |
1352 | u32 vga_control[6]; |
1521 | extern int radeon_acpi_init(struct radeon_device *rdev); |
1353 | u32 vga_render_control; |
- | |
1354 | u32 vga_hdp_control; |
1522 | #else |
Line 1355... | Line 1523... | ||
1355 | u32 crtc_control[6]; |
1523 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
Line 1356... | Line 1524... | ||
1356 | }; |
1524 | #endif |
Line 1366... | Line 1534... | ||
1366 | 1534 | ||
1367 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1535 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
Line -... | Line 1536... | ||
- | 1536 | videomode_t *mode, bool strict); |
|
- | 1537 | ||
- | 1538 | ||
- | 1539 | ||
- | 1540 | struct work_struct; |
|
- | 1541 | typedef void (*work_func_t)(struct work_struct *work); |
|
- | 1542 | ||
- | 1543 | /* |
|
- | 1544 | * The first word is the work queue pointer and the flags rolled into |
|
- | 1545 | * one |
|
- | 1546 | */ |
|
- | 1547 | #define work_data_bits(work) ((unsigned long *)(&(work)->data)) |
|
- | 1548 | ||
- | 1549 | struct work_struct { |
|
- | 1550 | atomic_long_t data; |
|
- | 1551 | #define WORK_STRUCT_PENDING 0 /* T if work item pending execution */ |
|
- | 1552 | #define WORK_STRUCT_FLAG_MASK (3UL) |
|
- | 1553 | #define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK) |
|
- | 1554 | struct list_head entry; |
|
1368 | videomode_t *mode, bool strict); |
1555 | work_func_t func; |