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Line 95... | Line 95... | ||
95 | extern int radeon_benchmarking; |
95 | extern int radeon_benchmarking; |
96 | extern int radeon_testing; |
96 | extern int radeon_testing; |
97 | extern int radeon_connector_table; |
97 | extern int radeon_connector_table; |
98 | extern int radeon_tv; |
98 | extern int radeon_tv; |
99 | extern int radeon_new_pll; |
99 | extern int radeon_new_pll; |
- | 100 | extern int radeon_dynpm; |
|
100 | extern int radeon_audio; |
101 | extern int radeon_audio; |
Line -... | Line 102... | ||
- | 102 | ||
- | 103 | typedef struct pm_message { |
|
- | 104 | int event; |
|
- | 105 | } pm_message_t; |
|
101 | 106 | ||
102 | typedef struct |
107 | typedef struct |
103 | { |
108 | { |
104 | int width; |
109 | int width; |
105 | int height; |
110 | int height; |
Line 179... | Line 184... | ||
179 | 184 | ||
180 | 185 | ||
181 | /* |
186 | /* |
- | 187 | * BIOS. |
|
- | 188 | */ |
|
- | 189 | #define ATRM_BIOS_PAGE 4096 |
|
- | 190 | ||
- | 191 | #if defined(CONFIG_VGA_SWITCHEROO) |
|
- | 192 | bool radeon_atrm_supported(struct pci_dev *pdev); |
|
- | 193 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
|
- | 194 | #else |
|
- | 195 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
|
- | 196 | { |
|
- | 197 | return false; |
|
- | 198 | } |
|
- | 199 | ||
- | 200 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
|
- | 201 | return -EINVAL; |
|
182 | * BIOS. |
202 | } |
Line 183... | Line 203... | ||
183 | */ |
203 | #endif |
184 | bool radeon_get_bios(struct radeon_device *rdev); |
204 | bool radeon_get_bios(struct radeon_device *rdev); |
Line 199... | Line 219... | ||
199 | * Clocks |
219 | * Clocks |
200 | */ |
220 | */ |
201 | struct radeon_clock { |
221 | struct radeon_clock { |
202 | struct radeon_pll p1pll; |
222 | struct radeon_pll p1pll; |
203 | struct radeon_pll p2pll; |
223 | struct radeon_pll p2pll; |
- | 224 | struct radeon_pll dcpll; |
|
204 | struct radeon_pll spll; |
225 | struct radeon_pll spll; |
205 | struct radeon_pll mpll; |
226 | struct radeon_pll mpll; |
206 | /* 10 Khz units */ |
227 | /* 10 Khz units */ |
207 | uint32_t default_mclk; |
228 | uint32_t default_mclk; |
208 | uint32_t default_sclk; |
229 | uint32_t default_sclk; |
- | 230 | uint32_t default_dispclk; |
|
- | 231 | uint32_t dp_extclk; |
|
209 | }; |
232 | }; |
Line 210... | Line 233... | ||
210 | 233 | ||
211 | /* |
234 | /* |
212 | * Power management |
235 | * Power management |
213 | */ |
236 | */ |
- | 237 | int radeon_pm_init(struct radeon_device *rdev); |
|
- | 238 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
|
- | 239 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
|
Line 214... | Line 240... | ||
214 | int radeon_pm_init(struct radeon_device *rdev); |
240 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
215 | 241 | ||
216 | /* |
242 | /* |
217 | * Fences. |
243 | * Fences. |
Line 337... | Line 363... | ||
337 | struct radeon_gart_table_ram ram; |
363 | struct radeon_gart_table_ram ram; |
338 | struct radeon_gart_table_vram vram; |
364 | struct radeon_gart_table_vram vram; |
339 | }; |
365 | }; |
Line 340... | Line 366... | ||
340 | 366 | ||
- | 367 | #define RADEON_GPU_PAGE_SIZE 4096 |
|
Line 341... | Line 368... | ||
341 | #define RADEON_GPU_PAGE_SIZE 4096 |
368 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
342 | 369 | ||
343 | struct radeon_gart { |
370 | struct radeon_gart { |
344 | dma_addr_t table_addr; |
371 | dma_addr_t table_addr; |
Line 371... | Line 398... | ||
371 | resource_size_t aper_base; |
398 | resource_size_t aper_base; |
372 | resource_size_t agp_base; |
399 | resource_size_t agp_base; |
373 | /* for some chips with <= 32MB we need to lie |
400 | /* for some chips with <= 32MB we need to lie |
374 | * about vram size near mc fb location */ |
401 | * about vram size near mc fb location */ |
375 | u64 mc_vram_size; |
402 | u64 mc_vram_size; |
376 | u64 gtt_location; |
403 | u64 visible_vram_size; |
377 | u64 gtt_size; |
404 | u64 gtt_size; |
378 | u64 gtt_start; |
405 | u64 gtt_start; |
379 | u64 gtt_end; |
406 | u64 gtt_end; |
380 | u64 vram_location; |
- | |
381 | u64 vram_start; |
407 | u64 vram_start; |
382 | u64 vram_end; |
408 | u64 vram_end; |
383 | unsigned vram_width; |
409 | unsigned vram_width; |
384 | u64 real_vram_size; |
410 | u64 real_vram_size; |
385 | int vram_mtrr; |
411 | int vram_mtrr; |
386 | bool vram_is_ddr; |
412 | bool vram_is_ddr; |
387 | bool igp_sideport_enabled; |
413 | bool igp_sideport_enabled; |
388 | }; |
414 | }; |
Line 389... | Line -... | ||
389 | - | ||
390 | int radeon_mc_setup(struct radeon_device *rdev); |
415 | |
391 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
416 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
Line 392... | Line 417... | ||
392 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
417 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
393 | 418 | ||
Line 441... | Line 466... | ||
441 | * mutex protects scheduled_ibs, ready, alloc_bm |
466 | * mutex protects scheduled_ibs, ready, alloc_bm |
442 | */ |
467 | */ |
443 | struct radeon_ib_pool { |
468 | struct radeon_ib_pool { |
444 | // struct mutex mutex; |
469 | // struct mutex mutex; |
445 | struct radeon_bo *robj; |
470 | struct radeon_bo *robj; |
- | 471 | struct list_head bogus_ib; |
|
446 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
472 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
447 | bool ready; |
473 | bool ready; |
448 | unsigned head_id; |
474 | unsigned head_id; |
449 | }; |
475 | }; |
Line 494... | Line 520... | ||
494 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
520 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
495 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
521 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
496 | int radeon_ib_pool_init(struct radeon_device *rdev); |
522 | int radeon_ib_pool_init(struct radeon_device *rdev); |
497 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
523 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
498 | int radeon_ib_test(struct radeon_device *rdev); |
524 | int radeon_ib_test(struct radeon_device *rdev); |
- | 525 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
|
499 | /* Ring access between begin & end cannot sleep */ |
526 | /* Ring access between begin & end cannot sleep */ |
500 | void radeon_ring_free_size(struct radeon_device *rdev); |
527 | void radeon_ring_free_size(struct radeon_device *rdev); |
501 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
528 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
502 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
529 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
503 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
530 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
Line 527... | Line 554... | ||
527 | int last_copied_page; |
554 | int last_copied_page; |
528 | int last_page_index; |
555 | int last_page_index; |
529 | }; |
556 | }; |
Line 530... | Line 557... | ||
530 | 557 | ||
- | 558 | struct radeon_cs_parser { |
|
531 | struct radeon_cs_parser { |
559 | struct device *dev; |
532 | struct radeon_device *rdev; |
560 | struct radeon_device *rdev; |
533 | // struct drm_file *filp; |
561 | // struct drm_file *filp; |
534 | /* chunks */ |
562 | /* chunks */ |
535 | unsigned nchunks; |
563 | unsigned nchunks; |
Line 630... | Line 658... | ||
630 | * It keeps track of various data needed to take powermanagement decision. |
658 | * It keeps track of various data needed to take powermanagement decision. |
631 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
659 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
632 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
660 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
633 | * (type of memory, bus size, efficiency, ...) |
661 | * (type of memory, bus size, efficiency, ...) |
634 | */ |
662 | */ |
- | 663 | enum radeon_pm_state { |
|
- | 664 | PM_STATE_DISABLED, |
|
- | 665 | PM_STATE_MINIMUM, |
|
- | 666 | PM_STATE_PAUSED, |
|
- | 667 | PM_STATE_ACTIVE |
|
- | 668 | }; |
|
- | 669 | enum radeon_pm_action { |
|
- | 670 | PM_ACTION_NONE, |
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- | 671 | PM_ACTION_MINIMUM, |
|
- | 672 | PM_ACTION_DOWNCLOCK, |
|
- | 673 | PM_ACTION_UPCLOCK |
|
- | 674 | }; |
|
- | 675 | ||
- | 676 | enum radeon_voltage_type { |
|
- | 677 | VOLTAGE_NONE = 0, |
|
- | 678 | VOLTAGE_GPIO, |
|
- | 679 | VOLTAGE_VDDC, |
|
- | 680 | VOLTAGE_SW |
|
- | 681 | }; |
|
- | 682 | ||
- | 683 | enum radeon_pm_state_type { |
|
- | 684 | POWER_STATE_TYPE_DEFAULT, |
|
- | 685 | POWER_STATE_TYPE_POWERSAVE, |
|
- | 686 | POWER_STATE_TYPE_BATTERY, |
|
- | 687 | POWER_STATE_TYPE_BALANCED, |
|
- | 688 | POWER_STATE_TYPE_PERFORMANCE, |
|
- | 689 | }; |
|
- | 690 | ||
- | 691 | enum radeon_pm_clock_mode_type { |
|
- | 692 | POWER_MODE_TYPE_DEFAULT, |
|
- | 693 | POWER_MODE_TYPE_LOW, |
|
- | 694 | POWER_MODE_TYPE_MID, |
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- | 695 | POWER_MODE_TYPE_HIGH, |
|
- | 696 | }; |
|
- | 697 | ||
- | 698 | struct radeon_voltage { |
|
- | 699 | enum radeon_voltage_type type; |
|
- | 700 | /* gpio voltage */ |
|
- | 701 | struct radeon_gpio_rec gpio; |
|
- | 702 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
|
- | 703 | bool active_high; /* voltage drop is active when bit is high */ |
|
- | 704 | /* VDDC voltage */ |
|
- | 705 | u8 vddc_id; /* index into vddc voltage table */ |
|
- | 706 | u8 vddci_id; /* index into vddci voltage table */ |
|
- | 707 | bool vddci_enabled; |
|
- | 708 | /* r6xx+ sw */ |
|
- | 709 | u32 voltage; |
|
- | 710 | }; |
|
- | 711 | ||
- | 712 | struct radeon_pm_non_clock_info { |
|
- | 713 | /* pcie lanes */ |
|
- | 714 | int pcie_lanes; |
|
- | 715 | /* standardized non-clock flags */ |
|
- | 716 | u32 flags; |
|
- | 717 | }; |
|
- | 718 | ||
- | 719 | struct radeon_pm_clock_info { |
|
- | 720 | /* memory clock */ |
|
- | 721 | u32 mclk; |
|
- | 722 | /* engine clock */ |
|
- | 723 | u32 sclk; |
|
- | 724 | /* voltage info */ |
|
- | 725 | struct radeon_voltage voltage; |
|
- | 726 | /* standardized clock flags - not sure we'll need these */ |
|
- | 727 | u32 flags; |
|
- | 728 | }; |
|
- | 729 | ||
- | 730 | struct radeon_power_state { |
|
- | 731 | enum radeon_pm_state_type type; |
|
- | 732 | /* XXX: use a define for num clock modes */ |
|
- | 733 | struct radeon_pm_clock_info clock_info[8]; |
|
- | 734 | /* number of valid clock modes in this power state */ |
|
- | 735 | int num_clock_modes; |
|
- | 736 | struct radeon_pm_clock_info *default_clock_mode; |
|
- | 737 | /* non clock info about this state */ |
|
- | 738 | struct radeon_pm_non_clock_info non_clock_info; |
|
- | 739 | bool voltage_drop_active; |
|
- | 740 | }; |
|
- | 741 | ||
- | 742 | /* |
|
- | 743 | * Some modes are overclocked by very low value, accept them |
|
- | 744 | */ |
|
- | 745 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
|
- | 746 | ||
635 | struct radeon_pm { |
747 | struct radeon_pm { |
- | 748 | // struct mutex mutex; |
|
- | 749 | // struct delayed_work idle_work; |
|
- | 750 | enum radeon_pm_state state; |
|
- | 751 | enum radeon_pm_action planned_action; |
|
- | 752 | unsigned long action_timeout; |
|
- | 753 | bool downclocked; |
|
- | 754 | int active_crtcs; |
|
- | 755 | int req_vblank; |
|
636 | fixed20_12 max_bandwidth; |
756 | fixed20_12 max_bandwidth; |
637 | fixed20_12 igp_sideport_mclk; |
757 | fixed20_12 igp_sideport_mclk; |
638 | fixed20_12 igp_system_mclk; |
758 | fixed20_12 igp_system_mclk; |
639 | fixed20_12 igp_ht_link_clk; |
759 | fixed20_12 igp_ht_link_clk; |
640 | fixed20_12 igp_ht_link_width; |
760 | fixed20_12 igp_ht_link_width; |
Line 642... | Line 762... | ||
642 | fixed20_12 sideport_bandwidth; |
762 | fixed20_12 sideport_bandwidth; |
643 | fixed20_12 ht_bandwidth; |
763 | fixed20_12 ht_bandwidth; |
644 | fixed20_12 core_bandwidth; |
764 | fixed20_12 core_bandwidth; |
645 | fixed20_12 sclk; |
765 | fixed20_12 sclk; |
646 | fixed20_12 needed_bandwidth; |
766 | fixed20_12 needed_bandwidth; |
- | 767 | /* XXX: use a define for num power modes */ |
|
- | 768 | struct radeon_power_state power_state[8]; |
|
- | 769 | /* number of valid power states */ |
|
- | 770 | int num_power_states; |
|
- | 771 | struct radeon_power_state *current_power_state; |
|
- | 772 | struct radeon_pm_clock_info *current_clock_mode; |
|
- | 773 | struct radeon_power_state *requested_power_state; |
|
- | 774 | struct radeon_pm_clock_info *requested_clock_mode; |
|
- | 775 | struct radeon_power_state *default_power_state; |
|
647 | }; |
776 | }; |
Line 648... | Line 777... | ||
648 | 777 | ||
649 | /* |
778 | /* |
650 | * ASIC specific functions. |
779 | * ASIC specific functions. |
Line 687... | Line 816... | ||
687 | struct radeon_fence *fence); |
816 | struct radeon_fence *fence); |
688 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
817 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
689 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
818 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
690 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
819 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
691 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
820 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
- | 821 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
|
692 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
822 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
693 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
823 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
694 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
824 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
695 | uint32_t tiling_flags, uint32_t pitch, |
825 | uint32_t tiling_flags, uint32_t pitch, |
696 | uint32_t offset, uint32_t obj_size); |
826 | uint32_t offset, uint32_t obj_size); |
Line 737... | Line 867... | ||
737 | unsigned max_gs_threads; |
867 | unsigned max_gs_threads; |
738 | unsigned sx_max_export_size; |
868 | unsigned sx_max_export_size; |
739 | unsigned sx_max_export_pos_size; |
869 | unsigned sx_max_export_pos_size; |
740 | unsigned sx_max_export_smx_size; |
870 | unsigned sx_max_export_smx_size; |
741 | unsigned sq_num_cf_insts; |
871 | unsigned sq_num_cf_insts; |
- | 872 | unsigned tiling_nbanks; |
|
- | 873 | unsigned tiling_npipes; |
|
- | 874 | unsigned tiling_group_size; |
|
742 | }; |
875 | }; |
Line 743... | Line 876... | ||
743 | 876 | ||
744 | struct rv770_asic { |
877 | struct rv770_asic { |
745 | unsigned max_pipes; |
878 | unsigned max_pipes; |
Line 757... | Line 890... | ||
757 | unsigned sq_num_cf_insts; |
890 | unsigned sq_num_cf_insts; |
758 | unsigned sx_num_of_sets; |
891 | unsigned sx_num_of_sets; |
759 | unsigned sc_prim_fifo_size; |
892 | unsigned sc_prim_fifo_size; |
760 | unsigned sc_hiz_tile_fifo_size; |
893 | unsigned sc_hiz_tile_fifo_size; |
761 | unsigned sc_earlyz_tile_fifo_fize; |
894 | unsigned sc_earlyz_tile_fifo_fize; |
- | 895 | unsigned tiling_nbanks; |
|
- | 896 | unsigned tiling_npipes; |
|
- | 897 | unsigned tiling_group_size; |
|
762 | }; |
898 | }; |
Line 763... | Line 899... | ||
763 | 899 | ||
764 | union radeon_asic_config { |
900 | union radeon_asic_config { |
765 | struct r300_asic r300; |
901 | struct r300_asic r300; |
Line 838... | Line 974... | ||
838 | const struct firmware *me_fw; /* all family ME firmware */ |
974 | const struct firmware *me_fw; /* all family ME firmware */ |
839 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
975 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
840 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
976 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
841 | struct r600_blit r600_blit; |
977 | struct r600_blit r600_blit; |
842 | int msi_enabled; /* msi enabled */ |
978 | int msi_enabled; /* msi enabled */ |
- | 979 | int num_crtc; /* number of crtcs */ |
|
Line 843... | Line 980... | ||
843 | 980 | ||
844 | /* audio stuff */ |
981 | /* audio stuff */ |
845 | // struct timer_list audio_timer; |
982 | // struct timer_list audio_timer; |
846 | int audio_channels; |
983 | int audio_channels; |
847 | int audio_rate; |
984 | int audio_rate; |
848 | int audio_bits_per_sample; |
985 | int audio_bits_per_sample; |
849 | uint8_t audio_status_bits; |
986 | uint8_t audio_status_bits; |
- | 987 | uint8_t audio_category_code; |
|
- | 988 | ||
850 | uint8_t audio_category_code; |
989 | bool powered_down; |
Line 851... | Line 990... | ||
851 | }; |
990 | }; |
852 | 991 | ||
853 | int radeon_device_init(struct radeon_device *rdev, |
992 | int radeon_device_init(struct radeon_device *rdev, |
Line 902... | Line 1041... | ||
902 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
1041 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
903 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
1042 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
904 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
1043 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
905 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1044 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
906 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
1045 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
- | 1046 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
|
- | 1047 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
|
907 | #define WREG32_P(reg, val, mask) \ |
1048 | #define WREG32_P(reg, val, mask) \ |
908 | do { \ |
1049 | do { \ |
909 | uint32_t tmp_ = RREG32(reg); \ |
1050 | uint32_t tmp_ = RREG32(reg); \ |
910 | tmp_ &= (mask); \ |
1051 | tmp_ &= (mask); \ |
911 | tmp_ |= ((val) & ~(mask)); \ |
1052 | tmp_ |= ((val) & ~(mask)); \ |
Line 962... | Line 1103... | ||
962 | (rdev->family == CHIP_RS400) || \ |
1103 | (rdev->family == CHIP_RS400) || \ |
963 | (rdev->family == CHIP_RS480)) |
1104 | (rdev->family == CHIP_RS480)) |
964 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1105 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
965 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1106 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
966 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
1107 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
967 | - | ||
- | 1108 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
|
Line 968... | Line 1109... | ||
968 | 1109 | ||
969 | /* |
1110 | /* |
970 | * BIOS helpers. |
1111 | * BIOS helpers. |
971 | */ |
1112 | */ |
Line 1021... | Line 1162... | ||
1021 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
1162 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
1022 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1163 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1023 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1164 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1024 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
1165 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
1025 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
1166 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
- | 1167 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
|
1026 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1168 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1027 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
1169 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
1028 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1170 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1029 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
1171 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
1030 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
1172 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
Line 1035... | Line 1177... | ||
1035 | 1177 | ||
1036 | /* Common functions */ |
1178 | /* Common functions */ |
1037 | /* AGP */ |
1179 | /* AGP */ |
1038 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1180 | extern void radeon_agp_disable(struct radeon_device *rdev); |
- | 1181 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
|
1039 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
1182 | extern void radeon_gart_restore(struct radeon_device *rdev); |
1040 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1183 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1041 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
1184 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
1042 | extern bool radeon_card_posted(struct radeon_device *rdev); |
1185 | extern bool radeon_card_posted(struct radeon_device *rdev); |
1043 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1186 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Line 1048... | Line 1191... | ||
1048 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
1191 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
1049 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1192 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1050 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
1193 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
1051 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1194 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1052 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1195 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
- | 1196 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
|
- | 1197 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
|
- | 1198 | extern int radeon_resume_kms(struct drm_device *dev); |
|
- | 1199 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
|
Line 1053... | Line 1200... | ||
1053 | 1200 | ||
1054 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
1201 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
1055 | struct r100_mc_save { |
1202 | struct r100_mc_save { |
1056 | u32 GENMO_WT; |
1203 | u32 GENMO_WT; |
Line 1102... | Line 1249... | ||
1102 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
1249 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
Line 1103... | Line 1250... | ||
1103 | 1250 | ||
1104 | /* r300,r350,rv350,rv370,rv380 */ |
1251 | /* r300,r350,rv350,rv370,rv380 */ |
1105 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1252 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1106 | extern void r300_mc_program(struct radeon_device *rdev); |
1253 | extern void r300_mc_program(struct radeon_device *rdev); |
1107 | extern void r300_vram_info(struct radeon_device *rdev); |
1254 | extern void r300_mc_init(struct radeon_device *rdev); |
1108 | extern void r300_clock_startup(struct radeon_device *rdev); |
1255 | extern void r300_clock_startup(struct radeon_device *rdev); |
1109 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1256 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1110 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1257 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1111 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
1258 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
1112 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
1259 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
Line 1113... | Line 1260... | ||
1113 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
1260 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
1114 | - | ||
1115 | /* r420,r423,rv410 */ |
1261 | |
1116 | extern int r420_mc_init(struct radeon_device *rdev); |
1262 | /* r420,r423,rv410 */ |
1117 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1263 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1118 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
1264 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Line 1153... | Line 1299... | ||
1153 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
1299 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
1154 | struct drm_display_mode *mode1, |
1300 | struct drm_display_mode *mode1, |
1155 | struct drm_display_mode *mode2); |
1301 | struct drm_display_mode *mode2); |
Line 1156... | Line 1302... | ||
1156 | 1302 | ||
- | 1303 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
|
1157 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
1304 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
1158 | extern bool r600_card_posted(struct radeon_device *rdev); |
1305 | extern bool r600_card_posted(struct radeon_device *rdev); |
1159 | extern void r600_cp_stop(struct radeon_device *rdev); |
1306 | extern void r600_cp_stop(struct radeon_device *rdev); |
1160 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1307 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1161 | extern int r600_cp_resume(struct radeon_device *rdev); |
1308 | extern int r600_cp_resume(struct radeon_device *rdev); |
1162 | extern void r600_cp_fini(struct radeon_device *rdev); |
1309 | extern void r600_cp_fini(struct radeon_device *rdev); |
1163 | extern int r600_count_pipe_bits(uint32_t val); |
- | |
1164 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); |
1310 | extern int r600_count_pipe_bits(uint32_t val); |
1165 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1311 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1166 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
1312 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
1167 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1313 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1168 | extern int r600_ib_test(struct radeon_device *rdev); |
1314 | extern int r600_ib_test(struct radeon_device *rdev); |
Line 1195... | Line 1341... | ||
1195 | int rate, |
1341 | int rate, |
1196 | int bps, |
1342 | int bps, |
1197 | uint8_t status_bits, |
1343 | uint8_t status_bits, |
1198 | uint8_t category_code); |
1344 | uint8_t category_code); |
Line -... | Line 1345... | ||
- | 1345 | ||
- | 1346 | /* evergreen */ |
|
- | 1347 | struct evergreen_mc_save { |
|
- | 1348 | u32 vga_control[6]; |
|
- | 1349 | u32 vga_render_control; |
|
- | 1350 | u32 vga_hdp_control; |
|
- | 1351 | u32 crtc_control[6]; |
|
- | 1352 | }; |
|
1199 | 1353 | ||
Line 1200... | Line 1354... | ||
1200 | #include "radeon_object.h" |
1354 | #include "radeon_object.h" |
Line 1201... | Line 1355... | ||
1201 | 1355 |