WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon.h

  *          Jerome Glisse
  */
 #ifndef __RADEON_H__
 #define __RADEON_H__
-//#include "radeon_object.h"
 /* TODO: Here are things that needs to be done :
  *	- surface allocator & initializer : (bit like scratch reg) should
  *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  *	  related to surface
  *                          function should do is setting the GPU
  *                          memory controller (only MC setup failure
  *                          are considered as fatal)
  */
+#include
+#include
+#include
+#include
 #include
 #include
 #include
 extern int radeon_gart_size;
 extern int radeon_benchmarking;
 extern int radeon_testing;
 extern int radeon_connector_table;
 extern int radeon_tv;
+extern int radeon_new_pll;
 typedef struct
+{
   int width;
   int height;
   int bpp;
   int freq;
-}mode_t;
+}videomode_t;
 static inline uint8_t __raw_readb(const volatile void __iomem *addr)
+{
 /*
  * Fences.
  */
 struct radeon_fence_driver {
 	uint32_t			scratch_reg;
-//	atomic_t			seq;
+	atomic_t			seq;
 	uint32_t			last_seq;
 	unsigned long			count_timeout;
 //	wait_queue_head_t		queue;
-//	rwlock_t			lock;
+	rwlock_t			lock;
 	struct list_head		created;
 	struct list_head		emited;
 	struct list_head		signaled;
 };
 struct radeon_fence {
 	struct radeon_device		*rdev;
-//	struct kref			kref;
+	struct kref			kref;
 	struct list_head		list;
 	/* protected by radeon_fence.lock */
 	uint32_t			seq;
 	unsigned long			timeout;
 /*
  * Tiling registers
  */
 struct radeon_surface_reg {
-	struct radeon_object *robj;
+	struct radeon_bo *bo;
 };
 #define RADEON_GEM_MAX_SURFACES 8
+/*
+ * TTM.
+ */
+struct radeon_mman {
+	struct ttm_bo_global_ref        bo_global_ref;
+	struct ttm_global_reference	mem_global_ref;
+	bool				mem_global_referenced;
-/*
+	struct ttm_bo_device		bdev;
+};
+struct radeon_bo {
+	/* Protected by gem.mutex */
+	struct list_head		list;
+	/* Protected by tbo.reserved */
+	u32				placements[3];
+	struct ttm_placement		placement;
+	struct ttm_buffer_object	tbo;
+	struct ttm_bo_kmap_obj		kmap;
+	unsigned			pin_count;
+	void				*kptr;
+	u32				tiling_flags;
+	u32				pitch;
+	int				surface_reg;
+	/* Constant after initialization */
- * Radeon buffer.
+	struct radeon_device		*rdev;
- */
+	struct drm_gem_object		*gobj;
-struct radeon_object;
+};
-struct radeon_object_list {
+struct radeon_bo_list {
 	struct list_head	list;
-	struct radeon_object	*robj;
+	struct radeon_bo	*bo;
 	uint64_t		gpu_offset;
-	unsigned		rdomain;
-	unsigned		wdomain;
-	uint32_t                tiling_flags;
-};
-int radeon_object_init(struct radeon_device *rdev);
-void radeon_object_fini(struct radeon_device *rdev);
-int radeon_object_create(struct radeon_device *rdev,
-			 struct drm_gem_object *gobj,
-			 unsigned long size,
-			 bool kernel,
-			 uint32_t domain,
+	unsigned		rdomain;
-			 bool interruptible,
+	unsigned		wdomain;
-			 struct radeon_object **robj_ptr);
+	u32			tiling_flags;
 };
 int radeon_gem_init(struct radeon_device *rdev);
 void radeon_gem_fini(struct radeon_device *rdev);
 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 			     int alignment, int initial_domain,
 			     bool discardable, bool kernel,
-			     bool interruptible,
 			     struct drm_gem_object **obj);
 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 			  uint64_t *gpu_addr);
 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 struct radeon_gart_table_ram {
     volatile uint32_t       *ptr;
 };
 struct radeon_gart_table_vram {
-    struct radeon_object        *robj;
+	struct radeon_bo		*robj;
     volatile uint32_t       *ptr;
 };
 struct radeon_irq {
 	bool		installed;
 	bool		sw_int;
 	/* FIXME: use a define max crtc rather than hardcode it */
 	bool		crtc_vblank_int[2];
+	/* FIXME: use defines for max hpd/dacs */
+	bool            hpd[6];
+    spinlock_t  sw_lock;
+	int sw_refcount;
 };
 int radeon_irq_kms_init(struct radeon_device *rdev);
-void radeon_irq_kms_fini(struct radeon_device *rdev);
+void radeon_irq_kms_fini(struct radeon_device *rdev);
+void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 /*
  * CP & ring.
  * locking -
  * mutex protects scheduled_ibs, ready, alloc_bm
  */
 struct radeon_ib_pool {
 //	struct mutex		mutex;
-	struct radeon_object	*robj;
+	struct radeon_bo	*robj;
 	struct list_head	scheduled_ibs;
 	struct radeon_ib	ibs[RADEON_IB_POOL_SIZE];
 	bool			ready;
 	DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
 };
 struct radeon_cp {
-	struct radeon_object	*ring_obj;
+	struct radeon_bo	*ring_obj;
 	volatile uint32_t	*ring;
 	unsigned		rptr;
 	unsigned		wptr;
 	unsigned		wptr_old;
 	uint32_t		ptr_mask;
 //	struct mutex		mutex;
 	bool			ready;
 };
+/*
+ * R6xx+ IH ring
+ */
+struct r600_ih {
+	struct radeon_bo	*ring_obj;
+	volatile uint32_t	*ring;
+    unsigned            rptr;
+    unsigned            wptr;
+    unsigned            wptr_old;
+    unsigned            ring_size;
+    uint64_t            gpu_addr;
+    uint32_t            align_mask;
+    uint32_t            ptr_mask;
+    spinlock_t              lock;
+    bool                enabled;
+};
 struct r600_blit {
-	struct radeon_object	*shader_obj;
+	struct radeon_bo	*shader_obj;
 	u64 shader_gpu_addr;
 	u32 vs_offset, ps_offset;
 	u32 state_offset;
 	u32 state_len;
 /*
  * CS.
  */
 struct radeon_cs_reloc {
 //	struct drm_gem_object		*gobj;
-	struct radeon_object		*robj;
+	struct radeon_bo		*robj;
-	struct radeon_object_list	lobj;
+//    struct radeon_bo_list   lobj;
 	uint32_t			handle;
 	uint32_t			flags;
 };
 /*
  * AGP
  */
+int radeon_agp_init(struct radeon_device *rdev);
-int radeon_agp_init(struct radeon_device *rdev);
+void radeon_agp_resume(struct radeon_device *rdev);
 void radeon_agp_fini(struct radeon_device *rdev);
 /*
  * Writeback
  */
 struct radeon_wb {
-	struct radeon_object	*wb_obj;
+	struct radeon_bo	*wb_obj;
 	volatile uint32_t	*wb;
 	int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 			       uint32_t tiling_flags, uint32_t pitch,
 			       uint32_t offset, uint32_t obj_size);
 	int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 	void (*bandwidth_update)(struct radeon_device *rdev);
+	void (*hdp_flush)(struct radeon_device *rdev);
+	void (*hpd_init)(struct radeon_device *rdev);
+	void (*hpd_fini)(struct radeon_device *rdev);
+	bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
+	void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 };
 /*
  * Asic structures
     int                         disp_priority;
     /* BIOS */
     uint8_t                     *bios;
     bool                        is_atom_bios;
     uint16_t                    bios_header_start;
-//    struct radeon_object        *stollen_vga_memory;
+	struct radeon_bo		*stollen_vga_memory;
     struct fb_info              *fbdev_info;
-    struct radeon_object        *fbdev_robj;
+	struct radeon_bo		*fbdev_rbo;
     struct radeon_framebuffer   *fbdev_rfb;
     /* Register mmio */
     unsigned long               rmmio_base;
     unsigned long               rmmio_size;
     void                       *rmmio;
     struct radeon_clock         clock;
     struct radeon_mc            mc;
     struct radeon_gart          gart;
 	struct radeon_mode_info		mode_info;
     struct radeon_scratch       scratch;
-//    struct radeon_mman          mman;
+    struct radeon_mman          mman;
 	struct radeon_fence_driver	fence_drv;
     struct radeon_cp            cp;
     struct radeon_ib_pool       ib_pool;
 //    struct radeon_irq       irq;
     struct radeon_asic         *asic;
 		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 		writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
+	}
+}
+/*
+ * Cast helper
+ */
 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
 /*
  * Registers read & write functions.
 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
-#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
+#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
+#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
+#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
+#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
+#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
+#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
 /* Common functions */
 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
 extern void radeon_modeset_fini(struct radeon_device *rdev);
+extern bool radeon_card_posted(struct radeon_device *rdev);
-extern bool radeon_card_posted(struct radeon_device *rdev);
+extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
 extern int radeon_clocks_init(struct radeon_device *rdev);
 extern void radeon_clocks_fini(struct radeon_device *rdev);
 extern void radeon_scratch_init(struct radeon_device *rdev);
 extern void radeon_surface_init(struct radeon_device *rdev);
 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
+extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
-extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
+extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 struct r100_mc_save {
 extern int r100_rb2d_reset(struct radeon_device *rdev);
 extern int r100_cp_reset(struct radeon_device *rdev);
 extern void r100_vga_render_disable(struct radeon_device *rdev);
 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 						struct radeon_cs_packet *pkt,
-						struct radeon_object *robj);
+						struct radeon_bo *robj);
 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 				struct radeon_cs_packet *pkt,
 				const unsigned *auth, unsigned n,
 				radeon_packet0_check_t check);
 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
 				struct radeon_cs_packet *pkt,
 				unsigned idx);
+extern void r100_enable_bm(struct radeon_device *rdev);
+extern void r100_set_common_regs(struct radeon_device *rdev);
 /* rv200,rv250,rv280 */
 extern void r200_set_safe_registers(struct radeon_device *rdev);
 extern int r600_wb_enable(struct radeon_device *rdev);
 extern void r600_wb_disable(struct radeon_device *rdev);
 extern void r600_scratch_init(struct radeon_device *rdev);
 extern int r600_blit_init(struct radeon_device *rdev);
 extern void r600_blit_fini(struct radeon_device *rdev);
-extern int r600_cp_init_microcode(struct radeon_device *rdev);
+extern int r600_init_microcode(struct radeon_device *rdev);
 extern int r600_gpu_reset(struct radeon_device *rdev);
+/* r600 irq */
+extern int r600_irq_init(struct radeon_device *rdev);
+extern void r600_irq_fini(struct radeon_device *rdev);
+extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
+extern int r600_irq_set(struct radeon_device *rdev);
 #include "radeon_object.h"
 #define DRM_UDELAY(d)           udelay(d)

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon.h @ 1268 – Rev 1268 → 1321