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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #ifndef __RADEON_H__ |
28 | #ifndef __RADEON_H__ |
29 | #define __RADEON_H__ |
29 | #define __RADEON_H__ |
30 | 30 | ||
31 | //#include "radeon_object.h" |
31 | //#include "radeon_object.h" |
32 | 32 | ||
33 | /* TODO: Here are things that needs to be done : |
33 | /* TODO: Here are things that needs to be done : |
34 | * - surface allocator & initializer : (bit like scratch reg) should |
34 | * - surface allocator & initializer : (bit like scratch reg) should |
35 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
35 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
36 | * related to surface |
36 | * related to surface |
37 | * - WB : write back stuff (do it bit like scratch reg things) |
37 | * - WB : write back stuff (do it bit like scratch reg things) |
38 | * - Vblank : look at Jesse's rework and what we should do |
38 | * - Vblank : look at Jesse's rework and what we should do |
39 | * - r600/r700: gart & cp |
39 | * - r600/r700: gart & cp |
40 | * - cs : clean cs ioctl use bitmap & things like that. |
40 | * - cs : clean cs ioctl use bitmap & things like that. |
41 | * - power management stuff |
41 | * - power management stuff |
42 | * - Barrier in gart code |
42 | * - Barrier in gart code |
43 | * - Unmappabled vram ? |
43 | * - Unmappabled vram ? |
44 | * - TESTING, TESTING, TESTING |
44 | * - TESTING, TESTING, TESTING |
45 | */ |
45 | */ |
46 | 46 | ||
47 | /* Initialization path: |
47 | /* Initialization path: |
48 | * We expect that acceleration initialization might fail for various |
48 | * We expect that acceleration initialization might fail for various |
49 | * reasons even thought we work hard to make it works on most |
49 | * reasons even thought we work hard to make it works on most |
50 | * configurations. In order to still have a working userspace in such |
50 | * configurations. In order to still have a working userspace in such |
51 | * situation the init path must succeed up to the memory controller |
51 | * situation the init path must succeed up to the memory controller |
52 | * initialization point. Failure before this point are considered as |
52 | * initialization point. Failure before this point are considered as |
53 | * fatal error. Here is the init callchain : |
53 | * fatal error. Here is the init callchain : |
54 | * radeon_device_init perform common structure, mutex initialization |
54 | * radeon_device_init perform common structure, mutex initialization |
55 | * asic_init setup the GPU memory layout and perform all |
55 | * asic_init setup the GPU memory layout and perform all |
56 | * one time initialization (failure in this |
56 | * one time initialization (failure in this |
57 | * function are considered fatal) |
57 | * function are considered fatal) |
58 | * asic_startup setup the GPU acceleration, in order to |
58 | * asic_startup setup the GPU acceleration, in order to |
59 | * follow guideline the first thing this |
59 | * follow guideline the first thing this |
60 | * function should do is setting the GPU |
60 | * function should do is setting the GPU |
61 | * memory controller (only MC setup failure |
61 | * memory controller (only MC setup failure |
62 | * are considered as fatal) |
62 | * are considered as fatal) |
63 | */ |
63 | */ |
64 | 64 | ||
65 | 65 | ||
66 | #include |
66 | #include |
67 | 67 | ||
68 | 68 | ||
69 | #include |
69 | #include |
70 | 70 | ||
71 | #include |
71 | #include |
72 | 72 | ||
73 | #include |
73 | #include |
74 | #include "drm_edid.h" |
74 | #include "drm_edid.h" |
75 | 75 | ||
76 | #include "radeon_family.h" |
76 | #include "radeon_family.h" |
77 | #include "radeon_mode.h" |
77 | #include "radeon_mode.h" |
78 | #include "radeon_reg.h" |
78 | #include "radeon_reg.h" |
79 | 79 | ||
80 | #include |
80 | #include |
81 | 81 | ||
82 | /* |
82 | /* |
83 | * Modules parameters. |
83 | * Modules parameters. |
84 | */ |
84 | */ |
85 | extern int radeon_no_wb; |
85 | extern int radeon_no_wb; |
86 | extern int radeon_modeset; |
86 | extern int radeon_modeset; |
87 | extern int radeon_dynclks; |
87 | extern int radeon_dynclks; |
88 | extern int radeon_r4xx_atom; |
88 | extern int radeon_r4xx_atom; |
89 | extern int radeon_agpmode; |
89 | extern int radeon_agpmode; |
90 | extern int radeon_vram_limit; |
90 | extern int radeon_vram_limit; |
91 | extern int radeon_gart_size; |
91 | extern int radeon_gart_size; |
92 | extern int radeon_benchmarking; |
92 | extern int radeon_benchmarking; |
93 | extern int radeon_testing; |
93 | extern int radeon_testing; |
94 | extern int radeon_connector_table; |
94 | extern int radeon_connector_table; |
95 | extern int radeon_tv; |
95 | extern int radeon_tv; |
96 | 96 | ||
97 | typedef struct |
97 | typedef struct |
98 | { |
98 | { |
99 | int width; |
99 | int width; |
100 | int height; |
100 | int height; |
101 | int bpp; |
101 | int bpp; |
102 | int freq; |
102 | int freq; |
103 | }mode_t; |
103 | }mode_t; |
104 | 104 | ||
105 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
105 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
106 | { |
106 | { |
107 | return *(const volatile uint8_t __force *) addr; |
107 | return *(const volatile uint8_t __force *) addr; |
108 | } |
108 | } |
109 | 109 | ||
110 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
110 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
111 | { |
111 | { |
112 | return *(const volatile uint16_t __force *) addr; |
112 | return *(const volatile uint16_t __force *) addr; |
113 | } |
113 | } |
114 | 114 | ||
115 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
115 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
116 | { |
116 | { |
117 | return *(const volatile uint32_t __force *) addr; |
117 | return *(const volatile uint32_t __force *) addr; |
118 | } |
118 | } |
119 | 119 | ||
120 | #define readb __raw_readb |
120 | #define readb __raw_readb |
121 | #define readw __raw_readw |
121 | #define readw __raw_readw |
122 | #define readl __raw_readl |
122 | #define readl __raw_readl |
123 | 123 | ||
124 | 124 | ||
125 | 125 | ||
126 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
126 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
127 | { |
127 | { |
128 | *(volatile uint8_t __force *) addr = b; |
128 | *(volatile uint8_t __force *) addr = b; |
129 | } |
129 | } |
130 | 130 | ||
131 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
131 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
132 | { |
132 | { |
133 | *(volatile uint16_t __force *) addr = b; |
133 | *(volatile uint16_t __force *) addr = b; |
134 | } |
134 | } |
135 | 135 | ||
136 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
136 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
137 | { |
137 | { |
138 | *(volatile uint32_t __force *) addr = b; |
138 | *(volatile uint32_t __force *) addr = b; |
139 | } |
139 | } |
140 | 140 | ||
141 | static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
141 | static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
142 | { |
142 | { |
143 | *(volatile __u64 *)addr = b; |
143 | *(volatile __u64 *)addr = b; |
144 | } |
144 | } |
145 | 145 | ||
146 | #define writeb __raw_writeb |
146 | #define writeb __raw_writeb |
147 | #define writew __raw_writew |
147 | #define writew __raw_writew |
148 | #define writel __raw_writel |
148 | #define writel __raw_writel |
149 | #define writeq __raw_writeq |
149 | #define writeq __raw_writeq |
150 | 150 | ||
151 | 151 | ||
152 | /* |
152 | /* |
153 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
153 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
154 | * symbol; |
154 | * symbol; |
155 | */ |
155 | */ |
156 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
156 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
157 | #define RADEON_IB_POOL_SIZE 16 |
157 | #define RADEON_IB_POOL_SIZE 16 |
158 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
158 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
159 | #define RADEONFB_CONN_LIMIT 4 |
159 | #define RADEONFB_CONN_LIMIT 4 |
160 | #define RADEON_BIOS_NUM_SCRATCH 8 |
160 | #define RADEON_BIOS_NUM_SCRATCH 8 |
161 | 161 | ||
162 | /* |
162 | /* |
163 | * Errata workarounds. |
163 | * Errata workarounds. |
164 | */ |
164 | */ |
165 | enum radeon_pll_errata { |
165 | enum radeon_pll_errata { |
166 | CHIP_ERRATA_R300_CG = 0x00000001, |
166 | CHIP_ERRATA_R300_CG = 0x00000001, |
167 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
167 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
168 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
168 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
169 | }; |
169 | }; |
170 | 170 | ||
171 | 171 | ||
172 | struct radeon_device; |
172 | struct radeon_device; |
173 | 173 | ||
174 | 174 | ||
175 | /* |
175 | /* |
176 | * BIOS. |
176 | * BIOS. |
177 | */ |
177 | */ |
178 | bool radeon_get_bios(struct radeon_device *rdev); |
178 | bool radeon_get_bios(struct radeon_device *rdev); |
179 | 179 | ||
180 | 180 | ||
181 | /* |
181 | /* |
182 | * Dummy page |
182 | * Dummy page |
183 | */ |
183 | */ |
184 | struct radeon_dummy_page { |
184 | struct radeon_dummy_page { |
185 | struct page *page; |
185 | struct page *page; |
186 | dma_addr_t addr; |
186 | dma_addr_t addr; |
187 | }; |
187 | }; |
188 | int radeon_dummy_page_init(struct radeon_device *rdev); |
188 | int radeon_dummy_page_init(struct radeon_device *rdev); |
189 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
189 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
190 | 190 | ||
191 | 191 | ||
192 | /* |
192 | /* |
193 | * Clocks |
193 | * Clocks |
194 | */ |
194 | */ |
195 | struct radeon_clock { |
195 | struct radeon_clock { |
196 | struct radeon_pll p1pll; |
196 | struct radeon_pll p1pll; |
197 | struct radeon_pll p2pll; |
197 | struct radeon_pll p2pll; |
198 | struct radeon_pll spll; |
198 | struct radeon_pll spll; |
199 | struct radeon_pll mpll; |
199 | struct radeon_pll mpll; |
200 | /* 10 Khz units */ |
200 | /* 10 Khz units */ |
201 | uint32_t default_mclk; |
201 | uint32_t default_mclk; |
202 | uint32_t default_sclk; |
202 | uint32_t default_sclk; |
203 | }; |
203 | }; |
- | 204 | ||
- | 205 | /* |
|
- | 206 | * Power management |
|
- | 207 | */ |
|
204 | 208 | int radeon_pm_init(struct radeon_device *rdev); |
|
205 | 209 | ||
206 | /* |
210 | /* |
207 | * Fences. |
211 | * Fences. |
208 | */ |
212 | */ |
209 | struct radeon_fence_driver { |
213 | struct radeon_fence_driver { |
210 | uint32_t scratch_reg; |
214 | uint32_t scratch_reg; |
211 | // atomic_t seq; |
215 | // atomic_t seq; |
212 | uint32_t last_seq; |
216 | uint32_t last_seq; |
213 | unsigned long count_timeout; |
217 | unsigned long count_timeout; |
214 | // wait_queue_head_t queue; |
218 | // wait_queue_head_t queue; |
215 | // rwlock_t lock; |
219 | // rwlock_t lock; |
216 | struct list_head created; |
220 | struct list_head created; |
217 | struct list_head emited; |
221 | struct list_head emited; |
218 | struct list_head signaled; |
222 | struct list_head signaled; |
219 | }; |
223 | }; |
220 | 224 | ||
221 | struct radeon_fence { |
225 | struct radeon_fence { |
222 | struct radeon_device *rdev; |
226 | struct radeon_device *rdev; |
223 | // struct kref kref; |
227 | // struct kref kref; |
224 | struct list_head list; |
228 | struct list_head list; |
225 | /* protected by radeon_fence.lock */ |
229 | /* protected by radeon_fence.lock */ |
226 | uint32_t seq; |
230 | uint32_t seq; |
227 | unsigned long timeout; |
231 | unsigned long timeout; |
228 | bool emited; |
232 | bool emited; |
229 | bool signaled; |
233 | bool signaled; |
230 | }; |
234 | }; |
231 | 235 | ||
232 | int radeon_fence_driver_init(struct radeon_device *rdev); |
236 | int radeon_fence_driver_init(struct radeon_device *rdev); |
233 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
237 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
234 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
238 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
235 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
239 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
236 | void radeon_fence_process(struct radeon_device *rdev); |
240 | void radeon_fence_process(struct radeon_device *rdev); |
237 | bool radeon_fence_signaled(struct radeon_fence *fence); |
241 | bool radeon_fence_signaled(struct radeon_fence *fence); |
238 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
242 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
239 | int radeon_fence_wait_next(struct radeon_device *rdev); |
243 | int radeon_fence_wait_next(struct radeon_device *rdev); |
240 | int radeon_fence_wait_last(struct radeon_device *rdev); |
244 | int radeon_fence_wait_last(struct radeon_device *rdev); |
241 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
245 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
242 | void radeon_fence_unref(struct radeon_fence **fence); |
246 | void radeon_fence_unref(struct radeon_fence **fence); |
243 | 247 | ||
244 | /* |
248 | /* |
245 | * Tiling registers |
249 | * Tiling registers |
246 | */ |
250 | */ |
247 | struct radeon_surface_reg { |
251 | struct radeon_surface_reg { |
248 | struct radeon_object *robj; |
252 | struct radeon_object *robj; |
249 | }; |
253 | }; |
250 | 254 | ||
251 | #define RADEON_GEM_MAX_SURFACES 8 |
255 | #define RADEON_GEM_MAX_SURFACES 8 |
252 | 256 | ||
253 | /* |
257 | /* |
254 | * Radeon buffer. |
258 | * Radeon buffer. |
255 | */ |
259 | */ |
256 | struct radeon_object; |
260 | struct radeon_object; |
257 | 261 | ||
258 | struct radeon_object_list { |
262 | struct radeon_object_list { |
259 | struct list_head list; |
263 | struct list_head list; |
260 | struct radeon_object *robj; |
264 | struct radeon_object *robj; |
261 | uint64_t gpu_offset; |
265 | uint64_t gpu_offset; |
262 | unsigned rdomain; |
266 | unsigned rdomain; |
263 | unsigned wdomain; |
267 | unsigned wdomain; |
264 | uint32_t tiling_flags; |
268 | uint32_t tiling_flags; |
265 | }; |
269 | }; |
266 | 270 | ||
267 | int radeon_object_init(struct radeon_device *rdev); |
271 | int radeon_object_init(struct radeon_device *rdev); |
268 | void radeon_object_fini(struct radeon_device *rdev); |
272 | void radeon_object_fini(struct radeon_device *rdev); |
269 | int radeon_object_create(struct radeon_device *rdev, |
273 | int radeon_object_create(struct radeon_device *rdev, |
270 | struct drm_gem_object *gobj, |
274 | struct drm_gem_object *gobj, |
271 | unsigned long size, |
275 | unsigned long size, |
272 | bool kernel, |
276 | bool kernel, |
273 | uint32_t domain, |
277 | uint32_t domain, |
274 | bool interruptible, |
278 | bool interruptible, |
275 | struct radeon_object **robj_ptr); |
279 | struct radeon_object **robj_ptr); |
276 | 280 | ||
277 | 281 | ||
278 | /* |
282 | /* |
279 | * GEM objects. |
283 | * GEM objects. |
280 | */ |
284 | */ |
281 | struct radeon_gem { |
285 | struct radeon_gem { |
282 | struct list_head objects; |
286 | struct list_head objects; |
283 | }; |
287 | }; |
284 | 288 | ||
285 | int radeon_gem_init(struct radeon_device *rdev); |
289 | int radeon_gem_init(struct radeon_device *rdev); |
286 | void radeon_gem_fini(struct radeon_device *rdev); |
290 | void radeon_gem_fini(struct radeon_device *rdev); |
287 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
291 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
288 | int alignment, int initial_domain, |
292 | int alignment, int initial_domain, |
289 | bool discardable, bool kernel, |
293 | bool discardable, bool kernel, |
290 | bool interruptible, |
294 | bool interruptible, |
291 | struct drm_gem_object **obj); |
295 | struct drm_gem_object **obj); |
292 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
296 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
293 | uint64_t *gpu_addr); |
297 | uint64_t *gpu_addr); |
294 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
298 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
295 | 299 | ||
296 | 300 | ||
297 | /* |
301 | /* |
298 | * GART structures, functions & helpers |
302 | * GART structures, functions & helpers |
299 | */ |
303 | */ |
300 | struct radeon_mc; |
304 | struct radeon_mc; |
301 | 305 | ||
302 | struct radeon_gart_table_ram { |
306 | struct radeon_gart_table_ram { |
303 | volatile uint32_t *ptr; |
307 | volatile uint32_t *ptr; |
304 | }; |
308 | }; |
305 | 309 | ||
306 | struct radeon_gart_table_vram { |
310 | struct radeon_gart_table_vram { |
307 | struct radeon_object *robj; |
311 | struct radeon_object *robj; |
308 | volatile uint32_t *ptr; |
312 | volatile uint32_t *ptr; |
309 | }; |
313 | }; |
310 | 314 | ||
311 | union radeon_gart_table { |
315 | union radeon_gart_table { |
312 | struct radeon_gart_table_ram ram; |
316 | struct radeon_gart_table_ram ram; |
313 | struct radeon_gart_table_vram vram; |
317 | struct radeon_gart_table_vram vram; |
314 | }; |
318 | }; |
- | 319 | ||
- | 320 | #define RADEON_GPU_PAGE_SIZE 4096 |
|
315 | 321 | ||
316 | struct radeon_gart { |
322 | struct radeon_gart { |
317 | dma_addr_t table_addr; |
323 | dma_addr_t table_addr; |
318 | unsigned num_gpu_pages; |
324 | unsigned num_gpu_pages; |
319 | unsigned num_cpu_pages; |
325 | unsigned num_cpu_pages; |
320 | unsigned table_size; |
326 | unsigned table_size; |
321 | union radeon_gart_table table; |
327 | union radeon_gart_table table; |
322 | struct page **pages; |
328 | struct page **pages; |
323 | dma_addr_t *pages_addr; |
329 | dma_addr_t *pages_addr; |
324 | bool ready; |
330 | bool ready; |
325 | }; |
331 | }; |
326 | 332 | ||
327 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
333 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
328 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
334 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
329 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
335 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
330 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
336 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
331 | int radeon_gart_init(struct radeon_device *rdev); |
337 | int radeon_gart_init(struct radeon_device *rdev); |
332 | void radeon_gart_fini(struct radeon_device *rdev); |
338 | void radeon_gart_fini(struct radeon_device *rdev); |
333 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
339 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
334 | int pages); |
340 | int pages); |
335 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
341 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
336 | int pages, u32_t *pagelist); |
342 | int pages, u32_t *pagelist); |
337 | 343 | ||
338 | 344 | ||
339 | /* |
345 | /* |
340 | * GPU MC structures, functions & helpers |
346 | * GPU MC structures, functions & helpers |
341 | */ |
347 | */ |
342 | struct radeon_mc { |
348 | struct radeon_mc { |
343 | resource_size_t aper_size; |
349 | resource_size_t aper_size; |
344 | resource_size_t aper_base; |
350 | resource_size_t aper_base; |
345 | resource_size_t agp_base; |
351 | resource_size_t agp_base; |
346 | /* for some chips with <= 32MB we need to lie |
352 | /* for some chips with <= 32MB we need to lie |
347 | * about vram size near mc fb location */ |
353 | * about vram size near mc fb location */ |
348 | u64 mc_vram_size; |
354 | u64 mc_vram_size; |
349 | u64 gtt_location; |
355 | u64 gtt_location; |
350 | u64 gtt_size; |
356 | u64 gtt_size; |
351 | u64 gtt_start; |
357 | u64 gtt_start; |
352 | u64 gtt_end; |
358 | u64 gtt_end; |
353 | u64 vram_location; |
359 | u64 vram_location; |
354 | u64 vram_start; |
360 | u64 vram_start; |
355 | u64 vram_end; |
361 | u64 vram_end; |
356 | unsigned vram_width; |
362 | unsigned vram_width; |
357 | u64 real_vram_size; |
363 | u64 real_vram_size; |
358 | int vram_mtrr; |
364 | int vram_mtrr; |
359 | bool vram_is_ddr; |
365 | bool vram_is_ddr; |
360 | }; |
366 | }; |
361 | 367 | ||
362 | int radeon_mc_setup(struct radeon_device *rdev); |
368 | int radeon_mc_setup(struct radeon_device *rdev); |
363 | 369 | ||
364 | 370 | ||
365 | /* |
371 | /* |
366 | * GPU scratch registers structures, functions & helpers |
372 | * GPU scratch registers structures, functions & helpers |
367 | */ |
373 | */ |
368 | struct radeon_scratch { |
374 | struct radeon_scratch { |
369 | unsigned num_reg; |
375 | unsigned num_reg; |
370 | bool free[32]; |
376 | bool free[32]; |
371 | uint32_t reg[32]; |
377 | uint32_t reg[32]; |
372 | }; |
378 | }; |
373 | 379 | ||
374 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
380 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
375 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
381 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
376 | 382 | ||
377 | 383 | ||
378 | /* |
384 | /* |
379 | * IRQS. |
385 | * IRQS. |
380 | */ |
386 | */ |
381 | struct radeon_irq { |
387 | struct radeon_irq { |
382 | bool installed; |
388 | bool installed; |
383 | bool sw_int; |
389 | bool sw_int; |
384 | /* FIXME: use a define max crtc rather than hardcode it */ |
390 | /* FIXME: use a define max crtc rather than hardcode it */ |
385 | bool crtc_vblank_int[2]; |
391 | bool crtc_vblank_int[2]; |
386 | }; |
392 | }; |
387 | 393 | ||
388 | int radeon_irq_kms_init(struct radeon_device *rdev); |
394 | int radeon_irq_kms_init(struct radeon_device *rdev); |
389 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
395 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
390 | 396 | ||
391 | 397 | ||
392 | /* |
398 | /* |
393 | * CP & ring. |
399 | * CP & ring. |
394 | */ |
400 | */ |
395 | struct radeon_ib { |
401 | struct radeon_ib { |
396 | struct list_head list; |
402 | struct list_head list; |
397 | unsigned long idx; |
403 | unsigned long idx; |
398 | uint64_t gpu_addr; |
404 | uint64_t gpu_addr; |
399 | struct radeon_fence *fence; |
405 | struct radeon_fence *fence; |
400 | uint32_t *ptr; |
406 | uint32_t *ptr; |
401 | uint32_t length_dw; |
407 | uint32_t length_dw; |
402 | }; |
408 | }; |
403 | 409 | ||
404 | /* |
410 | /* |
405 | * locking - |
411 | * locking - |
406 | * mutex protects scheduled_ibs, ready, alloc_bm |
412 | * mutex protects scheduled_ibs, ready, alloc_bm |
407 | */ |
413 | */ |
408 | struct radeon_ib_pool { |
414 | struct radeon_ib_pool { |
409 | // struct mutex mutex; |
415 | // struct mutex mutex; |
410 | struct radeon_object *robj; |
416 | struct radeon_object *robj; |
411 | struct list_head scheduled_ibs; |
417 | struct list_head scheduled_ibs; |
412 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
418 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
413 | bool ready; |
419 | bool ready; |
414 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); |
420 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); |
415 | }; |
421 | }; |
416 | 422 | ||
417 | struct radeon_cp { |
423 | struct radeon_cp { |
418 | struct radeon_object *ring_obj; |
424 | struct radeon_object *ring_obj; |
419 | volatile uint32_t *ring; |
425 | volatile uint32_t *ring; |
420 | unsigned rptr; |
426 | unsigned rptr; |
421 | unsigned wptr; |
427 | unsigned wptr; |
422 | unsigned wptr_old; |
428 | unsigned wptr_old; |
423 | unsigned ring_size; |
429 | unsigned ring_size; |
424 | unsigned ring_free_dw; |
430 | unsigned ring_free_dw; |
425 | int count_dw; |
431 | int count_dw; |
426 | uint64_t gpu_addr; |
432 | uint64_t gpu_addr; |
427 | uint32_t align_mask; |
433 | uint32_t align_mask; |
428 | uint32_t ptr_mask; |
434 | uint32_t ptr_mask; |
429 | // struct mutex mutex; |
435 | // struct mutex mutex; |
430 | bool ready; |
436 | bool ready; |
431 | }; |
437 | }; |
432 | 438 | ||
433 | struct r600_blit { |
439 | struct r600_blit { |
434 | struct radeon_object *shader_obj; |
440 | struct radeon_object *shader_obj; |
435 | u64 shader_gpu_addr; |
441 | u64 shader_gpu_addr; |
436 | u32 vs_offset, ps_offset; |
442 | u32 vs_offset, ps_offset; |
437 | u32 state_offset; |
443 | u32 state_offset; |
438 | u32 state_len; |
444 | u32 state_len; |
439 | u32 vb_used, vb_total; |
445 | u32 vb_used, vb_total; |
440 | struct radeon_ib *vb_ib; |
446 | struct radeon_ib *vb_ib; |
441 | }; |
447 | }; |
442 | 448 | ||
443 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
449 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
444 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
450 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
445 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
451 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
446 | int radeon_ib_pool_init(struct radeon_device *rdev); |
452 | int radeon_ib_pool_init(struct radeon_device *rdev); |
447 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
453 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
448 | int radeon_ib_test(struct radeon_device *rdev); |
454 | int radeon_ib_test(struct radeon_device *rdev); |
449 | /* Ring access between begin & end cannot sleep */ |
455 | /* Ring access between begin & end cannot sleep */ |
450 | void radeon_ring_free_size(struct radeon_device *rdev); |
456 | void radeon_ring_free_size(struct radeon_device *rdev); |
451 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
457 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
452 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
458 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
453 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
459 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
454 | int radeon_ring_test(struct radeon_device *rdev); |
460 | int radeon_ring_test(struct radeon_device *rdev); |
455 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
461 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
456 | void radeon_ring_fini(struct radeon_device *rdev); |
462 | void radeon_ring_fini(struct radeon_device *rdev); |
457 | 463 | ||
458 | 464 | ||
459 | /* |
465 | /* |
460 | * CS. |
466 | * CS. |
461 | */ |
467 | */ |
462 | struct radeon_cs_reloc { |
468 | struct radeon_cs_reloc { |
463 | // struct drm_gem_object *gobj; |
469 | // struct drm_gem_object *gobj; |
464 | struct radeon_object *robj; |
470 | struct radeon_object *robj; |
465 | struct radeon_object_list lobj; |
471 | struct radeon_object_list lobj; |
466 | uint32_t handle; |
472 | uint32_t handle; |
467 | uint32_t flags; |
473 | uint32_t flags; |
468 | }; |
474 | }; |
469 | 475 | ||
470 | struct radeon_cs_chunk { |
476 | struct radeon_cs_chunk { |
471 | uint32_t chunk_id; |
477 | uint32_t chunk_id; |
472 | uint32_t length_dw; |
478 | uint32_t length_dw; |
473 | int kpage_idx[2]; |
479 | int kpage_idx[2]; |
474 | uint32_t *kpage[2]; |
480 | uint32_t *kpage[2]; |
475 | uint32_t *kdata; |
481 | uint32_t *kdata; |
476 | void __user *user_ptr; |
482 | void __user *user_ptr; |
477 | int last_copied_page; |
483 | int last_copied_page; |
478 | int last_page_index; |
484 | int last_page_index; |
479 | }; |
485 | }; |
480 | 486 | ||
481 | struct radeon_cs_parser { |
487 | struct radeon_cs_parser { |
482 | struct radeon_device *rdev; |
488 | struct radeon_device *rdev; |
483 | // struct drm_file *filp; |
489 | // struct drm_file *filp; |
484 | /* chunks */ |
490 | /* chunks */ |
485 | unsigned nchunks; |
491 | unsigned nchunks; |
486 | struct radeon_cs_chunk *chunks; |
492 | struct radeon_cs_chunk *chunks; |
487 | uint64_t *chunks_array; |
493 | uint64_t *chunks_array; |
488 | /* IB */ |
494 | /* IB */ |
489 | unsigned idx; |
495 | unsigned idx; |
490 | /* relocations */ |
496 | /* relocations */ |
491 | unsigned nrelocs; |
497 | unsigned nrelocs; |
492 | struct radeon_cs_reloc *relocs; |
498 | struct radeon_cs_reloc *relocs; |
493 | struct radeon_cs_reloc **relocs_ptr; |
499 | struct radeon_cs_reloc **relocs_ptr; |
494 | struct list_head validated; |
500 | struct list_head validated; |
495 | /* indices of various chunks */ |
501 | /* indices of various chunks */ |
496 | int chunk_ib_idx; |
502 | int chunk_ib_idx; |
497 | int chunk_relocs_idx; |
503 | int chunk_relocs_idx; |
498 | struct radeon_ib *ib; |
504 | struct radeon_ib *ib; |
499 | void *track; |
505 | void *track; |
500 | unsigned family; |
506 | unsigned family; |
501 | int parser_error; |
507 | int parser_error; |
502 | }; |
508 | }; |
503 | 509 | ||
504 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
510 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
505 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
511 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
506 | 512 | ||
507 | 513 | ||
508 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
514 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
509 | { |
515 | { |
510 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
516 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
511 | u32 pg_idx, pg_offset; |
517 | u32 pg_idx, pg_offset; |
512 | u32 idx_value = 0; |
518 | u32 idx_value = 0; |
513 | int new_page; |
519 | int new_page; |
514 | 520 | ||
515 | pg_idx = (idx * 4) / PAGE_SIZE; |
521 | pg_idx = (idx * 4) / PAGE_SIZE; |
516 | pg_offset = (idx * 4) % PAGE_SIZE; |
522 | pg_offset = (idx * 4) % PAGE_SIZE; |
517 | 523 | ||
518 | if (ibc->kpage_idx[0] == pg_idx) |
524 | if (ibc->kpage_idx[0] == pg_idx) |
519 | return ibc->kpage[0][pg_offset/4]; |
525 | return ibc->kpage[0][pg_offset/4]; |
520 | if (ibc->kpage_idx[1] == pg_idx) |
526 | if (ibc->kpage_idx[1] == pg_idx) |
521 | return ibc->kpage[1][pg_offset/4]; |
527 | return ibc->kpage[1][pg_offset/4]; |
522 | 528 | ||
523 | new_page = radeon_cs_update_pages(p, pg_idx); |
529 | new_page = radeon_cs_update_pages(p, pg_idx); |
524 | if (new_page < 0) { |
530 | if (new_page < 0) { |
525 | p->parser_error = new_page; |
531 | p->parser_error = new_page; |
526 | return 0; |
532 | return 0; |
527 | } |
533 | } |
528 | 534 | ||
529 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
535 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
530 | return idx_value; |
536 | return idx_value; |
531 | } |
537 | } |
532 | 538 | ||
533 | struct radeon_cs_packet { |
539 | struct radeon_cs_packet { |
534 | unsigned idx; |
540 | unsigned idx; |
535 | unsigned type; |
541 | unsigned type; |
536 | unsigned reg; |
542 | unsigned reg; |
537 | unsigned opcode; |
543 | unsigned opcode; |
538 | int count; |
544 | int count; |
539 | unsigned one_reg_wr; |
545 | unsigned one_reg_wr; |
540 | }; |
546 | }; |
541 | 547 | ||
542 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
548 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
543 | struct radeon_cs_packet *pkt, |
549 | struct radeon_cs_packet *pkt, |
544 | unsigned idx, unsigned reg); |
550 | unsigned idx, unsigned reg); |
545 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
551 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
546 | struct radeon_cs_packet *pkt); |
552 | struct radeon_cs_packet *pkt); |
547 | 553 | ||
548 | 554 | ||
549 | /* |
555 | /* |
550 | * AGP |
556 | * AGP |
551 | */ |
557 | */ |
552 | int radeon_agp_init(struct radeon_device *rdev); |
558 | int radeon_agp_init(struct radeon_device *rdev); |
553 | void radeon_agp_fini(struct radeon_device *rdev); |
559 | void radeon_agp_fini(struct radeon_device *rdev); |
554 | 560 | ||
555 | 561 | ||
556 | /* |
562 | /* |
557 | * Writeback |
563 | * Writeback |
558 | */ |
564 | */ |
559 | struct radeon_wb { |
565 | struct radeon_wb { |
560 | struct radeon_object *wb_obj; |
566 | struct radeon_object *wb_obj; |
561 | volatile uint32_t *wb; |
567 | volatile uint32_t *wb; |
562 | uint64_t gpu_addr; |
568 | uint64_t gpu_addr; |
563 | }; |
569 | }; |
564 | 570 | ||
565 | /** |
571 | /** |
566 | * struct radeon_pm - power management datas |
572 | * struct radeon_pm - power management datas |
567 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
573 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
568 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
574 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
569 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
575 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
570 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
576 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
571 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
577 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
572 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
578 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
573 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
579 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
574 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
580 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
575 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
581 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
576 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
582 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
577 | * @needed_bandwidth: current bandwidth needs |
583 | * @needed_bandwidth: current bandwidth needs |
578 | * |
584 | * |
579 | * It keeps track of various data needed to take powermanagement decision. |
585 | * It keeps track of various data needed to take powermanagement decision. |
580 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
586 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
581 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
587 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
582 | * (type of memory, bus size, efficiency, ...) |
588 | * (type of memory, bus size, efficiency, ...) |
583 | */ |
589 | */ |
584 | struct radeon_pm { |
590 | struct radeon_pm { |
585 | fixed20_12 max_bandwidth; |
591 | fixed20_12 max_bandwidth; |
586 | fixed20_12 igp_sideport_mclk; |
592 | fixed20_12 igp_sideport_mclk; |
587 | fixed20_12 igp_system_mclk; |
593 | fixed20_12 igp_system_mclk; |
588 | fixed20_12 igp_ht_link_clk; |
594 | fixed20_12 igp_ht_link_clk; |
589 | fixed20_12 igp_ht_link_width; |
595 | fixed20_12 igp_ht_link_width; |
590 | fixed20_12 k8_bandwidth; |
596 | fixed20_12 k8_bandwidth; |
591 | fixed20_12 sideport_bandwidth; |
597 | fixed20_12 sideport_bandwidth; |
592 | fixed20_12 ht_bandwidth; |
598 | fixed20_12 ht_bandwidth; |
593 | fixed20_12 core_bandwidth; |
599 | fixed20_12 core_bandwidth; |
594 | fixed20_12 sclk; |
600 | fixed20_12 sclk; |
595 | fixed20_12 needed_bandwidth; |
601 | fixed20_12 needed_bandwidth; |
596 | }; |
602 | }; |
597 | 603 | ||
598 | /* |
604 | /* |
599 | * ASIC specific functions. |
605 | * ASIC specific functions. |
600 | */ |
606 | */ |
601 | struct radeon_asic { |
607 | struct radeon_asic { |
602 | int (*init)(struct radeon_device *rdev); |
608 | int (*init)(struct radeon_device *rdev); |
603 | void (*fini)(struct radeon_device *rdev); |
609 | void (*fini)(struct radeon_device *rdev); |
604 | int (*resume)(struct radeon_device *rdev); |
610 | int (*resume)(struct radeon_device *rdev); |
605 | int (*suspend)(struct radeon_device *rdev); |
611 | int (*suspend)(struct radeon_device *rdev); |
606 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
612 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
607 | int (*gpu_reset)(struct radeon_device *rdev); |
613 | int (*gpu_reset)(struct radeon_device *rdev); |
608 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
614 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
609 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
615 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
610 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
616 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
611 | void (*cp_fini)(struct radeon_device *rdev); |
617 | void (*cp_fini)(struct radeon_device *rdev); |
612 | void (*cp_disable)(struct radeon_device *rdev); |
618 | void (*cp_disable)(struct radeon_device *rdev); |
613 | void (*cp_commit)(struct radeon_device *rdev); |
619 | void (*cp_commit)(struct radeon_device *rdev); |
614 | void (*ring_start)(struct radeon_device *rdev); |
620 | void (*ring_start)(struct radeon_device *rdev); |
615 | int (*ring_test)(struct radeon_device *rdev); |
621 | int (*ring_test)(struct radeon_device *rdev); |
616 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
622 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
617 | int (*irq_set)(struct radeon_device *rdev); |
623 | int (*irq_set)(struct radeon_device *rdev); |
618 | int (*irq_process)(struct radeon_device *rdev); |
624 | int (*irq_process)(struct radeon_device *rdev); |
619 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
625 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
620 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
626 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
621 | int (*cs_parse)(struct radeon_cs_parser *p); |
627 | int (*cs_parse)(struct radeon_cs_parser *p); |
622 | int (*copy_blit)(struct radeon_device *rdev, |
628 | int (*copy_blit)(struct radeon_device *rdev, |
623 | uint64_t src_offset, |
629 | uint64_t src_offset, |
624 | uint64_t dst_offset, |
630 | uint64_t dst_offset, |
625 | unsigned num_pages, |
631 | unsigned num_pages, |
626 | struct radeon_fence *fence); |
632 | struct radeon_fence *fence); |
627 | int (*copy_dma)(struct radeon_device *rdev, |
633 | int (*copy_dma)(struct radeon_device *rdev, |
628 | uint64_t src_offset, |
634 | uint64_t src_offset, |
629 | uint64_t dst_offset, |
635 | uint64_t dst_offset, |
630 | unsigned num_pages, |
636 | unsigned num_pages, |
631 | struct radeon_fence *fence); |
637 | struct radeon_fence *fence); |
632 | int (*copy)(struct radeon_device *rdev, |
638 | int (*copy)(struct radeon_device *rdev, |
633 | uint64_t src_offset, |
639 | uint64_t src_offset, |
634 | uint64_t dst_offset, |
640 | uint64_t dst_offset, |
635 | unsigned num_pages, |
641 | unsigned num_pages, |
636 | struct radeon_fence *fence); |
642 | struct radeon_fence *fence); |
- | 643 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
|
637 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
644 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
- | 645 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
|
638 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
646 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
639 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
647 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
640 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
648 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
641 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
649 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
642 | uint32_t tiling_flags, uint32_t pitch, |
650 | uint32_t tiling_flags, uint32_t pitch, |
643 | uint32_t offset, uint32_t obj_size); |
651 | uint32_t offset, uint32_t obj_size); |
644 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
652 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
645 | void (*bandwidth_update)(struct radeon_device *rdev); |
653 | void (*bandwidth_update)(struct radeon_device *rdev); |
646 | }; |
654 | }; |
647 | 655 | ||
648 | /* |
656 | /* |
649 | * Asic structures |
657 | * Asic structures |
650 | */ |
658 | */ |
651 | struct r100_asic { |
659 | struct r100_asic { |
652 | const unsigned *reg_safe_bm; |
660 | const unsigned *reg_safe_bm; |
653 | unsigned reg_safe_bm_size; |
661 | unsigned reg_safe_bm_size; |
654 | }; |
662 | }; |
655 | 663 | ||
656 | struct r300_asic { |
664 | struct r300_asic { |
657 | const unsigned *reg_safe_bm; |
665 | const unsigned *reg_safe_bm; |
658 | unsigned reg_safe_bm_size; |
666 | unsigned reg_safe_bm_size; |
659 | }; |
667 | }; |
660 | 668 | ||
661 | struct r600_asic { |
669 | struct r600_asic { |
662 | unsigned max_pipes; |
670 | unsigned max_pipes; |
663 | unsigned max_tile_pipes; |
671 | unsigned max_tile_pipes; |
664 | unsigned max_simds; |
672 | unsigned max_simds; |
665 | unsigned max_backends; |
673 | unsigned max_backends; |
666 | unsigned max_gprs; |
674 | unsigned max_gprs; |
667 | unsigned max_threads; |
675 | unsigned max_threads; |
668 | unsigned max_stack_entries; |
676 | unsigned max_stack_entries; |
669 | unsigned max_hw_contexts; |
677 | unsigned max_hw_contexts; |
670 | unsigned max_gs_threads; |
678 | unsigned max_gs_threads; |
671 | unsigned sx_max_export_size; |
679 | unsigned sx_max_export_size; |
672 | unsigned sx_max_export_pos_size; |
680 | unsigned sx_max_export_pos_size; |
673 | unsigned sx_max_export_smx_size; |
681 | unsigned sx_max_export_smx_size; |
674 | unsigned sq_num_cf_insts; |
682 | unsigned sq_num_cf_insts; |
675 | }; |
683 | }; |
676 | 684 | ||
677 | struct rv770_asic { |
685 | struct rv770_asic { |
678 | unsigned max_pipes; |
686 | unsigned max_pipes; |
679 | unsigned max_tile_pipes; |
687 | unsigned max_tile_pipes; |
680 | unsigned max_simds; |
688 | unsigned max_simds; |
681 | unsigned max_backends; |
689 | unsigned max_backends; |
682 | unsigned max_gprs; |
690 | unsigned max_gprs; |
683 | unsigned max_threads; |
691 | unsigned max_threads; |
684 | unsigned max_stack_entries; |
692 | unsigned max_stack_entries; |
685 | unsigned max_hw_contexts; |
693 | unsigned max_hw_contexts; |
686 | unsigned max_gs_threads; |
694 | unsigned max_gs_threads; |
687 | unsigned sx_max_export_size; |
695 | unsigned sx_max_export_size; |
688 | unsigned sx_max_export_pos_size; |
696 | unsigned sx_max_export_pos_size; |
689 | unsigned sx_max_export_smx_size; |
697 | unsigned sx_max_export_smx_size; |
690 | unsigned sq_num_cf_insts; |
698 | unsigned sq_num_cf_insts; |
691 | unsigned sx_num_of_sets; |
699 | unsigned sx_num_of_sets; |
692 | unsigned sc_prim_fifo_size; |
700 | unsigned sc_prim_fifo_size; |
693 | unsigned sc_hiz_tile_fifo_size; |
701 | unsigned sc_hiz_tile_fifo_size; |
694 | unsigned sc_earlyz_tile_fifo_fize; |
702 | unsigned sc_earlyz_tile_fifo_fize; |
695 | }; |
703 | }; |
696 | 704 | ||
697 | union radeon_asic_config { |
705 | union radeon_asic_config { |
698 | struct r300_asic r300; |
706 | struct r300_asic r300; |
699 | struct r100_asic r100; |
707 | struct r100_asic r100; |
700 | struct r600_asic r600; |
708 | struct r600_asic r600; |
701 | struct rv770_asic rv770; |
709 | struct rv770_asic rv770; |
702 | }; |
710 | }; |
703 | 711 | ||
704 | 712 | ||
705 | /* |
713 | /* |
706 | 714 | ||
707 | 715 | ||
708 | 716 | ||
709 | 717 | ||
710 | /* |
718 | /* |
711 | * Core structure, functions and helpers. |
719 | * Core structure, functions and helpers. |
712 | */ |
720 | */ |
713 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
721 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
714 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
722 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
715 | 723 | ||
716 | struct radeon_device { |
724 | struct radeon_device { |
717 | void *dev; |
725 | void *dev; |
718 | struct drm_device *ddev; |
726 | struct drm_device *ddev; |
719 | struct pci_dev *pdev; |
727 | struct pci_dev *pdev; |
720 | /* ASIC */ |
728 | /* ASIC */ |
721 | union radeon_asic_config config; |
729 | union radeon_asic_config config; |
722 | enum radeon_family family; |
730 | enum radeon_family family; |
723 | unsigned long flags; |
731 | unsigned long flags; |
724 | int usec_timeout; |
732 | int usec_timeout; |
725 | enum radeon_pll_errata pll_errata; |
733 | enum radeon_pll_errata pll_errata; |
726 | int num_gb_pipes; |
734 | int num_gb_pipes; |
727 | int num_z_pipes; |
735 | int num_z_pipes; |
728 | int disp_priority; |
736 | int disp_priority; |
729 | /* BIOS */ |
737 | /* BIOS */ |
730 | uint8_t *bios; |
738 | uint8_t *bios; |
731 | bool is_atom_bios; |
739 | bool is_atom_bios; |
732 | uint16_t bios_header_start; |
740 | uint16_t bios_header_start; |
733 | 741 | ||
734 | // struct radeon_object *stollen_vga_memory; |
742 | // struct radeon_object *stollen_vga_memory; |
735 | struct fb_info *fbdev_info; |
743 | struct fb_info *fbdev_info; |
736 | struct radeon_object *fbdev_robj; |
744 | struct radeon_object *fbdev_robj; |
737 | struct radeon_framebuffer *fbdev_rfb; |
745 | struct radeon_framebuffer *fbdev_rfb; |
738 | /* Register mmio */ |
746 | /* Register mmio */ |
739 | unsigned long rmmio_base; |
747 | unsigned long rmmio_base; |
740 | unsigned long rmmio_size; |
748 | unsigned long rmmio_size; |
741 | void *rmmio; |
749 | void *rmmio; |
742 | radeon_rreg_t mc_rreg; |
750 | radeon_rreg_t mc_rreg; |
743 | radeon_wreg_t mc_wreg; |
751 | radeon_wreg_t mc_wreg; |
744 | radeon_rreg_t pll_rreg; |
752 | radeon_rreg_t pll_rreg; |
745 | radeon_wreg_t pll_wreg; |
753 | radeon_wreg_t pll_wreg; |
746 | uint32_t pcie_reg_mask; |
754 | uint32_t pcie_reg_mask; |
747 | radeon_rreg_t pciep_rreg; |
755 | radeon_rreg_t pciep_rreg; |
748 | radeon_wreg_t pciep_wreg; |
756 | radeon_wreg_t pciep_wreg; |
749 | struct radeon_clock clock; |
757 | struct radeon_clock clock; |
750 | struct radeon_mc mc; |
758 | struct radeon_mc mc; |
751 | struct radeon_gart gart; |
759 | struct radeon_gart gart; |
752 | struct radeon_mode_info mode_info; |
760 | struct radeon_mode_info mode_info; |
753 | struct radeon_scratch scratch; |
761 | struct radeon_scratch scratch; |
754 | // struct radeon_mman mman; |
762 | // struct radeon_mman mman; |
755 | struct radeon_fence_driver fence_drv; |
763 | struct radeon_fence_driver fence_drv; |
756 | struct radeon_cp cp; |
764 | struct radeon_cp cp; |
757 | struct radeon_ib_pool ib_pool; |
765 | struct radeon_ib_pool ib_pool; |
758 | // struct radeon_irq irq; |
766 | // struct radeon_irq irq; |
759 | struct radeon_asic *asic; |
767 | struct radeon_asic *asic; |
760 | struct radeon_gem gem; |
768 | struct radeon_gem gem; |
761 | struct radeon_pm pm; |
769 | struct radeon_pm pm; |
762 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
770 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
763 | // struct mutex cs_mutex; |
771 | // struct mutex cs_mutex; |
764 | struct radeon_wb wb; |
772 | struct radeon_wb wb; |
765 | struct radeon_dummy_page dummy_page; |
773 | struct radeon_dummy_page dummy_page; |
766 | bool gpu_lockup; |
774 | bool gpu_lockup; |
767 | bool shutdown; |
775 | bool shutdown; |
768 | bool suspend; |
776 | bool suspend; |
769 | bool need_dma32; |
777 | bool need_dma32; |
770 | bool accel_working; |
778 | bool accel_working; |
771 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
779 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
772 | const struct firmware *me_fw; /* all family ME firmware */ |
780 | const struct firmware *me_fw; /* all family ME firmware */ |
773 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
781 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
774 | struct r600_blit r600_blit; |
782 | struct r600_blit r600_blit; |
- | 783 | int msi_enabled; /* msi enabled */ |
|
775 | }; |
784 | }; |
776 | 785 | ||
777 | int radeon_device_init(struct radeon_device *rdev, |
786 | int radeon_device_init(struct radeon_device *rdev, |
778 | struct drm_device *ddev, |
787 | struct drm_device *ddev, |
779 | struct pci_dev *pdev, |
788 | struct pci_dev *pdev, |
780 | uint32_t flags); |
789 | uint32_t flags); |
781 | void radeon_device_fini(struct radeon_device *rdev); |
790 | void radeon_device_fini(struct radeon_device *rdev); |
782 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
791 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
783 | 792 | ||
784 | /* r600 blit */ |
793 | /* r600 blit */ |
785 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
794 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
786 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
795 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
787 | void r600_kms_blit_copy(struct radeon_device *rdev, |
796 | void r600_kms_blit_copy(struct radeon_device *rdev, |
788 | u64 src_gpu_addr, u64 dst_gpu_addr, |
797 | u64 src_gpu_addr, u64 dst_gpu_addr, |
789 | int size_bytes); |
798 | int size_bytes); |
790 | 799 | ||
791 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
800 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
792 | { |
801 | { |
793 | if (reg < 0x10000) |
802 | if (reg < 0x10000) |
794 | return readl(((void __iomem *)rdev->rmmio) + reg); |
803 | return readl(((void __iomem *)rdev->rmmio) + reg); |
795 | else { |
804 | else { |
796 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
805 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
797 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
806 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
798 | } |
807 | } |
799 | } |
808 | } |
800 | 809 | ||
801 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
810 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
802 | { |
811 | { |
803 | if (reg < 0x10000) |
812 | if (reg < 0x10000) |
804 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
813 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
805 | else { |
814 | else { |
806 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
815 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
807 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
816 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
808 | } |
817 | } |
809 | } |
818 | } |
810 | 819 | ||
811 | 820 | ||
812 | /* |
821 | /* |
813 | * Registers read & write functions. |
822 | * Registers read & write functions. |
814 | */ |
823 | */ |
815 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
824 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
816 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
825 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
817 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
826 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
818 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
827 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
819 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
828 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
820 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
829 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
821 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
830 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
822 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
831 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
823 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
832 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
824 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
833 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
825 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
834 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
826 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
835 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
827 | #define WREG32_P(reg, val, mask) \ |
836 | #define WREG32_P(reg, val, mask) \ |
828 | do { \ |
837 | do { \ |
829 | uint32_t tmp_ = RREG32(reg); \ |
838 | uint32_t tmp_ = RREG32(reg); \ |
830 | tmp_ &= (mask); \ |
839 | tmp_ &= (mask); \ |
831 | tmp_ |= ((val) & ~(mask)); \ |
840 | tmp_ |= ((val) & ~(mask)); \ |
832 | WREG32(reg, tmp_); \ |
841 | WREG32(reg, tmp_); \ |
833 | } while (0) |
842 | } while (0) |
834 | #define WREG32_PLL_P(reg, val, mask) \ |
843 | #define WREG32_PLL_P(reg, val, mask) \ |
835 | do { \ |
844 | do { \ |
836 | uint32_t tmp_ = RREG32_PLL(reg); \ |
845 | uint32_t tmp_ = RREG32_PLL(reg); \ |
837 | tmp_ &= (mask); \ |
846 | tmp_ &= (mask); \ |
838 | tmp_ |= ((val) & ~(mask)); \ |
847 | tmp_ |= ((val) & ~(mask)); \ |
839 | WREG32_PLL(reg, tmp_); \ |
848 | WREG32_PLL(reg, tmp_); \ |
840 | } while (0) |
849 | } while (0) |
841 | 850 | ||
842 | /* |
851 | /* |
843 | * Indirect registers accessor |
852 | * Indirect registers accessor |
844 | */ |
853 | */ |
845 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
854 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
846 | { |
855 | { |
847 | uint32_t r; |
856 | uint32_t r; |
848 | 857 | ||
849 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
858 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
850 | r = RREG32(RADEON_PCIE_DATA); |
859 | r = RREG32(RADEON_PCIE_DATA); |
851 | return r; |
860 | return r; |
852 | } |
861 | } |
853 | 862 | ||
854 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
863 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
855 | { |
864 | { |
856 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
865 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
857 | WREG32(RADEON_PCIE_DATA, (v)); |
866 | WREG32(RADEON_PCIE_DATA, (v)); |
858 | } |
867 | } |
859 | 868 | ||
860 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
869 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
861 | 870 | ||
862 | 871 | ||
863 | /* |
872 | /* |
864 | * ASICs helpers. |
873 | * ASICs helpers. |
865 | */ |
874 | */ |
866 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
875 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
867 | (rdev->pdev->device == 0x5969)) |
876 | (rdev->pdev->device == 0x5969)) |
868 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
877 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
869 | (rdev->family == CHIP_RV200) || \ |
878 | (rdev->family == CHIP_RV200) || \ |
870 | (rdev->family == CHIP_RS100) || \ |
879 | (rdev->family == CHIP_RS100) || \ |
871 | (rdev->family == CHIP_RS200) || \ |
880 | (rdev->family == CHIP_RS200) || \ |
872 | (rdev->family == CHIP_RV250) || \ |
881 | (rdev->family == CHIP_RV250) || \ |
873 | (rdev->family == CHIP_RV280) || \ |
882 | (rdev->family == CHIP_RV280) || \ |
874 | (rdev->family == CHIP_RS300)) |
883 | (rdev->family == CHIP_RS300)) |
875 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
884 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
876 | (rdev->family == CHIP_RV350) || \ |
885 | (rdev->family == CHIP_RV350) || \ |
877 | (rdev->family == CHIP_R350) || \ |
886 | (rdev->family == CHIP_R350) || \ |
878 | (rdev->family == CHIP_RV380) || \ |
887 | (rdev->family == CHIP_RV380) || \ |
879 | (rdev->family == CHIP_R420) || \ |
888 | (rdev->family == CHIP_R420) || \ |
880 | (rdev->family == CHIP_R423) || \ |
889 | (rdev->family == CHIP_R423) || \ |
881 | (rdev->family == CHIP_RV410) || \ |
890 | (rdev->family == CHIP_RV410) || \ |
882 | (rdev->family == CHIP_RS400) || \ |
891 | (rdev->family == CHIP_RS400) || \ |
883 | (rdev->family == CHIP_RS480)) |
892 | (rdev->family == CHIP_RS480)) |
884 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
893 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
885 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
894 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
886 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
895 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
887 | 896 | ||
888 | 897 | ||
889 | /* |
898 | /* |
890 | * BIOS helpers. |
899 | * BIOS helpers. |
891 | */ |
900 | */ |
892 | #define RBIOS8(i) (rdev->bios[i]) |
901 | #define RBIOS8(i) (rdev->bios[i]) |
893 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
902 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
894 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
903 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
895 | 904 | ||
896 | int radeon_combios_init(struct radeon_device *rdev); |
905 | int radeon_combios_init(struct radeon_device *rdev); |
897 | void radeon_combios_fini(struct radeon_device *rdev); |
906 | void radeon_combios_fini(struct radeon_device *rdev); |
898 | int radeon_atombios_init(struct radeon_device *rdev); |
907 | int radeon_atombios_init(struct radeon_device *rdev); |
899 | void radeon_atombios_fini(struct radeon_device *rdev); |
908 | void radeon_atombios_fini(struct radeon_device *rdev); |
900 | 909 | ||
901 | 910 | ||
902 | /* |
911 | /* |
903 | * RING helpers. |
912 | * RING helpers. |
904 | */ |
913 | */ |
905 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
914 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
906 | { |
915 | { |
907 | #if DRM_DEBUG_CODE |
916 | #if DRM_DEBUG_CODE |
908 | if (rdev->cp.count_dw <= 0) { |
917 | if (rdev->cp.count_dw <= 0) { |
909 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
918 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
910 | } |
919 | } |
911 | #endif |
920 | #endif |
912 | rdev->cp.ring[rdev->cp.wptr++] = v; |
921 | rdev->cp.ring[rdev->cp.wptr++] = v; |
913 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
922 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
914 | rdev->cp.count_dw--; |
923 | rdev->cp.count_dw--; |
915 | rdev->cp.ring_free_dw--; |
924 | rdev->cp.ring_free_dw--; |
916 | } |
925 | } |
917 | 926 | ||
918 | 927 | ||
919 | /* |
928 | /* |
920 | * ASICs macro. |
929 | * ASICs macro. |
921 | */ |
930 | */ |
922 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
931 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
923 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
932 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
924 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
933 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
925 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
934 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
926 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
935 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
927 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
936 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
928 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
937 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
929 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
938 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
930 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
939 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
931 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
940 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
932 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
941 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
933 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
942 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
934 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
943 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
935 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
944 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
936 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
945 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
937 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
946 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
938 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
947 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
939 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
948 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
940 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
949 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
941 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
950 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
- | 951 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
|
942 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
952 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
- | 953 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
|
943 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
954 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
944 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
955 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
945 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
956 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
946 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
957 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
947 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
958 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
948 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
959 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
949 | 960 | ||
950 | /* Common functions */ |
961 | /* Common functions */ |
951 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
962 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
952 | extern int radeon_modeset_init(struct radeon_device *rdev); |
963 | extern int radeon_modeset_init(struct radeon_device *rdev); |
953 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
964 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
954 | extern bool radeon_card_posted(struct radeon_device *rdev); |
965 | extern bool radeon_card_posted(struct radeon_device *rdev); |
955 | extern int radeon_clocks_init(struct radeon_device *rdev); |
966 | extern int radeon_clocks_init(struct radeon_device *rdev); |
956 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
967 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
957 | extern void radeon_scratch_init(struct radeon_device *rdev); |
968 | extern void radeon_scratch_init(struct radeon_device *rdev); |
958 | extern void radeon_surface_init(struct radeon_device *rdev); |
969 | extern void radeon_surface_init(struct radeon_device *rdev); |
959 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
970 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
960 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
971 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
961 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
972 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
962 | 973 | ||
963 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
974 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
964 | struct r100_mc_save { |
975 | struct r100_mc_save { |
965 | u32 GENMO_WT; |
976 | u32 GENMO_WT; |
966 | u32 CRTC_EXT_CNTL; |
977 | u32 CRTC_EXT_CNTL; |
967 | u32 CRTC_GEN_CNTL; |
978 | u32 CRTC_GEN_CNTL; |
968 | u32 CRTC2_GEN_CNTL; |
979 | u32 CRTC2_GEN_CNTL; |
969 | u32 CUR_OFFSET; |
980 | u32 CUR_OFFSET; |
970 | u32 CUR2_OFFSET; |
981 | u32 CUR2_OFFSET; |
971 | }; |
982 | }; |
972 | extern void r100_cp_disable(struct radeon_device *rdev); |
983 | extern void r100_cp_disable(struct radeon_device *rdev); |
973 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
984 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
974 | extern void r100_cp_fini(struct radeon_device *rdev); |
985 | extern void r100_cp_fini(struct radeon_device *rdev); |
975 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
986 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
976 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
987 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
977 | extern void r100_pci_gart_fini(struct radeon_device *rdev); |
988 | extern void r100_pci_gart_fini(struct radeon_device *rdev); |
978 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
989 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
979 | extern void r100_pci_gart_disable(struct radeon_device *rdev); |
990 | extern void r100_pci_gart_disable(struct radeon_device *rdev); |
980 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
991 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
981 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
992 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
982 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
993 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
983 | extern void r100_ib_fini(struct radeon_device *rdev); |
994 | extern void r100_ib_fini(struct radeon_device *rdev); |
984 | extern int r100_ib_init(struct radeon_device *rdev); |
995 | extern int r100_ib_init(struct radeon_device *rdev); |
985 | extern void r100_irq_disable(struct radeon_device *rdev); |
996 | extern void r100_irq_disable(struct radeon_device *rdev); |
986 | extern int r100_irq_set(struct radeon_device *rdev); |
997 | extern int r100_irq_set(struct radeon_device *rdev); |
987 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
998 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
988 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
999 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
989 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
1000 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
990 | extern void r100_wb_disable(struct radeon_device *rdev); |
1001 | extern void r100_wb_disable(struct radeon_device *rdev); |
991 | extern void r100_wb_fini(struct radeon_device *rdev); |
1002 | extern void r100_wb_fini(struct radeon_device *rdev); |
992 | extern int r100_wb_init(struct radeon_device *rdev); |
1003 | extern int r100_wb_init(struct radeon_device *rdev); |
993 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1004 | extern void r100_hdp_reset(struct radeon_device *rdev); |
994 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
1005 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
995 | extern int r100_cp_reset(struct radeon_device *rdev); |
1006 | extern int r100_cp_reset(struct radeon_device *rdev); |
996 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
1007 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
997 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1008 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
998 | struct radeon_cs_packet *pkt, |
1009 | struct radeon_cs_packet *pkt, |
999 | struct radeon_object *robj); |
1010 | struct radeon_object *robj); |
1000 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1011 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1001 | struct radeon_cs_packet *pkt, |
1012 | struct radeon_cs_packet *pkt, |
1002 | const unsigned *auth, unsigned n, |
1013 | const unsigned *auth, unsigned n, |
1003 | radeon_packet0_check_t check); |
1014 | radeon_packet0_check_t check); |
1004 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
1015 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
1005 | struct radeon_cs_packet *pkt, |
1016 | struct radeon_cs_packet *pkt, |
1006 | unsigned idx); |
1017 | unsigned idx); |
1007 | 1018 | ||
1008 | /* rv200,rv250,rv280 */ |
1019 | /* rv200,rv250,rv280 */ |
1009 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
1020 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
1010 | 1021 | ||
1011 | /* r300,r350,rv350,rv370,rv380 */ |
1022 | /* r300,r350,rv350,rv370,rv380 */ |
1012 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1023 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1013 | extern void r300_mc_program(struct radeon_device *rdev); |
1024 | extern void r300_mc_program(struct radeon_device *rdev); |
1014 | extern void r300_vram_info(struct radeon_device *rdev); |
1025 | extern void r300_vram_info(struct radeon_device *rdev); |
1015 | extern void r300_clock_startup(struct radeon_device *rdev); |
1026 | extern void r300_clock_startup(struct radeon_device *rdev); |
1016 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1027 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1017 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1028 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1018 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
1029 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
1019 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
1030 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
1020 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
1031 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
1021 | 1032 | ||
1022 | /* r420,r423,rv410 */ |
1033 | /* r420,r423,rv410 */ |
1023 | extern int r420_mc_init(struct radeon_device *rdev); |
1034 | extern int r420_mc_init(struct radeon_device *rdev); |
1024 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1035 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1025 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
1036 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
1026 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
1037 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
1027 | extern void r420_pipes_init(struct radeon_device *rdev); |
1038 | extern void r420_pipes_init(struct radeon_device *rdev); |
1028 | 1039 | ||
1029 | /* rv515 */ |
1040 | /* rv515 */ |
1030 | struct rv515_mc_save { |
1041 | struct rv515_mc_save { |
1031 | u32 d1vga_control; |
1042 | u32 d1vga_control; |
1032 | u32 d2vga_control; |
1043 | u32 d2vga_control; |
1033 | u32 vga_render_control; |
1044 | u32 vga_render_control; |
1034 | u32 vga_hdp_control; |
1045 | u32 vga_hdp_control; |
1035 | u32 d1crtc_control; |
1046 | u32 d1crtc_control; |
1036 | u32 d2crtc_control; |
1047 | u32 d2crtc_control; |
1037 | }; |
1048 | }; |
1038 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1049 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1039 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1050 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1040 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
1051 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
1041 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1052 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1042 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
1053 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
1043 | extern void rv515_clock_startup(struct radeon_device *rdev); |
1054 | extern void rv515_clock_startup(struct radeon_device *rdev); |
1044 | extern void rv515_debugfs(struct radeon_device *rdev); |
1055 | extern void rv515_debugfs(struct radeon_device *rdev); |
1045 | extern int rv515_suspend(struct radeon_device *rdev); |
1056 | extern int rv515_suspend(struct radeon_device *rdev); |
1046 | 1057 | ||
1047 | /* rs400 */ |
1058 | /* rs400 */ |
1048 | extern int rs400_gart_init(struct radeon_device *rdev); |
1059 | extern int rs400_gart_init(struct radeon_device *rdev); |
1049 | extern int rs400_gart_enable(struct radeon_device *rdev); |
1060 | extern int rs400_gart_enable(struct radeon_device *rdev); |
1050 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
1061 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
1051 | extern void rs400_gart_disable(struct radeon_device *rdev); |
1062 | extern void rs400_gart_disable(struct radeon_device *rdev); |
1052 | extern void rs400_gart_fini(struct radeon_device *rdev); |
1063 | extern void rs400_gart_fini(struct radeon_device *rdev); |
1053 | 1064 | ||
1054 | /* rs600 */ |
1065 | /* rs600 */ |
1055 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
1066 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
1056 | extern int rs600_irq_set(struct radeon_device *rdev); |
1067 | extern int rs600_irq_set(struct radeon_device *rdev); |
1057 | extern void rs600_irq_disable(struct radeon_device *rdev); |
1068 | extern void rs600_irq_disable(struct radeon_device *rdev); |
1058 | 1069 | ||
1059 | /* rs690, rs740 */ |
1070 | /* rs690, rs740 */ |
1060 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
1071 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
1061 | struct drm_display_mode *mode1, |
1072 | struct drm_display_mode *mode1, |
1062 | struct drm_display_mode *mode2); |
1073 | struct drm_display_mode *mode2); |
1063 | 1074 | ||
1064 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
1075 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
1065 | extern bool r600_card_posted(struct radeon_device *rdev); |
1076 | extern bool r600_card_posted(struct radeon_device *rdev); |
1066 | extern void r600_cp_stop(struct radeon_device *rdev); |
1077 | extern void r600_cp_stop(struct radeon_device *rdev); |
1067 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1078 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1068 | extern int r600_cp_resume(struct radeon_device *rdev); |
1079 | extern int r600_cp_resume(struct radeon_device *rdev); |
1069 | extern int r600_count_pipe_bits(uint32_t val); |
1080 | extern int r600_count_pipe_bits(uint32_t val); |
1070 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); |
1081 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); |
1071 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1082 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1072 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
1083 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
1073 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1084 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1074 | extern int r600_ib_test(struct radeon_device *rdev); |
1085 | extern int r600_ib_test(struct radeon_device *rdev); |
1075 | extern int r600_ring_test(struct radeon_device *rdev); |
1086 | extern int r600_ring_test(struct radeon_device *rdev); |
1076 | extern void r600_wb_fini(struct radeon_device *rdev); |
1087 | extern void r600_wb_fini(struct radeon_device *rdev); |
1077 | extern int r600_wb_enable(struct radeon_device *rdev); |
1088 | extern int r600_wb_enable(struct radeon_device *rdev); |
1078 | extern void r600_wb_disable(struct radeon_device *rdev); |
1089 | extern void r600_wb_disable(struct radeon_device *rdev); |
1079 | extern void r600_scratch_init(struct radeon_device *rdev); |
1090 | extern void r600_scratch_init(struct radeon_device *rdev); |
1080 | extern int r600_blit_init(struct radeon_device *rdev); |
1091 | extern int r600_blit_init(struct radeon_device *rdev); |
1081 | extern void r600_blit_fini(struct radeon_device *rdev); |
1092 | extern void r600_blit_fini(struct radeon_device *rdev); |
1082 | extern int r600_cp_init_microcode(struct radeon_device *rdev); |
1093 | extern int r600_cp_init_microcode(struct radeon_device *rdev); |
1083 | extern int r600_gpu_reset(struct radeon_device *rdev); |
1094 | extern int r600_gpu_reset(struct radeon_device *rdev); |
1084 | 1095 | ||
1085 | 1096 | ||
1086 | 1097 | ||
1087 | #define DRM_UDELAY(d) udelay(d) |
1098 | #define DRM_UDELAY(d) udelay(d) |
1088 | 1099 | ||
1089 | resource_size_t |
1100 | resource_size_t |
1090 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
1101 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
1091 | resource_size_t |
1102 | resource_size_t |
1092 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
1103 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
1093 | 1104 | ||
1094 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1105 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1095 | mode_t *mode, bool strict); |
1106 | mode_t *mode, bool strict); |
1096 | 1107 | ||
1097 | 1108 | ||
1098 | #endif=>><>><>><>><>>>>=> |
1109 | #endif=>><>><>><>><>>>>=> |