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| Rev 1179 | Rev 1221 | ||
|---|---|---|---|
| Line 42... | Line 42... | ||
| 42 | * - Barrier in gart code |
42 | * - Barrier in gart code |
| 43 | * - Unmappabled vram ? |
43 | * - Unmappabled vram ? |
| 44 | * - TESTING, TESTING, TESTING |
44 | * - TESTING, TESTING, TESTING |
| 45 | */ |
45 | */ |
| Line -... | Line 46... | ||
| - | 46 | ||
| - | 47 | /* Initialization path: |
|
| - | 48 | * We expect that acceleration initialization might fail for various |
|
| - | 49 | * reasons even thought we work hard to make it works on most |
|
| - | 50 | * configurations. In order to still have a working userspace in such |
|
| - | 51 | * situation the init path must succeed up to the memory controller |
|
| - | 52 | * initialization point. Failure before this point are considered as |
|
| - | 53 | * fatal error. Here is the init callchain : |
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| - | 54 | * radeon_device_init perform common structure, mutex initialization |
|
| - | 55 | * asic_init setup the GPU memory layout and perform all |
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| - | 56 | * one time initialization (failure in this |
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| - | 57 | * function are considered fatal) |
|
| - | 58 | * asic_startup setup the GPU acceleration, in order to |
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| - | 59 | * follow guideline the first thing this |
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| - | 60 | * function should do is setting the GPU |
|
| - | 61 | * memory controller (only MC setup failure |
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| - | 62 | * are considered as fatal) |
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| - | 63 | */ |
|
| - | 64 | ||
| 46 | 65 | ||
| - | 66 | #include |
|
| - | 67 | ||
| 47 | #include |
68 | |
| Line 48... | Line 69... | ||
| 48 | #include |
69 | #include |
| Line 49... | Line 70... | ||
| 49 | 70 | ||
| Line 118... | Line 139... | ||
| 118 | #define writeb __raw_writeb |
139 | #define writeb __raw_writeb |
| 119 | #define writew __raw_writew |
140 | #define writew __raw_writew |
| 120 | #define writel __raw_writel |
141 | #define writel __raw_writel |
| 121 | #define writeq __raw_writeq |
142 | #define writeq __raw_writeq |
| Line 122... | Line -... | ||
| 122 | - | ||
| 123 | //#define writeb(b,addr) *(volatile uint8_t* ) addr = (uint8_t)b |
- | |
| 124 | //#define writew(b,addr) *(volatile uint16_t*) addr = (uint16_t)b |
- | |
| 125 | //#define writel(b,addr) *(volatile uint32_t*) addr = (uint32_t)b |
- | |
| Line 126... | Line 143... | ||
| 126 | 143 | ||
| 127 | 144 | ||
| 128 | /* |
145 | /* |
| 129 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
146 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| Line 371... | Line 388... | ||
| 371 | struct radeon_ib { |
388 | struct radeon_ib { |
| 372 | struct list_head list; |
389 | struct list_head list; |
| 373 | unsigned long idx; |
390 | unsigned long idx; |
| 374 | uint64_t gpu_addr; |
391 | uint64_t gpu_addr; |
| 375 | struct radeon_fence *fence; |
392 | struct radeon_fence *fence; |
| 376 | volatile uint32_t *ptr; |
393 | uint32_t *ptr; |
| 377 | uint32_t length_dw; |
394 | uint32_t length_dw; |
| 378 | }; |
395 | }; |
| Line 379... | Line 396... | ||
| 379 | 396 | ||
| 380 | /* |
397 | /* |
| Line 444... | Line 461... | ||
| 444 | }; |
461 | }; |
| Line 445... | Line 462... | ||
| 445 | 462 | ||
| 446 | struct radeon_cs_chunk { |
463 | struct radeon_cs_chunk { |
| 447 | uint32_t chunk_id; |
464 | uint32_t chunk_id; |
| - | 465 | uint32_t length_dw; |
|
| - | 466 | int kpage_idx[2]; |
|
| 448 | uint32_t length_dw; |
467 | uint32_t *kpage[2]; |
| - | 468 | uint32_t *kdata; |
|
| - | 469 | void __user *user_ptr; |
|
| - | 470 | int last_copied_page; |
|
| 449 | uint32_t *kdata; |
471 | int last_page_index; |
| Line 450... | Line 472... | ||
| 450 | }; |
472 | }; |
| 451 | 473 | ||
| 452 | struct radeon_cs_parser { |
474 | struct radeon_cs_parser { |
| Line 467... | Line 489... | ||
| 467 | int chunk_ib_idx; |
489 | int chunk_ib_idx; |
| 468 | int chunk_relocs_idx; |
490 | int chunk_relocs_idx; |
| 469 | struct radeon_ib *ib; |
491 | struct radeon_ib *ib; |
| 470 | void *track; |
492 | void *track; |
| 471 | unsigned family; |
493 | unsigned family; |
| - | 494 | int parser_error; |
|
| 472 | }; |
495 | }; |
| Line -... | Line 496... | ||
| - | 496 | ||
| - | 497 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
|
| - | 498 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
|
| - | 499 | ||
| - | 500 | ||
| - | 501 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
|
| - | 502 | { |
|
| - | 503 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
|
| - | 504 | u32 pg_idx, pg_offset; |
|
| - | 505 | u32 idx_value = 0; |
|
| - | 506 | int new_page; |
|
| - | 507 | ||
| - | 508 | pg_idx = (idx * 4) / PAGE_SIZE; |
|
| - | 509 | pg_offset = (idx * 4) % PAGE_SIZE; |
|
| - | 510 | ||
| - | 511 | if (ibc->kpage_idx[0] == pg_idx) |
|
| - | 512 | return ibc->kpage[0][pg_offset/4]; |
|
| - | 513 | if (ibc->kpage_idx[1] == pg_idx) |
|
| - | 514 | return ibc->kpage[1][pg_offset/4]; |
|
| - | 515 | ||
| - | 516 | new_page = radeon_cs_update_pages(p, pg_idx); |
|
| - | 517 | if (new_page < 0) { |
|
| - | 518 | p->parser_error = new_page; |
|
| - | 519 | return 0; |
|
| - | 520 | } |
|
| - | 521 | ||
| - | 522 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
|
| - | 523 | return idx_value; |
|
| - | 524 | } |
|
| 473 | 525 | ||
| 474 | struct radeon_cs_packet { |
526 | struct radeon_cs_packet { |
| 475 | unsigned idx; |
527 | unsigned idx; |
| 476 | unsigned type; |
528 | unsigned type; |
| 477 | unsigned reg; |
529 | unsigned reg; |
| Line 542... | Line 594... | ||
| 542 | struct radeon_asic { |
594 | struct radeon_asic { |
| 543 | int (*init)(struct radeon_device *rdev); |
595 | int (*init)(struct radeon_device *rdev); |
| 544 | void (*fini)(struct radeon_device *rdev); |
596 | void (*fini)(struct radeon_device *rdev); |
| 545 | int (*resume)(struct radeon_device *rdev); |
597 | int (*resume)(struct radeon_device *rdev); |
| 546 | int (*suspend)(struct radeon_device *rdev); |
598 | int (*suspend)(struct radeon_device *rdev); |
| 547 | void (*errata)(struct radeon_device *rdev); |
- | |
| 548 | void (*vram_info)(struct radeon_device *rdev); |
- | |
| 549 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
599 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
| 550 | int (*gpu_reset)(struct radeon_device *rdev); |
600 | int (*gpu_reset)(struct radeon_device *rdev); |
| 551 | int (*mc_init)(struct radeon_device *rdev); |
- | |
| 552 | void (*mc_fini)(struct radeon_device *rdev); |
- | |
| 553 | int (*wb_init)(struct radeon_device *rdev); |
- | |
| 554 | void (*wb_fini)(struct radeon_device *rdev); |
- | |
| 555 | int (*gart_init)(struct radeon_device *rdev); |
- | |
| 556 | void (*gart_fini)(struct radeon_device *rdev); |
- | |
| 557 | int (*gart_enable)(struct radeon_device *rdev); |
- | |
| 558 | void (*gart_disable)(struct radeon_device *rdev); |
- | |
| 559 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
601 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
| 560 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
602 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 561 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
603 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 562 | void (*cp_fini)(struct radeon_device *rdev); |
604 | void (*cp_fini)(struct radeon_device *rdev); |
| 563 | void (*cp_disable)(struct radeon_device *rdev); |
605 | void (*cp_disable)(struct radeon_device *rdev); |
| 564 | void (*cp_commit)(struct radeon_device *rdev); |
606 | void (*cp_commit)(struct radeon_device *rdev); |
| 565 | void (*ring_start)(struct radeon_device *rdev); |
607 | void (*ring_start)(struct radeon_device *rdev); |
| 566 | int (*ring_test)(struct radeon_device *rdev); |
608 | int (*ring_test)(struct radeon_device *rdev); |
| 567 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
609 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
| 568 | int (*ib_test)(struct radeon_device *rdev); |
- | |
| 569 | int (*irq_set)(struct radeon_device *rdev); |
610 | int (*irq_set)(struct radeon_device *rdev); |
| 570 | int (*irq_process)(struct radeon_device *rdev); |
611 | int (*irq_process)(struct radeon_device *rdev); |
| 571 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
612 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
| 572 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
613 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
| 573 | int (*cs_parse)(struct radeon_cs_parser *p); |
614 | int (*cs_parse)(struct radeon_cs_parser *p); |
| Line 664... | Line 705... | ||
| 664 | */ |
705 | */ |
| 665 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
706 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 666 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
707 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| Line 667... | Line 708... | ||
| 667 | 708 | ||
| - | 709 | struct radeon_device { |
|
| 668 | struct radeon_device { |
710 | void *dev; |
| 669 | struct drm_device *ddev; |
711 | struct drm_device *ddev; |
| 670 | struct pci_dev *pdev; |
712 | struct pci_dev *pdev; |
| 671 | /* ASIC */ |
713 | /* ASIC */ |
| 672 | union radeon_asic_config config; |
714 | union radeon_asic_config config; |
| Line 716... | Line 758... | ||
| 716 | struct radeon_dummy_page dummy_page; |
758 | struct radeon_dummy_page dummy_page; |
| 717 | bool gpu_lockup; |
759 | bool gpu_lockup; |
| 718 | bool shutdown; |
760 | bool shutdown; |
| 719 | bool suspend; |
761 | bool suspend; |
| 720 | bool need_dma32; |
762 | bool need_dma32; |
| 721 | bool new_init_path; |
- | |
| 722 | bool accel_working; |
763 | bool accel_working; |
| 723 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
764 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
| 724 | const struct firmware *me_fw; /* all family ME firmware */ |
765 | const struct firmware *me_fw; /* all family ME firmware */ |
| 725 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
766 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
| 726 | struct r600_blit r600_blit; |
767 | struct r600_blit r600_blit; |
| Line 811... | Line 852... | ||
| 811 | 852 | ||
| Line 812... | Line -... | ||
| 812 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
- | |
| 813 | - | ||
| 814 | - | ||
| 815 | - | ||
| 816 | - | ||
| 817 | - | ||
| 818 | - | ||
| 819 | - | ||
| 820 | - | ||
| 821 | - | ||
| 822 | #define radeon_PCI_IDS \ |
- | |
| 823 | {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
- | |
| 824 | {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 825 | {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 826 | {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 827 | {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 828 | {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \ |
- | |
| 829 | {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
- | |
| 830 | {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 831 | {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 832 | {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 833 | {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 834 | {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 835 | {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 836 | {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 837 | {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 838 | {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
- | |
| 839 | {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
- | |
| 840 | {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
- | |
| 841 | {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
- | |
| 842 | {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
- | |
| 843 | {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
- | |
| 844 | {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
- | |
| 845 | {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
- | |
| 846 | {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
- | |
| 847 | {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
- | |
| 848 | {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
- | |
| 849 | {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
- | |
| 850 | {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
- | |
| 851 | {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
- | |
| 852 | {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
- | |
| 853 | {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 854 | {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 855 | {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 856 | {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 857 | {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 858 | {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 859 | {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 860 | {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 861 | {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 862 | {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 863 | {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 864 | {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 865 | {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 866 | {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
- | |
| 867 | {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
- | |
| 868 | {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
- | |
| 869 | {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
- | |
| 870 | {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
- | |
| 871 | {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
- | |
| 872 | {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
- | |
| 873 | {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
- | |
| 874 | {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 875 | {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 876 | {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 877 | {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
- | |
| 878 | {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 879 | {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 880 | {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 881 | {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
- | |
| 882 | {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
- | |
| 883 | {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
- | |
| 884 | {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
- | |
| 885 | {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
- | |
| 886 | {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
- | |
| 887 | {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
- | |
| 888 | {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
- | |
| 889 | {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
- | |
| 890 | {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
- | |
| 891 | {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
- | |
| 892 | {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
- | |
| 893 | {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
- | |
| 894 | {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
- | |
| 895 | {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
- | |
| 896 | {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
- | |
| 897 | {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
- | |
| 898 | {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
- | |
| 899 | {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
- | |
| 900 | {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
- | |
| 901 | {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
- | |
| 902 | {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
- | |
| 903 | {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 904 | {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 905 | {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 906 | {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 907 | {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 908 | {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 909 | {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 910 | {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 911 | {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 912 | {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 913 | {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 914 | {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 915 | {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 916 | {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 917 | {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 918 | {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 919 | {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 920 | {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 921 | {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ |
- | |
| 922 | {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
- | |
| 923 | {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
- | |
| 924 | {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
- | |
| 925 | {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
- | |
| 926 | {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
- | |
| 927 | {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
- | |
| 928 | {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
- | |
| 929 | {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
- | |
| 930 | {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
- | |
| 931 | {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
- | |
| 932 | {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
- | |
| 933 | {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
- | |
| 934 | {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
- | |
| 935 | {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
- | |
| 936 | {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
- | |
| 937 | {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 938 | {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 939 | {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 940 | {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 941 | {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
- | |
| 942 | {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
- | |
| 943 | {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
- | |
| 944 | {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 945 | {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 946 | {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 947 | {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 948 | {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 949 | {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 950 | {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 951 | {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 952 | {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 953 | {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
- | |
| 954 | {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
- | |
| 955 | {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
- | |
| 956 | {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
- | |
| 957 | {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
- | |
| 958 | {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
- | |
| 959 | {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
- | |
| 960 | {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 961 | {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 962 | {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 963 | {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 964 | {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 965 | {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 966 | {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 967 | {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 968 | {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 969 | {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 970 | {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 971 | {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 972 | {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 973 | {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
- | |
| 974 | {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 975 | {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 976 | {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 977 | {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 978 | {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 979 | {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 980 | {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 981 | {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 982 | {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 983 | {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 984 | {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 985 | {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 986 | {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 987 | {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 988 | {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 989 | {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 990 | {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 991 | {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 992 | {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 993 | {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 994 | {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 995 | {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 996 | {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 997 | {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 998 | {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 999 | {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1000 | {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1001 | {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1002 | {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1003 | {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1004 | {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 1005 | {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 1006 | {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1007 | {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 1008 | {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 1009 | {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1010 | {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1011 | {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1012 | {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1013 | {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1014 | {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1015 | {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1016 | {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1017 | {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1018 | {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1019 | {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1020 | {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1021 | {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1022 | {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1023 | {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
- | |
| 1024 | {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1025 | {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
- | |
| 1026 | {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1027 | {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1028 | {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1029 | {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1030 | {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1031 | {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1032 | {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1033 | {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1034 | {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1035 | {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1036 | {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1037 | {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1038 | {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1039 | {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1040 | {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1041 | {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
- | |
| 1042 | {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
- | |
| 1043 | {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
- | |
| 1044 | {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
- | |
| 1045 | {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1046 | {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
- | |
| 1047 | {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
- | |
| 1048 | {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
- | |
| 1049 | {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
- | |
| 1050 | {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
- | |
| 1051 | {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
- | |
| 1052 | {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
- | |
| 1053 | {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
- | |
| 1054 | {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
- | |
| 1055 | {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
- | |
| 1056 | {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1057 | {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
- | |
| 1058 | {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
- | |
| 1059 | {0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
- | |
| 1060 | {0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
- | |
| 1061 | {0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
- | |
| 1062 | {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
- | |
| 1063 | {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
- | |
| 1064 | {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
- | |
| 1065 | {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
- | |
| 1066 | {0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1067 | {0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1068 | {0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1069 | {0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1070 | {0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1071 | {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1072 | {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1073 | {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
- | |
| 1074 | {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1075 | {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1076 | {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1077 | {0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1078 | {0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1079 | {0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1080 | {0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1081 | {0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1082 | {0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1083 | {0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1084 | {0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1085 | {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1086 | {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1087 | {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1088 | {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1089 | {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
- | |
| 1090 | {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1091 | {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1092 | {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1093 | {0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1094 | {0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1095 | {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
- | |
| 1096 | {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1097 | {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1098 | {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
- | |
| 1099 | {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
- | |
| 1100 | {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1101 | {0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
- | |
| 1102 | {0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
- | |
| 1103 | {0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
- | |
| 1104 | {0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
- | |
| 1105 | {0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1106 | {0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1107 | {0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1108 | {0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1109 | {0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1110 | {0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1111 | {0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1112 | {0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1113 | {0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1114 | {0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1115 | {0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1116 | {0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
- | |
| 1117 | {0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1118 | {0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1119 | {0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1120 | {0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1121 | {0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1122 | {0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1123 | {0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1124 | {0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1125 | {0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1126 | {0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1127 | {0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1128 | {0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1129 | {0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
- | |
| 1130 | {0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
- | |
| 1131 | {0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
- | |
| 1132 | {0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
- | |
| 1133 | {0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
- | |
| 1134 | {0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
- | |
| 1135 | {0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1136 | {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1137 | {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1138 | {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1139 | {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1140 | {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1141 | {0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1142 | {0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1143 | {0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1144 | {0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1145 | {0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1146 | {0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1147 | {0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1148 | {0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1149 | {0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
- | |
| 1150 | {0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1151 | {0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
- | |
| 1152 | {0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1153 | {0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1154 | {0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1155 | {0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
- | |
| 1156 | {0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
- | |
| 1157 | {0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
- | |
| 1158 | {0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
- | |
| 1159 | {0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1160 | {0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1161 | {0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1162 | {0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1163 | {0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1164 | {0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1165 | {0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1166 | {0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
- | |
| 1167 | {0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1168 | {0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1169 | {0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1170 | {0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
- | |
| 1171 | {0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
- | |
| 1172 | {0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
- | |
| 1173 | {0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
- | |
| 1174 | {0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
- | |
| 1175 | {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
- | |
| 1176 | {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
- | |
| 1177 | {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
853 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 1178 | {0, 0, 0} |
854 | |
| 1179 | 855 | ||
| 1180 | 856 | ||
| Line 1222... | Line 898... | ||
| 1222 | int cant_use_aperture; |
898 | int cant_use_aperture; |
| 1223 | unsigned long page_mask; |
899 | unsigned long page_mask; |
| 1224 | }; |
900 | }; |
| Line 1225... | Line -... | ||
| 1225 | - | ||
| 1226 | - | ||
| Line 1227... | Line 901... | ||
| 1227 | #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
901 | |
| 1228 | 902 | ||
| 1229 | 903 | ||
| 1230 | /* |
904 | /* |
| Line 1267... | Line 941... | ||
| 1267 | 941 | ||
| 1268 | 942 | ||
| 1269 | /* |
943 | /* |
| 1270 | * RING helpers. |
- | |
| 1271 | */ |
- | |
| 1272 | #define CP_PACKET0 0x00000000 |
- | |
| 1273 | #define PACKET0_BASE_INDEX_SHIFT 0 |
- | |
| 1274 | #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
- | |
| 1275 | #define PACKET0_COUNT_SHIFT 16 |
- | |
| 1276 | #define PACKET0_COUNT_MASK (0x3fff << 16) |
- | |
| 1277 | #define CP_PACKET1 0x40000000 |
- | |
| 1278 | #define CP_PACKET2 0x80000000 |
- | |
| 1279 | #define PACKET2_PAD_SHIFT 0 |
- | |
| 1280 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
- | |
| 1281 | #define CP_PACKET3 0xC0000000 |
- | |
| 1282 | #define PACKET3_IT_OPCODE_SHIFT 8 |
- | |
| 1283 | #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
- | |
| 1284 | #define PACKET3_COUNT_SHIFT 16 |
- | |
| 1285 | #define PACKET3_COUNT_MASK (0x3fff << 16) |
- | |
| 1286 | /* PACKET3 op code */ |
- | |
| 1287 | #define PACKET3_NOP 0x10 |
- | |
| 1288 | #define PACKET3_3D_DRAW_VBUF 0x28 |
- | |
| 1289 | #define PACKET3_3D_DRAW_IMMD 0x29 |
- | |
| 1290 | #define PACKET3_3D_DRAW_INDX 0x2A |
- | |
| 1291 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
- | |
| 1292 | #define PACKET3_INDX_BUFFER 0x33 |
- | |
| 1293 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
- | |
| 1294 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
- | |
| 1295 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
- | |
| 1296 | #define PACKET3_BITBLT_MULTI 0x9B |
- | |
| 1297 | - | ||
| 1298 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
- | |
| 1299 | REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
- | |
| 1300 | REG_SET(PACKET0_COUNT, (n))) |
- | |
| 1301 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
- | |
| 1302 | #define PACKET3(op, n) (CP_PACKET3 | \ |
- | |
| 1303 | REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
- | |
| 1304 | REG_SET(PACKET3_COUNT, (n))) |
- | |
| 1305 | - | ||
| 1306 | #define PACKET_TYPE0 0 |
- | |
| 1307 | #define PACKET_TYPE1 1 |
- | |
| 1308 | #define PACKET_TYPE2 2 |
- | |
| 1309 | #define PACKET_TYPE3 3 |
- | |
| 1310 | - | ||
| 1311 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
- | |
| 1312 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
- | |
| 1313 | #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) |
- | |
| 1314 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
- | |
| 1315 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
944 | * RING helpers. |
| 1316 | 945 | */ |
|
| 1317 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
946 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| 1318 | { |
947 | { |
| 1319 | #if DRM_DEBUG_CODE |
948 | #if DRM_DEBUG_CODE |
| Line 1334... | Line 963... | ||
| 1334 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
963 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
| 1335 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
964 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 1336 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
965 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 1337 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
966 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
| 1338 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
967 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
| 1339 | #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
- | |
| 1340 | #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) |
- | |
| 1341 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
968 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
| 1342 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
969 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
| 1343 | #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) |
- | |
| 1344 | #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) |
- | |
| 1345 | #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) |
- | |
| 1346 | #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) |
- | |
| 1347 | #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev)) |
- | |
| 1348 | #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev)) |
- | |
| 1349 | #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) |
- | |
| 1350 | #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) |
- | |
| 1351 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
970 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| 1352 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
971 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
| 1353 | #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) |
- | |
| 1354 | #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) |
- | |
| 1355 | #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) |
- | |
| 1356 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
972 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
| 1357 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
973 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
| 1358 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
974 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
| 1359 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
975 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
| 1360 | #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev)) |
- | |
| 1361 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
976 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| 1362 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
977 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
| 1363 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
978 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
| 1364 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
979 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
| 1365 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
980 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| Line 1381... | Line 996... | ||
| 1381 | extern int radeon_clocks_init(struct radeon_device *rdev); |
996 | extern int radeon_clocks_init(struct radeon_device *rdev); |
| 1382 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
997 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
| 1383 | extern void radeon_scratch_init(struct radeon_device *rdev); |
998 | extern void radeon_scratch_init(struct radeon_device *rdev); |
| 1384 | extern void radeon_surface_init(struct radeon_device *rdev); |
999 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1385 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
1000 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
| - | 1001 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
|
| - | 1002 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
|
| Line 1386... | Line 1003... | ||
| 1386 | 1003 | ||
| 1387 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
1004 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
| 1388 | struct r100_mc_save { |
1005 | struct r100_mc_save { |
| 1389 | u32 GENMO_WT; |
1006 | u32 GENMO_WT; |
| Line 1412... | Line 1029... | ||
| 1412 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
1029 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
| 1413 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
1030 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
| 1414 | extern void r100_wb_disable(struct radeon_device *rdev); |
1031 | extern void r100_wb_disable(struct radeon_device *rdev); |
| 1415 | extern void r100_wb_fini(struct radeon_device *rdev); |
1032 | extern void r100_wb_fini(struct radeon_device *rdev); |
| 1416 | extern int r100_wb_init(struct radeon_device *rdev); |
1033 | extern int r100_wb_init(struct radeon_device *rdev); |
| - | 1034 | extern void r100_hdp_reset(struct radeon_device *rdev); |
|
| - | 1035 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
|
| - | 1036 | extern int r100_cp_reset(struct radeon_device *rdev); |
|
| - | 1037 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
|
| - | 1038 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
|
| - | 1039 | struct radeon_cs_packet *pkt, |
|
| - | 1040 | struct radeon_object *robj); |
|
| - | 1041 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
|
| - | 1042 | struct radeon_cs_packet *pkt, |
|
| - | 1043 | const unsigned *auth, unsigned n, |
|
| - | 1044 | radeon_packet0_check_t check); |
|
| - | 1045 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
|
| - | 1046 | struct radeon_cs_packet *pkt, |
|
| - | 1047 | unsigned idx); |
|
| - | 1048 | ||
| - | 1049 | /* rv200,rv250,rv280 */ |
|
| - | 1050 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
|
| Line 1417... | Line 1051... | ||
| 1417 | 1051 | ||
| 1418 | /* r300,r350,rv350,rv370,rv380 */ |
1052 | /* r300,r350,rv350,rv370,rv380 */ |
| 1419 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1053 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 1420 | extern void r300_mc_program(struct radeon_device *rdev); |
1054 | extern void r300_mc_program(struct radeon_device *rdev); |
| - | 1055 | extern void r300_vram_info(struct radeon_device *rdev); |
|
| - | 1056 | extern void r300_clock_startup(struct radeon_device *rdev); |
|
| 1421 | extern void r300_vram_info(struct radeon_device *rdev); |
1057 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| 1422 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1058 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
| 1423 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
1059 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
| 1424 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
1060 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
| Line 1425... | Line 1061... | ||
| 1425 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
1061 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| - | 1062 | ||
| 1426 | 1063 | /* r420,r423,rv410 */ |
|
| 1427 | /* r420,r423,rv410 */ |
1064 | extern int r420_mc_init(struct radeon_device *rdev); |
| 1428 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1065 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| - | 1066 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
|
| Line 1429... | Line 1067... | ||
| 1429 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
1067 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
| - | 1068 | extern void r420_pipes_init(struct radeon_device *rdev); |
|
| - | 1069 | ||
| - | 1070 | /* rv515 */ |
|
| - | 1071 | struct rv515_mc_save { |
|
| - | 1072 | u32 d1vga_control; |
|
| - | 1073 | u32 d2vga_control; |
|
| - | 1074 | u32 vga_render_control; |
|
| - | 1075 | u32 vga_hdp_control; |
|
| 1430 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
1076 | u32 d1crtc_control; |
| - | 1077 | u32 d2crtc_control; |
|
| - | 1078 | }; |
|
| - | 1079 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
|
| - | 1080 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
|
| - | 1081 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
|
| - | 1082 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
|
| - | 1083 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
|
| - | 1084 | extern void rv515_clock_startup(struct radeon_device *rdev); |
|
| - | 1085 | extern void rv515_debugfs(struct radeon_device *rdev); |
|
| - | 1086 | extern int rv515_suspend(struct radeon_device *rdev); |
|
| - | 1087 | ||
| - | 1088 | /* rs400 */ |
|
| - | 1089 | extern int rs400_gart_init(struct radeon_device *rdev); |
|
| - | 1090 | extern int rs400_gart_enable(struct radeon_device *rdev); |
|
| - | 1091 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
|
| - | 1092 | extern void rs400_gart_disable(struct radeon_device *rdev); |
|
| - | 1093 | extern void rs400_gart_fini(struct radeon_device *rdev); |
|
| - | 1094 | ||
| - | 1095 | /* rs600 */ |
|
| Line 1431... | Line 1096... | ||
| 1431 | 1096 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
|
| 1432 | /* rv515 */ |
1097 | extern int rs600_irq_set(struct radeon_device *rdev); |
| 1433 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1098 | extern void rs600_irq_disable(struct radeon_device *rdev); |
| 1434 | 1099 | ||
| Line 1447... | Line 1112... | ||
| 1447 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1112 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| 1448 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
1113 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
| 1449 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1114 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 1450 | extern int r600_ib_test(struct radeon_device *rdev); |
1115 | extern int r600_ib_test(struct radeon_device *rdev); |
| 1451 | extern int r600_ring_test(struct radeon_device *rdev); |
1116 | extern int r600_ring_test(struct radeon_device *rdev); |
| 1452 | extern int r600_wb_init(struct radeon_device *rdev); |
- | |
| 1453 | extern void r600_wb_fini(struct radeon_device *rdev); |
1117 | extern void r600_wb_fini(struct radeon_device *rdev); |
| - | 1118 | extern int r600_wb_enable(struct radeon_device *rdev); |
|
| - | 1119 | extern void r600_wb_disable(struct radeon_device *rdev); |
|
| 1454 | extern void r600_scratch_init(struct radeon_device *rdev); |
1120 | extern void r600_scratch_init(struct radeon_device *rdev); |
| 1455 | extern int r600_blit_init(struct radeon_device *rdev); |
1121 | extern int r600_blit_init(struct radeon_device *rdev); |
| 1456 | extern void r600_blit_fini(struct radeon_device *rdev); |
1122 | extern void r600_blit_fini(struct radeon_device *rdev); |
| 1457 | extern int r600_cp_init_microcode(struct radeon_device *rdev); |
1123 | extern int r600_cp_init_microcode(struct radeon_device *rdev); |
| 1458 | extern int r600_gpu_reset(struct radeon_device *rdev); |
1124 | extern int r600_gpu_reset(struct radeon_device *rdev); |