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Rev 2004 | Rev 2997 | ||
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Line 64... | Line 64... | ||
64 | 64 | ||
65 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
65 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
66 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
66 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
Line -... | Line 67... | ||
- | 67 | #define BACKEND_DISABLE(x) ((x) << 16) |
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- | 68 | ||
- | 69 | #define R_028808_CB_COLOR_CONTROL 0x28808 |
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- | 70 | #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) |
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- | 71 | #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) |
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- | 72 | #define C_028808_SPECIAL_OP 0xFFFFFF8F |
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- | 73 | #define V_028808_SPECIAL_NORMAL 0x00 |
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- | 74 | #define V_028808_SPECIAL_DISABLE 0x01 |
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67 | #define BACKEND_DISABLE(x) ((x) << 16) |
75 | #define V_028808_SPECIAL_RESOLVE_BOX 0x07 |
68 | 76 | ||
69 | #define CB_COLOR0_BASE 0x28040 |
77 | #define CB_COLOR0_BASE 0x28040 |
70 | #define CB_COLOR1_BASE 0x28044 |
78 | #define CB_COLOR1_BASE 0x28044 |
71 | #define CB_COLOR2_BASE 0x28048 |
79 | #define CB_COLOR2_BASE 0x28048 |
Line 76... | Line 84... | ||
76 | #define CB_COLOR7_BASE 0x2805C |
84 | #define CB_COLOR7_BASE 0x2805C |
77 | #define CB_COLOR7_FRAG 0x280FC |
85 | #define CB_COLOR7_FRAG 0x280FC |
Line 78... | Line 86... | ||
78 | 86 | ||
79 | #define CB_COLOR0_SIZE 0x28060 |
87 | #define CB_COLOR0_SIZE 0x28060 |
- | 88 | #define CB_COLOR0_VIEW 0x28080 |
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- | 89 | #define R_028080_CB_COLOR0_VIEW 0x028080 |
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- | 90 | #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) |
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- | 91 | #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) |
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- | 92 | #define C_028080_SLICE_START 0xFFFFF800 |
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- | 93 | #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
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- | 94 | #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
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- | 95 | #define C_028080_SLICE_MAX 0xFF001FFF |
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- | 96 | #define R_028084_CB_COLOR1_VIEW 0x028084 |
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- | 97 | #define R_028088_CB_COLOR2_VIEW 0x028088 |
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- | 98 | #define R_02808C_CB_COLOR3_VIEW 0x02808C |
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- | 99 | #define R_028090_CB_COLOR4_VIEW 0x028090 |
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- | 100 | #define R_028094_CB_COLOR5_VIEW 0x028094 |
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- | 101 | #define R_028098_CB_COLOR6_VIEW 0x028098 |
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- | 102 | #define R_02809C_CB_COLOR7_VIEW 0x02809C |
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- | 103 | #define R_028100_CB_COLOR0_MASK 0x028100 |
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- | 104 | #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) |
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- | 105 | #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) |
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- | 106 | #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 |
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- | 107 | #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) |
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- | 108 | #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) |
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- | 109 | #define C_028100_FMASK_TILE_MAX 0x00000FFF |
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- | 110 | #define R_028104_CB_COLOR1_MASK 0x028104 |
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- | 111 | #define R_028108_CB_COLOR2_MASK 0x028108 |
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- | 112 | #define R_02810C_CB_COLOR3_MASK 0x02810C |
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- | 113 | #define R_028110_CB_COLOR4_MASK 0x028110 |
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- | 114 | #define R_028114_CB_COLOR5_MASK 0x028114 |
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- | 115 | #define R_028118_CB_COLOR6_MASK 0x028118 |
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80 | #define CB_COLOR0_VIEW 0x28080 |
116 | #define R_02811C_CB_COLOR7_MASK 0x02811C |
- | 117 | #define CB_COLOR0_INFO 0x280a0 |
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- | 118 | # define CB_FORMAT(x) ((x) << 2) |
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- | 119 | # define CB_ARRAY_MODE(x) ((x) << 8) |
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- | 120 | # define CB_SOURCE_FORMAT(x) ((x) << 27) |
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- | 121 | # define CB_SF_EXPORT_FULL 0 |
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81 | #define CB_COLOR0_INFO 0x280a0 |
122 | # define CB_SF_EXPORT_NORM 1 |
82 | #define CB_COLOR0_TILE 0x280c0 |
123 | #define CB_COLOR0_TILE 0x280c0 |
83 | #define CB_COLOR0_FRAG 0x280e0 |
124 | #define CB_COLOR0_FRAG 0x280e0 |
Line 84... | Line 125... | ||
84 | #define CB_COLOR0_MASK 0x28100 |
125 | #define CB_COLOR0_MASK 0x28100 |
Line 132... | Line 173... | ||
132 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
173 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
133 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
174 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
Line 134... | Line 175... | ||
134 | 175 | ||
135 | #define CONFIG_MEMSIZE 0x5428 |
176 | #define CONFIG_MEMSIZE 0x5428 |
- | 177 | #define CONFIG_CNTL 0x5424 |
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- | 178 | #define CP_STALLED_STAT1 0x8674 |
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- | 179 | #define CP_STALLED_STAT2 0x8678 |
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136 | #define CONFIG_CNTL 0x5424 |
180 | #define CP_BUSY_STAT 0x867C |
137 | #define CP_STAT 0x8680 |
181 | #define CP_STAT 0x8680 |
138 | #define CP_COHER_BASE 0x85F8 |
182 | #define CP_COHER_BASE 0x85F8 |
139 | #define CP_DEBUG 0xC1FC |
183 | #define CP_DEBUG 0xC1FC |
140 | #define R_0086D8_CP_ME_CNTL 0x86D8 |
184 | #define R_0086D8_CP_ME_CNTL 0x86D8 |
Line 174... | Line 218... | ||
174 | 218 | ||
175 | #define DB_DEBUG 0x9830 |
219 | #define DB_DEBUG 0x9830 |
176 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) |
220 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) |
177 | #define DB_DEPTH_BASE 0x2800C |
221 | #define DB_DEPTH_BASE 0x2800C |
- | 222 | #define DB_HTILE_DATA_BASE 0x28014 |
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- | 223 | #define DB_HTILE_SURFACE 0x28D24 |
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- | 224 | #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) |
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- | 225 | #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) |
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- | 226 | #define C_028D24_HTILE_WIDTH 0xFFFFFFFE |
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- | 227 | #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) |
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- | 228 | #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) |
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- | 229 | #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD |
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178 | #define DB_HTILE_DATA_BASE 0x28014 |
230 | #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) |
179 | #define DB_WATERMARKS 0x9838 |
231 | #define DB_WATERMARKS 0x9838 |
180 | #define DEPTH_FREE(x) ((x) << 0) |
232 | #define DEPTH_FREE(x) ((x) << 0) |
181 | #define DEPTH_FLUSH(x) ((x) << 5) |
233 | #define DEPTH_FLUSH(x) ((x) << 5) |
182 | #define DEPTH_PENDING_FREE(x) ((x) << 15) |
234 | #define DEPTH_PENDING_FREE(x) ((x) << 15) |
Line 190... | Line 242... | ||
190 | #define BANK_SWAPS(x) ((x) << 11) |
242 | #define BANK_SWAPS(x) ((x) << 11) |
191 | #define SAMPLE_SPLIT(x) ((x) << 14) |
243 | #define SAMPLE_SPLIT(x) ((x) << 14) |
192 | #define BACKEND_MAP(x) ((x) << 16) |
244 | #define BACKEND_MAP(x) ((x) << 16) |
Line 193... | Line 245... | ||
193 | 245 | ||
- | 246 | #define GB_TILING_CONFIG 0x98F0 |
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- | 247 | #define PIPE_TILING__SHIFT 1 |
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Line 194... | Line 248... | ||
194 | #define GB_TILING_CONFIG 0x98F0 |
248 | #define PIPE_TILING__MASK 0x0000000e |
195 | 249 | ||
196 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
250 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
197 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
251 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
Line 415... | Line 469... | ||
415 | #define SQ_PGM_EXPORTS_PS 0x28854 |
469 | #define SQ_PGM_EXPORTS_PS 0x28854 |
416 | #define SQ_PGM_CF_OFFSET_PS 0x288cc |
470 | #define SQ_PGM_CF_OFFSET_PS 0x288cc |
417 | #define SQ_PGM_START_VS 0x28858 |
471 | #define SQ_PGM_START_VS 0x28858 |
418 | #define SQ_PGM_RESOURCES_VS 0x28868 |
472 | #define SQ_PGM_RESOURCES_VS 0x28868 |
419 | #define SQ_PGM_CF_OFFSET_VS 0x288d0 |
473 | #define SQ_PGM_CF_OFFSET_VS 0x288d0 |
- | 474 | ||
- | 475 | #define SQ_VTX_CONSTANT_WORD0_0 0x30000 |
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- | 476 | #define SQ_VTX_CONSTANT_WORD1_0 0x30004 |
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- | 477 | #define SQ_VTX_CONSTANT_WORD2_0 0x30008 |
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- | 478 | # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) |
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- | 479 | # define SQ_VTXC_STRIDE(x) ((x) << 8) |
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- | 480 | # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) |
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- | 481 | # define SQ_ENDIAN_NONE 0 |
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- | 482 | # define SQ_ENDIAN_8IN16 1 |
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- | 483 | # define SQ_ENDIAN_8IN32 2 |
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- | 484 | #define SQ_VTX_CONSTANT_WORD3_0 0x3000c |
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420 | #define SQ_VTX_CONSTANT_WORD6_0 0x38018 |
485 | #define SQ_VTX_CONSTANT_WORD6_0 0x38018 |
421 | #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) |
486 | #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) |
422 | #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) |
487 | #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) |
423 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
488 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
424 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 |
489 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 |
Line 443... | Line 508... | ||
443 | 508 | ||
444 | #define TC_CNTL 0x9608 |
509 | #define TC_CNTL 0x9608 |
445 | #define TC_L2_SIZE(x) ((x)<<5) |
510 | #define TC_L2_SIZE(x) ((x)<<5) |
Line -... | Line 511... | ||
- | 511 | #define L2_DISABLE_LATE_HIT (1<<9) |
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Line 446... | Line 512... | ||
446 | #define L2_DISABLE_LATE_HIT (1<<9) |
512 | |
447 | 513 | #define VC_ENHANCE 0x9714 |
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448 | 514 | ||
449 | #define VGT_CACHE_INVALIDATION 0x88C4 |
515 | #define VGT_CACHE_INVALIDATION 0x88C4 |
Line 475... | Line 541... | ||
475 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 |
541 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 |
476 | #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC |
542 | #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC |
477 | #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC |
543 | #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC |
478 | #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC |
544 | #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC |
479 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C |
545 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C |
- | 546 | #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 |
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- | 547 | #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 |
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- | 548 | #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 |
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- | 549 | #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 |
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- | 550 | ||
480 | #define VGT_STRMOUT_EN 0x28AB0 |
551 | #define VGT_STRMOUT_EN 0x28AB0 |
481 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
552 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
482 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
553 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
483 | #define VGT_EVENT_INITIATOR 0x28a90 |
554 | #define VGT_EVENT_INITIATOR 0x28a90 |
484 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
555 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
Line 551... | Line 622... | ||
551 | #define RLC_HB_CNTL 0x3f0c |
622 | #define RLC_HB_CNTL 0x3f0c |
552 | #define RLC_HB_RPTR 0x3f20 |
623 | #define RLC_HB_RPTR 0x3f20 |
553 | #define RLC_HB_WPTR 0x3f1c |
624 | #define RLC_HB_WPTR 0x3f1c |
554 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 |
625 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 |
555 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 |
626 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 |
- | 627 | #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 |
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- | 628 | #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c |
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- | 629 | #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 |
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556 | #define RLC_MC_CNTL 0x3f44 |
630 | #define RLC_MC_CNTL 0x3f44 |
557 | #define RLC_UCODE_CNTL 0x3f48 |
631 | #define RLC_UCODE_CNTL 0x3f48 |
558 | #define RLC_UCODE_ADDR 0x3f2c |
632 | #define RLC_UCODE_ADDR 0x3f2c |
559 | #define RLC_UCODE_DATA 0x3f30 |
633 | #define RLC_UCODE_DATA 0x3f30 |
Line -... | Line 634... | ||
- | 634 | ||
- | 635 | /* new for TN */ |
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- | 636 | #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 |
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- | 637 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
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560 | 638 | ||
561 | #define SRBM_SOFT_RESET 0xe60 |
639 | #define SRBM_SOFT_RESET 0xe60 |
Line 562... | Line 640... | ||
562 | # define SOFT_RESET_RLC (1 << 13) |
640 | # define SOFT_RESET_RLC (1 << 13) |
563 | 641 | ||
Line 775... | Line 853... | ||
775 | # define MM_WR_TO_CFG_EN (1 << 3) |
853 | # define MM_WR_TO_CFG_EN (1 << 3) |
776 | #define LINK_CNTL2 0x88 /* F0 */ |
854 | #define LINK_CNTL2 0x88 /* F0 */ |
777 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
855 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
778 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
856 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
Line -... | Line 857... | ||
- | 857 | ||
- | 858 | /* Audio clocks */ |
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- | 859 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 |
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- | 860 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 |
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- | 861 | #define DCCG_AUDIO_DTO0_LOAD 0x051c |
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- | 862 | # define DTO_LOAD (1 << 31) |
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- | 863 | #define DCCG_AUDIO_DTO0_CNTL 0x0520 |
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- | 864 | ||
- | 865 | #define DCCG_AUDIO_DTO1_PHASE 0x0524 |
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- | 866 | #define DCCG_AUDIO_DTO1_MODULE 0x0528 |
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- | 867 | #define DCCG_AUDIO_DTO1_LOAD 0x052c |
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- | 868 | #define DCCG_AUDIO_DTO1_CNTL 0x0530 |
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- | 869 | ||
- | 870 | #define DCCG_AUDIO_DTO_SELECT 0x0534 |
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- | 871 | ||
- | 872 | /* digital blocks */ |
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- | 873 | #define TMDSA_CNTL 0x7880 |
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- | 874 | # define TMDSA_HDMI_EN (1 << 2) |
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- | 875 | #define LVTMA_CNTL 0x7a80 |
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- | 876 | # define LVTMA_HDMI_EN (1 << 2) |
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- | 877 | #define DDIA_CNTL 0x7200 |
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- | 878 | # define DDIA_HDMI_EN (1 << 2) |
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- | 879 | #define DIG0_CNTL 0x75a0 |
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- | 880 | # define DIG_MODE(x) (((x) & 7) << 8) |
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- | 881 | # define DIG_MODE_DP 0 |
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- | 882 | # define DIG_MODE_LVDS 1 |
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- | 883 | # define DIG_MODE_TMDS_DVI 2 |
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- | 884 | # define DIG_MODE_TMDS_HDMI 3 |
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- | 885 | # define DIG_MODE_SDVO 4 |
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- | 886 | #define DIG1_CNTL 0x79a0 |
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- | 887 | ||
- | 888 | /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one |
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- | 889 | * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly |
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- | 890 | * different due to the new DIG blocks, but also have 2 instances. |
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- | 891 | * DCE 3.0 HDMI blocks are part of each DIG encoder. |
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- | 892 | */ |
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- | 893 | ||
- | 894 | /* rs6xx/rs740/r6xx/dce3 */ |
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- | 895 | #define HDMI0_CONTROL 0x7400 |
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- | 896 | /* rs6xx/rs740/r6xx */ |
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- | 897 | # define HDMI0_ENABLE (1 << 0) |
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- | 898 | # define HDMI0_STREAM(x) (((x) & 3) << 2) |
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- | 899 | # define HDMI0_STREAM_TMDSA 0 |
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- | 900 | # define HDMI0_STREAM_LVTMA 1 |
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- | 901 | # define HDMI0_STREAM_DVOA 2 |
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- | 902 | # define HDMI0_STREAM_DDIA 3 |
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- | 903 | /* rs6xx/r6xx/dce3 */ |
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- | 904 | # define HDMI0_ERROR_ACK (1 << 8) |
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- | 905 | # define HDMI0_ERROR_MASK (1 << 9) |
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- | 906 | #define HDMI0_STATUS 0x7404 |
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- | 907 | # define HDMI0_ACTIVE_AVMUTE (1 << 0) |
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- | 908 | # define HDMI0_AUDIO_ENABLE (1 << 4) |
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- | 909 | # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) |
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- | 910 | # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) |
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- | 911 | #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 |
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- | 912 | # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) |
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- | 913 | # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) |
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- | 914 | # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) |
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- | 915 | # define HDMI0_AUDIO_TEST_EN (1 << 12) |
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- | 916 | # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) |
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- | 917 | # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) |
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- | 918 | # define HDMI0_60958_CS_UPDATE (1 << 26) |
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- | 919 | # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) |
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- | 920 | # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) |
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- | 921 | #define HDMI0_AUDIO_CRC_CONTROL 0x740c |
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- | 922 | # define HDMI0_AUDIO_CRC_EN (1 << 0) |
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- | 923 | #define HDMI0_VBI_PACKET_CONTROL 0x7410 |
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- | 924 | # define HDMI0_NULL_SEND (1 << 0) |
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- | 925 | # define HDMI0_GC_SEND (1 << 4) |
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- | 926 | # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ |
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- | 927 | #define HDMI0_INFOFRAME_CONTROL0 0x7414 |
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- | 928 | # define HDMI0_AVI_INFO_SEND (1 << 0) |
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- | 929 | # define HDMI0_AVI_INFO_CONT (1 << 1) |
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- | 930 | # define HDMI0_AUDIO_INFO_SEND (1 << 4) |
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- | 931 | # define HDMI0_AUDIO_INFO_CONT (1 << 5) |
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- | 932 | # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ |
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- | 933 | # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) |
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- | 934 | # define HDMI0_MPEG_INFO_SEND (1 << 8) |
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- | 935 | # define HDMI0_MPEG_INFO_CONT (1 << 9) |
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- | 936 | # define HDMI0_MPEG_INFO_UPDATE (1 << 10) |
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- | 937 | #define HDMI0_INFOFRAME_CONTROL1 0x7418 |
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- | 938 | # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) |
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- | 939 | # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) |
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- | 940 | # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) |
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- | 941 | #define HDMI0_GENERIC_PACKET_CONTROL 0x741c |
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- | 942 | # define HDMI0_GENERIC0_SEND (1 << 0) |
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- | 943 | # define HDMI0_GENERIC0_CONT (1 << 1) |
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- | 944 | # define HDMI0_GENERIC0_UPDATE (1 << 2) |
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- | 945 | # define HDMI0_GENERIC1_SEND (1 << 4) |
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- | 946 | # define HDMI0_GENERIC1_CONT (1 << 5) |
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- | 947 | # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) |
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- | 948 | # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) |
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- | 949 | #define HDMI0_GC 0x7428 |
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- | 950 | # define HDMI0_GC_AVMUTE (1 << 0) |
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- | 951 | #define HDMI0_AVI_INFO0 0x7454 |
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- | 952 | # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
|
- | 953 | # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) |
|
- | 954 | # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) |
|
- | 955 | # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) |
|
- | 956 | # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) |
|
- | 957 | # define HDMI0_AVI_INFO_Y_RGB 0 |
|
- | 958 | # define HDMI0_AVI_INFO_Y_YCBCR422 1 |
|
- | 959 | # define HDMI0_AVI_INFO_Y_YCBCR444 2 |
|
- | 960 | # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) |
|
- | 961 | # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) |
|
- | 962 | # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) |
|
- | 963 | # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) |
|
- | 964 | # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) |
|
- | 965 | # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) |
|
- | 966 | # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) |
|
- | 967 | #define HDMI0_AVI_INFO1 0x7458 |
|
- | 968 | # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ |
|
- | 969 | # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ |
|
- | 970 | # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) |
|
- | 971 | #define HDMI0_AVI_INFO2 0x745c |
|
- | 972 | # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) |
|
- | 973 | # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) |
|
- | 974 | #define HDMI0_AVI_INFO3 0x7460 |
|
- | 975 | # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) |
|
- | 976 | # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) |
|
- | 977 | #define HDMI0_MPEG_INFO0 0x7464 |
|
- | 978 | # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
|
- | 979 | # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) |
|
- | 980 | # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) |
|
- | 981 | # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) |
|
- | 982 | #define HDMI0_MPEG_INFO1 0x7468 |
|
- | 983 | # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) |
|
- | 984 | # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) |
|
- | 985 | # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) |
|
- | 986 | #define HDMI0_GENERIC0_HDR 0x746c |
|
- | 987 | #define HDMI0_GENERIC0_0 0x7470 |
|
- | 988 | #define HDMI0_GENERIC0_1 0x7474 |
|
- | 989 | #define HDMI0_GENERIC0_2 0x7478 |
|
- | 990 | #define HDMI0_GENERIC0_3 0x747c |
|
- | 991 | #define HDMI0_GENERIC0_4 0x7480 |
|
- | 992 | #define HDMI0_GENERIC0_5 0x7484 |
|
- | 993 | #define HDMI0_GENERIC0_6 0x7488 |
|
- | 994 | #define HDMI0_GENERIC1_HDR 0x748c |
|
- | 995 | #define HDMI0_GENERIC1_0 0x7490 |
|
- | 996 | #define HDMI0_GENERIC1_1 0x7494 |
|
- | 997 | #define HDMI0_GENERIC1_2 0x7498 |
|
- | 998 | #define HDMI0_GENERIC1_3 0x749c |
|
- | 999 | #define HDMI0_GENERIC1_4 0x74a0 |
|
- | 1000 | #define HDMI0_GENERIC1_5 0x74a4 |
|
- | 1001 | #define HDMI0_GENERIC1_6 0x74a8 |
|
- | 1002 | #define HDMI0_ACR_32_0 0x74ac |
|
- | 1003 | # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) |
|
- | 1004 | #define HDMI0_ACR_32_1 0x74b0 |
|
- | 1005 | # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) |
|
- | 1006 | #define HDMI0_ACR_44_0 0x74b4 |
|
- | 1007 | # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) |
|
- | 1008 | #define HDMI0_ACR_44_1 0x74b8 |
|
- | 1009 | # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) |
|
- | 1010 | #define HDMI0_ACR_48_0 0x74bc |
|
- | 1011 | # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) |
|
- | 1012 | #define HDMI0_ACR_48_1 0x74c0 |
|
- | 1013 | # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) |
|
- | 1014 | #define HDMI0_ACR_STATUS_0 0x74c4 |
|
- | 1015 | #define HDMI0_ACR_STATUS_1 0x74c8 |
|
- | 1016 | #define HDMI0_AUDIO_INFO0 0x74cc |
|
- | 1017 | # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
|
- | 1018 | # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) |
|
- | 1019 | #define HDMI0_AUDIO_INFO1 0x74d0 |
|
- | 1020 | # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) |
|
- | 1021 | # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) |
|
- | 1022 | # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) |
|
- | 1023 | # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) |
|
- | 1024 | #define HDMI0_60958_0 0x74d4 |
|
- | 1025 | # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) |
|
- | 1026 | # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) |
|
- | 1027 | # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) |
|
- | 1028 | # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) |
|
- | 1029 | # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) |
|
- | 1030 | # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) |
|
- | 1031 | # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) |
|
- | 1032 | # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) |
|
- | 1033 | # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) |
|
- | 1034 | # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) |
|
- | 1035 | #define HDMI0_60958_1 0x74d8 |
|
- | 1036 | # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) |
|
- | 1037 | # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) |
|
- | 1038 | # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) |
|
- | 1039 | # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) |
|
- | 1040 | # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) |
|
- | 1041 | #define HDMI0_ACR_PACKET_CONTROL 0x74dc |
|
- | 1042 | # define HDMI0_ACR_SEND (1 << 0) |
|
- | 1043 | # define HDMI0_ACR_CONT (1 << 1) |
|
- | 1044 | # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) |
|
- | 1045 | # define HDMI0_ACR_HW 0 |
|
- | 1046 | # define HDMI0_ACR_32 1 |
|
- | 1047 | # define HDMI0_ACR_44 2 |
|
- | 1048 | # define HDMI0_ACR_48 3 |
|
- | 1049 | # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ |
|
- | 1050 | # define HDMI0_ACR_AUTO_SEND (1 << 12) |
|
- | 1051 | #define HDMI0_RAMP_CONTROL0 0x74e0 |
|
- | 1052 | # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) |
|
- | 1053 | #define HDMI0_RAMP_CONTROL1 0x74e4 |
|
- | 1054 | # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) |
|
- | 1055 | #define HDMI0_RAMP_CONTROL2 0x74e8 |
|
- | 1056 | # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) |
|
- | 1057 | #define HDMI0_RAMP_CONTROL3 0x74ec |
|
- | 1058 | # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) |
|
- | 1059 | /* HDMI0_60958_2 is r7xx only */ |
|
- | 1060 | #define HDMI0_60958_2 0x74f0 |
|
- | 1061 | # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) |
|
- | 1062 | # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) |
|
- | 1063 | # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) |
|
- | 1064 | # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) |
|
- | 1065 | # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) |
|
- | 1066 | # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) |
|
- | 1067 | /* r6xx only; second instance starts at 0x7700 */ |
|
- | 1068 | #define HDMI1_CONTROL 0x7700 |
|
- | 1069 | #define HDMI1_STATUS 0x7704 |
|
- | 1070 | #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 |
|
- | 1071 | /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ |
|
- | 1072 | #define DCE3_HDMI1_CONTROL 0x7800 |
|
- | 1073 | #define DCE3_HDMI1_STATUS 0x7804 |
|
- | 1074 | #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 |
|
- | 1075 | /* DCE3.2 (for interrupts) */ |
|
- | 1076 | #define AFMT_STATUS 0x7600 |
|
- | 1077 | # define AFMT_AUDIO_ENABLE (1 << 4) |
|
- | 1078 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) |
|
- | 1079 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) |
|
- | 1080 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) |
|
- | 1081 | #define AFMT_AUDIO_PACKET_CONTROL 0x7604 |
|
- | 1082 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) |
|
- | 1083 | # define AFMT_AUDIO_TEST_EN (1 << 12) |
|
- | 1084 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) |
|
- | 1085 | # define AFMT_60958_CS_UPDATE (1 << 26) |
|
- | 1086 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) |
|
- | 1087 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) |
|
- | 1088 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) |
|
- | 1089 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) |
|
779 | 1090 | ||
780 | /* |
1091 | /* |
781 | * PM4 |
1092 | * PM4 |
782 | */ |
1093 | */ |
783 | #define PACKET_TYPE0 0 |
1094 | #define PACKET_TYPE0 0 |
Line 813... | Line 1124... | ||
813 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
1124 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
814 | #define PACKET3_NUM_INSTANCES 0x2F |
1125 | #define PACKET3_NUM_INSTANCES 0x2F |
815 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
1126 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
816 | #define PACKET3_INDIRECT_BUFFER_MP 0x38 |
1127 | #define PACKET3_INDIRECT_BUFFER_MP 0x38 |
817 | #define PACKET3_MEM_SEMAPHORE 0x39 |
1128 | #define PACKET3_MEM_SEMAPHORE 0x39 |
- | 1129 | # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) |
|
- | 1130 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) |
|
- | 1131 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29) |
|
818 | #define PACKET3_MPEG_INDEX 0x3A |
1132 | #define PACKET3_MPEG_INDEX 0x3A |
- | 1133 | #define PACKET3_COPY_DW 0x3B |
|
819 | #define PACKET3_WAIT_REG_MEM 0x3C |
1134 | #define PACKET3_WAIT_REG_MEM 0x3C |
820 | #define PACKET3_MEM_WRITE 0x3D |
1135 | #define PACKET3_MEM_WRITE 0x3D |
821 | #define PACKET3_INDIRECT_BUFFER 0x32 |
1136 | #define PACKET3_INDIRECT_BUFFER 0x32 |
822 | #define PACKET3_SURFACE_SYNC 0x43 |
1137 | #define PACKET3_SURFACE_SYNC 0x43 |
823 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
1138 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
Line 875... | Line 1190... | ||
875 | #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 |
1190 | #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 |
876 | #define PACKET3_SET_SAMPLER_END 0x0003cff0 |
1191 | #define PACKET3_SET_SAMPLER_END 0x0003cff0 |
877 | #define PACKET3_SET_CTL_CONST 0x6F |
1192 | #define PACKET3_SET_CTL_CONST 0x6F |
878 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 |
1193 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 |
879 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 |
1194 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 |
- | 1195 | #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ |
|
880 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 |
1196 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 |
Line 881... | Line 1197... | ||
881 | 1197 | ||
882 | 1198 | ||
Line 1104... | Line 1420... | ||
1104 | #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) |
1420 | #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) |
1105 | #define C_0280A0_COMP_SWAP 0xFFFCFFFF |
1421 | #define C_0280A0_COMP_SWAP 0xFFFCFFFF |
1106 | #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) |
1422 | #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) |
1107 | #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) |
1423 | #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) |
1108 | #define C_0280A0_TILE_MODE 0xFFF3FFFF |
1424 | #define C_0280A0_TILE_MODE 0xFFF3FFFF |
- | 1425 | #define V_0280A0_TILE_DISABLE 0 |
|
- | 1426 | #define V_0280A0_CLEAR_ENABLE 1 |
|
- | 1427 | #define V_0280A0_FRAG_ENABLE 2 |
|
1109 | #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) |
1428 | #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) |
1110 | #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) |
1429 | #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) |
1111 | #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF |
1430 | #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF |
1112 | #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) |
1431 | #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) |
1113 | #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) |
1432 | #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) |
Line 1350... | Line 1669... | ||
1350 | #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) |
1669 | #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) |
1351 | #define C_038010_DST_SEL_Z 0xFE3FFFFF |
1670 | #define C_038010_DST_SEL_Z 0xFE3FFFFF |
1352 | #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) |
1671 | #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) |
1353 | #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) |
1672 | #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) |
1354 | #define C_038010_DST_SEL_W 0xF1FFFFFF |
1673 | #define C_038010_DST_SEL_W 0xF1FFFFFF |
- | 1674 | # define SQ_SEL_X 0 |
|
- | 1675 | # define SQ_SEL_Y 1 |
|
- | 1676 | # define SQ_SEL_Z 2 |
|
- | 1677 | # define SQ_SEL_W 3 |
|
- | 1678 | # define SQ_SEL_0 4 |
|
- | 1679 | # define SQ_SEL_1 5 |
|
1355 | #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) |
1680 | #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) |
1356 | #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) |
1681 | #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) |
1357 | #define C_038010_BASE_LEVEL 0x0FFFFFFF |
1682 | #define C_038010_BASE_LEVEL 0x0FFFFFFF |
1358 | #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 |
1683 | #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 |
1359 | #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) |
1684 | #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) |