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Rev 5139 | Rev 5271 | ||
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Line 321... | Line 321... | ||
321 | #define HDP_NONSURFACE_SIZE 0x2C0C |
321 | #define HDP_NONSURFACE_SIZE 0x2C0C |
322 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
322 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
323 | #define HDP_TILING_CONFIG 0x2F3C |
323 | #define HDP_TILING_CONFIG 0x2F3C |
324 | #define HDP_DEBUG1 0x2F34 |
324 | #define HDP_DEBUG1 0x2F34 |
Line -... | Line 325... | ||
- | 325 | ||
325 | 326 | #define MC_CONFIG 0x2000 |
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326 | #define MC_VM_AGP_TOP 0x2184 |
327 | #define MC_VM_AGP_TOP 0x2184 |
327 | #define MC_VM_AGP_BOT 0x2188 |
328 | #define MC_VM_AGP_BOT 0x2188 |
328 | #define MC_VM_AGP_BASE 0x218C |
329 | #define MC_VM_AGP_BASE 0x218C |
329 | #define MC_VM_FB_LOCATION 0x2180 |
330 | #define MC_VM_FB_LOCATION 0x2180 |
330 | #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C |
331 | #define MC_VM_L1_TLB_MCB_RD_UVD_CNTL 0x2124 |
331 | #define ENABLE_L1_TLB (1 << 0) |
332 | #define ENABLE_L1_TLB (1 << 0) |
332 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
333 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
333 | #define ENABLE_L1_STRICT_ORDERING (1 << 2) |
334 | #define ENABLE_L1_STRICT_ORDERING (1 << 2) |
334 | #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 |
335 | #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 |
Line 345... | Line 346... | ||
345 | #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 |
346 | #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 |
346 | #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 |
347 | #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 |
347 | #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) |
348 | #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) |
348 | #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 |
349 | #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 |
349 | #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 |
350 | #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 |
- | 351 | #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C |
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350 | #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 |
352 | #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 |
351 | #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC |
353 | #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC |
352 | #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 |
354 | #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 |
353 | #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 |
355 | #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 |
354 | #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C |
356 | #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C |
355 | #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 |
357 | #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 |
- | 358 | #define MC_VM_L1_TLB_MCB_WR_UVD_CNTL 0x212c |
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356 | #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 |
359 | #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 |
357 | #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 |
360 | #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 |
358 | #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 |
361 | #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 |
359 | #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 |
362 | #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 |
360 | #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C |
363 | #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C |
Line 364... | Line 367... | ||
364 | #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
367 | #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
365 | #define LOGICAL_PAGE_NUMBER_SHIFT 0 |
368 | #define LOGICAL_PAGE_NUMBER_SHIFT 0 |
366 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
369 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
367 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
370 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
Line -... | Line 371... | ||
- | 371 | ||
- | 372 | #define RS_DQ_RD_RET_CONF 0x2348 |
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368 | 373 | ||
369 | #define PA_CL_ENHANCE 0x8A14 |
374 | #define PA_CL_ENHANCE 0x8A14 |
370 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
375 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
371 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
376 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
372 | #define PA_SC_AA_CONFIG 0x28C04 |
377 | #define PA_SC_AA_CONFIG 0x28C04 |
Line 920... | Line 925... | ||
920 | # define MM_WR_TO_CFG_EN (1 << 3) |
925 | # define MM_WR_TO_CFG_EN (1 << 3) |
921 | #define LINK_CNTL2 0x88 /* F0 */ |
926 | #define LINK_CNTL2 0x88 /* F0 */ |
922 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
927 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
923 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
928 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
Line -... | Line 929... | ||
- | 929 | ||
- | 930 | /* Audio */ |
|
- | 931 | #define AZ_HOT_PLUG_CONTROL 0x7300 |
|
- | 932 | # define AZ_FORCE_CODEC_WAKE (1 << 0) |
|
- | 933 | # define JACK_DETECTION_ENABLE (1 << 4) |
|
- | 934 | # define UNSOLICITED_RESPONSE_ENABLE (1 << 8) |
|
- | 935 | # define CODEC_HOT_PLUG_ENABLE (1 << 12) |
|
- | 936 | # define AUDIO_ENABLED (1 << 31) |
|
- | 937 | /* DCE3 adds */ |
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- | 938 | # define PIN0_JACK_DETECTION_ENABLE (1 << 4) |
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- | 939 | # define PIN1_JACK_DETECTION_ENABLE (1 << 5) |
|
- | 940 | # define PIN2_JACK_DETECTION_ENABLE (1 << 6) |
|
- | 941 | # define PIN3_JACK_DETECTION_ENABLE (1 << 7) |
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- | 942 | # define PIN0_AUDIO_ENABLED (1 << 24) |
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- | 943 | # define PIN1_AUDIO_ENABLED (1 << 25) |
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- | 944 | # define PIN2_AUDIO_ENABLED (1 << 26) |
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- | 945 | # define PIN3_AUDIO_ENABLED (1 << 27) |
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924 | 946 | ||
925 | /* Audio clocks DCE 2.0/3.0 */ |
947 | /* Audio clocks DCE 2.0/3.0 */ |
926 | #define AUDIO_DTO 0x7340 |
948 | #define AUDIO_DTO 0x7340 |
927 | # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) |
949 | # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) |
Line 1474... | Line 1496... | ||
1474 | 1496 | ||
1475 | #define UVD_LMI_EXT40_ADDR 0xf498 |
1497 | #define UVD_LMI_EXT40_ADDR 0xf498 |
1476 | #define UVD_CGC_GATE 0xf4a8 |
1498 | #define UVD_CGC_GATE 0xf4a8 |
1477 | #define UVD_LMI_CTRL2 0xf4f4 |
1499 | #define UVD_LMI_CTRL2 0xf4f4 |
- | 1500 | #define UVD_MASTINT_EN 0xf500 |
|
1478 | #define UVD_MASTINT_EN 0xf500 |
1501 | #define UVD_FW_START 0xf51C |
1479 | #define UVD_LMI_ADDR_EXT 0xf594 |
1502 | #define UVD_LMI_ADDR_EXT 0xf594 |
1480 | #define UVD_LMI_CTRL 0xf598 |
1503 | #define UVD_LMI_CTRL 0xf598 |
1481 | #define UVD_LMI_SWAP_CNTL 0xf5b4 |
1504 | #define UVD_LMI_SWAP_CNTL 0xf5b4 |
1482 | #define UVD_MP_SWAP_CNTL 0xf5bC |
1505 | #define UVD_MP_SWAP_CNTL 0xf5bC |
Line 1486... | Line 1509... | ||
1486 | #define UVD_MPC_SET_MUXB0 0xf5eC |
1509 | #define UVD_MPC_SET_MUXB0 0xf5eC |
1487 | #define UVD_MPC_SET_MUXB1 0xf5f0 |
1510 | #define UVD_MPC_SET_MUXB1 0xf5f0 |
1488 | #define UVD_MPC_SET_MUX 0xf5f4 |
1511 | #define UVD_MPC_SET_MUX 0xf5f4 |
1489 | #define UVD_MPC_SET_ALU 0xf5f8 |
1512 | #define UVD_MPC_SET_ALU 0xf5f8 |
Line -... | Line 1513... | ||
- | 1513 | ||
- | 1514 | #define UVD_VCPU_CACHE_OFFSET0 0xf608 |
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- | 1515 | #define UVD_VCPU_CACHE_SIZE0 0xf60c |
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- | 1516 | #define UVD_VCPU_CACHE_OFFSET1 0xf610 |
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- | 1517 | #define UVD_VCPU_CACHE_SIZE1 0xf614 |
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- | 1518 | #define UVD_VCPU_CACHE_OFFSET2 0xf618 |
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- | 1519 | #define UVD_VCPU_CACHE_SIZE2 0xf61c |
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1490 | 1520 | ||
1491 | #define UVD_VCPU_CNTL 0xf660 |
1521 | #define UVD_VCPU_CNTL 0xf660 |
1492 | #define UVD_SOFT_RESET 0xf680 |
1522 | #define UVD_SOFT_RESET 0xf680 |
1493 | #define RBC_SOFT_RESET (1<<0) |
1523 | #define RBC_SOFT_RESET (1<<0) |
1494 | #define LBSI_SOFT_RESET (1<<1) |
1524 | #define LBSI_SOFT_RESET (1<<1) |
Line 1515... | Line 1545... | ||
1515 | #define UVD_RBC_RB_CNTL 0xf6a4 |
1545 | #define UVD_RBC_RB_CNTL 0xf6a4 |
1516 | #define UVD_RBC_RB_RPTR_ADDR 0xf6a8 |
1546 | #define UVD_RBC_RB_RPTR_ADDR 0xf6a8 |
Line 1517... | Line 1547... | ||
1517 | 1547 | ||
Line -... | Line 1548... | ||
- | 1548 | #define UVD_CONTEXT_ID 0xf6f4 |
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- | 1549 | ||
- | 1550 | /* rs780 only */ |
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- | 1551 | #define GFX_MACRO_BYPASS_CNTL 0x30c0 |
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- | 1552 | #define SPLL_BYPASS_CNTL (1 << 0) |
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- | 1553 | #define UPLL_BYPASS_CNTL (1 << 1) |
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- | 1554 | ||
- | 1555 | #define CG_UPLL_FUNC_CNTL 0x7e0 |
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- | 1556 | # define UPLL_RESET_MASK 0x00000001 |
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1518 | #define UVD_CONTEXT_ID 0xf6f4 |
1557 | # define UPLL_SLEEP_MASK 0x00000002 |
- | 1558 | # define UPLL_BYPASS_EN_MASK 0x00000004 |
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- | 1559 | # define UPLL_CTLREQ_MASK 0x00000008 |
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- | 1560 | # define UPLL_FB_DIV(x) ((x) << 4) |
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- | 1561 | # define UPLL_FB_DIV_MASK 0x0000FFF0 |
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- | 1562 | # define UPLL_REF_DIV(x) ((x) << 16) |
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1519 | 1563 | # define UPLL_REF_DIV_MASK 0x003F0000 |
|
1520 | # define UPLL_CTLREQ_MASK 0x00000008 |
1564 | # define UPLL_REFCLK_SRC_SEL_MASK 0x20000000 |
- | 1565 | # define UPLL_CTLACK_MASK 0x40000000 |
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- | 1566 | # define UPLL_CTLACK2_MASK 0x80000000 |
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- | 1567 | #define CG_UPLL_FUNC_CNTL_2 0x7e4 |
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- | 1568 | # define UPLL_SW_HILEN(x) ((x) << 0) |
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- | 1569 | # define UPLL_SW_LOLEN(x) ((x) << 4) |
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- | 1570 | # define UPLL_SW_HILEN2(x) ((x) << 8) |
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- | 1571 | # define UPLL_SW_LOLEN2(x) ((x) << 12) |
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- | 1572 | # define UPLL_DIVEN_MASK 0x00010000 |
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- | 1573 | # define UPLL_DIVEN2_MASK 0x00020000 |
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- | 1574 | # define UPLL_SW_MASK 0x0003FFFF |
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- | 1575 | # define VCLK_SRC_SEL(x) ((x) << 20) |
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- | 1576 | # define VCLK_SRC_SEL_MASK 0x01F00000 |
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Line 1521... | Line 1577... | ||
1521 | # define UPLL_CTLACK_MASK 0x40000000 |
1577 | # define DCLK_SRC_SEL(x) ((x) << 25) |
1522 | # define UPLL_CTLACK2_MASK 0x80000000 |
1578 | # define DCLK_SRC_SEL_MASK 0x3E000000 |
1523 | 1579 | ||
1524 | /* |
1580 | /* |