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Rev 2175 | Rev 2997 | ||
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Line 21... | Line 21... | ||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. |
22 | * DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | */ |
24 | */ |
Line 25... | Line 25... | ||
25 | 25 | ||
26 | #include "drmP.h" |
- | |
27 | #include "drm.h" |
26 | #include |
28 | #include "radeon_drm.h" |
27 | #include |
Line 29... | Line 28... | ||
29 | #include "radeon.h" |
28 | #include "radeon.h" |
30 | 29 | ||
31 | #include "r600d.h" |
- | |
32 | #include "r600_blit_shaders.h" |
- | |
33 | - | ||
34 | #define DI_PT_RECTLIST 0x11 |
30 | #include "r600d.h" |
35 | #define DI_INDEX_SIZE_16_BIT 0x0 |
- | |
36 | #define DI_SRC_SEL_AUTO_INDEX 0x2 |
- | |
37 | - | ||
38 | #define FMT_8 0x1 |
- | |
39 | #define FMT_5_6_5 0x8 |
- | |
40 | #define FMT_8_8_8_8 0x1a |
- | |
41 | #define COLOR_8 0x1 |
- | |
Line 42... | Line 31... | ||
42 | #define COLOR_5_6_5 0x8 |
31 | #include "r600_blit_shaders.h" |
43 | #define COLOR_8_8_8_8 0x1a |
32 | #include "radeon_blit_common.h" |
44 | 33 | ||
45 | /* emits 21 on rv770+, 23 on r600 */ |
34 | /* emits 21 on rv770+, 23 on r600 */ |
46 | static void |
35 | static void |
- | 36 | set_render_target(struct radeon_device *rdev, int format, |
|
47 | set_render_target(struct radeon_device *rdev, int format, |
37 | int w, int h, u64 gpu_addr) |
48 | int w, int h, u64 gpu_addr) |
38 | { |
Line 49... | Line 39... | ||
49 | { |
39 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
50 | u32 cb_color_info; |
40 | u32 cb_color_info; |
51 | int pitch, slice; |
41 | int pitch, slice; |
Line 52... | Line 42... | ||
52 | 42 | ||
- | 43 | h = ALIGN(h, 8); |
|
- | 44 | if (h < 8) |
|
53 | h = ALIGN(h, 8); |
45 | h = 8; |
54 | if (h < 8) |
46 | |
Line 55... | Line 47... | ||
55 | h = 8; |
47 | cb_color_info = CB_FORMAT(format) | |
56 | 48 | CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) | |
|
57 | cb_color_info = ((format << 2) | (1 << 27) | (1 << 8)); |
49 | CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); |
Line 58... | Line 50... | ||
58 | pitch = (w / 8) - 1; |
50 | pitch = (w / 8) - 1; |
59 | slice = ((w * h) / 64) - 1; |
51 | slice = ((w * h) / 64) - 1; |
60 | 52 | ||
61 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
53 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
Line 62... | Line 54... | ||
62 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
54 | radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
63 | radeon_ring_write(rdev, gpu_addr >> 8); |
55 | radeon_ring_write(ring, gpu_addr >> 8); |
64 | 56 | ||
Line 65... | Line 57... | ||
65 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { |
57 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { |
66 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
58 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
67 | radeon_ring_write(rdev, 2 << 0); |
59 | radeon_ring_write(ring, 2 << 0); |
Line 68... | Line 60... | ||
68 | } |
60 | } |
69 | 61 | ||
70 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
62 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
Line 71... | Line 63... | ||
71 | radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
63 | radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
72 | radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
64 | radeon_ring_write(ring, (pitch << 0) | (slice << 10)); |
73 | 65 | ||
Line 74... | Line 66... | ||
74 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
66 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
75 | radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
67 | radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
76 | radeon_ring_write(rdev, 0); |
68 | radeon_ring_write(ring, 0); |
Line 77... | Line 69... | ||
77 | 69 | ||
78 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
70 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
79 | radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
71 | radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
80 | radeon_ring_write(rdev, cb_color_info); |
72 | radeon_ring_write(ring, cb_color_info); |
Line 81... | Line 73... | ||
81 | 73 | ||
82 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
74 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
83 | radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
75 | radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
84 | radeon_ring_write(rdev, 0); |
76 | radeon_ring_write(ring, 0); |
85 | 77 | ||
86 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
78 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
- | 79 | radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
|
87 | radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
80 | radeon_ring_write(ring, 0); |
Line 88... | Line 81... | ||
88 | radeon_ring_write(rdev, 0); |
81 | |
89 | 82 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
|
90 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
83 | radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
91 | radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
84 | radeon_ring_write(ring, 0); |
Line 92... | Line 85... | ||
92 | radeon_ring_write(rdev, 0); |
85 | } |
93 | } |
86 | |
94 | 87 | /* emits 5dw */ |
|
95 | /* emits 5dw */ |
88 | static void |
96 | static void |
89 | cp_set_surface_sync(struct radeon_device *rdev, |
97 | cp_set_surface_sync(struct radeon_device *rdev, |
90 | u32 sync_type, u32 size, |
Line 98... | Line 91... | ||
98 | u32 sync_type, u32 size, |
91 | u64 mc_addr) |
99 | u64 mc_addr) |
92 | { |
100 | { |
93 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
101 | u32 cp_coher_size; |
94 | u32 cp_coher_size; |
- | 95 | ||
102 | 96 | if (size == 0xffffffff) |
|
103 | if (size == 0xffffffff) |
97 | cp_coher_size = 0xffffffff; |
Line 104... | Line 98... | ||
104 | cp_coher_size = 0xffffffff; |
98 | else |
105 | else |
99 | cp_coher_size = ((size + 255) >> 8); |
Line 106... | Line 100... | ||
106 | cp_coher_size = ((size + 255) >> 8); |
100 | |
107 | 101 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
|
108 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
102 | radeon_ring_write(ring, sync_type); |
109 | radeon_ring_write(rdev, sync_type); |
103 | radeon_ring_write(ring, cp_coher_size); |
110 | radeon_ring_write(rdev, cp_coher_size); |
104 | radeon_ring_write(ring, mc_addr >> 8); |
111 | radeon_ring_write(rdev, mc_addr >> 8); |
105 | radeon_ring_write(ring, 10); /* poll interval */ |
112 | radeon_ring_write(rdev, 10); /* poll interval */ |
106 | } |
113 | } |
107 | |
114 | 108 | /* emits 21dw + 1 surface sync = 26dw */ |
|
115 | /* emits 21dw + 1 surface sync = 26dw */ |
109 | static void |
116 | static void |
110 | set_shaders(struct radeon_device *rdev) |
117 | set_shaders(struct radeon_device *rdev) |
111 | { |
118 | { |
112 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Line 119... | Line 113... | ||
119 | u64 gpu_addr; |
113 | u64 gpu_addr; |
120 | u32 sq_pgm_resources; |
114 | u32 sq_pgm_resources; |
121 | 115 | ||
122 | /* setup shader regs */ |
116 | /* setup shader regs */ |
123 | sq_pgm_resources = (1 << 0); |
117 | sq_pgm_resources = (1 << 0); |
124 | 118 | ||
125 | /* VS */ |
119 | /* VS */ |
126 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
120 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
127 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
121 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
128 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
122 | radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
129 | radeon_ring_write(rdev, gpu_addr >> 8); |
123 | radeon_ring_write(ring, gpu_addr >> 8); |
130 | 124 | ||
131 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
125 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
132 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
126 | radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
133 | radeon_ring_write(rdev, sq_pgm_resources); |
127 | radeon_ring_write(ring, sq_pgm_resources); |
134 | 128 | ||
135 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
129 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
Line 136... | Line 130... | ||
136 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
130 | radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
137 | radeon_ring_write(rdev, 0); |
131 | radeon_ring_write(ring, 0); |
138 | 132 | ||
Line 139... | Line 133... | ||
139 | /* PS */ |
133 | /* PS */ |
140 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
134 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
141 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
135 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
142 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
136 | radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
- | 137 | radeon_ring_write(ring, gpu_addr >> 8); |
|
143 | radeon_ring_write(rdev, gpu_addr >> 8); |
138 | |
Line 144... | Line 139... | ||
144 | 139 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
|
- | 140 | radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
|
145 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
141 | radeon_ring_write(ring, sq_pgm_resources | (1 << 28)); |
146 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
142 | |
147 | radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
143 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
Line 148... | Line 144... | ||
148 | 144 | radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
|
149 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
145 | radeon_ring_write(ring, 2); |
150 | radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
146 | |
151 | radeon_ring_write(rdev, 2); |
147 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
152 | 148 | radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
|
153 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
149 | radeon_ring_write(ring, 0); |
154 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
150 | |
155 | radeon_ring_write(rdev, 0); |
151 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
156 | 152 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
|
Line 157... | Line 153... | ||
157 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
153 | } |
158 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
154 | |
159 | } |
155 | /* emits 9 + 1 sync (5) = 14*/ |
160 | 156 | static void |
|
Line 193... | Line 189... | ||
193 | 189 | ||
194 | /* emits 9 */ |
190 | /* emits 9 */ |
195 | static void |
191 | static void |
196 | set_tex_resource(struct radeon_device *rdev, |
192 | set_tex_resource(struct radeon_device *rdev, |
197 | int format, int w, int h, int pitch, |
193 | int format, int w, int h, int pitch, |
198 | u64 gpu_addr) |
194 | u64 gpu_addr, u32 size) |
- | 195 | { |
|
199 | { |
196 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Line 200... | Line 197... | ||
200 | uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; |
197 | uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; |
201 | 198 | ||
Line 202... | Line 199... | ||
202 | if (h < 1) |
199 | if (h < 1) |
- | 200 | h = 1; |
|
203 | h = 1; |
201 | |
204 | 202 | sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) | |
|
205 | sq_tex_resource_word0 = (1 << 0) | (1 << 3); |
203 | S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); |
206 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | |
204 | sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) | |
207 | ((w - 1) << 19)); |
205 | S_038000_TEX_WIDTH(w - 1); |
208 | 206 | ||
209 | sq_tex_resource_word1 = (format << 26); |
207 | sq_tex_resource_word1 = S_038004_DATA_FORMAT(format); |
210 | sq_tex_resource_word1 |= ((h - 1) << 0); |
208 | sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1); |
211 | 209 | ||
212 | sq_tex_resource_word4 = ((1 << 14) | |
210 | sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) | |
213 | (0 << 16) | |
211 | S_038010_DST_SEL_X(SQ_SEL_X) | |
- | 212 | S_038010_DST_SEL_Y(SQ_SEL_Y) | |
|
- | 213 | S_038010_DST_SEL_Z(SQ_SEL_Z) | |
|
- | 214 | S_038010_DST_SEL_W(SQ_SEL_W); |
|
214 | (1 << 19) | |
215 | |
215 | (2 << 22) | |
216 | cp_set_surface_sync(rdev, |
216 | (3 << 25)); |
217 | PACKET3_TC_ACTION_ENA, size, gpu_addr); |
217 | 218 | ||
218 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
219 | radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7)); |
219 | radeon_ring_write(rdev, 0); |
220 | radeon_ring_write(ring, 0); |
220 | radeon_ring_write(rdev, sq_tex_resource_word0); |
221 | radeon_ring_write(ring, sq_tex_resource_word0); |
221 | radeon_ring_write(rdev, sq_tex_resource_word1); |
222 | radeon_ring_write(ring, sq_tex_resource_word1); |
222 | radeon_ring_write(rdev, gpu_addr >> 8); |
223 | radeon_ring_write(ring, gpu_addr >> 8); |
223 | radeon_ring_write(rdev, gpu_addr >> 8); |
224 | radeon_ring_write(ring, gpu_addr >> 8); |
224 | radeon_ring_write(rdev, sq_tex_resource_word4); |
225 | radeon_ring_write(ring, sq_tex_resource_word4); |
Line 225... | Line 226... | ||
225 | radeon_ring_write(rdev, 0); |
226 | radeon_ring_write(ring, 0); |
226 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); |
227 | radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30); |
227 | } |
228 | } |
228 | 229 | ||
229 | /* emits 12 */ |
230 | /* emits 12 */ |
- | 231 | static void |
|
230 | static void |
232 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
231 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
233 | int x2, int y2) |
232 | int x2, int y2) |
234 | { |
233 | { |
235 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
234 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
236 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
235 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
237 | radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
236 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
238 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); |
237 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
239 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
238 | 240 | ||
239 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
241 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
240 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
242 | radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
241 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
243 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
242 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
244 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
243 | 245 | ||
244 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
246 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
Line 245... | Line 247... | ||
245 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
247 | radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
246 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
248 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
247 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
249 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
248 | } |
250 | } |
- | 251 | ||
249 | 252 | /* emits 10 */ |
|
250 | /* emits 10 */ |
253 | static void |
251 | static void |
254 | draw_auto(struct radeon_device *rdev) |
Line 252... | Line 255... | ||
252 | draw_auto(struct radeon_device *rdev) |
255 | { |
253 | { |
256 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
254 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
257 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
255 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
258 | radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
256 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
259 | radeon_ring_write(ring, DI_PT_RECTLIST); |
257 | 260 | ||
Line 258... | Line 261... | ||
258 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
261 | radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0)); |
259 | radeon_ring_write(rdev, |
262 | radeon_ring_write(ring, |
Line 260... | Line 263... | ||
260 | #ifdef __BIG_ENDIAN |
263 | #ifdef __BIG_ENDIAN |
261 | (2 << 2) | |
264 | (2 << 2) | |
262 | #endif |
265 | #endif |
Line 263... | Line 266... | ||
263 | DI_INDEX_SIZE_16_BIT); |
266 | DI_INDEX_SIZE_16_BIT); |
Line 264... | Line 267... | ||
264 | 267 | ||
265 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
268 | radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
266 | radeon_ring_write(rdev, 1); |
269 | radeon_ring_write(ring, 1); |
267 | 270 | ||
- | 271 | radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
|
268 | radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
272 | radeon_ring_write(ring, 3); |
269 | radeon_ring_write(rdev, 3); |
273 | radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX); |
270 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
274 | |
271 | 275 | } |
|
272 | } |
276 | |
Line 428... | Line 432... | ||
428 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
432 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
Line 429... | Line 433... | ||
429 | 433 | ||
430 | /* emit an IB pointing at default state */ |
434 | /* emit an IB pointing at default state */ |
431 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
435 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
432 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
436 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
433 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
437 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
434 | radeon_ring_write(rdev, |
438 | radeon_ring_write(ring, |
435 | #ifdef __BIG_ENDIAN |
439 | #ifdef __BIG_ENDIAN |
436 | (2 << 0) | |
440 | (2 << 0) | |
437 | #endif |
441 | #endif |
438 | (gpu_addr & 0xFFFFFFFC)); |
442 | (gpu_addr & 0xFFFFFFFC)); |
439 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
443 | radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); |
Line 440... | Line 444... | ||
440 | radeon_ring_write(rdev, dwords); |
444 | radeon_ring_write(ring, dwords); |
441 | 445 | ||
442 | /* SQ config */ |
446 | /* SQ config */ |
443 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
447 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
444 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
448 | radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
445 | radeon_ring_write(rdev, sq_config); |
449 | radeon_ring_write(ring, sq_config); |
446 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
450 | radeon_ring_write(ring, sq_gpr_resource_mgmt_1); |
447 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
451 | radeon_ring_write(ring, sq_gpr_resource_mgmt_2); |
448 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
452 | radeon_ring_write(ring, sq_thread_resource_mgmt); |
449 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
- | |
450 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
- | |
451 | } |
- | |
452 | - | ||
453 | static inline uint32_t i2f(uint32_t input) |
- | |
454 | { |
- | |
455 | u32 result, i, exponent, fraction; |
- | |
456 | - | ||
457 | if ((input & 0x3fff) == 0) |
- | |
458 | result = 0; /* 0 is a special case */ |
- | |
459 | else { |
- | |
460 | exponent = 140; /* exponent biased by 127; */ |
- | |
461 | fraction = (input & 0x3fff) << 10; /* cheat and only |
- | |
462 | handle numbers below 2^^15 */ |
- | |
463 | for (i = 0; i < 14; i++) { |
- | |
464 | if (fraction & 0x800000) |
- | |
465 | break; |
- | |
466 | else { |
- | |
467 | fraction = fraction << 1; /* keep |
- | |
468 | shifting left until top bit = 1 */ |
- | |
469 | exponent = exponent - 1; |
- | |
470 | } |
- | |
471 | } |
- | |
472 | result = exponent << 23 | (fraction & 0x7fffff); /* mask |
- | |
473 | off top bit; assumed 1 */ |
- | |
474 | } |
453 | radeon_ring_write(ring, sq_stack_resource_mgmt_1); |
Line 475... | Line 454... | ||
475 | return result; |
454 | radeon_ring_write(ring, sq_stack_resource_mgmt_2); |
476 | } |
455 | } |
477 | 456 | ||
478 | int r600_blit_init(struct radeon_device *rdev) |
457 | int r600_blit_init(struct radeon_device *rdev) |
479 | { |
458 | { |
480 | u32 obj_size; |
459 | u32 obj_size; |
481 | int i, r, dwords; |
460 | int i, r, dwords; |
Line -... | Line 461... | ||
- | 461 | void *ptr; |
|
- | 462 | u32 packet2s[16]; |
|
- | 463 | int num_packet2s = 0; |
|
- | 464 | ||
- | 465 | rdev->r600_blit.primitives.set_render_target = set_render_target; |
|
- | 466 | rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync; |
|
- | 467 | rdev->r600_blit.primitives.set_shaders = set_shaders; |
|
- | 468 | rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource; |
|
- | 469 | rdev->r600_blit.primitives.set_tex_resource = set_tex_resource; |
|
- | 470 | rdev->r600_blit.primitives.set_scissors = set_scissors; |
|
- | 471 | rdev->r600_blit.primitives.draw_auto = draw_auto; |
|
- | 472 | rdev->r600_blit.primitives.set_default_state = set_default_state; |
|
- | 473 | ||
- | 474 | rdev->r600_blit.ring_size_common = 8; /* sync semaphore */ |
|
- | 475 | rdev->r600_blit.ring_size_common += 40; /* shaders + def state */ |
|
482 | void *ptr; |
476 | rdev->r600_blit.ring_size_common += 5; /* done copy */ |
- | 477 | rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */ |
|
483 | u32 packet2s[16]; |
478 | |
- | 479 | rdev->r600_blit.ring_size_per_loop = 76; |
|
484 | int num_packet2s = 0; |
480 | /* set_render_target emits 2 extra dwords on rv6xx */ |
Line 485... | Line -... | ||
485 | - | ||
486 | /* pin copy shader into vram if already initialized */ |
481 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) |
Line 487... | Line 482... | ||
487 | if (rdev->r600_blit.shader_obj) |
482 | rdev->r600_blit.ring_size_per_loop += 2; |
488 | goto done; |
483 | |
489 | 484 | rdev->r600_blit.max_dim = 8192; |
|
Line 510... | Line 505... | ||
510 | 505 | ||
511 | rdev->r600_blit.ps_offset = obj_size; |
506 | rdev->r600_blit.ps_offset = obj_size; |
512 | obj_size += r6xx_ps_size * 4; |
507 | obj_size += r6xx_ps_size * 4; |
Line -... | Line 508... | ||
- | 508 | obj_size = ALIGN(obj_size, 256); |
|
- | 509 | ||
513 | obj_size = ALIGN(obj_size, 256); |
510 | /* pin copy shader into vram if not already initialized */ |
- | 511 | if (rdev->r600_blit.shader_obj == NULL) { |
|
514 | 512 | r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, |
|
515 | r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
513 | RADEON_GEM_DOMAIN_VRAM, |
516 | &rdev->r600_blit.shader_obj); |
514 | NULL, &rdev->r600_blit.shader_obj); |
517 | if (r) { |
515 | if (r) { |
518 | DRM_ERROR("r600 failed to allocate shader\n"); |
516 | DRM_ERROR("r600 failed to allocate shader\n"); |
Line -... | Line 517... | ||
- | 517 | return r; |
|
- | 518 | } |
|
- | 519 | ||
- | 520 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
|
- | 521 | if (unlikely(r != 0)) |
|
- | 522 | return r; |
|
- | 523 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
|
- | 524 | &rdev->r600_blit.shader_gpu_addr); |
|
- | 525 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
|
- | 526 | if (r) { |
|
- | 527 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
|
- | 528 | return r; |
|
519 | return r; |
529 | } |
520 | } |
530 | } |
521 | 531 | ||
Line 522... | Line 532... | ||
522 | DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", |
532 | DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", |
Line 545... | Line 555... | ||
545 | for (i = 0; i < r6xx_ps_size; i++) |
555 | for (i = 0; i < r6xx_ps_size; i++) |
546 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]); |
556 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]); |
547 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
557 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
548 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
558 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
Line 549... | Line -... | ||
549 | - | ||
550 | done: |
- | |
551 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
- | |
552 | if (unlikely(r != 0)) |
- | |
553 | return r; |
- | |
554 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
- | |
555 | &rdev->r600_blit.shader_gpu_addr); |
- | |
556 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
- | |
557 | if (r) { |
- | |
558 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
- | |
559 | return r; |
- | |
560 | } |
559 | |
561 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
- | |
562 | - | ||
563 | 560 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
|
564 | return 0; |
561 | return 0; |
Line 565... | Line 562... | ||
565 | } |
562 | } |
566 | 563 | ||
Line 580... | Line 577... | ||
580 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
577 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
581 | } |
578 | } |
582 | radeon_bo_unref(&rdev->r600_blit.shader_obj); |
579 | radeon_bo_unref(&rdev->r600_blit.shader_obj); |
583 | } |
580 | } |
Line 584... | Line 581... | ||
584 | 581 | ||
- | 582 | static unsigned r600_blit_create_rect(unsigned num_gpu_pages, |
|
585 | static int r600_vb_ib_get(struct radeon_device *rdev) |
583 | int *width, int *height, int max_dim) |
- | 584 | { |
|
- | 585 | unsigned max_pages; |
|
586 | { |
586 | unsigned pages = num_gpu_pages; |
- | 587 | int w, h; |
|
- | 588 | ||
587 | int r; |
589 | if (num_gpu_pages == 0) { |
- | 590 | /* not supposed to be called with no pages, but just in case */ |
|
- | 591 | h = 0; |
|
- | 592 | w = 0; |
|
- | 593 | pages = 0; |
|
588 | r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); |
594 | WARN_ON(1); |
- | 595 | } else { |
|
- | 596 | int rect_order = 2; |
|
589 | if (r) { |
597 | h = RECT_UNIT_H; |
- | 598 | while (num_gpu_pages / rect_order) { |
|
- | 599 | h *= 2; |
|
- | 600 | rect_order *= 4; |
|
- | 601 | if (h >= max_dim) { |
|
590 | DRM_ERROR("failed to get IB for vertex buffer\n"); |
602 | h = max_dim; |
591 | return r; |
603 | break; |
592 | } |
604 | } |
- | 605 | } |
|
- | 606 | max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H); |
|
- | 607 | if (pages > max_pages) |
|
593 | 608 | pages = max_pages; |
|
594 | rdev->r600_blit.vb_total = 64*1024; |
609 | w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h; |
- | 610 | w = (w / RECT_UNIT_W) * RECT_UNIT_W; |
|
595 | rdev->r600_blit.vb_used = 0; |
611 | pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H); |
596 | return 0; |
612 | BUG_ON(pages == 0); |
Line -... | Line 613... | ||
- | 613 | } |
|
597 | } |
614 | |
598 | 615 | ||
599 | static void r600_vb_ib_put(struct radeon_device *rdev) |
616 | DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages); |
- | 617 | ||
- | 618 | /* return width and height only of the caller wants it */ |
|
- | 619 | if (height) |
|
- | 620 | *height = h; |
|
- | 621 | if (width) |
|
600 | { |
622 | *width = w; |
601 | radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); |
623 | |
Line -... | Line 624... | ||
- | 624 | return pages; |
|
602 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
625 | } |
- | 626 | ||
- | 627 | ||
603 | } |
628 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
- | 629 | struct radeon_fence **fence, struct radeon_sa_bo **vb, |
|
604 | 630 | struct radeon_semaphore **sem) |
|
605 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) |
631 | { |
606 | { |
632 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
607 | int r; |
633 | int r; |
- | 634 | int ring_size; |
|
- | 635 | int num_loops = 0; |
|
- | 636 | int dwords_per_loop = rdev->r600_blit.ring_size_per_loop; |
|
- | 637 | ||
- | 638 | /* num loops */ |
|
608 | int ring_size, line_size; |
639 | while (num_gpu_pages) { |
- | 640 | num_gpu_pages -= |
|
- | 641 | r600_blit_create_rect(num_gpu_pages, NULL, NULL, |
|
Line -... | Line 642... | ||
- | 642 | rdev->r600_blit.max_dim); |
|
609 | int max_size; |
643 | num_loops++; |
- | 644 | } |
|
610 | /* loops of emits 64 + fence emit possible */ |
645 | |
611 | int dwords_per_loop = 76, num_loops; |
646 | /* 48 bytes for vertex per loop */ |
- | 647 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb, |
|
Line 612... | Line -... | ||
612 | - | ||
613 | r = r600_vb_ib_get(rdev); |
- | |
614 | if (r) |
- | |
615 | return r; |
- | |
616 | 648 | (num_loops*48)+256, 256, true); |
|
617 | /* set_render_target emits 2 extra dwords on rv6xx */ |
649 | if (r) { |
618 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) |
650 | return r; |
619 | dwords_per_loop += 2; |
- | |
620 | 651 | } |
|
621 | /* 8 bpp vs 32 bpp for xfer unit */ |
652 | |
622 | if (size_bytes & 3) |
- | |
Line 623... | Line -... | ||
623 | line_size = 8192; |
- | |
624 | else |
- | |
625 | line_size = 8192*4; |
- | |
626 | - | ||
627 | max_size = 8192 * line_size; |
653 | r = radeon_semaphore_create(rdev, sem); |
628 | 654 | if (r) { |
|
629 | /* major loops cover the max size transfer */ |
- | |
630 | num_loops = ((size_bytes + max_size) / max_size); |
- | |
631 | /* minor loops cover the extra non aligned bits */ |
- | |
632 | num_loops += ((size_bytes % line_size) ? 1 : 0); |
- | |
633 | /* calculate number of loops correctly */ |
655 | radeon_sa_bo_free(rdev, vb, NULL); |
634 | ring_size = num_loops * dwords_per_loop; |
656 | return r; |
635 | /* set default + shaders */ |
657 | } |
- | 658 | ||
- | 659 | /* calculate number of loops correctly */ |
|
636 | ring_size += 40; /* shaders + def state */ |
660 | ring_size = num_loops * dwords_per_loop; |
- | 661 | ring_size += rdev->r600_blit.ring_size_common; |
|
Line -... | Line 662... | ||
- | 662 | r = radeon_ring_lock(rdev, ring, ring_size); |
|
- | 663 | if (r) { |
|
- | 664 | radeon_sa_bo_free(rdev, vb, NULL); |
|
- | 665 | radeon_semaphore_free(rdev, sem, NULL); |
|
- | 666 | return r; |
|
637 | ring_size += 10; /* fence emit for VB IB */ |
667 | } |
- | 668 | ||
- | 669 | if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) { |
|
- | 670 | radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring, |
|
638 | ring_size += 5; /* done copy */ |
671 | RADEON_RING_TYPE_GFX_INDEX); |
639 | ring_size += 10; /* fence emit for done copy */ |
672 | radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX); |
640 | r = radeon_ring_lock(rdev, ring_size); |
673 | } else { |
Line 641... | Line 674... | ||
641 | if (r) |
674 | radeon_semaphore_free(rdev, sem, NULL); |
- | 675 | } |
|
642 | return r; |
676 | |
- | 677 | rdev->r600_blit.primitives.set_default_state(rdev); |
|
643 | 678 | rdev->r600_blit.primitives.set_shaders(rdev); |
|
Line 644... | Line 679... | ||
644 | set_default_state(rdev); /* 14 */ |
679 | return 0; |
645 | set_shaders(rdev); /* 26 */ |
- | |
646 | return 0; |
- | |
647 | } |
680 | } |
648 | 681 | ||
- | 682 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
|
- | 683 | struct radeon_sa_bo *vb, struct radeon_semaphore *sem) |
|
Line 649... | Line 684... | ||
649 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) |
684 | { |
- | 685 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
|
- | 686 | int r; |
|
650 | { |
687 | |
Line 651... | Line 688... | ||
651 | int r; |
688 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
652 | 689 | if (r) { |
|
653 | if (rdev->r600_blit.vb_ib) |
690 | radeon_ring_unlock_undo(rdev, ring); |
- | 691 | return; |
|
654 | r600_vb_ib_put(rdev); |
692 | } |
655 | - | ||
656 | if (fence) |
693 | |
657 | r = radeon_fence_emit(rdev, fence); |
- | |
658 | - | ||
659 | radeon_ring_unlock_commit(rdev); |
- | |
660 | } |
- | |
661 | - | ||
662 | void r600_kms_blit_copy(struct radeon_device *rdev, |
- | |
663 | u64 src_gpu_addr, u64 dst_gpu_addr, |
- | |
664 | int size_bytes) |
- | |
665 | { |
- | |
666 | int max_bytes; |
- | |
667 | u64 vb_gpu_addr; |
- | |
668 | u32 *vb; |
- | |
669 | - | ||
670 | DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, |
- | |
671 | size_bytes, rdev->r600_blit.vb_used); |
- | |
672 | vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
- | |
673 | if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { |
- | |
674 | max_bytes = 8192; |
- | |
675 | - | ||
676 | while (size_bytes) { |
- | |
677 | int cur_size = size_bytes; |
- | |
678 | int src_x = src_gpu_addr & 255; |
- | |
679 | int dst_x = dst_gpu_addr & 255; |
- | |
680 | int h = 1; |
- | |
681 | src_gpu_addr = src_gpu_addr & ~255ULL; |
- | |
682 | dst_gpu_addr = dst_gpu_addr & ~255ULL; |
- | |
683 | - | ||
684 | if (!src_x && !dst_x) { |
- | |
685 | h = (cur_size / max_bytes); |
- | |
686 | if (h > 8192) |
- | |
687 | h = 8192; |
- | |
688 | if (h == 0) |
- | |
689 | h = 1; |
- | |
690 | else |
- | |
691 | cur_size = max_bytes; |
- | |
692 | } else { |
- | |
693 | if (cur_size > max_bytes) |
- | |
694 | cur_size = max_bytes; |
- | |
695 | if (cur_size > (max_bytes - dst_x)) |
- | |
696 | cur_size = (max_bytes - dst_x); |
- | |
697 | if (cur_size > (max_bytes - src_x)) |
- | |
698 | cur_size = (max_bytes - src_x); |
- | |
699 | } |
- | |
700 | - | ||
701 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
- | |
702 | // WARN_ON(1); |
- | |
703 | } |
- | |
704 | - | ||
705 | vb[0] = i2f(dst_x); |
- | |
706 | vb[1] = 0; |
- | |
707 | vb[2] = i2f(src_x); |
- | |
708 | vb[3] = 0; |
- | |
709 | - | ||
710 | vb[4] = i2f(dst_x); |
- | |
711 | vb[5] = i2f(h); |
- | |
712 | vb[6] = i2f(src_x); |
694 | radeon_ring_unlock_commit(rdev, ring); |
713 | vb[7] = i2f(h); |
- | |
714 | - | ||
715 | vb[8] = i2f(dst_x + cur_size); |
- | |
716 | vb[9] = i2f(h); |
- | |
Line -... | Line 695... | ||
- | 695 | radeon_sa_bo_free(rdev, &vb, *fence); |
|
- | 696 | radeon_semaphore_free(rdev, &sem, *fence); |
|
- | 697 | } |
|
- | 698 | ||
- | 699 | void r600_kms_blit_copy(struct radeon_device *rdev, |
|
- | 700 | u64 src_gpu_addr, u64 dst_gpu_addr, |
|
717 | vb[10] = i2f(src_x + cur_size); |
701 | unsigned num_gpu_pages, |
- | 702 | struct radeon_sa_bo *vb) |
|
718 | vb[11] = i2f(h); |
703 | { |
719 | 704 | u64 vb_gpu_addr; |
|
720 | /* src 9 */ |
705 | u32 *vb_cpu_addr; |
721 | set_tex_resource(rdev, FMT_8, |
706 | |
722 | src_x + cur_size, h, src_x + cur_size, |
707 | DRM_DEBUG("emitting copy %16llx %16llx %d\n", |
723 | src_gpu_addr); |
708 | src_gpu_addr, dst_gpu_addr, num_gpu_pages); |
724 | 709 | vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb); |
|
- | 710 | vb_gpu_addr = radeon_sa_bo_gpu_addr(vb); |
|
725 | /* 5 */ |
711 | |
726 | cp_set_surface_sync(rdev, |
712 | while (num_gpu_pages) { |
727 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
713 | int w, h; |
728 | 714 | unsigned size_in_bytes; |
|
729 | /* dst 23 */ |
715 | unsigned pages_per_loop = |
- | 716 | r600_blit_create_rect(num_gpu_pages, &w, &h, |
|
730 | set_render_target(rdev, COLOR_8, |
717 | rdev->r600_blit.max_dim); |
- | 718 | ||
- | 719 | size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE; |
|
- | 720 | DRM_DEBUG("rectangle w=%d h=%d\n", w, h); |
|
- | 721 | ||
- | 722 | vb_cpu_addr[0] = 0; |
|
- | 723 | vb_cpu_addr[1] = 0; |
|
731 | dst_x + cur_size, h, |
724 | vb_cpu_addr[2] = 0; |
- | 725 | vb_cpu_addr[3] = 0; |
|
- | 726 | ||
- | 727 | vb_cpu_addr[4] = 0; |
|
732 | dst_gpu_addr); |
728 | vb_cpu_addr[5] = int2float(h); |
- | 729 | vb_cpu_addr[6] = 0; |
|
- | 730 | vb_cpu_addr[7] = int2float(h); |
|
- | 731 | ||
733 | 732 | vb_cpu_addr[8] = int2float(w); |
|
734 | /* scissors 12 */ |
733 | vb_cpu_addr[9] = int2float(h); |
735 | set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); |
734 | vb_cpu_addr[10] = int2float(w); |
736 | - | ||
737 | /* 14 */ |
- | |
738 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
- | |
Line 739... | Line 735... | ||
739 | set_vtx_resource(rdev, vb_gpu_addr); |
735 | vb_cpu_addr[11] = int2float(h); |
740 | 736 | ||
741 | /* draw 10 */ |
- | |
742 | draw_auto(rdev); |
- | |
743 | - | ||
744 | /* 5 */ |
- | |
745 | cp_set_surface_sync(rdev, |
- | |
746 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
- | |
747 | cur_size * h, dst_gpu_addr); |
- | |
748 | - | ||
749 | vb += 12; |
- | |
750 | rdev->r600_blit.vb_used += 12 * 4; |
- | |
751 | - | ||
752 | src_gpu_addr += cur_size * h; |
- | |
753 | dst_gpu_addr += cur_size * h; |
- | |
754 | size_bytes -= cur_size * h; |
- | |
755 | } |
- | |
756 | } else { |
- | |
757 | max_bytes = 8192 * 4; |
- | |
758 | - | ||
759 | while (size_bytes) { |
- | |
760 | int cur_size = size_bytes; |
- | |
761 | int src_x = (src_gpu_addr & 255); |
- | |
762 | int dst_x = (dst_gpu_addr & 255); |
- | |
763 | int h = 1; |
- | |
764 | src_gpu_addr = src_gpu_addr & ~255ULL; |
- | |
765 | dst_gpu_addr = dst_gpu_addr & ~255ULL; |
- | |
766 | - | ||
767 | if (!src_x && !dst_x) { |
- | |
768 | h = (cur_size / max_bytes); |
- | |
769 | if (h > 8192) |
- | |
770 | h = 8192; |
- | |
771 | if (h == 0) |
- | |
772 | h = 1; |
- | |
773 | else |
- | |
774 | cur_size = max_bytes; |
- | |
775 | } else { |
- | |
776 | if (cur_size > max_bytes) |
- | |
777 | cur_size = max_bytes; |
- | |
778 | if (cur_size > (max_bytes - dst_x)) |
- | |
779 | cur_size = (max_bytes - dst_x); |
- | |
780 | if (cur_size > (max_bytes - src_x)) |
- | |
781 | cur_size = (max_bytes - src_x); |
- | |
782 | } |
- | |
783 | - | ||
784 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
- | |
785 | // WARN_ON(1); |
- | |
786 | } |
- | |
787 | - | ||
788 | vb[0] = i2f(dst_x / 4); |
- | |
789 | vb[1] = 0; |
- | |
790 | vb[2] = i2f(src_x / 4); |
- | |
791 | vb[3] = 0; |
- | |
792 | - | ||
793 | vb[4] = i2f(dst_x / 4); |
- | |
794 | vb[5] = i2f(h); |
- | |
795 | vb[6] = i2f(src_x / 4); |
- | |
796 | vb[7] = i2f(h); |
- | |
797 | - | ||
798 | vb[8] = i2f((dst_x + cur_size) / 4); |
- | |
799 | vb[9] = i2f(h); |
- | |
800 | vb[10] = i2f((src_x + cur_size) / 4); |
- | |
801 | vb[11] = i2f(h); |
- | |
802 | - | ||
803 | /* src 9 */ |
- | |
804 | set_tex_resource(rdev, FMT_8_8_8_8, |
- | |
805 | (src_x + cur_size) / 4, |
- | |
806 | h, (src_x + cur_size) / 4, |
- | |
807 | src_gpu_addr); |
- | |
808 | /* 5 */ |
- | |
809 | cp_set_surface_sync(rdev, |
- | |
810 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
- | |
811 | - | ||
812 | /* dst 23 */ |
- | |
813 | set_render_target(rdev, COLOR_8_8_8_8, |
- | |
814 | (dst_x + cur_size) / 4, h, |
- | |
815 | dst_gpu_addr); |
- | |
816 | - | ||
817 | /* scissors 12 */ |
- | |
818 | set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); |
- | |
819 | - | ||
820 | /* Vertex buffer setup 14 */ |
- | |
821 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
- | |
822 | set_vtx_resource(rdev, vb_gpu_addr); |
- | |
823 | 737 | rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8, |
|
824 | /* draw 10 */ |
738 | w, h, w, src_gpu_addr, size_in_bytes); |
825 | draw_auto(rdev); |
739 | rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8, |
826 | - | ||
827 | /* 5 */ |
740 | w, h, dst_gpu_addr); |
828 | cp_set_surface_sync(rdev, |
741 | rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h); |
829 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
- | |
830 | cur_size * h, dst_gpu_addr); |
- | |
831 | - |