WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r600_blit_kms.c


/*
 * Copyright 2009 Advanced Micro Devices, Inc.
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 */
 
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon.h"
 
#include "r600d.h"
#include "r600_blit_shaders.h"
 
#define DI_PT_RECTLIST        0x11
#define DI_INDEX_SIZE_16_BIT  0x0
#define DI_SRC_SEL_AUTO_INDEX 0x2
 
#define FMT_8                 0x1
#define FMT_5_6_5             0x8
#define FMT_8_8_8_8           0x1a
#define COLOR_8               0x1
#define COLOR_5_6_5           0x8
#define COLOR_8_8_8_8         0x1a
 
/* emits 21 on rv770+, 23 on r600 */
static void
set_render_target(struct radeon_device *rdev, int format,
		  int w, int h, u64 gpu_addr)
{
	u32 cb_color_info;
	int pitch, slice;
 
	h = ALIGN(h, 8);
	if (h < 8)
		h = 8;
 
	cb_color_info = ((format << 2) | (1 << 27) | (1 << 8));
	pitch = (w / 8) - 1;
	slice = ((w * h) / 64) - 1;
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, gpu_addr >> 8);
 
	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
		radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
		radeon_ring_write(rdev, 2 << 0);
	}
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, 0);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, cb_color_info);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, 0);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, 0);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, 0);
}
 
/* emits 5dw */
static void
cp_set_surface_sync(struct radeon_device *rdev,
		    u32 sync_type, u32 size,
		    u64 mc_addr)
{
	u32 cp_coher_size;
 
	if (size == 0xffffffff)
		cp_coher_size = 0xffffffff;
	else
		cp_coher_size = ((size + 255) >> 8);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
	radeon_ring_write(rdev, sync_type);
	radeon_ring_write(rdev, cp_coher_size);
	radeon_ring_write(rdev, mc_addr >> 8);
	radeon_ring_write(rdev, 10); /* poll interval */
}
 
/* emits 21dw + 1 surface sync = 26dw */
static void
set_shaders(struct radeon_device *rdev)
{
	u64 gpu_addr;
	u32 sq_pgm_resources;
 
	/* setup shader regs */
	sq_pgm_resources = (1 << 0);
 
	/* VS */
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, gpu_addr >> 8);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, sq_pgm_resources);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, 0);
 
	/* PS */
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, gpu_addr >> 8);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, 2);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, 0);
 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
}
 
/* emits 9 + 1 sync (5) = 14*/
static void
set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
{
	u32 sq_vtx_constant_word2;
 
	sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
#ifdef __BIG_ENDIAN
	sq_vtx_constant_word2 |= (2 << 30);
#endif
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
	radeon_ring_write(rdev, 0x460);
	radeon_ring_write(rdev, gpu_addr & 0xffffffff);
	radeon_ring_write(rdev, 48 - 1);
	radeon_ring_write(rdev, sq_vtx_constant_word2);
	radeon_ring_write(rdev, 1 << 0);
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 
	if ((rdev->family == CHIP_RV610) ||
	    (rdev->family == CHIP_RV620) ||
	    (rdev->family == CHIP_RS780) ||
	    (rdev->family == CHIP_RS880) ||
	    (rdev->family == CHIP_RV710))
		cp_set_surface_sync(rdev,
				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);
	else
		cp_set_surface_sync(rdev,
				    PACKET3_VC_ACTION_ENA, 48, gpu_addr);
}
 
/* emits 9 */
static void
set_tex_resource(struct radeon_device *rdev,
		 int format, int w, int h, int pitch,
		 u64 gpu_addr)
{
	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 
	if (h < 1)
		h = 1;
 
	sq_tex_resource_word0 = (1 << 0) | (1 << 3);
	sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
				  ((w - 1) << 19));
 
	sq_tex_resource_word1 = (format << 26);
	sq_tex_resource_word1 |= ((h - 1) << 0);
 
	sq_tex_resource_word4 = ((1 << 14) |
				 (0 << 16) |
				 (1 << 19) |
				 (2 << 22) |
				 (3 << 25));
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, sq_tex_resource_word0);
	radeon_ring_write(rdev, sq_tex_resource_word1);
	radeon_ring_write(rdev, gpu_addr >> 8);
	radeon_ring_write(rdev, gpu_addr >> 8);
	radeon_ring_write(rdev, sq_tex_resource_word4);
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
}
 
/* emits 12 */
static void
set_scissors(struct radeon_device *rdev, int x1, int y1,
	     int x2, int y2)
{
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
	radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
	radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
	radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
}
 
/* emits 10 */
static void
draw_auto(struct radeon_device *rdev)
{
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
	radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, DI_PT_RECTLIST);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
	radeon_ring_write(rdev,
#ifdef __BIG_ENDIAN
			  (2 << 2) |
#endif
			  DI_INDEX_SIZE_16_BIT);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
	radeon_ring_write(rdev, 1);
 
	radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
	radeon_ring_write(rdev, 3);
	radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 
}
 
/* emits 14 */
static void
set_default_state(struct radeon_device *rdev)
{
	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
	u64 gpu_addr;
	int dwords;
 
	switch (rdev->family) {
	case CHIP_R600:
		num_ps_gprs = 192;
		num_vs_gprs = 56;
		num_temp_gprs = 4;
		num_gs_gprs = 0;
		num_es_gprs = 0;
		num_ps_threads = 136;
		num_vs_threads = 48;
		num_gs_threads = 4;
		num_es_threads = 4;
		num_ps_stack_entries = 128;
		num_vs_stack_entries = 128;
		num_gs_stack_entries = 0;
		num_es_stack_entries = 0;
		break;
	case CHIP_RV630:
	case CHIP_RV635:
		num_ps_gprs = 84;
		num_vs_gprs = 36;
		num_temp_gprs = 4;
		num_gs_gprs = 0;
		num_es_gprs = 0;
		num_ps_threads = 144;
		num_vs_threads = 40;
		num_gs_threads = 4;
		num_es_threads = 4;
		num_ps_stack_entries = 40;
		num_vs_stack_entries = 40;
		num_gs_stack_entries = 32;
		num_es_stack_entries = 16;
		break;
	case CHIP_RV610:
	case CHIP_RV620:
	case CHIP_RS780:
	case CHIP_RS880:
	default:
		num_ps_gprs = 84;
		num_vs_gprs = 36;
		num_temp_gprs = 4;
		num_gs_gprs = 0;
		num_es_gprs = 0;
		num_ps_threads = 136;
		num_vs_threads = 48;
		num_gs_threads = 4;
		num_es_threads = 4;
		num_ps_stack_entries = 40;
		num_vs_stack_entries = 40;
		num_gs_stack_entries = 32;
		num_es_stack_entries = 16;
		break;
	case CHIP_RV670:
		num_ps_gprs = 144;
		num_vs_gprs = 40;
		num_temp_gprs = 4;
		num_gs_gprs = 0;
		num_es_gprs = 0;
		num_ps_threads = 136;
		num_vs_threads = 48;
		num_gs_threads = 4;
		num_es_threads = 4;
		num_ps_stack_entries = 40;
		num_vs_stack_entries = 40;
		num_gs_stack_entries = 32;
		num_es_stack_entries = 16;
		break;
	case CHIP_RV770:
		num_ps_gprs = 192;
		num_vs_gprs = 56;
		num_temp_gprs = 4;
		num_gs_gprs = 0;
		num_es_gprs = 0;
		num_ps_threads = 188;
		num_vs_threads = 60;
		num_gs_threads = 0;
		num_es_threads = 0;
		num_ps_stack_entries = 256;
		num_vs_stack_entries = 256;
		num_gs_stack_entries = 0;
		num_es_stack_entries = 0;
		break;
	case CHIP_RV730:
	case CHIP_RV740:
		num_ps_gprs = 84;
		num_vs_gprs = 36;
		num_temp_gprs = 4;
		num_gs_gprs = 0;
		num_es_gprs = 0;
		num_ps_threads = 188;
		num_vs_threads = 60;
		num_gs_threads = 0;
		num_es_threads = 0;
		num_ps_stack_entries = 128;
		num_vs_stack_entries = 128;
		num_gs_stack_entries = 0;
		num_es_stack_entries = 0;
		break;
	case CHIP_RV710:
		num_ps_gprs = 192;
		num_vs_gprs = 56;
		num_temp_gprs = 4;
		num_gs_gprs = 0;
		num_es_gprs = 0;
		num_ps_threads = 144;
		num_vs_threads = 48;
		num_gs_threads = 0;
		num_es_threads = 0;
		num_ps_stack_entries = 128;
		num_vs_stack_entries = 128;
		num_gs_stack_entries = 0;
		num_es_stack_entries = 0;
		break;
	}
 
	if ((rdev->family == CHIP_RV610) ||
	    (rdev->family == CHIP_RV620) ||
	    (rdev->family == CHIP_RS780) ||
	    (rdev->family == CHIP_RS880) ||
	    (rdev->family == CHIP_RV710))
		sq_config = 0;
	else
		sq_config = VC_ENABLE;
 
	sq_config |= (DX9_CONSTS |
		      ALU_INST_PREFER_VECTOR |
		      PS_PRIO(0) |
		      VS_PRIO(1) |
		      GS_PRIO(2) |
		      ES_PRIO(3));
 
	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
				  NUM_VS_GPRS(num_vs_gprs) |
				  NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
				  NUM_ES_GPRS(num_es_gprs));
	sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
				   NUM_VS_THREADS(num_vs_threads) |
				   NUM_GS_THREADS(num_gs_threads) |
				   NUM_ES_THREADS(num_es_threads));
	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
				    NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
				    NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 
	/* emit an IB pointing at default state */
	dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
	radeon_ring_write(rdev,
#ifdef __BIG_ENDIAN
			  (2 << 0) |
#endif
			  (gpu_addr & 0xFFFFFFFC));
	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
	radeon_ring_write(rdev, dwords);
 
	/* SQ config */
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
	radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
	radeon_ring_write(rdev, sq_config);
	radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
	radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
	radeon_ring_write(rdev, sq_thread_resource_mgmt);
	radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
	radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
}
 
static inline uint32_t i2f(uint32_t input)
{
	u32 result, i, exponent, fraction;
 
	if ((input & 0x3fff) == 0)
		result = 0; /* 0 is a special case */
	else {
		exponent = 140; /* exponent biased by 127; */
		fraction = (input & 0x3fff) << 10; /* cheat and only
						      handle numbers below 2^^15 */
		for (i = 0; i < 14; i++) {
			if (fraction & 0x800000)
				break;
			else {
				fraction = fraction << 1; /* keep
							     shifting left until top bit = 1 */
				exponent = exponent - 1;
			}
		}
		result = exponent << 23 | (fraction & 0x7fffff); /* mask
								    off top bit; assumed 1 */
	}
	return result;
}
 
int r600_blit_init(struct radeon_device *rdev)
{
	u32 obj_size;
	int i, r, dwords;
	void *ptr;
	u32 packet2s[16];
	int num_packet2s = 0;
 
    ENTER();
 
	/* pin copy shader into vram if already initialized */
	if (rdev->r600_blit.shader_obj)
		goto done;
 
	mutex_init(&rdev->r600_blit.mutex);
	rdev->r600_blit.state_offset = 0;
 
	if (rdev->family >= CHIP_RV770)
		rdev->r600_blit.state_len = r7xx_default_size;
	else
		rdev->r600_blit.state_len = r6xx_default_size;
 
	dwords = rdev->r600_blit.state_len;
	while (dwords & 0xf) {
		packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
		dwords++;
	}
 
	obj_size = dwords * 4;
	obj_size = ALIGN(obj_size, 256);
 
	rdev->r600_blit.vs_offset = obj_size;
	obj_size += r6xx_vs_size * 4;
	obj_size = ALIGN(obj_size, 256);
 
	rdev->r600_blit.ps_offset = obj_size;
	obj_size += r6xx_ps_size * 4;
	obj_size = ALIGN(obj_size, 256);
 
	r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
				&rdev->r600_blit.shader_obj);
	if (r) {
		DRM_ERROR("r600 failed to allocate shader\n");
		return r;
	}
 
	DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
		  obj_size,
		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
	if (r) {
		DRM_ERROR("failed to map blit object %d\n", r);
		return r;
	}
	if (rdev->family >= CHIP_RV770)
        memcpy(ptr + rdev->r600_blit.state_offset,
			    r7xx_default_state, rdev->r600_blit.state_len * 4);
	else
        memcpy(ptr + rdev->r600_blit.state_offset,
			    r6xx_default_state, rdev->r600_blit.state_len * 4);
	if (num_packet2s)
        memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
			    packet2s, num_packet2s * 4);
	for (i = 0; i < r6xx_vs_size; i++)
		*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
	for (i = 0; i < r6xx_ps_size; i++)
		*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
	radeon_bo_kunmap(rdev->r600_blit.shader_obj);
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 
done:
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
			  &rdev->r600_blit.shader_gpu_addr);
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
	if (r) {
		dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
		return r;
	}
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 
    LEAVE();
 
	return 0;
}
 
void r600_blit_fini(struct radeon_device *rdev)
{
	int r;
 
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
	if (rdev->r600_blit.shader_obj == NULL)
		return;
	/* If we can't reserve the bo, unref should be enough to destroy
	 * it when it becomes idle.
	 */
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
	if (!r) {
		radeon_bo_unpin(rdev->r600_blit.shader_obj);
		radeon_bo_unreserve(rdev->r600_blit.shader_obj);
	}
	radeon_bo_unref(&rdev->r600_blit.shader_obj);
}
 
static int r600_vb_ib_get(struct radeon_device *rdev)
{
	int r;
	r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
	if (r) {
		DRM_ERROR("failed to get IB for vertex buffer\n");
		return r;
	}
 
	rdev->r600_blit.vb_total = 64*1024;
	rdev->r600_blit.vb_used = 0;
	return 0;
}
 
static void r600_vb_ib_put(struct radeon_device *rdev)
{
	radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
	radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
}
 
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
{
	int r;
	int ring_size, line_size;
	int max_size;
	/* loops of emits 64 + fence emit possible */
	int dwords_per_loop = 76, num_loops;
 
	r = r600_vb_ib_get(rdev);
	if (r)
		return r;
 
	/* set_render_target emits 2 extra dwords on rv6xx */
	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
		dwords_per_loop += 2;
 
	/* 8 bpp vs 32 bpp for xfer unit */
	if (size_bytes & 3)
		line_size = 8192;
	else
		line_size = 8192*4;
 
	max_size = 8192 * line_size;
 
	/* major loops cover the max size transfer */
	num_loops = ((size_bytes + max_size) / max_size);
	/* minor loops cover the extra non aligned bits */
	num_loops += ((size_bytes % line_size) ? 1 : 0);
	/* calculate number of loops correctly */
	ring_size = num_loops * dwords_per_loop;
	/* set default  + shaders */
	ring_size += 40; /* shaders + def state */
	ring_size += 10; /* fence emit for VB IB */
	ring_size += 5; /* done copy */
	ring_size += 10; /* fence emit for done copy */
	r = radeon_ring_lock(rdev, ring_size);
	if (r)
		return r;
 
	set_default_state(rdev); /* 14 */
	set_shaders(rdev); /* 26 */
	return 0;
}
 
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
{
	int r;
 
	if (rdev->r600_blit.vb_ib)
		r600_vb_ib_put(rdev);
 
	if (fence)
		r = radeon_fence_emit(rdev, fence);
 
	radeon_ring_unlock_commit(rdev);
}
 
void r600_kms_blit_copy(struct radeon_device *rdev,
			u64 src_gpu_addr, u64 dst_gpu_addr,
			int size_bytes)
{
	int max_bytes;
	u64 vb_gpu_addr;
	u32 *vb;
 
	DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
		  size_bytes, rdev->r600_blit.vb_used);
	vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
	if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
		max_bytes = 8192;
 
		while (size_bytes) {
			int cur_size = size_bytes;
			int src_x = src_gpu_addr & 255;
			int dst_x = dst_gpu_addr & 255;
			int h = 1;
			src_gpu_addr = src_gpu_addr & ~255ULL;
			dst_gpu_addr = dst_gpu_addr & ~255ULL;
 
			if (!src_x && !dst_x) {
				h = (cur_size / max_bytes);
				if (h > 8192)
					h = 8192;
				if (h == 0)
					h = 1;
				else
					cur_size = max_bytes;
			} else {
				if (cur_size > max_bytes)
					cur_size = max_bytes;
				if (cur_size > (max_bytes - dst_x))
					cur_size = (max_bytes - dst_x);
				if (cur_size > (max_bytes - src_x))
					cur_size = (max_bytes - src_x);
			}
 
			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
             //  WARN_ON(1);
			}
 
			vb[0] = i2f(dst_x);
			vb[1] = 0;
			vb[2] = i2f(src_x);
			vb[3] = 0;
 
			vb[4] = i2f(dst_x);
			vb[5] = i2f(h);
			vb[6] = i2f(src_x);
			vb[7] = i2f(h);
 
			vb[8] = i2f(dst_x + cur_size);
			vb[9] = i2f(h);
			vb[10] = i2f(src_x + cur_size);
			vb[11] = i2f(h);
 
			/* src 9 */
			set_tex_resource(rdev, FMT_8,
					 src_x + cur_size, h, src_x + cur_size,
					 src_gpu_addr);
 
			/* 5 */
			cp_set_surface_sync(rdev,
					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 
			/* dst 23 */
			set_render_target(rdev, COLOR_8,
					  dst_x + cur_size, h,
					  dst_gpu_addr);
 
			/* scissors 12 */
			set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
 
			/* 14 */
			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
			set_vtx_resource(rdev, vb_gpu_addr);
 
			/* draw 10 */
			draw_auto(rdev);
 
			/* 5 */
			cp_set_surface_sync(rdev,
					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
					    cur_size * h, dst_gpu_addr);
 
			vb += 12;
			rdev->r600_blit.vb_used += 12 * 4;
 
			src_gpu_addr += cur_size * h;
			dst_gpu_addr += cur_size * h;
			size_bytes -= cur_size * h;
		}
	} else {
		max_bytes = 8192 * 4;
 
		while (size_bytes) {
			int cur_size = size_bytes;
			int src_x = (src_gpu_addr & 255);
			int dst_x = (dst_gpu_addr & 255);
			int h = 1;
			src_gpu_addr = src_gpu_addr & ~255ULL;
			dst_gpu_addr = dst_gpu_addr & ~255ULL;
 
			if (!src_x && !dst_x) {
				h = (cur_size / max_bytes);
				if (h > 8192)
					h = 8192;
				if (h == 0)
					h = 1;
				else
					cur_size = max_bytes;
			} else {
				if (cur_size > max_bytes)
					cur_size = max_bytes;
				if (cur_size > (max_bytes - dst_x))
					cur_size = (max_bytes - dst_x);
				if (cur_size > (max_bytes - src_x))
					cur_size = (max_bytes - src_x);
			}
 
			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
              // WARN_ON(1);
			}
 
			vb[0] = i2f(dst_x / 4);
			vb[1] = 0;
			vb[2] = i2f(src_x / 4);
			vb[3] = 0;
 
			vb[4] = i2f(dst_x / 4);
			vb[5] = i2f(h);
			vb[6] = i2f(src_x / 4);
			vb[7] = i2f(h);
 
			vb[8] = i2f((dst_x + cur_size) / 4);
			vb[9] = i2f(h);
			vb[10] = i2f((src_x + cur_size) / 4);
			vb[11] = i2f(h);
 
			/* src 9 */
			set_tex_resource(rdev, FMT_8_8_8_8,
					 (src_x + cur_size) / 4,
					 h, (src_x + cur_size) / 4,
					 src_gpu_addr);
			/* 5 */
			cp_set_surface_sync(rdev,
					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 
			/* dst 23 */
			set_render_target(rdev, COLOR_8_8_8_8,
					  (dst_x + cur_size) / 4, h,
					  dst_gpu_addr);
 
			/* scissors 12  */
			set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
 
			/* Vertex buffer setup 14 */
			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
			set_vtx_resource(rdev, vb_gpu_addr);
 
			/* draw 10 */
			draw_auto(rdev);
 
			/* 5 */
			cp_set_surface_sync(rdev,
					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
					    cur_size * h, dst_gpu_addr);
 
			/* 78 ring dwords per loop */
			vb += 12;
			rdev->r600_blit.vb_used += 12 * 4;
 
			src_gpu_addr += cur_size * h;
			dst_gpu_addr += cur_size * h;
			size_bytes -= cur_size * h;
		}
	}
}
 
 
void r600_kms_video_blit(struct radeon_device *rdev,
            u64 src_gpu_addr, int dstx, int dsty, int w, int h, int pitch)
{
    u64 vb_gpu_addr;
    u32 *vb;
 
    DRM_DEBUG("emitting video copy\n");
    vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 
    if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
              // WARN_ON(1);
    }
 
    vb[0] = i2f(dstx);
    vb[1] = i2f(dsty);
    vb[2] = 0;
    vb[3] = 0;
 
    vb[4] = i2f(dstx);
    vb[5] = i2f(dsty+h);
    vb[6] = 0;
    vb[7] = i2f(h);
 
    vb[8] = i2f(dstx + w);
    vb[9] = i2f(dsty + h);
    vb[10] = i2f(w);
    vb[11] = i2f(h);
 
    /* src 9 */
    set_tex_resource(rdev, FMT_8_8_8_8,
                     w, h, pitch/4, src_gpu_addr);
    /* 5 */
    cp_set_surface_sync(rdev,
                        PACKET3_TC_ACTION_ENA, pitch * h, src_gpu_addr);
 
    /* dst 23 */
    set_render_target(rdev, COLOR_8_8_8_8,
                     1024, 768, rdev->mc.vram_start);
 
            /* scissors 12  */
    set_scissors(rdev, 0, 0, 1024, 768);
 
    /* Vertex buffer setup 14 */
    vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
    set_vtx_resource(rdev, vb_gpu_addr);
 
    /* draw 10 */
    draw_auto(rdev);
 
    /* 5 */
    cp_set_surface_sync(rdev,
                PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
                1024*4*768, rdev->mc.vram_start);
 
    /* 78 ring dwords per loop */
    vb += 12;
    rdev->r600_blit.vb_used += 12 * 4;
 
}
 
extern struct radeon_device *main_device;
 
int r600_video_blit(uint64_t src_offset, int  x, int y,
                    int w, int h, int pitch)
{
    int r;
    struct radeon_device *rdev = main_device;
 
    mutex_lock(&rdev->r600_blit.mutex);
    rdev->r600_blit.vb_ib = NULL;
    r = r600_blit_prepare_copy(rdev, h*pitch);
    if (r) {
//       if (rdev->r600_blit.vb_ib)
//           radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
        mutex_unlock(&rdev->r600_blit.mutex);
        return r;
    }
 
 
    r600_kms_video_blit(rdev, src_offset,x,y,w,h,pitch);
    r600_blit_done_copy(rdev, NULL);
    mutex_unlock(&rdev->r600_blit.mutex);
};
 
int r600_create_video(int w, int h, u32_t *outp)
{
    int r;
    struct radeon_device *rdev = main_device;
    struct radeon_bo *sobj = NULL;
    uint64_t saddr;
    void   *uaddr;
 
    size_t size;
    size_t pitch;
 
    pitch = radeon_align_pitch(rdev, w, 32, false) * 4;
 
    size = pitch * h;
    r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
                         RADEON_GEM_DOMAIN_GTT, &sobj);
    if (r) {
        goto fail;
    }
    r = radeon_bo_reserve(sobj, false);
    if (unlikely(r != 0))
        goto fail;
    r = radeon_bo_pin(sobj, RADEON_GEM_DOMAIN_GTT, &saddr);
//   radeon_bo_unreserve(sobj);
    if (r) {
        goto fail;
    }
 
    r = radeon_bo_user_map(sobj, &uaddr);
    if (r) {
        goto fail;
    }
 
    ((uint64_t*)outp)[0] = saddr;
    outp[2] = uaddr;
    outp[3] = pitch;
 
    dbgprintf("Create video surface %x, mapped at %x pitch %d\n",
              (uint32_t)saddr, uaddr, pitch);
    return 0;
 
fail:
    return -1;
};

Rev 2005	Rev 2007
1	/*	1	/*
2	* Copyright 2009 Advanced Micro Devices, Inc.	2	* Copyright 2009 Advanced Micro Devices, Inc.
3	* Copyright 2009 Red Hat Inc.	3	* Copyright 2009 Red Hat Inc.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),	6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation	7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the	9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:	10	* Software is furnished to do so, subject to the following conditions:
11	*	11	*
12	* The above copyright notice and this permission notice (including the next	12	* The above copyright notice and this permission notice (including the next
13	* paragraph) shall be included in all copies or substantial portions of the	13	* paragraph) shall be included in all copies or substantial portions of the
14	* Software.	14	* Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22	* DEALINGS IN THE SOFTWARE.	22	* DEALINGS IN THE SOFTWARE.
23	*	23	*
24	*/	24	*/
25		25
26	#include "drmP.h"	26	#include "drmP.h"
27	#include "drm.h"	27	#include "drm.h"
28	#include "radeon_drm.h"	28	#include "radeon_drm.h"
29	#include "radeon.h"	29	#include "radeon.h"
30		30
31	#include "r600d.h"	31	#include "r600d.h"
32	#include "r600_blit_shaders.h"	32	#include "r600_blit_shaders.h"
33		33
34	#define DI_PT_RECTLIST 0x11	34	#define DI_PT_RECTLIST 0x11
35	#define DI_INDEX_SIZE_16_BIT 0x0	35	#define DI_INDEX_SIZE_16_BIT 0x0
36	#define DI_SRC_SEL_AUTO_INDEX 0x2	36	#define DI_SRC_SEL_AUTO_INDEX 0x2
37		37
38	#define FMT_8 0x1	38	#define FMT_8 0x1
39	#define FMT_5_6_5 0x8	39	#define FMT_5_6_5 0x8
40	#define FMT_8_8_8_8 0x1a	40	#define FMT_8_8_8_8 0x1a
41	#define COLOR_8 0x1	41	#define COLOR_8 0x1
42	#define COLOR_5_6_5 0x8	42	#define COLOR_5_6_5 0x8
43	#define COLOR_8_8_8_8 0x1a	43	#define COLOR_8_8_8_8 0x1a
44		44
45	/* emits 21 on rv770+, 23 on r600 */	45	/* emits 21 on rv770+, 23 on r600 */
46	static void	46	static void
47	set_render_target(struct radeon_device *rdev, int format,	47	set_render_target(struct radeon_device *rdev, int format,
48	int w, int h, u64 gpu_addr)	48	int w, int h, u64 gpu_addr)
49	{	49	{
50	u32 cb_color_info;	50	u32 cb_color_info;
51	int pitch, slice;	51	int pitch, slice;
52		52
53	h = ALIGN(h, 8);	53	h = ALIGN(h, 8);
54	if (h < 8)	54	if (h < 8)
55	h = 8;	55	h = 8;
56		56
57	cb_color_info = ((format << 2) \| (1 << 27) \| (1 << 8));	57	cb_color_info = ((format << 2) \| (1 << 27) \| (1 << 8));
58	pitch = (w / 8) - 1;	58	pitch = (w / 8) - 1;
59	slice = ((w * h) / 64) - 1;	59	slice = ((w * h) / 64) - 1;
60		60
61	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	61	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
62	radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	62	radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
63	radeon_ring_write(rdev, gpu_addr >> 8);	63	radeon_ring_write(rdev, gpu_addr >> 8);
64		64
65	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {	65	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
66	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));	66	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
67	radeon_ring_write(rdev, 2 << 0);	67	radeon_ring_write(rdev, 2 << 0);
68	}	68	}
69		69
70	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	70	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71	radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	71	radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
72	radeon_ring_write(rdev, (pitch << 0) \| (slice << 10));	72	radeon_ring_write(rdev, (pitch << 0) \| (slice << 10));
73		73
74	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	74	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75	radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	75	radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76	radeon_ring_write(rdev, 0);	76	radeon_ring_write(rdev, 0);
77		77
78	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	78	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79	radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	79	radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80	radeon_ring_write(rdev, cb_color_info);	80	radeon_ring_write(rdev, cb_color_info);
81		81
82	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	82	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83	radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	83	radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84	radeon_ring_write(rdev, 0);	84	radeon_ring_write(rdev, 0);
85		85
86	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	86	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
87	radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	87	radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
88	radeon_ring_write(rdev, 0);	88	radeon_ring_write(rdev, 0);
89		89
90	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	90	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
91	radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	91	radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
92	radeon_ring_write(rdev, 0);	92	radeon_ring_write(rdev, 0);
93	}	93	}
94		94
95	/* emits 5dw */	95	/* emits 5dw */
96	static void	96	static void
97	cp_set_surface_sync(struct radeon_device *rdev,	97	cp_set_surface_sync(struct radeon_device *rdev,
98	u32 sync_type, u32 size,	98	u32 sync_type, u32 size,
99	u64 mc_addr)	99	u64 mc_addr)
100	{	100	{
101	u32 cp_coher_size;	101	u32 cp_coher_size;
102		102
103	if (size == 0xffffffff)	103	if (size == 0xffffffff)
104	cp_coher_size = 0xffffffff;	104	cp_coher_size = 0xffffffff;
105	else	105	else
106	cp_coher_size = ((size + 255) >> 8);	106	cp_coher_size = ((size + 255) >> 8);
107		107
108	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));	108	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
109	radeon_ring_write(rdev, sync_type);	109	radeon_ring_write(rdev, sync_type);
110	radeon_ring_write(rdev, cp_coher_size);	110	radeon_ring_write(rdev, cp_coher_size);
111	radeon_ring_write(rdev, mc_addr >> 8);	111	radeon_ring_write(rdev, mc_addr >> 8);
112	radeon_ring_write(rdev, 10); /* poll interval */	112	radeon_ring_write(rdev, 10); /* poll interval */
113	}	113	}
114		114
115	/* emits 21dw + 1 surface sync = 26dw */	115	/* emits 21dw + 1 surface sync = 26dw */
116	static void	116	static void
117	set_shaders(struct radeon_device *rdev)	117	set_shaders(struct radeon_device *rdev)
118	{	118	{
119	u64 gpu_addr;	119	u64 gpu_addr;
120	u32 sq_pgm_resources;	120	u32 sq_pgm_resources;
121		121
122	/* setup shader regs */	122	/* setup shader regs */
123	sq_pgm_resources = (1 << 0);	123	sq_pgm_resources = (1 << 0);
124		124
125	/* VS */	125	/* VS */
126	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;	126	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
127	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	127	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
128	radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	128	radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
129	radeon_ring_write(rdev, gpu_addr >> 8);	129	radeon_ring_write(rdev, gpu_addr >> 8);
130		130
131	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	131	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
132	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	132	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
133	radeon_ring_write(rdev, sq_pgm_resources);	133	radeon_ring_write(rdev, sq_pgm_resources);
134		134
135	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	135	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
136	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	136	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
137	radeon_ring_write(rdev, 0);	137	radeon_ring_write(rdev, 0);
138		138
139	/* PS */	139	/* PS */
140	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;	140	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
141	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	141	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
142	radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	142	radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
143	radeon_ring_write(rdev, gpu_addr >> 8);	143	radeon_ring_write(rdev, gpu_addr >> 8);
144		144
145	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	145	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
146	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	146	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
147	radeon_ring_write(rdev, sq_pgm_resources \| (1 << 28));	147	radeon_ring_write(rdev, sq_pgm_resources \| (1 << 28));
148		148
149	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	149	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
150	radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	150	radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
151	radeon_ring_write(rdev, 2);	151	radeon_ring_write(rdev, 2);
152		152
153	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));	153	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
154	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	154	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
155	radeon_ring_write(rdev, 0);	155	radeon_ring_write(rdev, 0);
156		156
157	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;	157	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
158	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);	158	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
159	}	159	}
160		160
161	/* emits 9 + 1 sync (5) = 14*/	161	/* emits 9 + 1 sync (5) = 14*/
162	static void	162	static void
163	set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)	163	set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
164	{	164	{
165	u32 sq_vtx_constant_word2;	165	u32 sq_vtx_constant_word2;
166		166
167	sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) \| (16 << 8));	167	sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) \| (16 << 8));
168	#ifdef __BIG_ENDIAN	168	#ifdef __BIG_ENDIAN
169	sq_vtx_constant_word2 \|= (2 << 30);	169	sq_vtx_constant_word2 \|= (2 << 30);
170	#endif	170	#endif
171		171
172	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));	172	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
173	radeon_ring_write(rdev, 0x460);	173	radeon_ring_write(rdev, 0x460);
174	radeon_ring_write(rdev, gpu_addr & 0xffffffff);	174	radeon_ring_write(rdev, gpu_addr & 0xffffffff);
175	radeon_ring_write(rdev, 48 - 1);	175	radeon_ring_write(rdev, 48 - 1);
176	radeon_ring_write(rdev, sq_vtx_constant_word2);	176	radeon_ring_write(rdev, sq_vtx_constant_word2);
177	radeon_ring_write(rdev, 1 << 0);	177	radeon_ring_write(rdev, 1 << 0);
178	radeon_ring_write(rdev, 0);	178	radeon_ring_write(rdev, 0);
179	radeon_ring_write(rdev, 0);	179	radeon_ring_write(rdev, 0);
180	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);	180	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
181		181
182	if ((rdev->family == CHIP_RV610) \|\|	182	if ((rdev->family == CHIP_RV610) \|\|
183	(rdev->family == CHIP_RV620) \|\|	183	(rdev->family == CHIP_RV620) \|\|
184	(rdev->family == CHIP_RS780) \|\|	184	(rdev->family == CHIP_RS780) \|\|
185	(rdev->family == CHIP_RS880) \|\|	185	(rdev->family == CHIP_RS880) \|\|
186	(rdev->family == CHIP_RV710))	186	(rdev->family == CHIP_RV710))
187	cp_set_surface_sync(rdev,	187	cp_set_surface_sync(rdev,
188	PACKET3_TC_ACTION_ENA, 48, gpu_addr);	188	PACKET3_TC_ACTION_ENA, 48, gpu_addr);
189	else	189	else
190	cp_set_surface_sync(rdev,	190	cp_set_surface_sync(rdev,
191	PACKET3_VC_ACTION_ENA, 48, gpu_addr);	191	PACKET3_VC_ACTION_ENA, 48, gpu_addr);
192	}	192	}
193		193
194	/* emits 9 */	194	/* emits 9 */
195	static void	195	static void
196	set_tex_resource(struct radeon_device *rdev,	196	set_tex_resource(struct radeon_device *rdev,
197	int format, int w, int h, int pitch,	197	int format, int w, int h, int pitch,
198	u64 gpu_addr)	198	u64 gpu_addr)
199	{	199	{
200	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;	200	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
201		201
202	if (h < 1)	202	if (h < 1)
203	h = 1;	203	h = 1;
204		204
205	sq_tex_resource_word0 = (1 << 0) \| (1 << 3);	205	sq_tex_resource_word0 = (1 << 0) \| (1 << 3);
206	sq_tex_resource_word0 \|= ((((pitch >> 3) - 1) << 8) \|	206	sq_tex_resource_word0 \|= ((((pitch >> 3) - 1) << 8) \|
207	((w - 1) << 19));	207	((w - 1) << 19));
208		208
209	sq_tex_resource_word1 = (format << 26);	209	sq_tex_resource_word1 = (format << 26);
210	sq_tex_resource_word1 \|= ((h - 1) << 0);	210	sq_tex_resource_word1 \|= ((h - 1) << 0);
211		211
212	sq_tex_resource_word4 = ((1 << 14) \|	212	sq_tex_resource_word4 = ((1 << 14) \|
213	(0 << 16) \|	213	(0 << 16) \|
214	(1 << 19) \|	214	(1 << 19) \|
215	(2 << 22) \|	215	(2 << 22) \|
216	(3 << 25));	216	(3 << 25));
217		217
218	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));	218	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
219	radeon_ring_write(rdev, 0);	219	radeon_ring_write(rdev, 0);
220	radeon_ring_write(rdev, sq_tex_resource_word0);	220	radeon_ring_write(rdev, sq_tex_resource_word0);
221	radeon_ring_write(rdev, sq_tex_resource_word1);	221	radeon_ring_write(rdev, sq_tex_resource_word1);
222	radeon_ring_write(rdev, gpu_addr >> 8);	222	radeon_ring_write(rdev, gpu_addr >> 8);
223	radeon_ring_write(rdev, gpu_addr >> 8);	223	radeon_ring_write(rdev, gpu_addr >> 8);
224	radeon_ring_write(rdev, sq_tex_resource_word4);	224	radeon_ring_write(rdev, sq_tex_resource_word4);
225	radeon_ring_write(rdev, 0);	225	radeon_ring_write(rdev, 0);
226	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);	226	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
227	}	227	}
228		228
229	/* emits 12 */	229	/* emits 12 */
230	static void	230	static void
231	set_scissors(struct radeon_device *rdev, int x1, int y1,	231	set_scissors(struct radeon_device *rdev, int x1, int y1,
232	int x2, int y2)	232	int x2, int y2)
233	{	233	{
234	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));	234	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
235	radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	235	radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
236	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16));	236	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16));
237	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));	237	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));
238		238
239	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));	239	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
240	radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	240	radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
241	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16) \| (1 << 31));	241	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16) \| (1 << 31));
242	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));	242	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));
243		243
244	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));	244	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
245	radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);	245	radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
246	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16) \| (1 << 31));	246	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16) \| (1 << 31));
247	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));	247	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));
248	}	248	}
249		249
250	/* emits 10 */	250	/* emits 10 */
251	static void	251	static void
252	draw_auto(struct radeon_device *rdev)	252	draw_auto(struct radeon_device *rdev)
253	{	253	{
254	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));	254	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
255	radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);	255	radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
256	radeon_ring_write(rdev, DI_PT_RECTLIST);	256	radeon_ring_write(rdev, DI_PT_RECTLIST);
257		257
258	radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));	258	radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
259	radeon_ring_write(rdev,	259	radeon_ring_write(rdev,
260	#ifdef __BIG_ENDIAN	260	#ifdef __BIG_ENDIAN
261	(2 << 2) \|	261	(2 << 2) \|
262	#endif	262	#endif
263	DI_INDEX_SIZE_16_BIT);	263	DI_INDEX_SIZE_16_BIT);
264		264
265	radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));	265	radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
266	radeon_ring_write(rdev, 1);	266	radeon_ring_write(rdev, 1);
267		267
268	radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));	268	radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
269	radeon_ring_write(rdev, 3);	269	radeon_ring_write(rdev, 3);
270	radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);	270	radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
271		271
272	}	272	}
273		273
274	/* emits 14 */	274	/* emits 14 */
275	static void	275	static void
276	set_default_state(struct radeon_device *rdev)	276	set_default_state(struct radeon_device *rdev)
277	{	277	{
278	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;	278	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
279	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;	279	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
280	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;	280	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
281	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;	281	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
282	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;	282	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
283	u64 gpu_addr;	283	u64 gpu_addr;
284	int dwords;	284	int dwords;
285		285
286	switch (rdev->family) {	286	switch (rdev->family) {
287	case CHIP_R600:	287	case CHIP_R600:
288	num_ps_gprs = 192;	288	num_ps_gprs = 192;
289	num_vs_gprs = 56;	289	num_vs_gprs = 56;
290	num_temp_gprs = 4;	290	num_temp_gprs = 4;
291	num_gs_gprs = 0;	291	num_gs_gprs = 0;
292	num_es_gprs = 0;	292	num_es_gprs = 0;
293	num_ps_threads = 136;	293	num_ps_threads = 136;
294	num_vs_threads = 48;	294	num_vs_threads = 48;
295	num_gs_threads = 4;	295	num_gs_threads = 4;
296	num_es_threads = 4;	296	num_es_threads = 4;
297	num_ps_stack_entries = 128;	297	num_ps_stack_entries = 128;
298	num_vs_stack_entries = 128;	298	num_vs_stack_entries = 128;
299	num_gs_stack_entries = 0;	299	num_gs_stack_entries = 0;
300	num_es_stack_entries = 0;	300	num_es_stack_entries = 0;
301	break;	301	break;
302	case CHIP_RV630:	302	case CHIP_RV630:
303	case CHIP_RV635:	303	case CHIP_RV635:
304	num_ps_gprs = 84;	304	num_ps_gprs = 84;
305	num_vs_gprs = 36;	305	num_vs_gprs = 36;
306	num_temp_gprs = 4;	306	num_temp_gprs = 4;
307	num_gs_gprs = 0;	307	num_gs_gprs = 0;
308	num_es_gprs = 0;	308	num_es_gprs = 0;
309	num_ps_threads = 144;	309	num_ps_threads = 144;
310	num_vs_threads = 40;	310	num_vs_threads = 40;
311	num_gs_threads = 4;	311	num_gs_threads = 4;
312	num_es_threads = 4;	312	num_es_threads = 4;
313	num_ps_stack_entries = 40;	313	num_ps_stack_entries = 40;
314	num_vs_stack_entries = 40;	314	num_vs_stack_entries = 40;
315	num_gs_stack_entries = 32;	315	num_gs_stack_entries = 32;
316	num_es_stack_entries = 16;	316	num_es_stack_entries = 16;
317	break;	317	break;
318	case CHIP_RV610:	318	case CHIP_RV610:
319	case CHIP_RV620:	319	case CHIP_RV620:
320	case CHIP_RS780:	320	case CHIP_RS780:
321	case CHIP_RS880:	321	case CHIP_RS880:
322	default:	322	default:
323	num_ps_gprs = 84;	323	num_ps_gprs = 84;
324	num_vs_gprs = 36;	324	num_vs_gprs = 36;
325	num_temp_gprs = 4;	325	num_temp_gprs = 4;
326	num_gs_gprs = 0;	326	num_gs_gprs = 0;
327	num_es_gprs = 0;	327	num_es_gprs = 0;
328	num_ps_threads = 136;	328	num_ps_threads = 136;
329	num_vs_threads = 48;	329	num_vs_threads = 48;
330	num_gs_threads = 4;	330	num_gs_threads = 4;
331	num_es_threads = 4;	331	num_es_threads = 4;
332	num_ps_stack_entries = 40;	332	num_ps_stack_entries = 40;
333	num_vs_stack_entries = 40;	333	num_vs_stack_entries = 40;
334	num_gs_stack_entries = 32;	334	num_gs_stack_entries = 32;
335	num_es_stack_entries = 16;	335	num_es_stack_entries = 16;
336	break;	336	break;
337	case CHIP_RV670:	337	case CHIP_RV670:
338	num_ps_gprs = 144;	338	num_ps_gprs = 144;
339	num_vs_gprs = 40;	339	num_vs_gprs = 40;
340	num_temp_gprs = 4;	340	num_temp_gprs = 4;
341	num_gs_gprs = 0;	341	num_gs_gprs = 0;
342	num_es_gprs = 0;	342	num_es_gprs = 0;
343	num_ps_threads = 136;	343	num_ps_threads = 136;
344	num_vs_threads = 48;	344	num_vs_threads = 48;
345	num_gs_threads = 4;	345	num_gs_threads = 4;
346	num_es_threads = 4;	346	num_es_threads = 4;
347	num_ps_stack_entries = 40;	347	num_ps_stack_entries = 40;
348	num_vs_stack_entries = 40;	348	num_vs_stack_entries = 40;
349	num_gs_stack_entries = 32;	349	num_gs_stack_entries = 32;
350	num_es_stack_entries = 16;	350	num_es_stack_entries = 16;
351	break;	351	break;
352	case CHIP_RV770:	352	case CHIP_RV770:
353	num_ps_gprs = 192;	353	num_ps_gprs = 192;
354	num_vs_gprs = 56;	354	num_vs_gprs = 56;
355	num_temp_gprs = 4;	355	num_temp_gprs = 4;
356	num_gs_gprs = 0;	356	num_gs_gprs = 0;
357	num_es_gprs = 0;	357	num_es_gprs = 0;
358	num_ps_threads = 188;	358	num_ps_threads = 188;
359	num_vs_threads = 60;	359	num_vs_threads = 60;
360	num_gs_threads = 0;	360	num_gs_threads = 0;
361	num_es_threads = 0;	361	num_es_threads = 0;
362	num_ps_stack_entries = 256;	362	num_ps_stack_entries = 256;
363	num_vs_stack_entries = 256;	363	num_vs_stack_entries = 256;
364	num_gs_stack_entries = 0;	364	num_gs_stack_entries = 0;
365	num_es_stack_entries = 0;	365	num_es_stack_entries = 0;
366	break;	366	break;
367	case CHIP_RV730:	367	case CHIP_RV730:
368	case CHIP_RV740:	368	case CHIP_RV740:
369	num_ps_gprs = 84;	369	num_ps_gprs = 84;
370	num_vs_gprs = 36;	370	num_vs_gprs = 36;
371	num_temp_gprs = 4;	371	num_temp_gprs = 4;
372	num_gs_gprs = 0;	372	num_gs_gprs = 0;
373	num_es_gprs = 0;	373	num_es_gprs = 0;
374	num_ps_threads = 188;	374	num_ps_threads = 188;
375	num_vs_threads = 60;	375	num_vs_threads = 60;
376	num_gs_threads = 0;	376	num_gs_threads = 0;
377	num_es_threads = 0;	377	num_es_threads = 0;
378	num_ps_stack_entries = 128;	378	num_ps_stack_entries = 128;
379	num_vs_stack_entries = 128;	379	num_vs_stack_entries = 128;
380	num_gs_stack_entries = 0;	380	num_gs_stack_entries = 0;
381	num_es_stack_entries = 0;	381	num_es_stack_entries = 0;
382	break;	382	break;
383	case CHIP_RV710:	383	case CHIP_RV710:
384	num_ps_gprs = 192;	384	num_ps_gprs = 192;
385	num_vs_gprs = 56;	385	num_vs_gprs = 56;
386	num_temp_gprs = 4;	386	num_temp_gprs = 4;
387	num_gs_gprs = 0;	387	num_gs_gprs = 0;
388	num_es_gprs = 0;	388	num_es_gprs = 0;
389	num_ps_threads = 144;	389	num_ps_threads = 144;
390	num_vs_threads = 48;	390	num_vs_threads = 48;
391	num_gs_threads = 0;	391	num_gs_threads = 0;
392	num_es_threads = 0;	392	num_es_threads = 0;
393	num_ps_stack_entries = 128;	393	num_ps_stack_entries = 128;
394	num_vs_stack_entries = 128;	394	num_vs_stack_entries = 128;
395	num_gs_stack_entries = 0;	395	num_gs_stack_entries = 0;
396	num_es_stack_entries = 0;	396	num_es_stack_entries = 0;
397	break;	397	break;
398	}	398	}
399		399
400	if ((rdev->family == CHIP_RV610) \|\|	400	if ((rdev->family == CHIP_RV610) \|\|
401	(rdev->family == CHIP_RV620) \|\|	401	(rdev->family == CHIP_RV620) \|\|
402	(rdev->family == CHIP_RS780) \|\|	402	(rdev->family == CHIP_RS780) \|\|
403	(rdev->family == CHIP_RS880) \|\|	403	(rdev->family == CHIP_RS880) \|\|
404	(rdev->family == CHIP_RV710))	404	(rdev->family == CHIP_RV710))
405	sq_config = 0;	405	sq_config = 0;
406	else	406	else
407	sq_config = VC_ENABLE;	407	sq_config = VC_ENABLE;
408		408
409	sq_config \|= (DX9_CONSTS \|	409	sq_config \|= (DX9_CONSTS \|
410	ALU_INST_PREFER_VECTOR \|	410	ALU_INST_PREFER_VECTOR \|
411	PS_PRIO(0) \|	411	PS_PRIO(0) \|
412	VS_PRIO(1) \|	412	VS_PRIO(1) \|
413	GS_PRIO(2) \|	413	GS_PRIO(2) \|
414	ES_PRIO(3));	414	ES_PRIO(3));
415		415
416	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) \|	416	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) \|
417	NUM_VS_GPRS(num_vs_gprs) \|	417	NUM_VS_GPRS(num_vs_gprs) \|
418	NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));	418	NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
419	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) \|	419	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) \|
420	NUM_ES_GPRS(num_es_gprs));	420	NUM_ES_GPRS(num_es_gprs));
421	sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) \|	421	sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) \|
422	NUM_VS_THREADS(num_vs_threads) \|	422	NUM_VS_THREADS(num_vs_threads) \|
423	NUM_GS_THREADS(num_gs_threads) \|	423	NUM_GS_THREADS(num_gs_threads) \|
424	NUM_ES_THREADS(num_es_threads));	424	NUM_ES_THREADS(num_es_threads));
425	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) \|	425	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) \|
426	NUM_VS_STACK_ENTRIES(num_vs_stack_entries));	426	NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
427	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) \|	427	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) \|
428	NUM_ES_STACK_ENTRIES(num_es_stack_entries));	428	NUM_ES_STACK_ENTRIES(num_es_stack_entries));
429		429
430	/* emit an IB pointing at default state */	430	/* emit an IB pointing at default state */
431	dwords = ALIGN(rdev->r600_blit.state_len, 0x10);	431	dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
432	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;	432	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
433	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));	433	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
434	radeon_ring_write(rdev,	434	radeon_ring_write(rdev,
435	#ifdef __BIG_ENDIAN	435	#ifdef __BIG_ENDIAN
436	(2 << 0) \|	436	(2 << 0) \|
437	#endif	437	#endif
438	(gpu_addr & 0xFFFFFFFC));	438	(gpu_addr & 0xFFFFFFFC));
439	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);	439	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
440	radeon_ring_write(rdev, dwords);	440	radeon_ring_write(rdev, dwords);
441		441
442	/* SQ config */	442	/* SQ config */
443	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));	443	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
444	radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);	444	radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
445	radeon_ring_write(rdev, sq_config);	445	radeon_ring_write(rdev, sq_config);
446	radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);	446	radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
447	radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);	447	radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
448	radeon_ring_write(rdev, sq_thread_resource_mgmt);	448	radeon_ring_write(rdev, sq_thread_resource_mgmt);
449	radeon_ring_write(rdev, sq_stack_resource_mgmt_1);	449	radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
450	radeon_ring_write(rdev, sq_stack_resource_mgmt_2);	450	radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
451	}	451	}
452		452
453	static inline uint32_t i2f(uint32_t input)	453	static inline uint32_t i2f(uint32_t input)
454	{	454	{
455	u32 result, i, exponent, fraction;	455	u32 result, i, exponent, fraction;
456		456
457	if ((input & 0x3fff) == 0)	457	if ((input & 0x3fff) == 0)
458	result = 0; /* 0 is a special case */	458	result = 0; /* 0 is a special case */
459	else {	459	else {
460	exponent = 140; /* exponent biased by 127; */	460	exponent = 140; /* exponent biased by 127; */
461	fraction = (input & 0x3fff) << 10; /* cheat and only	461	fraction = (input & 0x3fff) << 10; /* cheat and only
462	handle numbers below 2^^15 */	462	handle numbers below 2^^15 */
463	for (i = 0; i < 14; i++) {	463	for (i = 0; i < 14; i++) {
464	if (fraction & 0x800000)	464	if (fraction & 0x800000)
465	break;	465	break;
466	else {	466	else {
467	fraction = fraction << 1; /* keep	467	fraction = fraction << 1; /* keep
468	shifting left until top bit = 1 */	468	shifting left until top bit = 1 */
469	exponent = exponent - 1;	469	exponent = exponent - 1;
470	}	470	}
471	}	471	}
472	result = exponent << 23 \| (fraction & 0x7fffff); /* mask	472	result = exponent << 23 \| (fraction & 0x7fffff); /* mask
473	off top bit; assumed 1 */	473	off top bit; assumed 1 */
474	}	474	}
475	return result;	475	return result;
476	}	476	}
477		477
478	int r600_blit_init(struct radeon_device *rdev)	478	int r600_blit_init(struct radeon_device *rdev)
479	{	479	{
480	u32 obj_size;	480	u32 obj_size;
481	int i, r, dwords;	481	int i, r, dwords;
482	void *ptr;	482	void *ptr;
483	u32 packet2s[16];	483	u32 packet2s[16];
484	int num_packet2s = 0;	484	int num_packet2s = 0;
485		485
486	ENTER();	486	ENTER();
487		487
488	/* pin copy shader into vram if already initialized */	488	/* pin copy shader into vram if already initialized */
489	if (rdev->r600_blit.shader_obj)	489	if (rdev->r600_blit.shader_obj)
490	goto done;	490	goto done;
491		491
492	mutex_init(&rdev->r600_blit.mutex);	492	mutex_init(&rdev->r600_blit.mutex);
493	rdev->r600_blit.state_offset = 0;	493	rdev->r600_blit.state_offset = 0;
494		494
495	if (rdev->family >= CHIP_RV770)	495	if (rdev->family >= CHIP_RV770)
496	rdev->r600_blit.state_len = r7xx_default_size;	496	rdev->r600_blit.state_len = r7xx_default_size;
497	else	497	else
498	rdev->r600_blit.state_len = r6xx_default_size;	498	rdev->r600_blit.state_len = r6xx_default_size;
499		499
500	dwords = rdev->r600_blit.state_len;	500	dwords = rdev->r600_blit.state_len;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r600_blit_kms.c – Rev 2005 → 2007