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Rev 2175 | Rev 2997 | ||
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Line 26... | Line 26... | ||
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
- | 31 | #include |
|
31 | #include "drmP.h" |
32 | #include |
32 | #include "radeon_drm.h" |
33 | #include |
33 | #include "radeon.h" |
34 | #include "radeon.h" |
34 | #include "radeon_asic.h" |
35 | #include "radeon_asic.h" |
35 | #include "radeon_mode.h" |
36 | #include "radeon_mode.h" |
36 | #include "r600d.h" |
37 | #include "r600d.h" |
37 | #include "atom.h" |
38 | #include "atom.h" |
Line 45... | Line 46... | ||
45 | #define R700_RLC_UCODE_SIZE 1024 |
46 | #define R700_RLC_UCODE_SIZE 1024 |
46 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
47 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
47 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
48 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
48 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
49 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
49 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
50 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
- | 51 | #define ARUBA_RLC_UCODE_SIZE 1536 |
|
Line 50... | Line 52... | ||
50 | 52 | ||
51 | /* Firmware Names */ |
53 | /* Firmware Names */ |
52 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); |
54 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); |
53 | MODULE_FIRMWARE("radeon/R600_me.bin"); |
55 | MODULE_FIRMWARE("radeon/R600_me.bin"); |
Line 93... | Line 95... | ||
93 | 95 | ||
Line 94... | Line 96... | ||
94 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
96 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
95 | 97 | ||
96 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
98 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
97 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
99 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
98 | void r600_gpu_init(struct radeon_device *rdev); |
100 | static void r600_gpu_init(struct radeon_device *rdev); |
99 | void r600_fini(struct radeon_device *rdev); |
101 | void r600_fini(struct radeon_device *rdev); |
Line 100... | Line 102... | ||
100 | void r600_irq_disable(struct radeon_device *rdev); |
102 | void r600_irq_disable(struct radeon_device *rdev); |
Line 276... | Line 278... | ||
276 | 278 | ||
277 | void r600_hpd_init(struct radeon_device *rdev) |
279 | void r600_hpd_init(struct radeon_device *rdev) |
278 | { |
280 | { |
279 | struct drm_device *dev = rdev->ddev; |
281 | struct drm_device *dev = rdev->ddev; |
- | 282 | struct drm_connector *connector; |
|
Line -... | Line 283... | ||
- | 283 | unsigned enable = 0; |
|
- | 284 | ||
- | 285 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
- | 286 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 287 | ||
- | 288 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || |
|
- | 289 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { |
|
- | 290 | /* don't try to enable hpd on eDP or LVDS avoid breaking the |
|
- | 291 | * aux dp channel on imac and help (but not completely fix) |
|
- | 292 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 |
|
- | 293 | */ |
|
280 | struct drm_connector *connector; |
294 | continue; |
281 | 295 | } |
|
282 | if (ASIC_IS_DCE3(rdev)) { |
296 | if (ASIC_IS_DCE3(rdev)) { |
283 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); |
297 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); |
Line 284... | Line -... | ||
284 | if (ASIC_IS_DCE32(rdev)) |
- | |
285 | tmp |= DC_HPDx_EN; |
- | |
286 | 298 | if (ASIC_IS_DCE32(rdev)) |
|
287 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
299 | tmp |= DC_HPDx_EN; |
288 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
300 | |
289 | switch (radeon_connector->hpd.hpd) { |
- | |
290 | case RADEON_HPD_1: |
301 | switch (radeon_connector->hpd.hpd) { |
291 | WREG32(DC_HPD1_CONTROL, tmp); |
302 | case RADEON_HPD_1: |
292 | rdev->irq.hpd[0] = true; |
303 | WREG32(DC_HPD1_CONTROL, tmp); |
293 | break; |
- | |
294 | case RADEON_HPD_2: |
304 | break; |
295 | WREG32(DC_HPD2_CONTROL, tmp); |
305 | case RADEON_HPD_2: |
296 | rdev->irq.hpd[1] = true; |
306 | WREG32(DC_HPD2_CONTROL, tmp); |
297 | break; |
- | |
298 | case RADEON_HPD_3: |
307 | break; |
299 | WREG32(DC_HPD3_CONTROL, tmp); |
308 | case RADEON_HPD_3: |
300 | rdev->irq.hpd[2] = true; |
309 | WREG32(DC_HPD3_CONTROL, tmp); |
301 | break; |
- | |
302 | case RADEON_HPD_4: |
310 | break; |
303 | WREG32(DC_HPD4_CONTROL, tmp); |
311 | case RADEON_HPD_4: |
304 | rdev->irq.hpd[3] = true; |
312 | WREG32(DC_HPD4_CONTROL, tmp); |
305 | break; |
313 | break; |
306 | /* DCE 3.2 */ |
- | |
307 | case RADEON_HPD_5: |
314 | /* DCE 3.2 */ |
308 | WREG32(DC_HPD5_CONTROL, tmp); |
315 | case RADEON_HPD_5: |
309 | rdev->irq.hpd[4] = true; |
316 | WREG32(DC_HPD5_CONTROL, tmp); |
310 | break; |
- | |
311 | case RADEON_HPD_6: |
317 | break; |
312 | WREG32(DC_HPD6_CONTROL, tmp); |
318 | case RADEON_HPD_6: |
313 | rdev->irq.hpd[5] = true; |
319 | WREG32(DC_HPD6_CONTROL, tmp); |
314 | break; |
320 | break; |
315 | default: |
- | |
316 | break; |
321 | default: |
317 | } |
- | |
318 | } |
- | |
319 | } else { |
322 | break; |
320 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
323 | } |
321 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
324 | } else { |
322 | switch (radeon_connector->hpd.hpd) { |
- | |
323 | case RADEON_HPD_1: |
325 | switch (radeon_connector->hpd.hpd) { |
324 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
326 | case RADEON_HPD_1: |
325 | rdev->irq.hpd[0] = true; |
327 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
326 | break; |
- | |
327 | case RADEON_HPD_2: |
328 | break; |
328 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
329 | case RADEON_HPD_2: |
329 | rdev->irq.hpd[1] = true; |
330 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
330 | break; |
- | |
331 | case RADEON_HPD_3: |
331 | break; |
332 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
332 | case RADEON_HPD_3: |
333 | rdev->irq.hpd[2] = true; |
333 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
334 | break; |
334 | break; |
335 | default: |
335 | default: |
- | 336 | break; |
|
- | 337 | } |
|
336 | break; |
338 | } |
337 | } |
- | |
338 | } |
339 | enable |= 1 << radeon_connector->hpd.hpd; |
339 | } |
340 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
Line 340... | Line 341... | ||
340 | if (rdev->irq.installed) |
341 | } |
341 | r600_irq_set(rdev); |
342 | // radeon_irq_kms_enable_hpd(rdev, enable); |
342 | } |
343 | } |
343 | 344 | ||
- | 345 | void r600_hpd_fini(struct radeon_device *rdev) |
|
Line 344... | Line -... | ||
344 | void r600_hpd_fini(struct radeon_device *rdev) |
- | |
345 | { |
346 | { |
346 | struct drm_device *dev = rdev->ddev; |
347 | struct drm_device *dev = rdev->ddev; |
- | 348 | struct drm_connector *connector; |
|
347 | struct drm_connector *connector; |
349 | unsigned disable = 0; |
348 | 350 | ||
349 | if (ASIC_IS_DCE3(rdev)) { |
351 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
350 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
- | |
351 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
352 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
352 | switch (radeon_connector->hpd.hpd) { |
353 | if (ASIC_IS_DCE3(rdev)) { |
353 | case RADEON_HPD_1: |
354 | switch (radeon_connector->hpd.hpd) { |
354 | WREG32(DC_HPD1_CONTROL, 0); |
- | |
355 | rdev->irq.hpd[0] = false; |
355 | case RADEON_HPD_1: |
356 | break; |
356 | WREG32(DC_HPD1_CONTROL, 0); |
357 | case RADEON_HPD_2: |
357 | break; |
358 | WREG32(DC_HPD2_CONTROL, 0); |
- | |
359 | rdev->irq.hpd[1] = false; |
358 | case RADEON_HPD_2: |
360 | break; |
359 | WREG32(DC_HPD2_CONTROL, 0); |
361 | case RADEON_HPD_3: |
360 | break; |
362 | WREG32(DC_HPD3_CONTROL, 0); |
- | |
363 | rdev->irq.hpd[2] = false; |
361 | case RADEON_HPD_3: |
364 | break; |
362 | WREG32(DC_HPD3_CONTROL, 0); |
365 | case RADEON_HPD_4: |
363 | break; |
366 | WREG32(DC_HPD4_CONTROL, 0); |
364 | case RADEON_HPD_4: |
367 | rdev->irq.hpd[3] = false; |
- | |
368 | break; |
365 | WREG32(DC_HPD4_CONTROL, 0); |
369 | /* DCE 3.2 */ |
366 | break; |
370 | case RADEON_HPD_5: |
367 | /* DCE 3.2 */ |
371 | WREG32(DC_HPD5_CONTROL, 0); |
- | |
372 | rdev->irq.hpd[4] = false; |
368 | case RADEON_HPD_5: |
373 | break; |
369 | WREG32(DC_HPD5_CONTROL, 0); |
374 | case RADEON_HPD_6: |
370 | break; |
375 | WREG32(DC_HPD6_CONTROL, 0); |
371 | case RADEON_HPD_6: |
376 | rdev->irq.hpd[5] = false; |
- | |
377 | break; |
372 | WREG32(DC_HPD6_CONTROL, 0); |
378 | default: |
- | |
379 | break; |
- | |
380 | } |
373 | break; |
381 | } |
374 | default: |
382 | } else { |
375 | break; |
383 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
- | |
384 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
376 | } |
385 | switch (radeon_connector->hpd.hpd) { |
377 | } else { |
386 | case RADEON_HPD_1: |
378 | switch (radeon_connector->hpd.hpd) { |
387 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); |
- | |
388 | rdev->irq.hpd[0] = false; |
379 | case RADEON_HPD_1: |
389 | break; |
380 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); |
390 | case RADEON_HPD_2: |
381 | break; |
391 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); |
- | |
392 | rdev->irq.hpd[1] = false; |
382 | case RADEON_HPD_2: |
393 | break; |
383 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); |
394 | case RADEON_HPD_3: |
384 | break; |
395 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); |
385 | case RADEON_HPD_3: |
396 | rdev->irq.hpd[2] = false; |
386 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); |
- | 387 | break; |
|
397 | break; |
388 | default: |
- | 389 | break; |
|
398 | default: |
390 | } |
Line 399... | Line 391... | ||
399 | break; |
391 | } |
400 | } |
392 | disable |= 1 << radeon_connector->hpd.hpd; |
401 | } |
393 | } |
Line 411... | Line 403... | ||
411 | u32 tmp; |
403 | u32 tmp; |
Line 412... | Line 404... | ||
412 | 404 | ||
413 | /* flush hdp cache so updates hit vram */ |
405 | /* flush hdp cache so updates hit vram */ |
414 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
406 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
415 | !(rdev->flags & RADEON_IS_AGP)) { |
407 | !(rdev->flags & RADEON_IS_AGP)) { |
416 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
408 | void __iomem *ptr = (void *)rdev->gart.ptr; |
Line 417... | Line 409... | ||
417 | u32 tmp; |
409 | u32 tmp; |
418 | 410 | ||
419 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
411 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
Line 446... | Line 438... | ||
446 | 438 | ||
447 | int r600_pcie_gart_init(struct radeon_device *rdev) |
439 | int r600_pcie_gart_init(struct radeon_device *rdev) |
448 | { |
440 | { |
Line 449... | Line 441... | ||
449 | int r; |
441 | int r; |
450 | 442 | ||
451 | if (rdev->gart.table.vram.robj) { |
443 | if (rdev->gart.robj) { |
452 | WARN(1, "R600 PCIE GART already initialized\n"); |
444 | WARN(1, "R600 PCIE GART already initialized\n"); |
453 | return 0; |
445 | return 0; |
454 | } |
446 | } |
Line 458... | Line 450... | ||
458 | return r; |
450 | return r; |
459 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
451 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
460 | return radeon_gart_table_vram_alloc(rdev); |
452 | return radeon_gart_table_vram_alloc(rdev); |
461 | } |
453 | } |
Line 462... | Line 454... | ||
462 | 454 | ||
463 | int r600_pcie_gart_enable(struct radeon_device *rdev) |
455 | static int r600_pcie_gart_enable(struct radeon_device *rdev) |
464 | { |
456 | { |
465 | u32 tmp; |
457 | u32 tmp; |
Line 466... | Line 458... | ||
466 | int r, i; |
458 | int r, i; |
467 | 459 | ||
468 | if (rdev->gart.table.vram.robj == NULL) { |
460 | if (rdev->gart.robj == NULL) { |
469 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
461 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
470 | return -EINVAL; |
462 | return -EINVAL; |
471 | } |
463 | } |
Line 508... | Line 500... | ||
508 | (u32)(rdev->dummy_page.addr >> 12)); |
500 | (u32)(rdev->dummy_page.addr >> 12)); |
509 | for (i = 1; i < 7; i++) |
501 | for (i = 1; i < 7; i++) |
510 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
502 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
Line 511... | Line 503... | ||
511 | 503 | ||
- | 504 | r600_pcie_gart_tlb_flush(rdev); |
|
- | 505 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
|
- | 506 | (unsigned)(rdev->mc.gtt_size >> 20), |
|
512 | r600_pcie_gart_tlb_flush(rdev); |
507 | (unsigned long long)rdev->gart.table_addr); |
513 | rdev->gart.ready = true; |
508 | rdev->gart.ready = true; |
514 | return 0; |
509 | return 0; |
Line 515... | Line 510... | ||
515 | } |
510 | } |
516 | 511 | ||
517 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
512 | static void r600_pcie_gart_disable(struct radeon_device *rdev) |
518 | { |
513 | { |
Line 519... | Line 514... | ||
519 | u32 tmp; |
514 | u32 tmp; |
520 | int i, r; |
515 | int i; |
521 | 516 | ||
Line 542... | Line 537... | ||
542 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); |
537 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); |
543 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
538 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
544 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
539 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
545 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
540 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
546 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
541 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
547 | if (rdev->gart.table.vram.robj) { |
542 | radeon_gart_table_vram_unpin(rdev); |
548 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
- | |
549 | if (likely(r == 0)) { |
- | |
550 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
- | |
551 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
- | |
552 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
- | |
553 | } |
- | |
554 | } |
- | |
555 | } |
543 | } |
Line 556... | Line 544... | ||
556 | 544 | ||
557 | void r600_pcie_gart_fini(struct radeon_device *rdev) |
545 | static void r600_pcie_gart_fini(struct radeon_device *rdev) |
558 | { |
546 | { |
559 | radeon_gart_fini(rdev); |
547 | radeon_gart_fini(rdev); |
560 | r600_pcie_gart_disable(rdev); |
548 | r600_pcie_gart_disable(rdev); |
561 | radeon_gart_table_vram_free(rdev); |
549 | radeon_gart_table_vram_free(rdev); |
Line 562... | Line 550... | ||
562 | } |
550 | } |
563 | 551 | ||
564 | void r600_agp_enable(struct radeon_device *rdev) |
552 | static void r600_agp_enable(struct radeon_device *rdev) |
565 | { |
553 | { |
Line 566... | Line 554... | ||
566 | u32 tmp; |
554 | u32 tmp; |
Line 649... | Line 637... | ||
649 | } |
637 | } |
650 | } else { |
638 | } else { |
651 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); |
639 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); |
652 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); |
640 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); |
653 | } |
641 | } |
654 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
642 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
655 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
643 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
656 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
644 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
657 | WREG32(MC_VM_FB_LOCATION, tmp); |
645 | WREG32(MC_VM_FB_LOCATION, tmp); |
658 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
646 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
659 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
647 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
Line 707... | Line 695... | ||
707 | mc->real_vram_size = 0xE0000000; |
695 | mc->real_vram_size = 0xE0000000; |
708 | mc->mc_vram_size = 0xE0000000; |
696 | mc->mc_vram_size = 0xE0000000; |
709 | } |
697 | } |
710 | if (rdev->flags & RADEON_IS_AGP) { |
698 | if (rdev->flags & RADEON_IS_AGP) { |
711 | size_bf = mc->gtt_start; |
699 | size_bf = mc->gtt_start; |
712 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; |
700 | size_af = 0xFFFFFFFF - mc->gtt_end; |
713 | if (size_bf > size_af) { |
701 | if (size_bf > size_af) { |
714 | if (mc->mc_vram_size > size_bf) { |
702 | if (mc->mc_vram_size > size_bf) { |
715 | dev_warn(rdev->dev, "limiting VRAM\n"); |
703 | dev_warn(rdev->dev, "limiting VRAM\n"); |
716 | mc->real_vram_size = size_bf; |
704 | mc->real_vram_size = size_bf; |
717 | mc->mc_vram_size = size_bf; |
705 | mc->mc_vram_size = size_bf; |
Line 721... | Line 709... | ||
721 | if (mc->mc_vram_size > size_af) { |
709 | if (mc->mc_vram_size > size_af) { |
722 | dev_warn(rdev->dev, "limiting VRAM\n"); |
710 | dev_warn(rdev->dev, "limiting VRAM\n"); |
723 | mc->real_vram_size = size_af; |
711 | mc->real_vram_size = size_af; |
724 | mc->mc_vram_size = size_af; |
712 | mc->mc_vram_size = size_af; |
725 | } |
713 | } |
726 | mc->vram_start = mc->gtt_end; |
714 | mc->vram_start = mc->gtt_end + 1; |
727 | } |
715 | } |
728 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
716 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
729 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
717 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
730 | mc->mc_vram_size >> 20, mc->vram_start, |
718 | mc->mc_vram_size >> 20, mc->vram_start, |
731 | mc->vram_end, mc->real_vram_size >> 20); |
719 | mc->vram_end, mc->real_vram_size >> 20); |
Line 739... | Line 727... | ||
739 | rdev->mc.gtt_base_align = 0; |
727 | rdev->mc.gtt_base_align = 0; |
740 | radeon_gtt_location(rdev, mc); |
728 | radeon_gtt_location(rdev, mc); |
741 | } |
729 | } |
742 | } |
730 | } |
Line 743... | Line 731... | ||
743 | 731 | ||
744 | int r600_mc_init(struct radeon_device *rdev) |
732 | static int r600_mc_init(struct radeon_device *rdev) |
745 | { |
733 | { |
746 | u32 tmp; |
734 | u32 tmp; |
Line 747... | Line 735... | ||
747 | int chansize, numchan; |
735 | int chansize, numchan; |
Line 788... | Line 776... | ||
788 | } |
776 | } |
789 | radeon_update_bandwidth_info(rdev); |
777 | radeon_update_bandwidth_info(rdev); |
790 | return 0; |
778 | return 0; |
791 | } |
779 | } |
Line -... | Line 780... | ||
- | 780 | ||
- | 781 | int r600_vram_scratch_init(struct radeon_device *rdev) |
|
- | 782 | { |
|
- | 783 | int r; |
|
- | 784 | ||
- | 785 | if (rdev->vram_scratch.robj == NULL) { |
|
- | 786 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, |
|
- | 787 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
|
- | 788 | NULL, &rdev->vram_scratch.robj); |
|
- | 789 | if (r) { |
|
- | 790 | return r; |
|
- | 791 | } |
|
- | 792 | } |
|
- | 793 | ||
- | 794 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
|
- | 795 | if (unlikely(r != 0)) |
|
- | 796 | return r; |
|
- | 797 | r = radeon_bo_pin(rdev->vram_scratch.robj, |
|
- | 798 | RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); |
|
- | 799 | if (r) { |
|
- | 800 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
|
- | 801 | return r; |
|
- | 802 | } |
|
- | 803 | r = radeon_bo_kmap(rdev->vram_scratch.robj, |
|
- | 804 | (void **)&rdev->vram_scratch.ptr); |
|
- | 805 | if (r) |
|
- | 806 | radeon_bo_unpin(rdev->vram_scratch.robj); |
|
- | 807 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
|
- | 808 | ||
- | 809 | return r; |
|
792 | 810 | } |
|
793 | /* We doesn't check that the GPU really needs a reset we simply do the |
811 | /* We doesn't check that the GPU really needs a reset we simply do the |
794 | * reset, it's up to the caller to determine if the GPU needs one. We |
812 | * reset, it's up to the caller to determine if the GPU needs one. We |
795 | * might add an helper function to check that. |
813 | * might add an helper function to check that. |
796 | */ |
814 | */ |
797 | int r600_gpu_soft_reset(struct radeon_device *rdev) |
815 | static int r600_gpu_soft_reset(struct radeon_device *rdev) |
798 | { |
816 | { |
799 | struct rv515_mc_save save; |
817 | struct rv515_mc_save save; |
800 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
818 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
801 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | |
819 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | |
Line 823... | Line 841... | ||
823 | RREG32(R_008010_GRBM_STATUS)); |
841 | RREG32(R_008010_GRBM_STATUS)); |
824 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
842 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
825 | RREG32(R_008014_GRBM_STATUS2)); |
843 | RREG32(R_008014_GRBM_STATUS2)); |
826 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
844 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
827 | RREG32(R_000E50_SRBM_STATUS)); |
845 | RREG32(R_000E50_SRBM_STATUS)); |
- | 846 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
|
- | 847 | RREG32(CP_STALLED_STAT1)); |
|
- | 848 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
|
- | 849 | RREG32(CP_STALLED_STAT2)); |
|
- | 850 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
|
- | 851 | RREG32(CP_BUSY_STAT)); |
|
- | 852 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
|
- | 853 | RREG32(CP_STAT)); |
|
828 | rv515_mc_stop(rdev, &save); |
854 | rv515_mc_stop(rdev, &save); |
829 | if (r600_mc_wait_for_idle(rdev)) { |
855 | if (r600_mc_wait_for_idle(rdev)) { |
830 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
856 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
831 | } |
857 | } |
832 | /* Disable CP parsing/prefetching */ |
858 | /* Disable CP parsing/prefetching */ |
Line 866... | Line 892... | ||
866 | RREG32(R_008010_GRBM_STATUS)); |
892 | RREG32(R_008010_GRBM_STATUS)); |
867 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
893 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
868 | RREG32(R_008014_GRBM_STATUS2)); |
894 | RREG32(R_008014_GRBM_STATUS2)); |
869 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
895 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
870 | RREG32(R_000E50_SRBM_STATUS)); |
896 | RREG32(R_000E50_SRBM_STATUS)); |
- | 897 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
|
- | 898 | RREG32(CP_STALLED_STAT1)); |
|
- | 899 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
|
- | 900 | RREG32(CP_STALLED_STAT2)); |
|
- | 901 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
|
- | 902 | RREG32(CP_BUSY_STAT)); |
|
- | 903 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
|
- | 904 | RREG32(CP_STAT)); |
|
871 | rv515_mc_resume(rdev, &save); |
905 | rv515_mc_resume(rdev, &save); |
872 | return 0; |
906 | return 0; |
873 | } |
907 | } |
Line 874... | Line 908... | ||
874 | 908 | ||
875 | bool r600_gpu_is_lockup(struct radeon_device *rdev) |
909 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
876 | { |
910 | { |
877 | u32 srbm_status; |
911 | u32 srbm_status; |
878 | u32 grbm_status; |
912 | u32 grbm_status; |
879 | u32 grbm_status2; |
- | |
880 | struct r100_gpu_lockup *lockup; |
- | |
881 | int r; |
- | |
882 | - | ||
883 | if (rdev->family >= CHIP_RV770) |
- | |
884 | lockup = &rdev->config.rv770.lockup; |
- | |
885 | else |
- | |
Line 886... | Line 913... | ||
886 | lockup = &rdev->config.r600.lockup; |
913 | u32 grbm_status2; |
887 | 914 | ||
888 | srbm_status = RREG32(R_000E50_SRBM_STATUS); |
915 | srbm_status = RREG32(R_000E50_SRBM_STATUS); |
889 | grbm_status = RREG32(R_008010_GRBM_STATUS); |
916 | grbm_status = RREG32(R_008010_GRBM_STATUS); |
890 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); |
917 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); |
891 | if (!G_008010_GUI_ACTIVE(grbm_status)) { |
918 | if (!G_008010_GUI_ACTIVE(grbm_status)) { |
892 | r100_gpu_lockup_update(lockup, &rdev->cp); |
919 | radeon_ring_lockup_update(ring); |
893 | return false; |
920 | return false; |
894 | } |
- | |
895 | /* force CP activities */ |
- | |
896 | r = radeon_ring_lock(rdev, 2); |
- | |
897 | if (!r) { |
- | |
898 | /* PACKET2 NOP */ |
- | |
899 | radeon_ring_write(rdev, 0x80000000); |
921 | } |
900 | radeon_ring_write(rdev, 0x80000000); |
- | |
901 | radeon_ring_unlock_commit(rdev); |
- | |
902 | } |
922 | /* force CP activities */ |
903 | rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); |
923 | radeon_ring_force_activity(rdev, ring); |
Line 904... | Line 924... | ||
904 | return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); |
924 | return radeon_ring_test_lockup(rdev, ring); |
905 | } |
925 | } |
906 | 926 | ||
907 | int r600_asic_reset(struct radeon_device *rdev) |
927 | int r600_asic_reset(struct radeon_device *rdev) |
Line 908... | Line 928... | ||
908 | { |
928 | { |
- | 929 | return r600_gpu_soft_reset(rdev); |
|
909 | return r600_gpu_soft_reset(rdev); |
930 | } |
- | 931 | ||
910 | } |
932 | u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
911 | 933 | u32 tiling_pipe_num, |
|
912 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, |
934 | u32 max_rb_num, |
913 | u32 num_backends, |
935 | u32 total_max_rb_num, |
914 | u32 backend_disable_mask) |
936 | u32 disabled_rb_mask) |
915 | { |
937 | { |
916 | u32 backend_map = 0; |
- | |
917 | u32 enabled_backends_mask; |
- | |
918 | u32 enabled_backends_count; |
- | |
Line 919... | Line 938... | ||
919 | u32 cur_pipe; |
938 | u32 rendering_pipe_num, rb_num_width, req_rb_num; |
920 | u32 swizzle_pipe[R6XX_MAX_PIPES]; |
- | |
921 | u32 cur_backend; |
- | |
922 | u32 i; |
- | |
923 | 939 | u32 pipe_rb_ratio, pipe_rb_remain; |
|
924 | if (num_tile_pipes > R6XX_MAX_PIPES) |
- | |
925 | num_tile_pipes = R6XX_MAX_PIPES; |
- | |
926 | if (num_tile_pipes < 1) |
- | |
Line 927... | Line -... | ||
927 | num_tile_pipes = 1; |
- | |
928 | if (num_backends > R6XX_MAX_BACKENDS) |
- | |
929 | num_backends = R6XX_MAX_BACKENDS; |
- | |
930 | if (num_backends < 1) |
- | |
931 | num_backends = 1; |
940 | u32 data = 0, mask = 1 << (max_rb_num - 1); |
932 | - | ||
933 | enabled_backends_mask = 0; |
- | |
934 | enabled_backends_count = 0; |
941 | unsigned i, j; |
935 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { |
- | |
936 | if (((backend_disable_mask >> i) & 1) == 0) { |
- | |
937 | enabled_backends_mask |= (1 << i); |
- | |
938 | ++enabled_backends_count; |
942 | |
939 | } |
- | |
940 | if (enabled_backends_count == num_backends) |
- | |
941 | break; |
- | |
Line 942... | Line 943... | ||
942 | } |
943 | /* mask out the RBs that don't exist on that asic */ |
943 | 944 | disabled_rb_mask |= (0xff << max_rb_num) & 0xff; |
|
Line 944... | Line -... | ||
944 | if (enabled_backends_count == 0) { |
- | |
945 | enabled_backends_mask = 1; |
945 | |
946 | enabled_backends_count = 1; |
- | |
947 | } |
- | |
948 | - | ||
949 | if (enabled_backends_count != num_backends) |
- | |
950 | num_backends = enabled_backends_count; |
- | |
951 | - | ||
952 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); |
- | |
953 | switch (num_tile_pipes) { |
- | |
954 | case 1: |
- | |
955 | swizzle_pipe[0] = 0; |
- | |
956 | break; |
- | |
957 | case 2: |
- | |
958 | swizzle_pipe[0] = 0; |
- | |
959 | swizzle_pipe[1] = 1; |
- | |
960 | break; |
- | |
961 | case 3: |
- | |
962 | swizzle_pipe[0] = 0; |
- | |
963 | swizzle_pipe[1] = 1; |
- | |
964 | swizzle_pipe[2] = 2; |
- | |
965 | break; |
- | |
966 | case 4: |
- | |
967 | swizzle_pipe[0] = 0; |
- | |
968 | swizzle_pipe[1] = 1; |
- | |
969 | swizzle_pipe[2] = 2; |
- | |
970 | swizzle_pipe[3] = 3; |
- | |
971 | break; |
- | |
972 | case 5: |
946 | rendering_pipe_num = 1 << tiling_pipe_num; |
973 | swizzle_pipe[0] = 0; |
947 | req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); |
974 | swizzle_pipe[1] = 1; |
- | |
975 | swizzle_pipe[2] = 2; |
- | |
976 | swizzle_pipe[3] = 3; |
- | |
977 | swizzle_pipe[4] = 4; |
- | |
978 | break; |
- | |
979 | case 6: |
948 | BUG_ON(rendering_pipe_num < req_rb_num); |
980 | swizzle_pipe[0] = 0; |
- | |
981 | swizzle_pipe[1] = 2; |
- | |
982 | swizzle_pipe[2] = 4; |
- | |
983 | swizzle_pipe[3] = 5; |
- | |
984 | swizzle_pipe[4] = 1; |
- | |
985 | swizzle_pipe[5] = 3; |
- | |
986 | break; |
- | |
987 | case 7: |
- | |
988 | swizzle_pipe[0] = 0; |
949 | |
989 | swizzle_pipe[1] = 2; |
- | |
990 | swizzle_pipe[2] = 4; |
- | |
991 | swizzle_pipe[3] = 6; |
950 | pipe_rb_ratio = rendering_pipe_num / req_rb_num; |
992 | swizzle_pipe[4] = 1; |
- | |
993 | swizzle_pipe[5] = 3; |
- | |
994 | swizzle_pipe[6] = 5; |
- | |
995 | break; |
- | |
996 | case 8: |
- | |
997 | swizzle_pipe[0] = 0; |
- | |
998 | swizzle_pipe[1] = 2; |
951 | pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; |
Line 999... | Line 952... | ||
999 | swizzle_pipe[2] = 4; |
952 | |
- | 953 | if (rdev->family <= CHIP_RV740) { |
|
1000 | swizzle_pipe[3] = 6; |
954 | /* r6xx/r7xx */ |
1001 | swizzle_pipe[4] = 1; |
955 | rb_num_width = 2; |
1002 | swizzle_pipe[5] = 3; |
956 | } else { |
1003 | swizzle_pipe[6] = 5; |
957 | /* eg+ */ |
- | 958 | rb_num_width = 4; |
|
- | 959 | } |
|
1004 | swizzle_pipe[7] = 7; |
960 | |
- | 961 | for (i = 0; i < max_rb_num; i++) { |
|
- | 962 | if (!(mask & disabled_rb_mask)) { |
|
1005 | break; |
963 | for (j = 0; j < pipe_rb_ratio; j++) { |
1006 | } |
964 | data <<= rb_num_width; |
1007 | 965 | data |= max_rb_num - i - 1; |
|
Line 1008... | Line 966... | ||
1008 | cur_backend = 0; |
966 | } |
1009 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
967 | if (pipe_rb_remain) { |
Line 1010... | Line 968... | ||
1010 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
968 | data <<= rb_num_width; |
1011 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; |
969 | data |= max_rb_num - i - 1; |
1012 | 970 | pipe_rb_remain--; |
|
Line 1027... | Line 985... | ||
1027 | val >>= 1; |
985 | val >>= 1; |
1028 | } |
986 | } |
1029 | return ret; |
987 | return ret; |
1030 | } |
988 | } |
Line 1031... | Line 989... | ||
1031 | 989 | ||
1032 | void r600_gpu_init(struct radeon_device *rdev) |
990 | static void r600_gpu_init(struct radeon_device *rdev) |
1033 | { |
991 | { |
1034 | u32 tiling_config; |
992 | u32 tiling_config; |
1035 | u32 ramcfg; |
- | |
1036 | u32 backend_map; |
993 | u32 ramcfg; |
1037 | u32 cc_rb_backend_disable; |
994 | u32 cc_rb_backend_disable; |
1038 | u32 cc_gc_shader_pipe_config; |
995 | u32 cc_gc_shader_pipe_config; |
1039 | u32 tmp; |
996 | u32 tmp; |
1040 | int i, j; |
997 | int i, j; |
1041 | u32 sq_config; |
998 | u32 sq_config; |
1042 | u32 sq_gpr_resource_mgmt_1 = 0; |
999 | u32 sq_gpr_resource_mgmt_1 = 0; |
1043 | u32 sq_gpr_resource_mgmt_2 = 0; |
1000 | u32 sq_gpr_resource_mgmt_2 = 0; |
1044 | u32 sq_thread_resource_mgmt = 0; |
1001 | u32 sq_thread_resource_mgmt = 0; |
1045 | u32 sq_stack_resource_mgmt_1 = 0; |
1002 | u32 sq_stack_resource_mgmt_1 = 0; |
- | 1003 | u32 sq_stack_resource_mgmt_2 = 0; |
|
Line 1046... | Line 1004... | ||
1046 | u32 sq_stack_resource_mgmt_2 = 0; |
1004 | u32 disabled_rb_mask; |
1047 | 1005 | ||
1048 | /* FIXME: implement */ |
1006 | rdev->config.r600.tiling_group_size = 256; |
1049 | switch (rdev->family) { |
1007 | switch (rdev->family) { |
1050 | case CHIP_R600: |
1008 | case CHIP_R600: |
1051 | rdev->config.r600.max_pipes = 4; |
1009 | rdev->config.r600.max_pipes = 4; |
Line 1147... | Line 1105... | ||
1147 | } |
1105 | } |
1148 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
1106 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
1149 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1107 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1150 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1108 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1151 | tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
1109 | tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
1152 | if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) |
- | |
1153 | rdev->config.r600.tiling_group_size = 512; |
- | |
1154 | else |
1110 | |
1155 | rdev->config.r600.tiling_group_size = 256; |
- | |
1156 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
1111 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
1157 | if (tmp > 3) { |
1112 | if (tmp > 3) { |
1158 | tiling_config |= ROW_TILING(3); |
1113 | tiling_config |= ROW_TILING(3); |
1159 | tiling_config |= SAMPLE_SPLIT(3); |
1114 | tiling_config |= SAMPLE_SPLIT(3); |
1160 | } else { |
1115 | } else { |
Line 1162... | Line 1117... | ||
1162 | tiling_config |= SAMPLE_SPLIT(tmp); |
1117 | tiling_config |= SAMPLE_SPLIT(tmp); |
1163 | } |
1118 | } |
1164 | tiling_config |= BANK_SWAPS(1); |
1119 | tiling_config |= BANK_SWAPS(1); |
Line 1165... | Line 1120... | ||
1165 | 1120 | ||
1166 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
1121 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
- | 1122 | tmp = R6XX_MAX_BACKENDS - |
|
- | 1123 | r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); |
|
- | 1124 | if (tmp < rdev->config.r600.max_backends) { |
|
- | 1125 | rdev->config.r600.max_backends = tmp; |
|
- | 1126 | } |
|
- | 1127 | ||
- | 1128 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; |
|
- | 1129 | tmp = R6XX_MAX_PIPES - |
|
- | 1130 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); |
|
- | 1131 | if (tmp < rdev->config.r600.max_pipes) { |
|
- | 1132 | rdev->config.r600.max_pipes = tmp; |
|
- | 1133 | } |
|
- | 1134 | tmp = R6XX_MAX_SIMDS - |
|
- | 1135 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); |
|
- | 1136 | if (tmp < rdev->config.r600.max_simds) { |
|
- | 1137 | rdev->config.r600.max_simds = tmp; |
|
- | 1138 | } |
|
1167 | cc_rb_backend_disable |= |
1139 | |
- | 1140 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; |
|
- | 1141 | tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
|
- | 1142 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, |
|
- | 1143 | R6XX_MAX_BACKENDS, disabled_rb_mask); |
|
- | 1144 | tiling_config |= tmp << 16; |
|
Line 1168... | Line -... | ||
1168 | BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); |
- | |
1169 | - | ||
1170 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
- | |
1171 | cc_gc_shader_pipe_config |= |
- | |
1172 | INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); |
- | |
1173 | cc_gc_shader_pipe_config |= |
- | |
1174 | INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); |
- | |
1175 | - | ||
1176 | backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, |
- | |
1177 | (R6XX_MAX_BACKENDS - |
- | |
1178 | r600_count_pipe_bits((cc_rb_backend_disable & |
- | |
1179 | R6XX_MAX_BACKENDS_MASK) >> 16)), |
1145 | rdev->config.r600.backend_map = tmp; |
1180 | (cc_rb_backend_disable >> 16)); |
- | |
1181 | rdev->config.r600.tile_config = tiling_config; |
- | |
1182 | rdev->config.r600.backend_map = backend_map; |
1146 | |
1183 | tiling_config |= BACKEND_MAP(backend_map); |
1147 | rdev->config.r600.tile_config = tiling_config; |
1184 | WREG32(GB_TILING_CONFIG, tiling_config); |
1148 | WREG32(GB_TILING_CONFIG, tiling_config); |
Line 1185... | Line -... | ||
1185 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
- | |
1186 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); |
- | |
1187 | - | ||
1188 | /* Setup pipes */ |
- | |
1189 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
- | |
1190 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
1149 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
1191 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
1150 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); |
1192 | 1151 | ||
Line 1193... | Line 1152... | ||
1193 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
1152 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
Line 1431... | Line 1390... | ||
1431 | 1390 | ||
1432 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
1391 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
1433 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
1392 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
1434 | NUM_CLIP_SEQ(3))); |
1393 | NUM_CLIP_SEQ(3))); |
- | 1394 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); |
|
1435 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); |
1395 | WREG32(VC_ENHANCE, 0); |
Line 1436... | Line 1396... | ||
1436 | } |
1396 | } |
1437 | 1397 | ||
Line 1670... | Line 1630... | ||
1670 | return 0; |
1630 | return 0; |
1671 | } |
1631 | } |
Line 1672... | Line 1632... | ||
1672 | 1632 | ||
1673 | int r600_cp_start(struct radeon_device *rdev) |
1633 | int r600_cp_start(struct radeon_device *rdev) |
- | 1634 | { |
|
1674 | { |
1635 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
1675 | int r; |
1636 | int r; |
Line 1676... | Line 1637... | ||
1676 | uint32_t cp_me; |
1637 | uint32_t cp_me; |
1677 | 1638 | ||
1678 | r = radeon_ring_lock(rdev, 7); |
1639 | r = radeon_ring_lock(rdev, ring, 7); |
1679 | if (r) { |
1640 | if (r) { |
1680 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1641 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1681 | return r; |
1642 | return r; |
1682 | } |
1643 | } |
1683 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
1644 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
1684 | radeon_ring_write(rdev, 0x1); |
1645 | radeon_ring_write(ring, 0x1); |
1685 | if (rdev->family >= CHIP_RV770) { |
1646 | if (rdev->family >= CHIP_RV770) { |
1686 | radeon_ring_write(rdev, 0x0); |
1647 | radeon_ring_write(ring, 0x0); |
1687 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); |
1648 | radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); |
1688 | } else { |
1649 | } else { |
1689 | radeon_ring_write(rdev, 0x3); |
1650 | radeon_ring_write(ring, 0x3); |
1690 | radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); |
1651 | radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); |
1691 | } |
1652 | } |
1692 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
1653 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
1693 | radeon_ring_write(rdev, 0); |
1654 | radeon_ring_write(ring, 0); |
Line 1694... | Line 1655... | ||
1694 | radeon_ring_write(rdev, 0); |
1655 | radeon_ring_write(ring, 0); |
1695 | radeon_ring_unlock_commit(rdev); |
1656 | radeon_ring_unlock_commit(rdev, ring); |
1696 | 1657 | ||
1697 | cp_me = 0xff; |
1658 | cp_me = 0xff; |
Line 1698... | Line 1659... | ||
1698 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
1659 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
1699 | return 0; |
1660 | return 0; |
- | 1661 | } |
|
1700 | } |
1662 | |
1701 | 1663 | int r600_cp_resume(struct radeon_device *rdev) |
|
1702 | int r600_cp_resume(struct radeon_device *rdev) |
1664 | { |
Line 1703... | Line 1665... | ||
1703 | { |
1665 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Line 1710... | Line 1672... | ||
1710 | RREG32(GRBM_SOFT_RESET); |
1672 | RREG32(GRBM_SOFT_RESET); |
1711 | mdelay(15); |
1673 | mdelay(15); |
1712 | WREG32(GRBM_SOFT_RESET, 0); |
1674 | WREG32(GRBM_SOFT_RESET, 0); |
Line 1713... | Line 1675... | ||
1713 | 1675 | ||
1714 | /* Set ring buffer size */ |
1676 | /* Set ring buffer size */ |
1715 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); |
1677 | rb_bufsz = drm_order(ring->ring_size / 8); |
1716 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1678 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1717 | #ifdef __BIG_ENDIAN |
1679 | #ifdef __BIG_ENDIAN |
1718 | tmp |= BUF_SWAP_32BIT; |
1680 | tmp |= BUF_SWAP_32BIT; |
1719 | #endif |
1681 | #endif |
1720 | WREG32(CP_RB_CNTL, tmp); |
1682 | WREG32(CP_RB_CNTL, tmp); |
Line 1721... | Line 1683... | ||
1721 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
1683 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
1722 | 1684 | ||
Line 1723... | Line 1685... | ||
1723 | /* Set the write pointer delay */ |
1685 | /* Set the write pointer delay */ |
1724 | WREG32(CP_RB_WPTR_DELAY, 0); |
1686 | WREG32(CP_RB_WPTR_DELAY, 0); |
1725 | 1687 | ||
- | 1688 | /* Initialize the ring buffer's read and write pointers */ |
|
1726 | /* Initialize the ring buffer's read and write pointers */ |
1689 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
Line 1727... | Line 1690... | ||
1727 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
1690 | WREG32(CP_RB_RPTR_WR, 0); |
1728 | WREG32(CP_RB_RPTR_WR, 0); |
1691 | ring->wptr = 0; |
1729 | WREG32(CP_RB_WPTR, 0); |
1692 | WREG32(CP_RB_WPTR, ring->wptr); |
1730 | 1693 | ||
Line 1742... | Line 1705... | ||
1742 | } |
1705 | } |
Line 1743... | Line 1706... | ||
1743 | 1706 | ||
1744 | mdelay(1); |
1707 | mdelay(1); |
Line 1745... | Line 1708... | ||
1745 | WREG32(CP_RB_CNTL, tmp); |
1708 | WREG32(CP_RB_CNTL, tmp); |
1746 | 1709 | ||
Line 1747... | Line 1710... | ||
1747 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); |
1710 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
1748 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
- | |
Line 1749... | Line 1711... | ||
1749 | 1711 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
|
1750 | rdev->cp.rptr = RREG32(CP_RB_RPTR); |
1712 | |
1751 | rdev->cp.wptr = RREG32(CP_RB_WPTR); |
1713 | ring->rptr = RREG32(CP_RB_RPTR); |
1752 | 1714 | ||
1753 | r600_cp_start(rdev); |
1715 | r600_cp_start(rdev); |
1754 | rdev->cp.ready = true; |
1716 | ring->ready = true; |
1755 | r = radeon_ring_test(rdev); |
1717 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
1756 | if (r) { |
1718 | if (r) { |
1757 | rdev->cp.ready = false; |
1719 | ring->ready = false; |
Line 1758... | Line -... | ||
1758 | return r; |
- | |
1759 | } |
- | |
1760 | return 0; |
- | |
1761 | } |
- | |
1762 | - | ||
1763 | void r600_cp_commit(struct radeon_device *rdev) |
- | |
1764 | { |
1720 | return r; |
1765 | WREG32(CP_RB_WPTR, rdev->cp.wptr); |
1721 | } |
1766 | (void)RREG32(CP_RB_WPTR); |
1722 | return 0; |
- | 1723 | } |
|
Line 1767... | Line 1724... | ||
1767 | } |
1724 | |
1768 | 1725 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) |
|
1769 | void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) |
1726 | { |
1770 | { |
1727 | u32 rb_bufsz; |
1771 | u32 rb_bufsz; |
1728 | int r; |
- | 1729 | ||
- | 1730 | /* Align ring size */ |
|
- | 1731 | rb_bufsz = drm_order(ring_size / 8); |
|
- | 1732 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
|
- | 1733 | ring->ring_size = ring_size; |
|
- | 1734 | ring->align_mask = 16 - 1; |
|
- | 1735 | ||
- | 1736 | if (radeon_ring_supports_scratch_reg(rdev, ring)) { |
|
1772 | 1737 | r = radeon_scratch_get(rdev, &ring->rptr_save_reg); |
|
Line 1773... | Line 1738... | ||
1773 | /* Align ring size */ |
1738 | if (r) { |
1774 | rb_bufsz = drm_order(ring_size / 8); |
1739 | DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); |
- | 1740 | ring->rptr_save_reg = 0; |
|
1775 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
1741 | } |
1776 | rdev->cp.ring_size = ring_size; |
1742 | } |
- | 1743 | } |
|
1777 | rdev->cp.align_mask = 16 - 1; |
1744 | |
Line 1778... | Line 1745... | ||
1778 | } |
1745 | void r600_cp_fini(struct radeon_device *rdev) |
1779 | 1746 | { |
|
Line 1797... | Line 1764... | ||
1797 | rdev->scratch.free[i] = true; |
1764 | rdev->scratch.free[i] = true; |
1798 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
1765 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
1799 | } |
1766 | } |
1800 | } |
1767 | } |
Line 1801... | Line 1768... | ||
1801 | 1768 | ||
1802 | int r600_ring_test(struct radeon_device *rdev) |
1769 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
1803 | { |
1770 | { |
1804 | uint32_t scratch; |
1771 | uint32_t scratch; |
1805 | uint32_t tmp = 0; |
1772 | uint32_t tmp = 0; |
1806 | unsigned i; |
1773 | unsigned i; |
Line 1810... | Line 1777... | ||
1810 | if (r) { |
1777 | if (r) { |
1811 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
1778 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
1812 | return r; |
1779 | return r; |
1813 | } |
1780 | } |
1814 | WREG32(scratch, 0xCAFEDEAD); |
1781 | WREG32(scratch, 0xCAFEDEAD); |
1815 | r = radeon_ring_lock(rdev, 3); |
1782 | r = radeon_ring_lock(rdev, ring, 3); |
1816 | if (r) { |
1783 | if (r) { |
1817 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1784 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); |
1818 | radeon_scratch_free(rdev, scratch); |
1785 | radeon_scratch_free(rdev, scratch); |
1819 | return r; |
1786 | return r; |
1820 | } |
1787 | } |
1821 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1788 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1822 | radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
1789 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
1823 | radeon_ring_write(rdev, 0xDEADBEEF); |
1790 | radeon_ring_write(ring, 0xDEADBEEF); |
1824 | radeon_ring_unlock_commit(rdev); |
1791 | radeon_ring_unlock_commit(rdev, ring); |
1825 | for (i = 0; i < rdev->usec_timeout; i++) { |
1792 | for (i = 0; i < rdev->usec_timeout; i++) { |
1826 | tmp = RREG32(scratch); |
1793 | tmp = RREG32(scratch); |
1827 | if (tmp == 0xDEADBEEF) |
1794 | if (tmp == 0xDEADBEEF) |
1828 | break; |
1795 | break; |
1829 | DRM_UDELAY(1); |
1796 | DRM_UDELAY(1); |
1830 | } |
1797 | } |
1831 | if (i < rdev->usec_timeout) { |
1798 | if (i < rdev->usec_timeout) { |
1832 | DRM_INFO("ring test succeeded in %d usecs\n", i); |
1799 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
1833 | } else { |
1800 | } else { |
1834 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
1801 | DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
1835 | scratch, tmp); |
1802 | ring->idx, scratch, tmp); |
1836 | r = -EINVAL; |
1803 | r = -EINVAL; |
1837 | } |
1804 | } |
1838 | radeon_scratch_free(rdev, scratch); |
1805 | radeon_scratch_free(rdev, scratch); |
1839 | return r; |
1806 | return r; |
1840 | } |
1807 | } |
Line 1841... | Line 1808... | ||
1841 | 1808 | ||
1842 | void r600_fence_ring_emit(struct radeon_device *rdev, |
1809 | void r600_fence_ring_emit(struct radeon_device *rdev, |
1843 | struct radeon_fence *fence) |
1810 | struct radeon_fence *fence) |
- | 1811 | { |
|
- | 1812 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
|
1844 | { |
1813 | |
1845 | if (rdev->wb.use_event) { |
1814 | if (rdev->wb.use_event) { |
- | 1815 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
|
- | 1816 | /* flush read cache over gart */ |
|
- | 1817 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
|
- | 1818 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | |
|
- | 1819 | PACKET3_VC_ACTION_ENA | |
|
- | 1820 | PACKET3_SH_ACTION_ENA); |
|
- | 1821 | radeon_ring_write(ring, 0xFFFFFFFF); |
|
1846 | u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + |
1822 | radeon_ring_write(ring, 0); |
1847 | (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base); |
1823 | radeon_ring_write(ring, 10); /* poll interval */ |
1848 | /* EVENT_WRITE_EOP - flush caches, send int */ |
1824 | /* EVENT_WRITE_EOP - flush caches, send int */ |
1849 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
1825 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
1850 | radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
1826 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
1851 | radeon_ring_write(rdev, addr & 0xffffffff); |
1827 | radeon_ring_write(ring, addr & 0xffffffff); |
1852 | radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
1828 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
1853 | radeon_ring_write(rdev, fence->seq); |
1829 | radeon_ring_write(ring, fence->seq); |
1854 | radeon_ring_write(rdev, 0); |
1830 | radeon_ring_write(ring, 0); |
- | 1831 | } else { |
|
- | 1832 | /* flush read cache over gart */ |
|
- | 1833 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
|
- | 1834 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | |
|
- | 1835 | PACKET3_VC_ACTION_ENA | |
|
- | 1836 | PACKET3_SH_ACTION_ENA); |
|
- | 1837 | radeon_ring_write(ring, 0xFFFFFFFF); |
|
- | 1838 | radeon_ring_write(ring, 0); |
|
1855 | } else { |
1839 | radeon_ring_write(ring, 10); /* poll interval */ |
1856 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); |
1840 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); |
1857 | radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); |
1841 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); |
1858 | /* wait for 3D idle clean */ |
1842 | /* wait for 3D idle clean */ |
1859 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1843 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1860 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
1844 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
1861 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
1845 | radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
1862 | /* Emit fence sequence & fire IRQ */ |
1846 | /* Emit fence sequence & fire IRQ */ |
1863 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1847 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1864 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
1848 | radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
1865 | radeon_ring_write(rdev, fence->seq); |
1849 | radeon_ring_write(ring, fence->seq); |
1866 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
1850 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
1867 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); |
1851 | radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); |
1868 | radeon_ring_write(rdev, RB_INT_STAT); |
1852 | radeon_ring_write(ring, RB_INT_STAT); |
1869 | } |
1853 | } |
Line -... | Line 1854... | ||
- | 1854 | } |
|
- | 1855 | ||
- | 1856 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
|
- | 1857 | struct radeon_ring *ring, |
|
- | 1858 | struct radeon_semaphore *semaphore, |
|
- | 1859 | bool emit_wait) |
|
- | 1860 | { |
|
- | 1861 | uint64_t addr = semaphore->gpu_addr; |
|
- | 1862 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; |
|
- | 1863 | ||
- | 1864 | if (rdev->family < CHIP_CAYMAN) |
|
- | 1865 | sel |= PACKET3_SEM_WAIT_ON_SIGNAL; |
|
- | 1866 | ||
- | 1867 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); |
|
- | 1868 | radeon_ring_write(ring, addr & 0xffffffff); |
|
- | 1869 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); |
|
1870 | } |
1870 | } |
- | 1871 | ||
1871 | 1872 | int r600_copy_blit(struct radeon_device *rdev, |
|
- | 1873 | uint64_t src_offset, |
|
1872 | int r600_copy_blit(struct radeon_device *rdev, |
1874 | uint64_t dst_offset, |
1873 | uint64_t src_offset, uint64_t dst_offset, |
1875 | unsigned num_gpu_pages, |
- | 1876 | struct radeon_fence **fence) |
|
- | 1877 | { |
|
1874 | unsigned num_pages, struct radeon_fence *fence) |
1878 | struct radeon_semaphore *sem = NULL; |
Line 1875... | Line -... | ||
1875 | { |
- | |
1876 | int r; |
- | |
1877 | 1879 | struct radeon_sa_bo *vb = NULL; |
|
1878 | mutex_lock(&rdev->r600_blit.mutex); |
1880 | int r; |
1879 | rdev->r600_blit.vb_ib = NULL; |
- | |
1880 | r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); |
- | |
1881 | if (r) { |
- | |
1882 | // if (rdev->r600_blit.vb_ib) |
1881 | |
1883 | // radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
1882 | r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); |
1884 | mutex_unlock(&rdev->r600_blit.mutex); |
1883 | if (r) { |
1885 | return r; |
1884 | return r; |
1886 | } |
- | |
1887 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
1885 | } |
1888 | r600_blit_done_copy(rdev, fence); |
1886 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); |
Line 1889... | Line 1887... | ||
1889 | mutex_unlock(&rdev->r600_blit.mutex); |
1887 | r600_blit_done_copy(rdev, fence, vb, sem); |
1890 | return 0; |
1888 | return 0; |
Line 1901... | Line 1899... | ||
1901 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) |
1899 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) |
1902 | { |
1900 | { |
1903 | /* FIXME: implement */ |
1901 | /* FIXME: implement */ |
1904 | } |
1902 | } |
Line 1905... | Line 1903... | ||
1905 | 1903 | ||
1906 | int r600_startup(struct radeon_device *rdev) |
1904 | static int r600_startup(struct radeon_device *rdev) |
- | 1905 | { |
|
1907 | { |
1906 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Line 1908... | Line 1907... | ||
1908 | int r; |
1907 | int r; |
1909 | 1908 | ||
Line 1928... | Line 1927... | ||
1928 | } |
1927 | } |
1929 | r600_gpu_init(rdev); |
1928 | r600_gpu_init(rdev); |
1930 | r = r600_blit_init(rdev); |
1929 | r = r600_blit_init(rdev); |
1931 | if (r) { |
1930 | if (r) { |
1932 | // r600_blit_fini(rdev); |
1931 | // r600_blit_fini(rdev); |
1933 | rdev->asic->copy = NULL; |
1932 | rdev->asic->copy.copy = NULL; |
1934 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1933 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1935 | } |
1934 | } |
Line 1936... | Line -... | ||
1936 | - | ||
1937 | r = r600_video_init(rdev); |
- | |
1938 | if (r) { |
- | |
1939 | // r600_video_fini(rdev); |
- | |
1940 | // rdev->asic->copy = NULL; |
- | |
1941 | dev_warn(rdev->dev, "failed video blitter (%d) falling back to memcpy\n", r); |
- | |
1942 | } |
- | |
1943 | 1935 | ||
1944 | /* allocate wb buffer */ |
1936 | /* allocate wb buffer */ |
1945 | r = radeon_wb_init(rdev); |
1937 | r = radeon_wb_init(rdev); |
1946 | if (r) |
1938 | if (r) |
Line 1953... | Line 1945... | ||
1953 | // radeon_irq_kms_fini(rdev); |
1945 | // radeon_irq_kms_fini(rdev); |
1954 | return r; |
1946 | return r; |
1955 | } |
1947 | } |
1956 | r600_irq_set(rdev); |
1948 | r600_irq_set(rdev); |
Line 1957... | Line 1949... | ||
1957 | 1949 | ||
- | 1950 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
|
- | 1951 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
|
- | 1952 | 0, 0xfffff, RADEON_CP_PACKET2); |
|
1958 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1953 | |
1959 | if (r) |
1954 | if (r) |
1960 | return r; |
1955 | return r; |
1961 | r = r600_cp_load_microcode(rdev); |
1956 | r = r600_cp_load_microcode(rdev); |
1962 | if (r) |
1957 | if (r) |
Line 1997... | Line 1992... | ||
1997 | int r; |
1992 | int r; |
Line 1998... | Line 1993... | ||
1998 | 1993 | ||
1999 | if (r600_debugfs_mc_info_init(rdev)) { |
1994 | if (r600_debugfs_mc_info_init(rdev)) { |
2000 | DRM_ERROR("Failed to register debugfs file for mc !\n"); |
1995 | DRM_ERROR("Failed to register debugfs file for mc !\n"); |
2001 | } |
- | |
2002 | /* This don't do much */ |
- | |
2003 | r = radeon_gem_init(rdev); |
- | |
2004 | if (r) |
- | |
2005 | return r; |
1996 | } |
2006 | /* Read BIOS */ |
1997 | /* Read BIOS */ |
2007 | if (!radeon_get_bios(rdev)) { |
1998 | if (!radeon_get_bios(rdev)) { |
2008 | if (ASIC_IS_AVIVO(rdev)) |
1999 | if (ASIC_IS_AVIVO(rdev)) |
2009 | return -EINVAL; |
2000 | return -EINVAL; |
Line 2050... | Line 2041... | ||
2050 | 2041 | ||
2051 | r = radeon_irq_kms_init(rdev); |
2042 | r = radeon_irq_kms_init(rdev); |
2052 | if (r) |
2043 | if (r) |
Line 2053... | Line 2044... | ||
2053 | return r; |
2044 | return r; |
2054 | 2045 | ||
Line 2055... | Line 2046... | ||
2055 | rdev->cp.ring_obj = NULL; |
2046 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
2056 | r600_ring_init(rdev, 1024 * 1024); |
2047 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
Line 2057... | Line 2048... | ||
2057 | 2048 | ||
Line 2064... | Line 2055... | ||
2064 | 2055 | ||
2065 | rdev->accel_working = true; |
2056 | rdev->accel_working = true; |
2066 | r = r600_startup(rdev); |
2057 | r = r600_startup(rdev); |
2067 | if (r) { |
2058 | if (r) { |
2068 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
- | |
2069 | // r600_suspend(rdev); |
- | |
2070 | // r600_wb_fini(rdev); |
- | |
2071 | // radeon_ring_fini(rdev); |
2059 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
2072 | r600_pcie_gart_fini(rdev); |
2060 | r600_pcie_gart_fini(rdev); |
2073 | rdev->accel_working = false; |
2061 | rdev->accel_working = false; |
2074 | } |
- | |
2075 | if (rdev->accel_working) { |
- | |
2076 | r = radeon_ib_pool_init(rdev); |
- | |
2077 | if (r) { |
- | |
2078 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
- | |
2079 | rdev->accel_working = false; |
- | |
2080 | } else { |
- | |
2081 | r = r600_ib_test(rdev); |
- | |
2082 | if (r) { |
- | |
2083 | dev_err(rdev->dev, "IB test failed (%d).\n", r); |
- | |
2084 | rdev->accel_working = false; |
- | |
2085 | } |
- | |
2086 | } |
- | |
Line 2087... | Line 2062... | ||
2087 | } |
2062 | } |
2088 | 2063 | ||
Line 2089... | Line 2064... | ||
2089 | return 0; |
2064 | return 0; |
2090 | } |
2065 | } |
2091 | 2066 | ||
2092 | /* |
2067 | /* |
2093 | * CS stuff |
2068 | * CS stuff |
- | 2069 | */ |
|
- | 2070 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
|
- | 2071 | { |
|
2094 | */ |
2072 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
- | 2073 | u32 next_rptr; |
|
- | 2074 | ||
- | 2075 | if (ring->rptr_save_reg) { |
|
- | 2076 | next_rptr = ring->wptr + 3 + 4; |
|
- | 2077 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
|
- | 2078 | radeon_ring_write(ring, ((ring->rptr_save_reg - |
|
- | 2079 | PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
|
- | 2080 | radeon_ring_write(ring, next_rptr); |
|
- | 2081 | } else if (rdev->wb.enabled) { |
|
- | 2082 | next_rptr = ring->wptr + 5 + 4; |
|
- | 2083 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); |
|
- | 2084 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
|
- | 2085 | radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); |
|
- | 2086 | radeon_ring_write(ring, next_rptr); |
|
2095 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
2087 | radeon_ring_write(ring, 0); |
2096 | { |
2088 | } |
2097 | /* FIXME: implement */ |
2089 | |
2098 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2090 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2099 | radeon_ring_write(rdev, |
2091 | radeon_ring_write(ring, |
2100 | #ifdef __BIG_ENDIAN |
2092 | #ifdef __BIG_ENDIAN |
2101 | (2 << 0) | |
2093 | (2 << 0) | |
2102 | #endif |
2094 | #endif |
2103 | (ib->gpu_addr & 0xFFFFFFFC)); |
2095 | (ib->gpu_addr & 0xFFFFFFFC)); |
Line 2104... | Line 2096... | ||
2104 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); |
2096 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
2105 | radeon_ring_write(rdev, ib->length_dw); |
2097 | radeon_ring_write(ring, ib->length_dw); |
2106 | } |
2098 | } |
2107 | 2099 | ||
2108 | int r600_ib_test(struct radeon_device *rdev) |
2100 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
2109 | { |
2101 | { |
2110 | struct radeon_ib *ib; |
2102 | struct radeon_ib ib; |
Line 2117... | Line 2109... | ||
2117 | if (r) { |
2109 | if (r) { |
2118 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
2110 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
2119 | return r; |
2111 | return r; |
2120 | } |
2112 | } |
2121 | WREG32(scratch, 0xCAFEDEAD); |
2113 | WREG32(scratch, 0xCAFEDEAD); |
2122 | r = radeon_ib_get(rdev, &ib); |
2114 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
2123 | if (r) { |
2115 | if (r) { |
2124 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
2116 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
2125 | return r; |
2117 | goto free_scratch; |
2126 | } |
2118 | } |
2127 | ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); |
2119 | ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); |
2128 | ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
2120 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
2129 | ib->ptr[2] = 0xDEADBEEF; |
2121 | ib.ptr[2] = 0xDEADBEEF; |
2130 | ib->ptr[3] = PACKET2(0); |
- | |
2131 | ib->ptr[4] = PACKET2(0); |
- | |
2132 | ib->ptr[5] = PACKET2(0); |
- | |
2133 | ib->ptr[6] = PACKET2(0); |
- | |
2134 | ib->ptr[7] = PACKET2(0); |
- | |
2135 | ib->ptr[8] = PACKET2(0); |
- | |
2136 | ib->ptr[9] = PACKET2(0); |
- | |
2137 | ib->ptr[10] = PACKET2(0); |
- | |
2138 | ib->ptr[11] = PACKET2(0); |
- | |
2139 | ib->ptr[12] = PACKET2(0); |
- | |
2140 | ib->ptr[13] = PACKET2(0); |
- | |
2141 | ib->ptr[14] = PACKET2(0); |
- | |
2142 | ib->ptr[15] = PACKET2(0); |
- | |
2143 | ib->length_dw = 16; |
2122 | ib.length_dw = 3; |
2144 | r = radeon_ib_schedule(rdev, ib); |
2123 | r = radeon_ib_schedule(rdev, &ib, NULL); |
2145 | if (r) { |
2124 | if (r) { |
2146 | radeon_scratch_free(rdev, scratch); |
- | |
2147 | radeon_ib_free(rdev, &ib); |
- | |
2148 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
2125 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
2149 | return r; |
2126 | goto free_ib; |
2150 | } |
2127 | } |
2151 | r = radeon_fence_wait(ib->fence, false); |
2128 | r = radeon_fence_wait(ib.fence, false); |
2152 | if (r) { |
2129 | if (r) { |
2153 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
2130 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
2154 | return r; |
2131 | goto free_ib; |
2155 | } |
2132 | } |
2156 | for (i = 0; i < rdev->usec_timeout; i++) { |
2133 | for (i = 0; i < rdev->usec_timeout; i++) { |
2157 | tmp = RREG32(scratch); |
2134 | tmp = RREG32(scratch); |
2158 | if (tmp == 0xDEADBEEF) |
2135 | if (tmp == 0xDEADBEEF) |
2159 | break; |
2136 | break; |
2160 | DRM_UDELAY(1); |
2137 | DRM_UDELAY(1); |
2161 | } |
2138 | } |
2162 | if (i < rdev->usec_timeout) { |
2139 | if (i < rdev->usec_timeout) { |
2163 | DRM_INFO("ib test succeeded in %u usecs\n", i); |
2140 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
2164 | } else { |
2141 | } else { |
2165 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
2142 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
2166 | scratch, tmp); |
2143 | scratch, tmp); |
2167 | r = -EINVAL; |
2144 | r = -EINVAL; |
2168 | } |
2145 | } |
2169 | radeon_scratch_free(rdev, scratch); |
2146 | free_ib: |
2170 | radeon_ib_free(rdev, &ib); |
2147 | radeon_ib_free(rdev, &ib); |
- | 2148 | free_scratch: |
|
- | 2149 | radeon_scratch_free(rdev, scratch); |
|
2171 | return r; |
2150 | return r; |
2172 | } |
2151 | } |
Line 2173... | Line 2152... | ||
2173 | 2152 | ||
2174 | /* |
2153 | /* |
Line 2192... | Line 2171... | ||
2192 | rdev->ih.ring_size = ring_size; |
2171 | rdev->ih.ring_size = ring_size; |
2193 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
2172 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
2194 | rdev->ih.rptr = 0; |
2173 | rdev->ih.rptr = 0; |
2195 | } |
2174 | } |
Line 2196... | Line 2175... | ||
2196 | 2175 | ||
2197 | static int r600_ih_ring_alloc(struct radeon_device *rdev) |
2176 | int r600_ih_ring_alloc(struct radeon_device *rdev) |
2198 | { |
2177 | { |
Line 2199... | Line 2178... | ||
2199 | int r; |
2178 | int r; |
2200 | 2179 | ||
2201 | /* Allocate ring buffer */ |
2180 | /* Allocate ring buffer */ |
2202 | if (rdev->ih.ring_obj == NULL) { |
2181 | if (rdev->ih.ring_obj == NULL) { |
2203 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
2182 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
2204 | PAGE_SIZE, true, |
2183 | PAGE_SIZE, true, |
2205 | RADEON_GEM_DOMAIN_GTT, |
2184 | RADEON_GEM_DOMAIN_GTT, |
2206 | &rdev->ih.ring_obj); |
2185 | NULL, &rdev->ih.ring_obj); |
2207 | if (r) { |
2186 | if (r) { |
2208 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); |
2187 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); |
2209 | return r; |
2188 | return r; |
Line 2228... | Line 2207... | ||
2228 | } |
2207 | } |
2229 | } |
2208 | } |
2230 | return 0; |
2209 | return 0; |
2231 | } |
2210 | } |
Line 2232... | Line 2211... | ||
2232 | 2211 | ||
2233 | static void r600_ih_ring_fini(struct radeon_device *rdev) |
2212 | void r600_ih_ring_fini(struct radeon_device *rdev) |
2234 | { |
2213 | { |
2235 | int r; |
2214 | int r; |
2236 | if (rdev->ih.ring_obj) { |
2215 | if (rdev->ih.ring_obj) { |
2237 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2216 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
Line 2252... | Line 2231... | ||
2252 | if ((rdev->family >= CHIP_RV770) && |
2231 | if ((rdev->family >= CHIP_RV770) && |
2253 | (rdev->family <= CHIP_RV740)) { |
2232 | (rdev->family <= CHIP_RV740)) { |
2254 | /* r7xx asics need to soft reset RLC before halting */ |
2233 | /* r7xx asics need to soft reset RLC before halting */ |
2255 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); |
2234 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); |
2256 | RREG32(SRBM_SOFT_RESET); |
2235 | RREG32(SRBM_SOFT_RESET); |
2257 | udelay(15000); |
2236 | mdelay(15); |
2258 | WREG32(SRBM_SOFT_RESET, 0); |
2237 | WREG32(SRBM_SOFT_RESET, 0); |
2259 | RREG32(SRBM_SOFT_RESET); |
2238 | RREG32(SRBM_SOFT_RESET); |
2260 | } |
2239 | } |
Line 2261... | Line 2240... | ||
2261 | 2240 | ||
Line 2275... | Line 2254... | ||
2275 | if (!rdev->rlc_fw) |
2254 | if (!rdev->rlc_fw) |
2276 | return -EINVAL; |
2255 | return -EINVAL; |
Line 2277... | Line 2256... | ||
2277 | 2256 | ||
Line 2278... | Line -... | ||
2278 | r600_rlc_stop(rdev); |
- | |
2279 | 2257 | r600_rlc_stop(rdev); |
|
- | 2258 | ||
- | 2259 | WREG32(RLC_HB_CNTL, 0); |
|
- | 2260 | ||
- | 2261 | if (rdev->family == CHIP_ARUBA) { |
|
- | 2262 | WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); |
|
- | 2263 | WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); |
|
- | 2264 | } |
|
2280 | WREG32(RLC_HB_BASE, 0); |
2265 | if (rdev->family <= CHIP_CAYMAN) { |
2281 | WREG32(RLC_HB_CNTL, 0); |
2266 | WREG32(RLC_HB_BASE, 0); |
- | 2267 | WREG32(RLC_HB_RPTR, 0); |
|
2282 | WREG32(RLC_HB_RPTR, 0); |
2268 | WREG32(RLC_HB_WPTR, 0); |
2283 | WREG32(RLC_HB_WPTR, 0); |
2269 | } |
2284 | if (rdev->family <= CHIP_CAICOS) { |
2270 | if (rdev->family <= CHIP_CAICOS) { |
2285 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); |
2271 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); |
2286 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); |
2272 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); |
2287 | } |
2273 | } |
Line 2288... | Line 2274... | ||
2288 | WREG32(RLC_MC_CNTL, 0); |
2274 | WREG32(RLC_MC_CNTL, 0); |
2289 | WREG32(RLC_UCODE_CNTL, 0); |
2275 | WREG32(RLC_UCODE_CNTL, 0); |
- | 2276 | ||
- | 2277 | fw_data = (const __be32 *)rdev->rlc_fw->data; |
|
- | 2278 | if (rdev->family >= CHIP_ARUBA) { |
|
- | 2279 | for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { |
|
- | 2280 | WREG32(RLC_UCODE_ADDR, i); |
|
2290 | 2281 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
|
2291 | fw_data = (const __be32 *)rdev->rlc_fw->data; |
2282 | } |
2292 | if (rdev->family >= CHIP_CAYMAN) { |
2283 | } else if (rdev->family >= CHIP_CAYMAN) { |
2293 | for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { |
2284 | for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { |
2294 | WREG32(RLC_UCODE_ADDR, i); |
2285 | WREG32(RLC_UCODE_ADDR, i); |
Line 2340... | Line 2331... | ||
2340 | WREG32(IH_CNTL, ih_cntl); |
2331 | WREG32(IH_CNTL, ih_cntl); |
2341 | /* set rptr, wptr to 0 */ |
2332 | /* set rptr, wptr to 0 */ |
2342 | WREG32(IH_RB_RPTR, 0); |
2333 | WREG32(IH_RB_RPTR, 0); |
2343 | WREG32(IH_RB_WPTR, 0); |
2334 | WREG32(IH_RB_WPTR, 0); |
2344 | rdev->ih.enabled = false; |
2335 | rdev->ih.enabled = false; |
2345 | rdev->ih.wptr = 0; |
- | |
2346 | rdev->ih.rptr = 0; |
2336 | rdev->ih.rptr = 0; |
2347 | } |
2337 | } |
Line 2348... | Line 2338... | ||
2348 | 2338 | ||
2349 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
2339 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
Line 2369... | Line 2359... | ||
2369 | if (ASIC_IS_DCE32(rdev)) { |
2359 | if (ASIC_IS_DCE32(rdev)) { |
2370 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
2360 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
2371 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
2361 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
2372 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
2362 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
2373 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
2363 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
- | 2364 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
- | 2365 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); |
|
- | 2366 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
- | 2367 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); |
|
- | 2368 | } else { |
|
- | 2369 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
- | 2370 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); |
|
- | 2371 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
- | 2372 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); |
|
2374 | } |
2373 | } |
2375 | } else { |
2374 | } else { |
2376 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
2375 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
2377 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); |
2376 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); |
2378 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
2377 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
2379 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
2378 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
2380 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
2379 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
2381 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
2380 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
2382 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
2381 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
2383 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
2382 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
- | 2383 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
- | 2384 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); |
|
- | 2385 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
- | 2386 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); |
|
2384 | } |
2387 | } |
2385 | } |
2388 | } |
Line 2386... | Line 2389... | ||
2386 | 2389 | ||
2387 | int r600_irq_init(struct radeon_device *rdev) |
2390 | int r600_irq_init(struct radeon_device *rdev) |
Line 2448... | Line 2451... | ||
2448 | if (rdev->family >= CHIP_CEDAR) |
2451 | if (rdev->family >= CHIP_CEDAR) |
2449 | evergreen_disable_interrupt_state(rdev); |
2452 | evergreen_disable_interrupt_state(rdev); |
2450 | else |
2453 | else |
2451 | r600_disable_interrupt_state(rdev); |
2454 | r600_disable_interrupt_state(rdev); |
Line -... | Line 2455... | ||
- | 2455 | ||
- | 2456 | /* at this point everything should be setup correctly to enable master */ |
|
- | 2457 | pci_set_master(rdev->pdev); |
|
2452 | 2458 | ||
2453 | /* enable irqs */ |
2459 | /* enable irqs */ |
Line 2454... | Line 2460... | ||
2454 | r600_enable_interrupts(rdev); |
2460 | r600_enable_interrupts(rdev); |
2455 | 2461 | ||
Line 2459... | Line 2465... | ||
2459 | { |
2465 | { |
2460 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
2466 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
2461 | u32 mode_int = 0; |
2467 | u32 mode_int = 0; |
2462 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
2468 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
2463 | u32 grbm_int_cntl = 0; |
2469 | u32 grbm_int_cntl = 0; |
2464 | u32 hdmi1, hdmi2; |
2470 | u32 hdmi0, hdmi1; |
2465 | u32 d1grph = 0, d2grph = 0; |
2471 | u32 d1grph = 0, d2grph = 0; |
Line 2466... | Line 2472... | ||
2466 | 2472 | ||
2467 | if (!rdev->irq.installed) { |
2473 | if (!rdev->irq.installed) { |
2468 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
2474 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
Line 2474... | Line 2480... | ||
2474 | /* force the active interrupt state to all disabled */ |
2480 | /* force the active interrupt state to all disabled */ |
2475 | r600_disable_interrupt_state(rdev); |
2481 | r600_disable_interrupt_state(rdev); |
2476 | return 0; |
2482 | return 0; |
2477 | } |
2483 | } |
Line 2478... | Line -... | ||
2478 | - | ||
2479 | hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
2484 | |
2480 | if (ASIC_IS_DCE3(rdev)) { |
- | |
2481 | hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
2485 | if (ASIC_IS_DCE3(rdev)) { |
2482 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2486 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2483 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2487 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2484 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2488 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2485 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2489 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2486 | if (ASIC_IS_DCE32(rdev)) { |
2490 | if (ASIC_IS_DCE32(rdev)) { |
2487 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2491 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
- | 2492 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
|
- | 2493 | hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
|
- | 2494 | hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
|
- | 2495 | } else { |
|
- | 2496 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
2488 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2497 | hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
2489 | } |
2498 | } |
2490 | } else { |
- | |
2491 | hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
2499 | } else { |
2492 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2500 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2493 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2501 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
- | 2502 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
|
- | 2503 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
|
2494 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2504 | hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
Line 2495... | Line 2505... | ||
2495 | } |
2505 | } |
2496 | 2506 | ||
2497 | if (rdev->irq.sw_int) { |
2507 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
2498 | DRM_DEBUG("r600_irq_set: sw int\n"); |
2508 | DRM_DEBUG("r600_irq_set: sw int\n"); |
2499 | cp_int_cntl |= RB_INT_ENABLE; |
2509 | cp_int_cntl |= RB_INT_ENABLE; |
2500 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
2510 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
2501 | } |
2511 | } |
2502 | if (rdev->irq.crtc_vblank_int[0] || |
2512 | if (rdev->irq.crtc_vblank_int[0] || |
2503 | rdev->irq.pflip[0]) { |
2513 | atomic_read(&rdev->irq.pflip[0])) { |
2504 | DRM_DEBUG("r600_irq_set: vblank 0\n"); |
2514 | DRM_DEBUG("r600_irq_set: vblank 0\n"); |
2505 | mode_int |= D1MODE_VBLANK_INT_MASK; |
2515 | mode_int |= D1MODE_VBLANK_INT_MASK; |
2506 | } |
2516 | } |
2507 | if (rdev->irq.crtc_vblank_int[1] || |
2517 | if (rdev->irq.crtc_vblank_int[1] || |
2508 | rdev->irq.pflip[1]) { |
2518 | atomic_read(&rdev->irq.pflip[1])) { |
2509 | DRM_DEBUG("r600_irq_set: vblank 1\n"); |
2519 | DRM_DEBUG("r600_irq_set: vblank 1\n"); |
2510 | mode_int |= D2MODE_VBLANK_INT_MASK; |
2520 | mode_int |= D2MODE_VBLANK_INT_MASK; |
2511 | } |
2521 | } |
Line 2531... | Line 2541... | ||
2531 | } |
2541 | } |
2532 | if (rdev->irq.hpd[5]) { |
2542 | if (rdev->irq.hpd[5]) { |
2533 | DRM_DEBUG("r600_irq_set: hpd 6\n"); |
2543 | DRM_DEBUG("r600_irq_set: hpd 6\n"); |
2534 | hpd6 |= DC_HPDx_INT_EN; |
2544 | hpd6 |= DC_HPDx_INT_EN; |
2535 | } |
2545 | } |
2536 | if (rdev->irq.hdmi[0]) { |
2546 | if (rdev->irq.afmt[0]) { |
2537 | DRM_DEBUG("r600_irq_set: hdmi 1\n"); |
2547 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); |
2538 | hdmi1 |= R600_HDMI_INT_EN; |
2548 | hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; |
2539 | } |
2549 | } |
2540 | if (rdev->irq.hdmi[1]) { |
2550 | if (rdev->irq.afmt[1]) { |
2541 | DRM_DEBUG("r600_irq_set: hdmi 2\n"); |
2551 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); |
2542 | hdmi2 |= R600_HDMI_INT_EN; |
2552 | hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; |
2543 | } |
- | |
2544 | if (rdev->irq.gui_idle) { |
- | |
2545 | DRM_DEBUG("gui idle\n"); |
- | |
2546 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; |
- | |
2547 | } |
2553 | } |
Line 2548... | Line 2554... | ||
2548 | 2554 | ||
2549 | WREG32(CP_INT_CNTL, cp_int_cntl); |
2555 | WREG32(CP_INT_CNTL, cp_int_cntl); |
2550 | WREG32(DxMODE_INT_MASK, mode_int); |
2556 | WREG32(DxMODE_INT_MASK, mode_int); |
2551 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); |
2557 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); |
2552 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); |
2558 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); |
2553 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
- | |
2554 | WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); |
2559 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
2555 | if (ASIC_IS_DCE3(rdev)) { |
- | |
2556 | WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); |
2560 | if (ASIC_IS_DCE3(rdev)) { |
2557 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
2561 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
2558 | WREG32(DC_HPD2_INT_CONTROL, hpd2); |
2562 | WREG32(DC_HPD2_INT_CONTROL, hpd2); |
2559 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
2563 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
2560 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
2564 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
2561 | if (ASIC_IS_DCE32(rdev)) { |
2565 | if (ASIC_IS_DCE32(rdev)) { |
2562 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
2566 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
- | 2567 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
|
- | 2568 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); |
|
- | 2569 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); |
|
- | 2570 | } else { |
|
- | 2571 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
|
2563 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
2572 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); |
2564 | } |
2573 | } |
2565 | } else { |
- | |
2566 | WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2); |
2574 | } else { |
2567 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
2575 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
2568 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
2576 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
- | 2577 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
|
- | 2578 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
|
2569 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
2579 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); |
Line 2570... | Line 2580... | ||
2570 | } |
2580 | } |
2571 | 2581 | ||
Line 2572... | Line 2582... | ||
2572 | return 0; |
2582 | return 0; |
2573 | } |
2583 | } |
2574 | 2584 | ||
Line 2575... | Line 2585... | ||
2575 | static inline void r600_irq_ack(struct radeon_device *rdev) |
2585 | static void r600_irq_ack(struct radeon_device *rdev) |
2576 | { |
2586 | { |
2577 | u32 tmp; |
2587 | u32 tmp; |
2578 | 2588 | ||
- | 2589 | if (ASIC_IS_DCE3(rdev)) { |
|
- | 2590 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
|
- | 2591 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); |
|
- | 2592 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); |
|
- | 2593 | if (ASIC_IS_DCE32(rdev)) { |
|
- | 2594 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); |
|
- | 2595 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); |
|
2579 | if (ASIC_IS_DCE3(rdev)) { |
2596 | } else { |
2580 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
2597 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); |
2581 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); |
2598 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); |
2582 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); |
2599 | } |
- | 2600 | } else { |
|
- | 2601 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
|
2583 | } else { |
2602 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); |
2584 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
2603 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; |
2585 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); |
2604 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); |
Line 2586... | Line 2605... | ||
2586 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; |
2605 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); |
Line 2647... | Line 2666... | ||
2647 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
2666 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
2648 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
2667 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
2649 | tmp |= DC_HPDx_INT_ACK; |
2668 | tmp |= DC_HPDx_INT_ACK; |
2650 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
2669 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
2651 | } |
2670 | } |
- | 2671 | if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { |
|
- | 2672 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); |
|
- | 2673 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
|
- | 2674 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); |
|
- | 2675 | } |
|
- | 2676 | if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { |
|
- | 2677 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); |
|
- | 2678 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
|
- | 2679 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); |
|
- | 2680 | } |
|
- | 2681 | } else { |
|
- | 2682 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { |
|
- | 2683 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); |
|
- | 2684 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; |
|
- | 2685 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); |
|
2652 | } |
2686 | } |
2653 | if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
2687 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { |
2654 | WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); |
- | |
2655 | } |
- | |
2656 | if (ASIC_IS_DCE3(rdev)) { |
2688 | if (ASIC_IS_DCE3(rdev)) { |
2657 | if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
2689 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); |
- | 2690 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; |
|
2658 | WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); |
2691 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); |
2659 | } |
- | |
2660 | } else { |
2692 | } else { |
2661 | if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
2693 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); |
- | 2694 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; |
|
2662 | WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); |
2695 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); |
- | 2696 | } |
|
2663 | } |
2697 | } |
2664 | } |
2698 | } |
2665 | } |
2699 | } |
Line 2666... | Line 2700... | ||
2666 | 2700 | ||
2667 | static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) |
2701 | static u32 r600_get_ih_wptr(struct radeon_device *rdev) |
2668 | { |
2702 | { |
Line 2669... | Line 2703... | ||
2669 | u32 wptr, tmp; |
2703 | u32 wptr, tmp; |
2670 | 2704 | ||
Line 2724... | Line 2758... | ||
2724 | { |
2758 | { |
2725 | u32 wptr; |
2759 | u32 wptr; |
2726 | u32 rptr; |
2760 | u32 rptr; |
2727 | u32 src_id, src_data; |
2761 | u32 src_id, src_data; |
2728 | u32 ring_index; |
2762 | u32 ring_index; |
2729 | unsigned long flags; |
- | |
2730 | bool queue_hotplug = false; |
2763 | bool queue_hotplug = false; |
- | 2764 | bool queue_hdmi = false; |
|
Line 2731... | Line 2765... | ||
2731 | 2765 | ||
2732 | if (!rdev->ih.enabled || rdev->shutdown) |
2766 | if (!rdev->ih.enabled || rdev->shutdown) |
Line 2733... | Line 2767... | ||
2733 | return IRQ_NONE; |
2767 | return IRQ_NONE; |
2734 | 2768 | ||
2735 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
2769 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
Line 2736... | Line 2770... | ||
2736 | if (!rdev->msi_enabled) |
2770 | if (!rdev->msi_enabled) |
2737 | RREG32(IH_RB_WPTR); |
- | |
2738 | - | ||
2739 | wptr = r600_get_ih_wptr(rdev); |
- | |
2740 | rptr = rdev->ih.rptr; |
- | |
Line 2741... | Line 2771... | ||
2741 | // DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
2771 | RREG32(IH_RB_WPTR); |
- | 2772 | ||
2742 | 2773 | wptr = r600_get_ih_wptr(rdev); |
|
2743 | spin_lock_irqsave(&rdev->ih.lock, flags); |
2774 | |
2744 | - | ||
Line 2745... | Line 2775... | ||
2745 | if (rptr == wptr) { |
2775 | restart_ih: |
- | 2776 | /* is somebody else already processing irqs? */ |
|
- | 2777 | if (atomic_xchg(&rdev->ih.lock, 1)) |
|
2746 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
2778 | return IRQ_NONE; |
2747 | return IRQ_NONE; |
2779 | |
Line 2748... | Line 2780... | ||
2748 | } |
2780 | rptr = rdev->ih.rptr; |
2749 | 2781 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
|
Line 2750... | Line -... | ||
2750 | restart_ih: |
- | |
2751 | /* Order reading of wptr vs. reading of IH ring data */ |
2782 | |
2752 | rmb(); |
2783 | /* Order reading of wptr vs. reading of IH ring data */ |
2753 | 2784 | rmb(); |
|
2754 | /* display interrupts */ |
2785 | |
2755 | r600_irq_ack(rdev); |
2786 | /* display interrupts */ |
Line 2861... | Line 2892... | ||
2861 | default: |
2892 | default: |
2862 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2893 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2863 | break; |
2894 | break; |
2864 | } |
2895 | } |
2865 | break; |
2896 | break; |
2866 | case 21: /* HDMI */ |
2897 | case 21: /* hdmi */ |
- | 2898 | switch (src_data) { |
|
- | 2899 | case 4: |
|
- | 2900 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { |
|
- | 2901 | rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; |
|
- | 2902 | queue_hdmi = true; |
|
2867 | DRM_DEBUG("IH: HDMI: 0x%x\n", src_data); |
2903 | DRM_DEBUG("IH: HDMI0\n"); |
- | 2904 | } |
|
- | 2905 | break; |
|
- | 2906 | case 5: |
|
- | 2907 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { |
|
- | 2908 | rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; |
|
- | 2909 | queue_hdmi = true; |
|
- | 2910 | DRM_DEBUG("IH: HDMI1\n"); |
|
- | 2911 | } |
|
- | 2912 | break; |
|
- | 2913 | default: |
|
2868 | // r600_audio_schedule_polling(rdev); |
2914 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); |
- | 2915 | break; |
|
- | 2916 | } |
|
2869 | break; |
2917 | break; |
2870 | case 176: /* CP_INT in ring buffer */ |
2918 | case 176: /* CP_INT in ring buffer */ |
2871 | case 177: /* CP_INT in IB1 */ |
2919 | case 177: /* CP_INT in IB1 */ |
2872 | case 178: /* CP_INT in IB2 */ |
2920 | case 178: /* CP_INT in IB2 */ |
2873 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
2921 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
2874 | radeon_fence_process(rdev); |
2922 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2875 | break; |
2923 | break; |
2876 | case 181: /* CP EOP event */ |
2924 | case 181: /* CP EOP event */ |
2877 | DRM_DEBUG("IH: CP EOP\n"); |
2925 | DRM_DEBUG("IH: CP EOP\n"); |
2878 | radeon_fence_process(rdev); |
2926 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2879 | break; |
2927 | break; |
2880 | case 233: /* GUI IDLE */ |
2928 | case 233: /* GUI IDLE */ |
2881 | DRM_DEBUG("IH: GUI idle\n"); |
2929 | DRM_DEBUG("IH: GUI idle\n"); |
2882 | rdev->pm.gui_idle = true; |
- | |
2883 | // wake_up(&rdev->irq.idle_queue); |
- | |
2884 | break; |
2930 | break; |
2885 | default: |
2931 | default: |
2886 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2932 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2887 | break; |
2933 | break; |
2888 | } |
2934 | } |
Line 2889... | Line 2935... | ||
2889 | 2935 | ||
2890 | /* wptr/rptr are in bytes! */ |
2936 | /* wptr/rptr are in bytes! */ |
2891 | rptr += 16; |
2937 | rptr += 16; |
2892 | rptr &= rdev->ih.ptr_mask; |
2938 | rptr &= rdev->ih.ptr_mask; |
- | 2939 | } |
|
- | 2940 | rdev->ih.rptr = rptr; |
|
- | 2941 | WREG32(IH_RB_RPTR, rdev->ih.rptr); |
|
- | 2942 | atomic_set(&rdev->ih.lock, 0); |
|
2893 | } |
2943 | |
2894 | /* make sure wptr hasn't changed while processing */ |
2944 | /* make sure wptr hasn't changed while processing */ |
2895 | wptr = r600_get_ih_wptr(rdev); |
2945 | wptr = r600_get_ih_wptr(rdev); |
2896 | if (wptr != rdev->ih.wptr) |
2946 | if (wptr != rptr) |
2897 | goto restart_ih; |
- | |
2898 | // if (queue_hotplug) |
- | |
2899 | // schedule_work(&rdev->hotplug_work); |
- | |
2900 | rdev->ih.rptr = rptr; |
- | |
2901 | WREG32(IH_RB_RPTR, rdev->ih.rptr); |
- | |
- | 2947 | goto restart_ih; |
|
2902 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
2948 | |
2903 | return IRQ_HANDLED; |
2949 | return IRQ_HANDLED; |
Line 2904... | Line 2950... | ||
2904 | } |
2950 | } |
2905 | 2951 | ||
2906 | /* |
2952 | /* |
2907 | * Debugfs info |
2953 | * Debugfs info |
Line 2908... | Line -... | ||
2908 | */ |
- | |
2909 | #if defined(CONFIG_DEBUG_FS) |
- | |
2910 | - | ||
2911 | static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) |
- | |
2912 | { |
- | |
2913 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
- | |
2914 | struct drm_device *dev = node->minor->dev; |
- | |
2915 | struct radeon_device *rdev = dev->dev_private; |
- | |
2916 | unsigned count, i, j; |
- | |
2917 | - | ||
2918 | radeon_ring_free_size(rdev); |
- | |
2919 | count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; |
- | |
2920 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
- | |
2921 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); |
- | |
2922 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); |
- | |
2923 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); |
- | |
2924 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); |
- | |
2925 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
- | |
2926 | seq_printf(m, "%u dwords in ring\n", count); |
- | |
2927 | i = rdev->cp.rptr; |
- | |
2928 | for (j = 0; j <= count; j++) { |
- | |
2929 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
- | |
2930 | i = (i + 1) & rdev->cp.ptr_mask; |
- | |
2931 | } |
- | |
2932 | return 0; |
2954 | */ |
2933 | } |
2955 | #if defined(CONFIG_DEBUG_FS) |
2934 | 2956 | ||
2935 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
2957 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
2936 | { |
2958 | { |
Line 2943... | Line 2965... | ||
2943 | return 0; |
2965 | return 0; |
2944 | } |
2966 | } |
Line 2945... | Line 2967... | ||
2945 | 2967 | ||
2946 | static struct drm_info_list r600_mc_info_list[] = { |
2968 | static struct drm_info_list r600_mc_info_list[] = { |
2947 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, |
- | |
2948 | {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, |
2969 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, |
2949 | }; |
2970 | }; |
Line 2950... | Line 2971... | ||
2950 | #endif |
2971 | #endif |
2951 | 2972 | ||
Line 3105... | Line 3126... | ||
3105 | 3126 | ||
3106 | static void r600_pcie_gen2_enable(struct radeon_device *rdev) |
3127 | static void r600_pcie_gen2_enable(struct radeon_device *rdev) |
3107 | { |
3128 | { |
3108 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; |
3129 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; |
- | 3130 | u16 link_cntl2; |
|
- | 3131 | u32 mask; |
|
Line 3109... | Line 3132... | ||
3109 | u16 link_cntl2; |
3132 | int ret; |
3110 | 3133 | ||
Line 3111... | Line 3134... | ||
3111 | if (radeon_pcie_gen2 == 0) |
3134 | if (radeon_pcie_gen2 == 0) |
Line 3123... | Line 3146... | ||
3123 | 3146 | ||
3124 | /* only RV6xx+ chips are supported */ |
3147 | /* only RV6xx+ chips are supported */ |
3125 | if (rdev->family <= CHIP_R600) |
3148 | if (rdev->family <= CHIP_R600) |
Line -... | Line 3149... | ||
- | 3149 | return; |
|
- | 3150 | ||
- | 3151 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
|
- | 3152 | if (ret != 0) |
|
- | 3153 | return; |
|
- | 3154 | ||
- | 3155 | if (!(mask & DRM_PCIE_SPEED_50)) |
|
- | 3156 | return; |
|
- | 3157 | ||
- | 3158 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
|
- | 3159 | if (speed_cntl & LC_CURRENT_DATA_RATE) { |
|
- | 3160 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); |
|
- | 3161 | return; |
|
- | 3162 | } |
|
- | 3163 | ||
3126 | return; |
3164 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
3127 | 3165 | ||
3128 | /* 55 nm r6xx asics */ |
3166 | /* 55 nm r6xx asics */ |
3129 | if ((rdev->family == CHIP_RV670) || |
3167 | if ((rdev->family == CHIP_RV670) || |
3130 | (rdev->family == CHIP_RV620) || |
3168 | (rdev->family == CHIP_RV620) || |
Line 3202... | Line 3240... | ||
3202 | else |
3240 | else |
3203 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
3241 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
3204 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
3242 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
3205 | } |
3243 | } |
3206 | }><>=>><>=>=>><>>>>>=>=>><>>>><>1); |
3244 | } |
- | 3245 | ||
- | 3246 | /** |
|
- | 3247 | * r600_get_gpu_clock - return GPU clock counter snapshot |
|
- | 3248 | * |
|
- | 3249 | * @rdev: radeon_device pointer |
|
- | 3250 | * |
|
- | 3251 | * Fetches a GPU clock counter snapshot (R6xx-cayman). |
|
- | 3252 | * Returns the 64 bit clock counter snapshot. |
|
- | 3253 | */ |
|
- | 3254 | uint64_t r600_get_gpu_clock(struct radeon_device *rdev) |
|
- | 3255 | { |
|
- | 3256 | uint64_t clock; |
|
- | 3257 | ||
- | 3258 | mutex_lock(&rdev->gpu_clock_mutex); |
|
- | 3259 | WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); |
|
- | 3260 | clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | |
|
- | 3261 | ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); |
|
- | 3262 | mutex_unlock(&rdev->gpu_clock_mutex); |
|
- | 3263 | return clock; |
|
- | 3264 | }><>><>=>><>=>><>>>>>>=>=>=>><>>>><>><>1); |