Rev 2005 | Rev 2175 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 2005 | Rev 2160 | ||
|---|---|---|---|
| Line 1177... | Line 1177... | ||
| 1177 | (R6XX_MAX_BACKENDS - |
1177 | (R6XX_MAX_BACKENDS - |
| 1178 | r600_count_pipe_bits((cc_rb_backend_disable & |
1178 | r600_count_pipe_bits((cc_rb_backend_disable & |
| 1179 | R6XX_MAX_BACKENDS_MASK) >> 16)), |
1179 | R6XX_MAX_BACKENDS_MASK) >> 16)), |
| 1180 | (cc_rb_backend_disable >> 16)); |
1180 | (cc_rb_backend_disable >> 16)); |
| 1181 | rdev->config.r600.tile_config = tiling_config; |
1181 | rdev->config.r600.tile_config = tiling_config; |
| - | 1182 | rdev->config.r600.backend_map = backend_map; |
|
| 1182 | tiling_config |= BACKEND_MAP(backend_map); |
1183 | tiling_config |= BACKEND_MAP(backend_map); |
| 1183 | WREG32(GB_TILING_CONFIG, tiling_config); |
1184 | WREG32(GB_TILING_CONFIG, tiling_config); |
| 1184 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
1185 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
| 1185 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); |
1186 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); |
| Line 1727... | Line 1728... | ||
| 1727 | WREG32(CP_RB_RPTR_WR, 0); |
1728 | WREG32(CP_RB_RPTR_WR, 0); |
| 1728 | WREG32(CP_RB_WPTR, 0); |
1729 | WREG32(CP_RB_WPTR, 0); |
| Line 1729... | Line 1730... | ||
| 1729 | 1730 | ||
| 1730 | /* set the wb address whether it's enabled or not */ |
1731 | /* set the wb address whether it's enabled or not */ |
| 1731 | WREG32(CP_RB_RPTR_ADDR, |
- | |
| 1732 | #ifdef __BIG_ENDIAN |
- | |
| 1733 | RB_RPTR_SWAP(2) | |
- | |
| 1734 | #endif |
1732 | WREG32(CP_RB_RPTR_ADDR, |
| 1735 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
1733 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
| 1736 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1734 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
| Line 1737... | Line 1735... | ||
| 1737 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
1735 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
| Line 2435... | Line 2433... | ||
| 2435 | /* Default settings for IH_CNTL (disabled at first) */ |
2433 | /* Default settings for IH_CNTL (disabled at first) */ |
| 2436 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); |
2434 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); |
| 2437 | /* RPTR_REARM only works if msi's are enabled */ |
2435 | /* RPTR_REARM only works if msi's are enabled */ |
| 2438 | if (rdev->msi_enabled) |
2436 | if (rdev->msi_enabled) |
| 2439 | ih_cntl |= RPTR_REARM; |
2437 | ih_cntl |= RPTR_REARM; |
| 2440 | - | ||
| 2441 | #ifdef __BIG_ENDIAN |
- | |
| 2442 | ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); |
- | |
| 2443 | #endif |
- | |
| 2444 | WREG32(IH_CNTL, ih_cntl); |
2438 | WREG32(IH_CNTL, ih_cntl); |
| Line 2445... | Line 2439... | ||
| 2445 | 2439 | ||
| 2446 | /* force the active interrupt state to all disabled */ |
2440 | /* force the active interrupt state to all disabled */ |
| 2447 | if (rdev->family >= CHIP_CEDAR) |
2441 | if (rdev->family >= CHIP_CEDAR) |
| Line 2715... | Line 2709... | ||
| 2715 | * |
2709 | * |
| 2716 | * Note, these are based on r600 and may need to be |
2710 | * Note, these are based on r600 and may need to be |
| 2717 | * adjusted or added to on newer asics |
2711 | * adjusted or added to on newer asics |
| 2718 | */ |
2712 | */ |
| Line -... | Line 2713... | ||
| - | 2713 | ||
| - | 2714 | #define DRM_DEBUG(...) |
|
| 2719 | 2715 | ||
| 2720 | int r600_irq_process(struct radeon_device *rdev) |
2716 | int r600_irq_process(struct radeon_device *rdev) |
| 2721 | { |
2717 | { |
| 2722 | u32 wptr; |
2718 | u32 wptr; |
| 2723 | u32 rptr; |
2719 | u32 rptr; |
| Line 2727... | Line 2723... | ||
| 2727 | bool queue_hotplug = false; |
2723 | bool queue_hotplug = false; |
| Line 2728... | Line 2724... | ||
| 2728 | 2724 | ||
| 2729 | if (!rdev->ih.enabled || rdev->shutdown) |
2725 | if (!rdev->ih.enabled || rdev->shutdown) |
| Line -... | Line 2726... | ||
| - | 2726 | return IRQ_NONE; |
|
| - | 2727 | ||
| - | 2728 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
|
| - | 2729 | if (!rdev->msi_enabled) |
|
| 2730 | return IRQ_NONE; |
2730 | RREG32(IH_RB_WPTR); |
| 2731 | 2731 | ||
| 2732 | wptr = r600_get_ih_wptr(rdev); |
2732 | wptr = r600_get_ih_wptr(rdev); |
| Line 2733... | Line 2733... | ||
| 2733 | rptr = rdev->ih.rptr; |
2733 | rptr = rdev->ih.rptr; |
| Line 2734... | Line 2734... | ||
| 2734 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
2734 | // DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
| 2735 | 2735 | ||
| 2736 | spin_lock_irqsave(&rdev->ih.lock, flags); |
2736 | spin_lock_irqsave(&rdev->ih.lock, flags); |
| 2737 | 2737 | ||
| Line 2738... | Line 2738... | ||
| 2738 | if (rptr == wptr) { |
2738 | if (rptr == wptr) { |
| - | 2739 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
|
| - | 2740 | return IRQ_NONE; |
|
| - | 2741 | } |
|
| 2739 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
2742 | |
| 2740 | return IRQ_NONE; |
2743 | restart_ih: |
| Line 2741... | Line 2744... | ||
| 2741 | } |
2744 | /* Order reading of wptr vs. reading of IH ring data */ |
| 2742 | 2745 | rmb(); |
|