Rev 1128 | Rev 1221 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1128 | Rev 1179 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include "drmP.h" |
28 | #include "drmP.h" |
29 | #include "radeon_reg.h" |
29 | #include "radeon_reg.h" |
30 | #include "radeon.h" |
30 | #include "radeon.h" |
31 | 31 | ||
32 | /* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ |
32 | /* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ |
33 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
33 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
34 | 34 | ||
35 | /* This files gather functions specifics to: |
35 | /* This files gather functions specifics to: |
36 | * r600,rv610,rv630,rv620,rv635,rv670 |
36 | * r600,rv610,rv630,rv620,rv635,rv670 |
37 | * |
37 | * |
38 | * Some of these functions might be used by newer ASICs. |
38 | * Some of these functions might be used by newer ASICs. |
39 | */ |
39 | */ |
40 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
40 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
41 | void r600_gpu_init(struct radeon_device *rdev); |
41 | void r600_gpu_init(struct radeon_device *rdev); |
42 | 42 | ||
43 | 43 | ||
44 | /* |
44 | /* |
45 | * MC |
45 | * MC |
46 | */ |
46 | */ |
47 | int r600_mc_init(struct radeon_device *rdev) |
47 | int r600_mc_init(struct radeon_device *rdev) |
48 | { |
48 | { |
49 | uint32_t tmp; |
49 | uint32_t tmp; |
50 | 50 | ||
51 | r600_gpu_init(rdev); |
51 | r600_gpu_init(rdev); |
52 | 52 | ||
53 | /* setup the gart before changing location so we can ask to |
53 | /* setup the gart before changing location so we can ask to |
54 | * discard unmapped mc request |
54 | * discard unmapped mc request |
55 | */ |
55 | */ |
56 | /* FIXME: disable out of gart access */ |
56 | /* FIXME: disable out of gart access */ |
57 | tmp = rdev->mc.gtt_location / 4096; |
57 | tmp = rdev->mc.gtt_location / 4096; |
58 | tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
58 | tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
59 | WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); |
59 | WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); |
60 | tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; |
60 | tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; |
61 | tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
61 | tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
62 | WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
62 | WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
63 | 63 | ||
64 | rs600_mc_disable_clients(rdev); |
64 | rs600_mc_disable_clients(rdev); |
65 | if (r600_mc_wait_for_idle(rdev)) { |
65 | if (r600_mc_wait_for_idle(rdev)) { |
66 | printk(KERN_WARNING "Failed to wait MC idle while " |
66 | printk(KERN_WARNING "Failed to wait MC idle while " |
67 | "programming pipes. Bad things might happen.\n"); |
67 | "programming pipes. Bad things might happen.\n"); |
68 | } |
68 | } |
69 | 69 | ||
70 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
70 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
71 | tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); |
71 | tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); |
72 | tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); |
72 | tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); |
73 | WREG32(R600_MC_VM_FB_LOCATION, tmp); |
73 | WREG32(R600_MC_VM_FB_LOCATION, tmp); |
74 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
74 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
75 | tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); |
75 | tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); |
76 | WREG32(R600_MC_VM_AGP_TOP, tmp); |
76 | WREG32(R600_MC_VM_AGP_TOP, tmp); |
77 | tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); |
77 | tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); |
78 | WREG32(R600_MC_VM_AGP_BOT, tmp); |
78 | WREG32(R600_MC_VM_AGP_BOT, tmp); |
79 | return 0; |
79 | return 0; |
80 | } |
80 | } |
81 | 81 | ||
82 | void r600_mc_fini(struct radeon_device *rdev) |
82 | void r600_mc_fini(struct radeon_device *rdev) |
83 | { |
83 | { |
84 | /* FIXME: implement */ |
84 | /* FIXME: implement */ |
85 | } |
85 | } |
86 | 86 | ||
87 | 87 | ||
88 | /* |
88 | /* |
89 | * Global GPU functions |
89 | * Global GPU functions |
90 | */ |
90 | */ |
91 | void r600_errata(struct radeon_device *rdev) |
91 | void r600_errata(struct radeon_device *rdev) |
92 | { |
92 | { |
93 | rdev->pll_errata = 0; |
93 | rdev->pll_errata = 0; |
94 | } |
94 | } |
95 | 95 | ||
96 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
96 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
97 | { |
97 | { |
98 | /* FIXME: implement */ |
98 | /* FIXME: implement */ |
99 | return 0; |
99 | return 0; |
100 | } |
100 | } |
101 | 101 | ||
102 | void r600_gpu_init(struct radeon_device *rdev) |
102 | void r600_gpu_init(struct radeon_device *rdev) |
103 | { |
103 | { |
104 | /* FIXME: implement */ |
104 | /* FIXME: implement */ |
105 | } |
105 | } |
106 | 106 | ||
107 | 107 | ||
108 | /* |
108 | /* |
109 | * VRAM info |
109 | * VRAM info |
110 | */ |
110 | */ |
111 | void r600_vram_get_type(struct radeon_device *rdev) |
111 | void r600_vram_get_type(struct radeon_device *rdev) |
112 | { |
112 | { |
113 | uint32_t tmp; |
113 | uint32_t tmp; |
114 | int chansize; |
114 | int chansize; |
115 | 115 | ||
116 | rdev->mc.vram_width = 128; |
116 | rdev->mc.vram_width = 128; |
117 | rdev->mc.vram_is_ddr = true; |
117 | rdev->mc.vram_is_ddr = true; |
118 | 118 | ||
119 | tmp = RREG32(R600_RAMCFG); |
119 | tmp = RREG32(R600_RAMCFG); |
120 | if (tmp & R600_CHANSIZE_OVERRIDE) { |
120 | if (tmp & R600_CHANSIZE_OVERRIDE) { |
121 | chansize = 16; |
121 | chansize = 16; |
122 | } else if (tmp & R600_CHANSIZE) { |
122 | } else if (tmp & R600_CHANSIZE) { |
123 | chansize = 64; |
123 | chansize = 64; |
124 | } else { |
124 | } else { |
125 | chansize = 32; |
125 | chansize = 32; |
126 | } |
126 | } |
127 | if (rdev->family == CHIP_R600) { |
127 | if (rdev->family == CHIP_R600) { |
128 | rdev->mc.vram_width = 8 * chansize; |
128 | rdev->mc.vram_width = 8 * chansize; |
129 | } else if (rdev->family == CHIP_RV670) { |
129 | } else if (rdev->family == CHIP_RV670) { |
130 | rdev->mc.vram_width = 4 * chansize; |
130 | rdev->mc.vram_width = 4 * chansize; |
131 | } else if ((rdev->family == CHIP_RV610) || |
131 | } else if ((rdev->family == CHIP_RV610) || |
132 | (rdev->family == CHIP_RV620)) { |
132 | (rdev->family == CHIP_RV620)) { |
133 | rdev->mc.vram_width = chansize; |
133 | rdev->mc.vram_width = chansize; |
134 | } else if ((rdev->family == CHIP_RV630) || |
134 | } else if ((rdev->family == CHIP_RV630) || |
135 | (rdev->family == CHIP_RV635)) { |
135 | (rdev->family == CHIP_RV635)) { |
136 | rdev->mc.vram_width = 2 * chansize; |
136 | rdev->mc.vram_width = 2 * chansize; |
137 | } |
137 | } |
138 | } |
138 | } |
139 | 139 | ||
140 | void r600_vram_info(struct radeon_device *rdev) |
140 | void r600_vram_info(struct radeon_device *rdev) |
141 | { |
141 | { |
142 | r600_vram_get_type(rdev); |
142 | r600_vram_get_type(rdev); |
143 | rdev->mc.vram_size = RREG32(R600_CONFIG_MEMSIZE); |
143 | rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE); |
- | 144 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
|
144 | 145 | ||
145 | /* Could aper size report 0 ? */ |
146 | /* Could aper size report 0 ? */ |
146 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
147 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
147 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
148 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
148 | } |
149 | } |
149 | 150 | ||
150 | /* |
151 | /* |
151 | * Indirect registers accessor |
152 | * Indirect registers accessor |
152 | */ |
153 | */ |
153 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) |
154 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) |
154 | { |
155 | { |
155 | uint32_t r; |
156 | uint32_t r; |
156 | 157 | ||
157 | WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
158 | WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
158 | (void)RREG32(R600_PCIE_PORT_INDEX); |
159 | (void)RREG32(R600_PCIE_PORT_INDEX); |
159 | r = RREG32(R600_PCIE_PORT_DATA); |
160 | r = RREG32(R600_PCIE_PORT_DATA); |
160 | return r; |
161 | return r; |
161 | } |
162 | } |
162 | 163 | ||
163 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
164 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
164 | { |
165 | { |
165 | WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
166 | WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
166 | (void)RREG32(R600_PCIE_PORT_INDEX); |
167 | (void)RREG32(R600_PCIE_PORT_INDEX); |
167 | WREG32(R600_PCIE_PORT_DATA, (v)); |
168 | WREG32(R600_PCIE_PORT_DATA, (v)); |
168 | (void)RREG32(R600_PCIE_PORT_DATA); |
169 | (void)RREG32(R600_PCIE_PORT_DATA); |
169 | } |
170 | } |