WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r520.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "r520d.h"
 
/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
 
static int r520_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32_MC(R520_MC_STATUS);
		if (tmp & R520_MC_STATUS_IDLE) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}
 
static void r520_gpu_init(struct radeon_device *rdev)
{
	unsigned pipe_select_current, gb_pipe_select, tmp;
 
 
	rv515_vga_render_disable(rdev);
	/*
	 * DST_PIPE_CONFIG		0x170C
	 * GB_TILE_CONFIG		0x4018
	 * GB_FIFO_SIZE			0x4024
	 * GB_PIPE_SELECT		0x402C
	 * GB_PIPE_SELECT2              0x4124
	 *	Z_PIPE_SHIFT			0
	 *	Z_PIPE_MASK			0x000000003
	 * GB_FIFO_SIZE2                0x4128
	 *	SC_SFIFO_SIZE_SHIFT		0
	 *	SC_SFIFO_SIZE_MASK		0x000000003
	 *	SC_MFIFO_SIZE_SHIFT		2
	 *	SC_MFIFO_SIZE_MASK		0x00000000C
	 *	FG_SFIFO_SIZE_SHIFT		4
	 *	FG_SFIFO_SIZE_MASK		0x000000030
	 *	ZB_MFIFO_SIZE_SHIFT		6
	 *	ZB_MFIFO_SIZE_MASK		0x0000000C0
	 * GA_ENHANCE			0x4274
	 * SU_REG_DEST			0x42C8
	 */
	/* workaround for RV530 */
	if (rdev->family == CHIP_RV530) {
		WREG32(0x4128, 0xFF);
	}
	r420_pipes_init(rdev);
	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
	tmp = RREG32(R300_DST_PIPE_CONFIG);
	pipe_select_current = (tmp >> 2) & 3;
	tmp = (1 << pipe_select_current) |
	      (((gb_pipe_select >> 8) & 0xF) << 4);
	WREG32_PLL(0x000D, tmp);
	if (r520_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
}
 
static void r520_vram_get_type(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	rdev->mc.vram_width = 128;
	rdev->mc.vram_is_ddr = true;
	tmp = RREG32_MC(R520_MC_CNTL0);
	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
	case 0:
		rdev->mc.vram_width = 32;
		break;
	case 1:
		rdev->mc.vram_width = 64;
		break;
	case 2:
		rdev->mc.vram_width = 128;
		break;
	case 3:
		rdev->mc.vram_width = 256;
		break;
	default:
		rdev->mc.vram_width = 128;
		break;
	}
	if (tmp & R520_MC_CHANNEL_SIZE)
		rdev->mc.vram_width *= 2;
}
 
void r520_mc_init(struct radeon_device *rdev)
{
 
 
	r520_vram_get_type(rdev);
	r100_vram_init_sizes(rdev);
	radeon_vram_location(rdev, &rdev->mc, 0);
	rdev->mc.gtt_base_align = 0;
	if (!(rdev->flags & RADEON_IS_AGP))
		radeon_gtt_location(rdev, &rdev->mc);
 
 
 
	radeon_update_bandwidth_info(rdev);
 
 
}
 
void r520_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
 
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
 
	/* Wait for mc idle */
	if (r520_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
	/* Write VRAM size in case we are limiting it */
	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
	/* Program MC, should be a 32bits limited address space */
	WREG32_MC(R_000004_MC_FB_LOCATION,
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
	if (rdev->flags & RADEON_IS_AGP) {
		WREG32_MC(R_000005_MC_AGP_LOCATION,
			S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
			S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		WREG32_MC(R_000007_AGP_BASE_2,
			S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
	} else {
		WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
		WREG32_MC(R_000006_AGP_BASE, 0);
		WREG32_MC(R_000007_AGP_BASE_2, 0);
	}
 
	rv515_mc_resume(rdev, &save);
}
 
static int r520_startup(struct radeon_device *rdev)
{
	int r;
 
	r520_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	r520_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	/* Enable IRQ */
 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
    r = r100_cp_init(rdev, 1024 * 1024);
    if (r) {
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
        return r;
    }
 
 
 
 
 
 
 
 
	return 0;
}
 
 
 
int r520_init(struct radeon_device *rdev)
{
	int r;
 
 
 
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* restore some register to sane defaults */
	r100_restore_sanity(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;
 
	if (!radeon_card_posted(rdev) && rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		atom_asic_init(rdev->mode_info.atom_context);
	}
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
 
 
	/* initialize AGP */
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r) {
			radeon_agp_disable(rdev);
		}
	}
	/* initialize memory controller */
	r520_mc_init(rdev);
	rv515_debugfs(rdev);
	/* Fence driver */
 
 
 
 
 
 
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rv370_pcie_gart_init(rdev);
	if (r)
		return r;
	rv515_set_safe_registers(rdev);
	rdev->accel_working = true;
	r = r520_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
 
 
 
		rv370_pcie_gart_fini(rdev);
 
		rdev->accel_working = false;
	}
 
 
 
	return 0;
}

Rev 1430	Rev 1963
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include "drmP.h"	28	#include "drmP.h"
29	#include "radeon.h"	29	#include "radeon.h"
-		30	#include "radeon_asic.h"
30	#include "atom.h"	31	#include "atom.h"
31	#include "r520d.h"	32	#include "r520d.h"
32		33
33	/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */	34	/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
34		35
35	static int r520_mc_wait_for_idle(struct radeon_device *rdev)	36	static int r520_mc_wait_for_idle(struct radeon_device *rdev)
36	{	37	{
37	unsigned i;	38	unsigned i;
38	uint32_t tmp;	39	uint32_t tmp;
39		40
40	for (i = 0; i < rdev->usec_timeout; i++) {	41	for (i = 0; i < rdev->usec_timeout; i++) {
41	/* read MC_STATUS */	42	/* read MC_STATUS */
42	tmp = RREG32_MC(R520_MC_STATUS);	43	tmp = RREG32_MC(R520_MC_STATUS);
43	if (tmp & R520_MC_STATUS_IDLE) {	44	if (tmp & R520_MC_STATUS_IDLE) {
44	return 0;	45	return 0;
45	}	46	}
46	DRM_UDELAY(1);	47	DRM_UDELAY(1);
47	}	48	}
48	return -1;	49	return -1;
49	}	50	}
50		51
51	static void r520_gpu_init(struct radeon_device *rdev)	52	static void r520_gpu_init(struct radeon_device *rdev)
52	{	53	{
53	unsigned pipe_select_current, gb_pipe_select, tmp;	54	unsigned pipe_select_current, gb_pipe_select, tmp;
54		-
55	r100_hdp_reset(rdev);	55
56	rv515_vga_render_disable(rdev);	56	rv515_vga_render_disable(rdev);
57	/*	57	/*
58	* DST_PIPE_CONFIG 0x170C	58	* DST_PIPE_CONFIG 0x170C
59	* GB_TILE_CONFIG 0x4018	59	* GB_TILE_CONFIG 0x4018
60	* GB_FIFO_SIZE 0x4024	60	* GB_FIFO_SIZE 0x4024
61	* GB_PIPE_SELECT 0x402C	61	* GB_PIPE_SELECT 0x402C
62	* GB_PIPE_SELECT2 0x4124	62	* GB_PIPE_SELECT2 0x4124
63	* Z_PIPE_SHIFT 0	63	* Z_PIPE_SHIFT 0
64	* Z_PIPE_MASK 0x000000003	64	* Z_PIPE_MASK 0x000000003
65	* GB_FIFO_SIZE2 0x4128	65	* GB_FIFO_SIZE2 0x4128
66	* SC_SFIFO_SIZE_SHIFT 0	66	* SC_SFIFO_SIZE_SHIFT 0
67	* SC_SFIFO_SIZE_MASK 0x000000003	67	* SC_SFIFO_SIZE_MASK 0x000000003
68	* SC_MFIFO_SIZE_SHIFT 2	68	* SC_MFIFO_SIZE_SHIFT 2
69	* SC_MFIFO_SIZE_MASK 0x00000000C	69	* SC_MFIFO_SIZE_MASK 0x00000000C
70	* FG_SFIFO_SIZE_SHIFT 4	70	* FG_SFIFO_SIZE_SHIFT 4
71	* FG_SFIFO_SIZE_MASK 0x000000030	71	* FG_SFIFO_SIZE_MASK 0x000000030
72	* ZB_MFIFO_SIZE_SHIFT 6	72	* ZB_MFIFO_SIZE_SHIFT 6
73	* ZB_MFIFO_SIZE_MASK 0x0000000C0	73	* ZB_MFIFO_SIZE_MASK 0x0000000C0
74	* GA_ENHANCE 0x4274	74	* GA_ENHANCE 0x4274
75	* SU_REG_DEST 0x42C8	75	* SU_REG_DEST 0x42C8
76	*/	76	*/
77	/* workaround for RV530 */	77	/* workaround for RV530 */
78	if (rdev->family == CHIP_RV530) {	78	if (rdev->family == CHIP_RV530) {
79	WREG32(0x4128, 0xFF);	79	WREG32(0x4128, 0xFF);
80	}	80	}
81	r420_pipes_init(rdev);	81	r420_pipes_init(rdev);
82	gb_pipe_select = RREG32(0x402C);	82	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
83	tmp = RREG32(0x170C);	83	tmp = RREG32(R300_DST_PIPE_CONFIG);
84	pipe_select_current = (tmp >> 2) & 3;	84	pipe_select_current = (tmp >> 2) & 3;
85	tmp = (1 << pipe_select_current) \|	85	tmp = (1 << pipe_select_current) \|
86	(((gb_pipe_select >> 8) & 0xF) << 4);	86	(((gb_pipe_select >> 8) & 0xF) << 4);
87	WREG32_PLL(0x000D, tmp);	87	WREG32_PLL(0x000D, tmp);
88	if (r520_mc_wait_for_idle(rdev)) {	88	if (r520_mc_wait_for_idle(rdev)) {
89	printk(KERN_WARNING "Failed to wait MC idle while "	89	printk(KERN_WARNING "Failed to wait MC idle while "
90	"programming pipes. Bad things might happen.\n");	90	"programming pipes. Bad things might happen.\n");
91	}	91	}
92	}	92	}
93		93
94	static void r520_vram_get_type(struct radeon_device *rdev)	94	static void r520_vram_get_type(struct radeon_device *rdev)
95	{	95	{
96	uint32_t tmp;	96	uint32_t tmp;
97		97
98	rdev->mc.vram_width = 128;	98	rdev->mc.vram_width = 128;
99	rdev->mc.vram_is_ddr = true;	99	rdev->mc.vram_is_ddr = true;
100	tmp = RREG32_MC(R520_MC_CNTL0);	100	tmp = RREG32_MC(R520_MC_CNTL0);
101	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {	101	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
102	case 0:	102	case 0:
103	rdev->mc.vram_width = 32;	103	rdev->mc.vram_width = 32;
104	break;	104	break;
105	case 1:	105	case 1:
106	rdev->mc.vram_width = 64;	106	rdev->mc.vram_width = 64;
107	break;	107	break;
108	case 2:	108	case 2:
109	rdev->mc.vram_width = 128;	109	rdev->mc.vram_width = 128;
110	break;	110	break;
111	case 3:	111	case 3:
112	rdev->mc.vram_width = 256;	112	rdev->mc.vram_width = 256;
113	break;	113	break;
114	default:	114	default:
115	rdev->mc.vram_width = 128;	115	rdev->mc.vram_width = 128;
116	break;	116	break;
117	}	117	}
118	if (tmp & R520_MC_CHANNEL_SIZE)	118	if (tmp & R520_MC_CHANNEL_SIZE)
119	rdev->mc.vram_width *= 2;	119	rdev->mc.vram_width *= 2;
120	}	120	}
121		121
122	void r520_mc_init(struct radeon_device *rdev)	122	void r520_mc_init(struct radeon_device *rdev)
123	{	123	{
124	fixed20_12 a;	-
125		124
126	r520_vram_get_type(rdev);	125	r520_vram_get_type(rdev);
127	r100_vram_init_sizes(rdev);	126	r100_vram_init_sizes(rdev);
128	radeon_vram_location(rdev, &rdev->mc, 0);	127	radeon_vram_location(rdev, &rdev->mc, 0);
-		128	rdev->mc.gtt_base_align = 0;
129	if (!(rdev->flags & RADEON_IS_AGP))	129	if (!(rdev->flags & RADEON_IS_AGP))
130	radeon_gtt_location(rdev, &rdev->mc);	130	radeon_gtt_location(rdev, &rdev->mc);
131	/* FIXME: we should enforce default clock in case GPU is not in	-
132	* default setup	-
133	*/	-
134	a.full = rfixed_const(100);	131	radeon_update_bandwidth_info(rdev);
135	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);	-
136	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);	-
137	}	132	}
138		133
139	void r520_mc_program(struct radeon_device *rdev)	134	void r520_mc_program(struct radeon_device *rdev)
140	{	135	{
141	struct rv515_mc_save save;	136	struct rv515_mc_save save;
142		137
143	/* Stops all mc clients */	138	/* Stops all mc clients */
144	rv515_mc_stop(rdev, &save);	139	rv515_mc_stop(rdev, &save);
145		140
146	/* Wait for mc idle */	141	/* Wait for mc idle */
147	if (r520_mc_wait_for_idle(rdev))	142	if (r520_mc_wait_for_idle(rdev))
148	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");	143	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
149	/* Write VRAM size in case we are limiting it */	144	/* Write VRAM size in case we are limiting it */
150	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);	145	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
151	/* Program MC, should be a 32bits limited address space */	146	/* Program MC, should be a 32bits limited address space */
152	WREG32_MC(R_000004_MC_FB_LOCATION,	147	WREG32_MC(R_000004_MC_FB_LOCATION,
153	S_000004_MC_FB_START(rdev->mc.vram_start >> 16) \|	148	S_000004_MC_FB_START(rdev->mc.vram_start >> 16) \|
154	S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));	149	S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
155	WREG32(R_000134_HDP_FB_LOCATION,	150	WREG32(R_000134_HDP_FB_LOCATION,
156	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));	151	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
157	if (rdev->flags & RADEON_IS_AGP) {	152	if (rdev->flags & RADEON_IS_AGP) {
158	WREG32_MC(R_000005_MC_AGP_LOCATION,	153	WREG32_MC(R_000005_MC_AGP_LOCATION,
159	S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) \|	154	S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
160	S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));	155	S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
161	WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));	156	WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
162	WREG32_MC(R_000007_AGP_BASE_2,	157	WREG32_MC(R_000007_AGP_BASE_2,
163	S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));	158	S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
164	} else {	159	} else {
165	WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);	160	WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
166	WREG32_MC(R_000006_AGP_BASE, 0);	161	WREG32_MC(R_000006_AGP_BASE, 0);
167	WREG32_MC(R_000007_AGP_BASE_2, 0);	162	WREG32_MC(R_000007_AGP_BASE_2, 0);
168	}	163	}
169		164
170	rv515_mc_resume(rdev, &save);	165	rv515_mc_resume(rdev, &save);
171	}	166	}
172		167
173	static int r520_startup(struct radeon_device *rdev)	168	static int r520_startup(struct radeon_device *rdev)
174	{	169	{
175	int r;	170	int r;
176		171
177	r520_mc_program(rdev);	172	r520_mc_program(rdev);
178	/* Resume clock */	173	/* Resume clock */
179	rv515_clock_startup(rdev);	174	rv515_clock_startup(rdev);
180	/* Initialize GPU configuration (# pipes, ...) */	175	/* Initialize GPU configuration (# pipes, ...) */
181	r520_gpu_init(rdev);	176	r520_gpu_init(rdev);
182	/* Initialize GART (initialize after TTM so we can allocate	177	/* Initialize GART (initialize after TTM so we can allocate
183	* memory through TTM but finalize after TTM) */	178	* memory through TTM but finalize after TTM) */
184	if (rdev->flags & RADEON_IS_PCIE) {	179	if (rdev->flags & RADEON_IS_PCIE) {
185	r = rv370_pcie_gart_enable(rdev);	180	r = rv370_pcie_gart_enable(rdev);
186	if (r)	181	if (r)
187	return r;	182	return r;
188	}	183	}
189	/* Enable IRQ */	184	/* Enable IRQ */
190	// rs600_irq_set(rdev);	-
191	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);	185	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
192	/* 1M ring buffer */	186	/* 1M ring buffer */
193	r = r100_cp_init(rdev, 1024 * 1024);	187	r = r100_cp_init(rdev, 1024 * 1024);
194	if (r) {	188	if (r) {
195	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);	189	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
196	return r;	190	return r;
197	}	191	}
198	// r = r100_wb_init(rdev);	-
199	// if (r)	-
200	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);	-
201	// r = r100_ib_init(rdev);	-
202	// if (r) {	-
203	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);	-
204	// return r;	-
205	// }	-
206	return 0;	192	return 0;
207	}	193	}
208		194
209		195
210		196
211	int r520_init(struct radeon_device *rdev)	197	int r520_init(struct radeon_device *rdev)
212	{	198	{
213	int r;	199	int r;
214		-
215	ENTER();	-
216		200
217	/* Initialize scratch registers */	201	/* Initialize scratch registers */
218	radeon_scratch_init(rdev);	202	radeon_scratch_init(rdev);
219	/* Initialize surface registers */	203	/* Initialize surface registers */
220	radeon_surface_init(rdev);	204	radeon_surface_init(rdev);
-		205	/* restore some register to sane defaults */
-		206	r100_restore_sanity(rdev);
221	/* TODO: disable VGA need to use VGA request */	207	/* TODO: disable VGA need to use VGA request */
222	/* BIOS*/	208	/* BIOS*/
223	if (!radeon_get_bios(rdev)) {	209	if (!radeon_get_bios(rdev)) {
224	if (ASIC_IS_AVIVO(rdev))	210	if (ASIC_IS_AVIVO(rdev))
225	return -EINVAL;	211	return -EINVAL;
226	}	212	}
227	if (rdev->is_atom_bios) {	213	if (rdev->is_atom_bios) {
228	r = radeon_atombios_init(rdev);	214	r = radeon_atombios_init(rdev);
229	if (r)	215	if (r)
230	return r;	216	return r;
231	} else {	217	} else {
232	dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");	218	dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
233	return -EINVAL;	219	return -EINVAL;
234	}	220	}
235	/* Reset gpu before posting otherwise ATOM will enter infinite loop */	221	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
236	if (radeon_gpu_reset(rdev)) {	222	if (radeon_asic_reset(rdev)) {
237	dev_warn(rdev->dev,	223	dev_warn(rdev->dev,
238	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",	224	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
239	RREG32(R_000E40_RBBM_STATUS),	225	RREG32(R_000E40_RBBM_STATUS),
240	RREG32(R_0007C0_CP_STAT));	226	RREG32(R_0007C0_CP_STAT));
241	}	227	}
242	/* check if cards are posted or not */	228	/* check if cards are posted or not */
243	if (radeon_boot_test_post_card(rdev) == false)	229	if (radeon_boot_test_post_card(rdev) == false)
244	return -EINVAL;	230	return -EINVAL;
245		231
246	if (!radeon_card_posted(rdev) && rdev->bios) {	232	if (!radeon_card_posted(rdev) && rdev->bios) {
247	DRM_INFO("GPU not posted. posting now...\n");	233	DRM_INFO("GPU not posted. posting now...\n");
248	atom_asic_init(rdev->mode_info.atom_context);	234	atom_asic_init(rdev->mode_info.atom_context);
249	}	235	}
250	/* Initialize clocks */	236	/* Initialize clocks */
251	radeon_get_clock_info(rdev->ddev);	237	radeon_get_clock_info(rdev->ddev);
252	/* Initialize power management */	-
253	radeon_pm_init(rdev);	-
254	/* initialize AGP */	238	/* initialize AGP */
255	if (rdev->flags & RADEON_IS_AGP) {	239	if (rdev->flags & RADEON_IS_AGP) {
256	r = radeon_agp_init(rdev);	240	r = radeon_agp_init(rdev);
257	if (r) {	241	if (r) {
258	radeon_agp_disable(rdev);	242	radeon_agp_disable(rdev);
259	}	243	}
260	}	244	}
261	/* initialize memory controller */	245	/* initialize memory controller */
262	r520_mc_init(rdev);	246	r520_mc_init(rdev);
263	rv515_debugfs(rdev);	247	rv515_debugfs(rdev);
264	/* Fence driver */	248	/* Fence driver */
265	// r = radeon_fence_driver_init(rdev);	-
266	// if (r)	-
267	// return r;	-
268	// r = radeon_irq_kms_init(rdev);	-
269	// if (r)	-
270	// return r;	-
271	/* Memory manager */	249	/* Memory manager */
272	r = radeon_bo_init(rdev);	250	r = radeon_bo_init(rdev);
273	if (r)	251	if (r)
274	return r;	252	return r;
275	r = rv370_pcie_gart_init(rdev);	253	r = rv370_pcie_gart_init(rdev);
276	if (r)	254	if (r)
277	return r;	255	return r;
278	rv515_set_safe_registers(rdev);	256	rv515_set_safe_registers(rdev);
279	rdev->accel_working = true;	257	rdev->accel_working = true;
280	r = r520_startup(rdev);	258	r = r520_startup(rdev);
281	if (r) {	259	if (r) {
282	/* Somethings want wront with the accel init stop accel */	260	/* Somethings want wront with the accel init stop accel */
283	dev_err(rdev->dev, "Disabling GPU acceleration\n");	261	dev_err(rdev->dev, "Disabling GPU acceleration\n");
284	// r100_cp_fini(rdev);	-
285	// r100_wb_fini(rdev);	-
286	// r100_ib_fini(rdev);	-
287	rv370_pcie_gart_fini(rdev);	262	rv370_pcie_gart_fini(rdev);
288	// radeon_agp_fini(rdev);	-
289	rdev->accel_working = false;	263	rdev->accel_working = false;
290	}	264	}
291		-
292	LEAVE();	-
293		-
294	return 0;	265	return 0;
295	}	266	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r520.c – Rev 1430 → 1963