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Rev 1179 Rev 1221
Line 24... Line 24...
24 
 * Authors: Dave Airlie
 24 
 * Authors: Dave Airlie
25 
 *          Alex Deucher
 25 
 *          Alex Deucher
26 
 *          Jerome Glisse
 26 
 *          Jerome Glisse
27 
 */
 27 
 */
28 
#include "drmP.h"
 28 
#include "drmP.h"
29 
#include "radeon_reg.h"
 - 
 
30 
#include "radeon.h"
 29 
#include "radeon.h"
- 
 
 30 
#include "atom.h"
- 
 
 31 
#include "r520d.h"
Line 31... Line -...
31 
 
 - 
 
32 
/* r520,rv530,rv560,rv570,r580 depends on : */
 - 
 
33 
void r100_hdp_reset(struct radeon_device *rdev);
 - 
 
34 
void r420_pipes_init(struct radeon_device *rdev);
 - 
 
35 
void rs600_mc_disable_clients(struct radeon_device *rdev);
 - 
 
36 
void rs600_disable_vga(struct radeon_device *rdev);
 - 
 
37 
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
 - 
 
38 
int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
 - 
 
39 
 
 32 
 
40 
/* This files gather functions specifics to:
 - 
 
41 
 * r520,rv530,rv560,rv570,r580
 - 
 
42 
 *
 - 
 
43 
 * Some of these functions might be used by newer ASICs.
 - 
 
44 
 */
 - 
 
45 
void r520_gpu_init(struct radeon_device *rdev);
 - 
 
46 
int r520_mc_wait_for_idle(struct radeon_device *rdev);
 - 
 
47 
 
 - 
 
48 
 
 - 
 
49 
/*
 - 
 
50 
 * MC
 - 
 
51 
 */
 - 
 
52 
int r520_mc_init(struct radeon_device *rdev)
 - 
 
53 
{
 - 
 
54 
	uint32_t tmp;
 - 
 
55 
	int r;
 - 
 
56 
 
 - 
 
57 
       ENTER();
 - 
 
58 
 
 - 
 
59 
   if (r100_debugfs_rbbm_init(rdev)) {
 - 
 
60 
       DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 - 
 
61 
   }
 - 
 
62 
   if (rv515_debugfs_pipes_info_init(rdev)) {
 - 
 
63 
       DRM_ERROR("Failed to register debugfs file for pipes !\n");
 - 
 
64 
   }
 - 
 
65 
   if (rv515_debugfs_ga_info_init(rdev)) {
 - 
 
66 
       DRM_ERROR("Failed to register debugfs file for pipes !\n");
 - 
 
67 
   }
 - 
 
68 
 
 - 
 
69 
	r520_gpu_init(rdev);
 - 
 
70 
	rv370_pcie_gart_disable(rdev);
 - 
 
71 
 
 - 
 
72 
	/* Setup GPU memory space */
 - 
 
73 
	rdev->mc.vram_location = 0xFFFFFFFFUL;
 - 
 
74 
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
 - 
 
75 
	r = radeon_mc_setup(rdev);
 - 
 
76 
	if (r) {
 - 
 
77 
		return r;
 - 
 
78 
	}
 - 
 
79 
 
 - 
 
80 
	/* Program GPU memory space */
 - 
 
81 
    rs600_mc_disable_clients(rdev);
 - 
 
82 
    if (r520_mc_wait_for_idle(rdev)) {
 - 
 
83 
       printk(KERN_WARNING "Failed to wait MC idle while "
 - 
 
84 
		       "programming pipes. Bad things might happen.\n");
 - 
 
85 
	}
 - 
 
86 
	/* Write VRAM size in case we are limiting it */
 - 
 
87 
	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 - 
 
88 
	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 - 
 
89 
	tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
 - 
 
90 
	tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
 - 
 
91 
	WREG32_MC(R520_MC_FB_LOCATION, tmp);
 - 
 
92 
	WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 - 
 
93 
	WREG32(0x310, rdev->mc.vram_location);
 - 
 
94 
	if (rdev->flags & RADEON_IS_AGP) {
 - 
 
95 
		tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 - 
 
96 
		tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16);
 - 
 
97 
		tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16);
 - 
 
98 
		WREG32_MC(R520_MC_AGP_LOCATION, tmp);
 - 
 
99 
		WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base);
 - 
 
100 
		WREG32_MC(R520_MC_AGP_BASE_2, 0);
 - 
 
101 
	} else {
 - 
 
102 
		WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
 - 
 
103 
		WREG32_MC(R520_MC_AGP_BASE, 0);
 - 
 
104 
		WREG32_MC(R520_MC_AGP_BASE_2, 0);
 - 
 
Line 105... Line -...
105 
	}
 - 
 
106 
 
 - 
 
107 
    LEAVE();
 - 
 
108 
 
 - 
 
109 
	return 0;
 - 
 
110 
}
 - 
 
111 
 
 - 
 
112 
void r520_mc_fini(struct radeon_device *rdev)
 - 
 
113 
{
 - 
 
114 
}
 - 
 
115 
 
 - 
 
116 
 
 - 
 
117 
/*
 - 
 
118 
 * Global GPU functions
 - 
 
119 
 */
 - 
 
120 
void r520_errata(struct radeon_device *rdev)
 - 
 
121 
{
 - 
 
122 
	rdev->pll_errata = 0;
 - 
 
123 
}
 33 
/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
124 
 
 34 
 
125 
int r520_mc_wait_for_idle(struct radeon_device *rdev)
 35 
static int r520_mc_wait_for_idle(struct radeon_device *rdev)
126 
{
 36 
{
Line 127... Line 37...
127 
	unsigned i;
 37 
	unsigned i;
Line 136... Line 46...
136 
		DRM_UDELAY(1);
 46 
		DRM_UDELAY(1);
137 
	}
 47 
	}
138 
	return -1;
 48 
	return -1;
139 
}
 49 
}
Line 140... Line 50...
140 
 
 50 
 
141 
void r520_gpu_init(struct radeon_device *rdev)
 51 
static void r520_gpu_init(struct radeon_device *rdev)
142 
{
 52 
{
143 
	unsigned pipe_select_current, gb_pipe_select, tmp;
 53 
	unsigned pipe_select_current, gb_pipe_select, tmp;
Line 144... Line 54...
144 
    ENTER();
 54 
    ENTER();
145 
 
 55 
 
146 
	r100_hdp_reset(rdev);
 56 
	r100_hdp_reset(rdev);
147 
	rs600_disable_vga(rdev);
 57 
	rv515_vga_render_disable(rdev);
148 
	/*
 58 
	/*
149 
	 * DST_PIPE_CONFIG		0x170C
 59 
	 * DST_PIPE_CONFIG		0x170C
150 
	 * GB_TILE_CONFIG		0x4018
 60 
	 * GB_TILE_CONFIG		0x4018
Line 180... Line 90...
180 
		printk(KERN_WARNING "Failed to wait MC idle while "
 90 
		printk(KERN_WARNING "Failed to wait MC idle while "
181 
		       "programming pipes. Bad things might happen.\n");
 91 
		       "programming pipes. Bad things might happen.\n");
182 
	}
 92 
	}
183 
}
 93 
}
Line 184... Line -...
184 
 
 - 
 
185 
 
 - 
 
186 
/*
 - 
 
187 
 * VRAM info
 - 
 
188 
 */
 94 
 
189 
static void r520_vram_get_type(struct radeon_device *rdev)
 95 
static void r520_vram_get_type(struct radeon_device *rdev)
190 
{
 96 
{
191 
	uint32_t tmp;
 97 
	uint32_t tmp;
Line 228... Line 134...
228 
	a.full = rfixed_const(100);
 134 
	a.full = rfixed_const(100);
229 
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 135 
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
230 
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 136 
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
231 
}
 137 
}
Line 232... Line 138...
232 
 
 138 
 
233 
void r520_bandwidth_update(struct radeon_device *rdev)
 139 
void r520_mc_program(struct radeon_device *rdev)
- 
 
 140 
{
- 
 
 141 
	struct rv515_mc_save save;
- 
 
 142 
 
- 
 
 143 
	/* Stops all mc clients */
- 
 
 144 
	rv515_mc_stop(rdev, &save);
- 
 
 145 
 
- 
 
 146 
	/* Wait for mc idle */
- 
 
 147 
	if (r520_mc_wait_for_idle(rdev))
- 
 
 148 
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
- 
 
 149 
	/* Write VRAM size in case we are limiting it */
- 
 
 150 
	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
- 
 
 151 
	/* Program MC, should be a 32bits limited address space */
- 
 
 152 
	WREG32_MC(R_000004_MC_FB_LOCATION,
- 
 
 153 
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
- 
 
 154 
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
- 
 
 155 
	WREG32(R_000134_HDP_FB_LOCATION,
- 
 
 156 
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
- 
 
 157 
	if (rdev->flags & RADEON_IS_AGP) {
- 
 
 158 
		WREG32_MC(R_000005_MC_AGP_LOCATION,
- 
 
 159 
			S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
- 
 
 160 
			S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
- 
 
 161 
		WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
- 
 
 162 
		WREG32_MC(R_000007_AGP_BASE_2,
- 
 
 163 
			S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
- 
 
 164 
	} else {
- 
 
 165 
		WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
- 
 
 166 
		WREG32_MC(R_000006_AGP_BASE, 0);
- 
 
 167 
		WREG32_MC(R_000007_AGP_BASE_2, 0);
- 
 
 168 
	}
- 
 
 169 
 
- 
 
 170 
	rv515_mc_resume(rdev, &save);
- 
 
 171 
}
- 
 
 172 
 
- 
 
 173 
static int r520_startup(struct radeon_device *rdev)
- 
 
 174 
{
- 
 
 175 
	int r;
- 
 
 176 
 
- 
 
 177 
	r520_mc_program(rdev);
234 
{
 178 
	/* Resume clock */
- 
 
 179 
	rv515_clock_startup(rdev);
- 
 
 180 
	/* Initialize GPU configuration (# pipes, ...) */
- 
 
 181 
	r520_gpu_init(rdev);
- 
 
 182 
	/* Initialize GART (initialize after TTM so we can allocate
- 
 
 183 
	 * memory through TTM but finalize after TTM) */
- 
 
 184 
	if (rdev->flags & RADEON_IS_PCIE) {
- 
 
 185 
		r = rv370_pcie_gart_enable(rdev);
- 
 
 186 
		if (r)
- 
 
 187 
			return r;
- 
 
 188 
	}
- 
 
 189 
	/* Enable IRQ */
- 
 
 190 
//   rdev->irq.sw_int = true;
- 
 
 191 
//   rs600_irq_set(rdev);
- 
 
 192 
	/* 1M ring buffer */
- 
 
 193 
//   r = r100_cp_init(rdev, 1024 * 1024);
- 
 
 194 
//   if (r) {
- 
 
 195 
//       dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
- 
 
 196 
//       return r;
- 
 
 197 
//   }
- 
 
 198 
//	r = r100_wb_init(rdev);
- 
 
 199 
//	if (r)
- 
 
 200 
//		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
- 
 
 201 
//	r = r100_ib_init(rdev);
- 
 
 202 
//	if (r) {
- 
 
 203 
//		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
- 
 
 204 
//		return r;
- 
 
 205 
//	}
- 
 
 206 
	return 0;
- 
 
 207 
}
- 
 
 208 
 
- 
 
 209 
 
- 
 
 210 
 
- 
 
 211 
int r520_init(struct radeon_device *rdev)
- 
 
 212 
{
- 
 
 213 
	int r;
- 
 
 214 
 
- 
 
 215 
    ENTER();
- 
 
 216 
 
- 
 
 217 
	/* Initialize scratch registers */
- 
 
 218 
	radeon_scratch_init(rdev);
- 
 
 219 
	/* Initialize surface registers */
- 
 
 220 
	radeon_surface_init(rdev);
- 
 
 221 
	/* TODO: disable VGA need to use VGA request */
- 
 
 222 
	/* BIOS*/
- 
 
 223 
	if (!radeon_get_bios(rdev)) {
- 
 
 224 
		if (ASIC_IS_AVIVO(rdev))
- 
 
 225 
			return -EINVAL;
- 
 
 226 
	}
- 
 
 227 
	if (rdev->is_atom_bios) {
- 
 
 228 
		r = radeon_atombios_init(rdev);
- 
 
 229 
		if (r)
- 
 
 230 
			return r;
- 
 
 231 
	} else {
- 
 
 232 
		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
- 
 
 233 
		return -EINVAL;
- 
 
 234 
	}
- 
 
 235 
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
- 
 
 236 
	if (radeon_gpu_reset(rdev)) {
- 
 
 237 
		dev_warn(rdev->dev,
- 
 
 238 
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
- 
 
 239 
			RREG32(R_000E40_RBBM_STATUS),
- 
 
 240 
			RREG32(R_0007C0_CP_STAT));
- 
 
 241 
	}
- 
 
 242 
	/* check if cards are posted or not */
- 
 
 243 
	if (!radeon_card_posted(rdev) && rdev->bios) {
- 
 
 244 
		DRM_INFO("GPU not posted. posting now...\n");
- 
 
 245 
		atom_asic_init(rdev->mode_info.atom_context);
- 
 
 246 
	}
- 
 
 247 
	/* Initialize clocks */
- 
 
 248 
	radeon_get_clock_info(rdev->ddev);
- 
 
 249 
	/* Get vram informations */
- 
 
 250 
	r520_vram_info(rdev);
- 
 
 251 
	/* Initialize memory controller (also test AGP) */
- 
 
 252 
	r = r420_mc_init(rdev);
- 
 
 253 
	if (r)
- 
 
 254 
		return r;
- 
 
 255 
	rv515_debugfs(rdev);
- 
 
 256 
	/* Fence driver */
- 
 
 257 
//   r = radeon_fence_driver_init(rdev);
- 
 
 258 
//   if (r)
- 
 
 259 
//       return r;
- 
 
 260 
//   r = radeon_irq_kms_init(rdev);
- 
 
 261 
//   if (r)
- 
 
 262 
//       return r;
- 
 
 263 
	/* Memory manager */
- 
 
 264 
	r = radeon_object_init(rdev);
- 
 
 265 
	if (r)
- 
 
 266 
		return r;
- 
 
 267 
	r = rv370_pcie_gart_init(rdev);
- 
 
 268 
	if (r)
- 
 
 269 
		return r;
- 
 
 270 
	rv515_set_safe_registers(rdev);
- 
 
 271 
	rdev->accel_working = true;
- 
 
 272 
	r = r520_startup(rdev);
- 
 
 273 
	if (r) {
- 
 
 274 
		/* Somethings want wront with the accel init stop accel */
- 
 
 275 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
- 
 
 276 
//       rv515_suspend(rdev);
- 
 
 277 
//       r100_cp_fini(rdev);
- 
 
 278 
//       r100_wb_fini(rdev);
- 
 
 279 
//       r100_ib_fini(rdev);
- 
 
 280 
		rv370_pcie_gart_fini(rdev);
- 
 
 281 
//       radeon_agp_fini(rdev);
- 
 
 282 
//       radeon_irq_kms_fini(rdev);
- 
 
 283 
		rdev->accel_working = false;
- 
 
 284 
	}
- 
 
 285 
 
- 
 
 286 
    LEAVE();
- 
 
 287 
 
235 
	rv515_bandwidth_avivo_update(rdev);
 288 
	return 0;