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Line 29... Line 29...
29
#include "radeon_reg.h"
29
#include "radeon_reg.h"
30
#include "radeon.h"
30
#include "radeon.h"
Line 31... Line 31...
31
 
31
 
32
/* r520,rv530,rv560,rv570,r580 depends on : */
32
/* r520,rv530,rv560,rv570,r580 depends on : */
33
void r100_hdp_reset(struct radeon_device *rdev);
-
 
34
int rv370_pcie_gart_enable(struct radeon_device *rdev);
-
 
35
void rv370_pcie_gart_disable(struct radeon_device *rdev);
33
void r100_hdp_reset(struct radeon_device *rdev);
36
void r420_pipes_init(struct radeon_device *rdev);
34
void r420_pipes_init(struct radeon_device *rdev);
37
void rs600_mc_disable_clients(struct radeon_device *rdev);
35
void rs600_mc_disable_clients(struct radeon_device *rdev);
38
void rs600_disable_vga(struct radeon_device *rdev);
36
void rs600_disable_vga(struct radeon_device *rdev);
39
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
Line 45... Line 43...
45
 * Some of these functions might be used by newer ASICs.
43
 * Some of these functions might be used by newer ASICs.
46
 */
44
 */
47
void r520_gpu_init(struct radeon_device *rdev);
45
void r520_gpu_init(struct radeon_device *rdev);
48
int r520_mc_wait_for_idle(struct radeon_device *rdev);
46
int r520_mc_wait_for_idle(struct radeon_device *rdev);
Line -... Line 47...
-
 
47
 
49
 
48
 
50
/*
49
/*
51
 * MC
50
 * MC
52
 */
51
 */
53
int r520_mc_init(struct radeon_device *rdev)
52
int r520_mc_init(struct radeon_device *rdev)
54
{
53
{
55
	uint32_t tmp;
54
	uint32_t tmp;
Line 56... Line 55...
56
	int r;
55
	int r;
Line 57... Line 56...
57
 
56
 
58
    dbgprintf("%s\n",__FUNCTION__);
57
       ENTER();
59
 
58
 
60
   if (r100_debugfs_rbbm_init(rdev)) {
59
   if (r100_debugfs_rbbm_init(rdev)) {
Line 71... Line 70...
71
	rv370_pcie_gart_disable(rdev);
70
	rv370_pcie_gart_disable(rdev);
Line 72... Line 71...
72
 
71
 
73
	/* Setup GPU memory space */
72
	/* Setup GPU memory space */
74
	rdev->mc.vram_location = 0xFFFFFFFFUL;
73
	rdev->mc.vram_location = 0xFFFFFFFFUL;
75
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
-
 
76
	if (rdev->flags & RADEON_IS_AGP) {
-
 
77
		r = radeon_agp_init(rdev);
-
 
78
		if (r) {
-
 
79
			printk(KERN_WARNING "[drm] Disabling AGP\n");
-
 
80
			rdev->flags &= ~RADEON_IS_AGP;
-
 
81
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
-
 
82
		} else {
-
 
83
			rdev->mc.gtt_location = rdev->mc.agp_base;
-
 
84
		}
-
 
85
	}
74
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
86
	r = radeon_mc_setup(rdev);
75
	r = radeon_mc_setup(rdev);
87
	if (r) {
76
	if (r) {
88
		return r;
77
		return r;
Line 93... Line 82...
93
    if (r520_mc_wait_for_idle(rdev)) {
82
    if (r520_mc_wait_for_idle(rdev)) {
94
       printk(KERN_WARNING "Failed to wait MC idle while "
83
       printk(KERN_WARNING "Failed to wait MC idle while "
95
		       "programming pipes. Bad things might happen.\n");
84
		       "programming pipes. Bad things might happen.\n");
96
	}
85
	}
97
	/* Write VRAM size in case we are limiting it */
86
	/* Write VRAM size in case we are limiting it */
98
	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
87
	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
99
	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
88
	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
100
	tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
89
	tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
101
	tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
90
	tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
102
	WREG32_MC(R520_MC_FB_LOCATION, tmp);
91
	WREG32_MC(R520_MC_FB_LOCATION, tmp);
103
	WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
92
	WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
104
	WREG32(0x310, rdev->mc.vram_location);
93
	WREG32(0x310, rdev->mc.vram_location);
Line 113... Line 102...
113
		WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
102
		WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
114
		WREG32_MC(R520_MC_AGP_BASE, 0);
103
		WREG32_MC(R520_MC_AGP_BASE, 0);
115
		WREG32_MC(R520_MC_AGP_BASE_2, 0);
104
		WREG32_MC(R520_MC_AGP_BASE_2, 0);
116
	}
105
	}
Line 117... Line 106...
117
 
106
 
Line 118... Line 107...
118
    dbgprintf("done: %s\n",__FUNCTION__);
107
    LEAVE();
119
 
108
 
Line 120... Line 109...
120
	return 0;
109
	return 0;
121
}
110
}
122
 
-
 
123
void r520_mc_fini(struct radeon_device *rdev)
-
 
124
{
-
 
125
	rv370_pcie_gart_disable(rdev);
111
 
Line 126... Line 112...
126
	radeon_gart_table_vram_free(rdev);
112
void r520_mc_fini(struct radeon_device *rdev)
127
	radeon_gart_fini(rdev);
113
{
Line 153... Line 139...
153
}
139
}
Line 154... Line 140...
154
 
140
 
155
void r520_gpu_init(struct radeon_device *rdev)
141
void r520_gpu_init(struct radeon_device *rdev)
156
{
142
{
157
	unsigned pipe_select_current, gb_pipe_select, tmp;
143
	unsigned pipe_select_current, gb_pipe_select, tmp;
Line 158... Line 144...
158
    dbgprintf("%s\n",__FUNCTION__);
144
    ENTER();
159
 
145
 
160
	r100_hdp_reset(rdev);
146
	r100_hdp_reset(rdev);
161
	rs600_disable_vga(rdev);
147
	rs600_disable_vga(rdev);
Line 179... Line 165...
179
	 * GA_ENHANCE			0x4274
165
	 * GA_ENHANCE			0x4274
180
	 * SU_REG_DEST			0x42C8
166
	 * SU_REG_DEST			0x42C8
181
	 */
167
	 */
182
	/* workaround for RV530 */
168
	/* workaround for RV530 */
183
	if (rdev->family == CHIP_RV530) {
169
	if (rdev->family == CHIP_RV530) {
184
		WREG32(0x4124, 1);
-
 
185
		WREG32(0x4128, 0xFF);
170
		WREG32(0x4128, 0xFF);
186
	}
171
	}
187
	r420_pipes_init(rdev);
172
	r420_pipes_init(rdev);
188
	gb_pipe_select = RREG32(0x402C);
173
	gb_pipe_select = RREG32(0x402C);
189
	tmp = RREG32(0x170C);
174
	tmp = RREG32(0x170C);
Line 202... Line 187...
202
 * VRAM info
187
 * VRAM info
203
 */
188
 */
204
static void r520_vram_get_type(struct radeon_device *rdev)
189
static void r520_vram_get_type(struct radeon_device *rdev)
205
{
190
{
206
	uint32_t tmp;
191
	uint32_t tmp;
207
    dbgprintf("%s\n",__FUNCTION__);
192
    ENTER();
Line 208... Line 193...
208
 
193
 
209
	rdev->mc.vram_width = 128;
194
	rdev->mc.vram_width = 128;
210
	rdev->mc.vram_is_ddr = true;
195
	rdev->mc.vram_is_ddr = true;
211
	tmp = RREG32_MC(R520_MC_CNTL0);
196
	tmp = RREG32_MC(R520_MC_CNTL0);
Line 230... Line 215...
230
		rdev->mc.vram_width *= 2;
215
		rdev->mc.vram_width *= 2;
231
}
216
}
Line 232... Line 217...
232
 
217
 
233
void r520_vram_info(struct radeon_device *rdev)
218
void r520_vram_info(struct radeon_device *rdev)
234
{
-
 
235
	r520_vram_get_type(rdev);
-
 
236
	rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
-
 
237
 
-
 
238
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
-
 
239
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
-
 
240
}
-
 
241
 
-
 
242
 
-
 
243
int radeon_agp_init(struct radeon_device *rdev)
-
 
244
{
-
 
245
 
-
 
246
    dbgprintf("%s\n",__FUNCTION__);
-
 
247
 
-
 
248
#if __OS_HAS_AGP
-
 
249
    struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list;
-
 
250
    struct drm_agp_mode mode;
-
 
251
    struct drm_agp_info info;
-
 
252
    uint32_t agp_status;
-
 
253
    int default_mode;
-
 
254
    bool is_v3;
-
 
255
    int ret;
-
 
256
 
-
 
257
    /* Acquire AGP. */
-
 
258
    if (!rdev->ddev->agp->acquired) {
-
 
259
        ret = drm_agp_acquire(rdev->ddev);
-
 
260
        if (ret) {
-
 
261
            DRM_ERROR("Unable to acquire AGP: %d\n", ret);
-
 
262
            return ret;
-
 
263
        }
-
 
264
    }
-
 
265
 
-
 
266
    ret = drm_agp_info(rdev->ddev, &info);
-
 
267
    if (ret) {
-
 
268
        DRM_ERROR("Unable to get AGP info: %d\n", ret);
-
 
269
        return ret;
-
 
270
    }
-
 
271
    mode.mode = info.mode;
-
 
272
    agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
-
 
273
    is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
-
 
274
 
219
{
275
    if (is_v3) {
-
 
276
        default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
-
 
277
    } else {
-
 
278
        if (agp_status & RADEON_AGP_4X_MODE) {
-
 
279
            default_mode = 4;
-
 
280
        } else if (agp_status & RADEON_AGP_2X_MODE) {
-
 
281
            default_mode = 2;
-
 
282
        } else {
-
 
283
            default_mode = 1;
-
 
284
        }
-
 
285
    }
-
 
286
 
-
 
287
    /* Apply AGPMode Quirks */
-
 
288
    while (p && p->chip_device != 0) {
-
 
289
        if (info.id_vendor == p->hostbridge_vendor &&
-
 
290
            info.id_device == p->hostbridge_device &&
-
 
291
            rdev->pdev->vendor == p->chip_vendor &&
-
 
292
            rdev->pdev->device == p->chip_device &&
-
 
293
            rdev->pdev->subsystem_vendor == p->subsys_vendor &&
-
 
294
            rdev->pdev->subsystem_device == p->subsys_device) {
-
 
295
            default_mode = p->default_mode;
-
 
296
        }
-
 
297
        ++p;
-
 
298
    }
-
 
299
 
-
 
300
    if (radeon_agpmode > 0) {
-
 
301
        if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
-
 
302
            (radeon_agpmode > (is_v3 ? 8 : 4)) ||
-
 
303
            (radeon_agpmode & (radeon_agpmode - 1))) {
-
 
304
            DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
-
 
305
                  radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
-
 
306
                  default_mode);
-
 
307
            radeon_agpmode = default_mode;
-
 
308
        } else {
-
 
309
            DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
-
 
310
        }
-
 
311
    } else {
-
 
312
        radeon_agpmode = default_mode;
-
 
Line 313... Line -...
313
    }
-
 
314
 
-
 
315
    mode.mode &= ~RADEON_AGP_MODE_MASK;
-
 
316
    if (is_v3) {
-
 
317
        switch (radeon_agpmode) {
-
 
318
        case 8:
-
 
319
            mode.mode |= RADEON_AGPv3_8X_MODE;
-
 
320
            break;
-
 
321
        case 4:
-
 
322
        default:
-
 
323
            mode.mode |= RADEON_AGPv3_4X_MODE;
-
 
324
            break;
-
 
325
        }
-
 
326
    } else {
-
 
327
        switch (radeon_agpmode) {
-
 
328
        case 4:
-
 
329
            mode.mode |= RADEON_AGP_4X_MODE;
-
 
330
            break;
-
 
331
        case 2:
-
 
332
            mode.mode |= RADEON_AGP_2X_MODE;
-
 
333
            break;
-
 
334
        case 1:
-
 
335
        default:
-
 
336
            mode.mode |= RADEON_AGP_1X_MODE;
-
 
337
            break;
-
 
338
        }
-
 
339
    }
-
 
340
 
220
	fixed20_12 a;
341
    mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
-
 
342
    ret = drm_agp_enable(rdev->ddev, mode);
-
 
343
    if (ret) {
-
 
344
        DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
-
 
Line 345... Line 221...
345
        return ret;
221
 
346
    }
222
	r520_vram_get_type(rdev);
347
 
-
 
348
    rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base;
223
 
349
    rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20;
-
 
350
 
-
 
351
    /* workaround some hw issues */
224
	r100_vram_init_sizes(rdev);
352
    if (rdev->family < CHIP_R200) {
225
	/* FIXME: we should enforce default clock in case GPU is not in
353
        WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
-
 
-
 
226
	 * default setup
354
    }
227
	 */
355
    return 0;
-
 
356
#else
228
	a.full = rfixed_const(100);
Line 357... Line -...
357
    return 0;
-
 
358
#endif
-
 
359
}
-
 
360
 
229
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
361
 
-
 
362
 
-
 
363
 
-
 
364
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
-
 
365
 
-
 
366
 
230
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
367
 
231
}
368
 
-
 
369
int radeon_fence_driver_init(struct radeon_device *rdev)
-
 
370
{
-
 
371
    unsigned long irq_flags;
-
 
372
    int r;
-
 
373
 
-
 
374
//    write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
-
 
375
    r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
-
 
376
    if (r) {
232
 
377
        DRM_ERROR("Fence failed to get a scratch register.");
-
 
378
//        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
-
 
379
        return r;
-
 
380
    }
-
 
381
    WREG32(rdev->fence_drv.scratch_reg, 0);
-
 
382
//    atomic_set(&rdev->fence_drv.seq, 0);
-
 
383
//    INIT_LIST_HEAD(&rdev->fence_drv.created);
-
 
384
//    INIT_LIST_HEAD(&rdev->fence_drv.emited);
-
 
385
//    INIT_LIST_HEAD(&rdev->fence_drv.signaled);
-
 
386
    rdev->fence_drv.count_timeout = 0;
-
 
387
//    init_waitqueue_head(&rdev->fence_drv.queue);
-
 
388
//    write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
-
 
389
//    if (radeon_debugfs_fence_init(rdev)) {
-
 
390
//        DRM_ERROR("Failed to register debugfs file for fence !\n");
-
 
391
//    }
-