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401 | /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 |
401 | /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 |
402 | * block and vice versa. This applies to GRPH, CUR, etc. |
402 | * block and vice versa. This applies to GRPH, CUR, etc. |
403 | */ |
403 | */ |
- | 404 | #define AVIVO_D1GRPH_LUT_SEL 0x6108 |
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404 | #define AVIVO_D1GRPH_LUT_SEL 0x6108 |
405 | # define AVIVO_LUT_10BIT_BYPASS_EN (1 << 8) |
405 | #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
406 | #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
406 | #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 |
407 | #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 |
407 | #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 |
408 | #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 |
408 | #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 |
409 | #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 |