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Rev 3764 Rev 5078
Line 158... Line 158...
158 
		 rdev->num_gb_pipes, rdev->num_z_pipes);
 158 
		 rdev->num_gb_pipes, rdev->num_z_pipes);
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}
 159 
}
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 160 
 
161 
u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 161 
u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
- 
 
 162 
{
162 
{
 163 
	unsigned long flags;
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- 
 
 164 
	u32 r;
163 
	u32 r;
 165 
 
164 
 
 166 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
- 
 
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	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
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	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
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	r = RREG32(R_0001FC_MC_IND_DATA);
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	r = RREG32(R_0001FC_MC_IND_DATA);
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	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
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	return r;
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	return r;
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}
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}
- 
 
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- 
 
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void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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 174 
{
169 
 
 175 
	unsigned long flags;
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void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 176 
 
171 
{
 177 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
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	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
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	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
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		S_0001F8_MC_IND_WR_EN(1));
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		S_0001F8_MC_IND_WR_EN(1));
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	WREG32(R_0001FC_MC_IND_DATA, v);
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	WREG32(R_0001FC_MC_IND_DATA, v);
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	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
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}
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}
Line 210... Line 217...
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	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
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	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
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	radeon_ring_lock(rdev, ring, 8);
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	radeon_ring_lock(rdev, ring, 8);
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	radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
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	radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
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	radeon_ring_write(ring, rdev->config.r300.resync_scratch);
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	radeon_ring_write(ring, rdev->config.r300.resync_scratch);
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	radeon_ring_write(ring, 0xDEADBEEF);
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	radeon_ring_write(ring, 0xDEADBEEF);
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	radeon_ring_unlock_commit(rdev, ring);
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	radeon_ring_unlock_commit(rdev, ring, false);
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}
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}
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 224 
 
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static void r420_cp_errata_fini(struct radeon_device *rdev)
 225 
static void r420_cp_errata_fini(struct radeon_device *rdev)
219 
{
 226 
{
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	 * at the very beginning of the CP init.
 230 
	 * at the very beginning of the CP init.
224 
	 */
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	 */
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	radeon_ring_lock(rdev, ring, 8);
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	radeon_ring_lock(rdev, ring, 8);
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	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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	radeon_ring_write(ring, R300_RB3D_DC_FINISH);
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	radeon_ring_write(ring, R300_RB3D_DC_FINISH);
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	radeon_ring_unlock_commit(rdev, ring);
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	radeon_ring_unlock_commit(rdev, ring, false);
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	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 236 
	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
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}
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}
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 238 
 
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static int r420_startup(struct radeon_device *rdev)
 239 
static int r420_startup(struct radeon_device *rdev)
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		if (r)
 375 
		if (r)
369 
			return r;
 376 
			return r;
370 
	}
 377 
	}
371 
	r420_set_reg_safe(rdev);
 378 
	r420_set_reg_safe(rdev);
Line -... Line 379...
- 
 
 379 
 
- 
 
 380 
	/* Initialize power management */
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 381 
	radeon_pm_init(rdev);
372 
 
 382 
 
373 
	rdev->accel_working = true;
 383 
	rdev->accel_working = true;
374 
	r = r420_startup(rdev);
 384 
	r = r420_startup(rdev);
375 
	if (r) {
 385 
	if (r) {
376 
		/* Somethings want wront with the accel init stop accel */
 386 
		/* Somethings want wront with the accel init stop accel */