Subversion Repositories Kolibri OS

Rev

Rev 1430 | Rev 2005 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 1430 Rev 1963
Line 24... Line 24...
24 
 * Authors: Dave Airlie
 24 
 * Authors: Dave Airlie
25 
 *          Alex Deucher
 25 
 *          Alex Deucher
26 
 *          Jerome Glisse
 26 
 *          Jerome Glisse
27 
 */
 27 
 */
28 
#include
28 
#include
- 
 
 29 
#include
29 
#include "drmP.h"
 30 
#include "drmP.h"
30 
#include "radeon_reg.h"
 31 
#include "radeon_reg.h"
31 
#include "radeon.h"
 32 
#include "radeon.h"
- 
 
 33 
#include "radeon_asic.h"
32 
#include "atom.h"
 34 
#include "atom.h"
33 
#include "r100d.h"
 35 
#include "r100d.h"
34 
#include "r420d.h"
 36 
#include "r420d.h"
35 
#include "r420_reg_safe.h"
 37 
#include "r420_reg_safe.h"
Line 53... Line 55...
53 
	if (r100_gui_wait_for_idle(rdev)) {
 55 
	if (r100_gui_wait_for_idle(rdev)) {
54 
		printk(KERN_WARNING "Failed to wait GUI idle while "
 56 
		printk(KERN_WARNING "Failed to wait GUI idle while "
55 
		       "programming pipes. Bad things might happen.\n");
 57 
		       "programming pipes. Bad things might happen.\n");
56 
	}
 58 
	}
57 
	/* get max number of pipes */
 59 
	/* get max number of pipes */
58 
	gb_pipe_select = RREG32(0x402C);
 60 
	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
59 
	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
 61 
	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
- 
 
 62 
 
- 
 
 63 
	/* SE chips have 1 pipe */
- 
 
 64 
	if ((rdev->pdev->device == 0x5e4c) ||
- 
 
 65 
	    (rdev->pdev->device == 0x5e4f))
- 
 
 66 
		num_pipes = 1;
- 
 
 67 
 
60 
	rdev->num_gb_pipes = num_pipes;
 68 
	rdev->num_gb_pipes = num_pipes;
61 
	tmp = 0;
 69 
	tmp = 0;
62 
	switch (num_pipes) {
 70 
	switch (num_pipes) {
63 
	default:
 71 
	default:
64 
		/* force to 1 pipe */
 72 
		/* force to 1 pipe */
Line 200... Line 208...
200 
		if (r)
 208 
		if (r)
201 
			return r;
 209 
			return r;
202 
	}
 210 
	}
203 
	r420_pipes_init(rdev);
 211 
	r420_pipes_init(rdev);
204 
	/* Enable IRQ */
 212 
	/* Enable IRQ */
205 
//	r100_irq_set(rdev);
 - 
 
206 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 213 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
207 
	/* 1M ring buffer */
 214 
	/* 1M ring buffer */
208 
	r = r100_cp_init(rdev, 1024 * 1024);
 215 
	r = r100_cp_init(rdev, 1024 * 1024);
209 
	if (r) {
 216 
	if (r) {
210 
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 217 
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
211 
		return r;
 218 
		return r;
212 
	}
 219 
	}
213 
	r420_cp_errata_init(rdev);
 220 
	r420_cp_errata_init(rdev);
214 
//	r = r100_wb_init(rdev);
 - 
 
215 
//	if (r) {
 - 
 
216 
//		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 - 
 
217 
//	}
 - 
 
218 
//	r = r100_ib_init(rdev);
 - 
 
219 
//	if (r) {
 - 
 
220 
//		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 - 
 
221 
//		return r;
 - 
 
222 
//	}
 - 
 
223 
	return 0;
 221 
	return 0;
224 
}
 222 
}
Line 225... Line 223...
225 
 
 223 
 
226 
int r420_resume(struct radeon_device *rdev)
 224 
int r420_resume(struct radeon_device *rdev)
Line 231... Line 229...
231 
	if (rdev->flags & RADEON_IS_PCI)
 229 
	if (rdev->flags & RADEON_IS_PCI)
232 
		r100_pci_gart_disable(rdev);
 230 
		r100_pci_gart_disable(rdev);
233 
	/* Resume clock before doing reset */
 231 
	/* Resume clock before doing reset */
234 
	r420_clock_resume(rdev);
 232 
	r420_clock_resume(rdev);
235 
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
 233 
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
236 
	if (radeon_gpu_reset(rdev)) {
 234 
	if (radeon_asic_reset(rdev)) {
237 
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 235 
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
238 
			RREG32(R_000E40_RBBM_STATUS),
 236 
			RREG32(R_000E40_RBBM_STATUS),
239 
			RREG32(R_0007C0_CP_STAT));
 237 
			RREG32(R_0007C0_CP_STAT));
240 
	}
 238 
	}
241 
	/* check if cards are posted or not */
 239 
	/* check if cards are posted or not */
Line 260... Line 258...
260 
	/* Initialize scratch registers */
 258 
	/* Initialize scratch registers */
261 
	radeon_scratch_init(rdev);
 259 
	radeon_scratch_init(rdev);
262 
	/* Initialize surface registers */
 260 
	/* Initialize surface registers */
263 
	radeon_surface_init(rdev);
 261 
	radeon_surface_init(rdev);
264 
	/* TODO: disable VGA need to use VGA request */
 262 
	/* TODO: disable VGA need to use VGA request */
- 
 
 263 
	/* restore some register to sane defaults */
- 
 
 264 
	r100_restore_sanity(rdev);
265 
	/* BIOS*/
 265 
	/* BIOS*/
266 
	if (!radeon_get_bios(rdev)) {
 266 
	if (!radeon_get_bios(rdev)) {
267 
		if (ASIC_IS_AVIVO(rdev))
 267 
		if (ASIC_IS_AVIVO(rdev))
268 
			return -EINVAL;
 268 
			return -EINVAL;
269 
	}
 269 
	}
Line 277... Line 277...
277 
		if (r) {
 277 
		if (r) {
278 
			return r;
 278 
			return r;
279 
		}
 279 
		}
280 
	}
 280 
	}
281 
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
 281 
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
282 
	if (radeon_gpu_reset(rdev)) {
 282 
	if (radeon_asic_reset(rdev)) {
283 
		dev_warn(rdev->dev,
 283 
		dev_warn(rdev->dev,
284 
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 284 
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
285 
			RREG32(R_000E40_RBBM_STATUS),
 285 
			RREG32(R_000E40_RBBM_STATUS),
286 
			RREG32(R_0007C0_CP_STAT));
 286 
			RREG32(R_0007C0_CP_STAT));
287 
	}
 287 
	}
Line 289... Line 289...
289 
	if (radeon_boot_test_post_card(rdev) == false)
 289 
	if (radeon_boot_test_post_card(rdev) == false)
290 
		return -EINVAL;
 290 
		return -EINVAL;
Line 291... Line 291...
291 
 
 291 
 
292 
	/* Initialize clocks */
 292 
	/* Initialize clocks */
293 
	radeon_get_clock_info(rdev->ddev);
 - 
 
294 
	/* Initialize power management */
 - 
 
295 
	radeon_pm_init(rdev);
 293 
	radeon_get_clock_info(rdev->ddev);
296 
	/* initialize AGP */
 294 
	/* initialize AGP */
297 
	if (rdev->flags & RADEON_IS_AGP) {
 295 
	if (rdev->flags & RADEON_IS_AGP) {
298 
		r = radeon_agp_init(rdev);
 296 
		r = radeon_agp_init(rdev);
299 
	if (r) {
 297 
	if (r) {
Line 302... Line 300...
302 
	}
 300 
	}
303 
	/* initialize memory controller */
 301 
	/* initialize memory controller */
304 
	r300_mc_init(rdev);
 302 
	r300_mc_init(rdev);
305 
	r420_debugfs(rdev);
 303 
	r420_debugfs(rdev);
306 
	/* Fence driver */
 304 
	/* Fence driver */
307 
//	r = radeon_fence_driver_init(rdev);
 - 
 
308 
//	if (r) {
 - 
 
309 
//		return r;
 - 
 
310 
//	}
 - 
 
311 
//	r = radeon_irq_kms_init(rdev);
 - 
 
312 
//	if (r) {
 - 
 
313 
//		return r;
 - 
 
314 
//	}
 305 
 
315 
	/* Memory manager */
 306 
	/* Memory manager */
316 
	r = radeon_bo_init(rdev);
 307 
	r = radeon_bo_init(rdev);
317 
	if (r) {
 308 
	if (r) {
318 
		return r;
 309 
		return r;
319 
	}
 310 
	}
Line 334... Line 325...
334 
	rdev->accel_working = true;
 325 
	rdev->accel_working = true;
335 
	r = r420_startup(rdev);
 326 
	r = r420_startup(rdev);
336 
	if (r) {
 327 
	if (r) {
337 
		/* Somethings want wront with the accel init stop accel */
 328 
		/* Somethings want wront with the accel init stop accel */
338 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
 329 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
339 
//		r100_cp_fini(rdev);
 - 
 
340 
//		r100_wb_fini(rdev);
 - 
 
341 
//		r100_ib_fini(rdev);
 - 
 
342 
		if (rdev->flags & RADEON_IS_PCIE)
 330 
		if (rdev->flags & RADEON_IS_PCIE)
343 
			rv370_pcie_gart_fini(rdev);
 331 
			rv370_pcie_gart_fini(rdev);
344 
		if (rdev->flags & RADEON_IS_PCI)
 332 
		if (rdev->flags & RADEON_IS_PCI)
345 
			r100_pci_gart_fini(rdev);
 333 
			r100_pci_gart_fini(rdev);
346 
//		radeon_agp_fini(rdev);
 - 
 
347 
		rdev->accel_working = false;
 334 
		rdev->accel_working = false;
348 
	}
 335 
	}
349 
	return 0;
 336 
	return 0;
350 
}
 337 
}