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Rev 1413 Rev 1430
Line 38... Line 38...
38
{
38
{
39
	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
39
	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
40
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
40
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
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}
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}
Line 42... Line -...
42
 
-
 
43
int r420_mc_init(struct radeon_device *rdev)
-
 
44
{
-
 
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	int r;
-
 
46
 
-
 
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	/* Setup GPU memory space */
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48
	rdev->mc.vram_location = 0xFFFFFFFFUL;
-
 
49
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
-
 
50
	if (rdev->flags & RADEON_IS_AGP) {
-
 
51
		r = radeon_agp_init(rdev);
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52
		if (r) {
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53
			radeon_agp_disable(rdev);
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54
		} else {
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			rdev->mc.gtt_location = rdev->mc.agp_base;
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		}
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	}
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	r = radeon_mc_setup(rdev);
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	if (r) {
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		return r;
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	}
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	return 0;
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}
-
 
64
 
42
 
65
void r420_pipes_init(struct radeon_device *rdev)
43
void r420_pipes_init(struct radeon_device *rdev)
66
{
44
{
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	unsigned tmp;
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	unsigned tmp;
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	unsigned gb_pipe_select;
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	unsigned gb_pipe_select;
Line 69... Line 47...
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	unsigned num_pipes;
47
	unsigned num_pipes;
-
 
48
 
70
 
49
	/* GA_ENHANCE workaround TCL deadlock issue */
71
	/* GA_ENHANCE workaround TCL deadlock issue */
50
	WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
72
	WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
51
	       (1 << 2) | (1 << 3));
73
	/* add idle wait as per freedesktop.org bug 24041 */
52
	/* add idle wait as per freedesktop.org bug 24041 */
74
	if (r100_gui_wait_for_idle(rdev)) {
53
	if (r100_gui_wait_for_idle(rdev)) {
75
		printk(KERN_WARNING "Failed to wait GUI idle while "
54
		printk(KERN_WARNING "Failed to wait GUI idle while "
Line 95... Line 74...
95
		break;
74
		break;
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	case 4:
75
	case 4:
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		tmp = (7 << 1);
76
		tmp = (7 << 1);
98
		break;
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		break;
99
	}
78
	}
100
	WREG32(0x42C8, (1 << num_pipes) - 1);
79
	WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
101
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
80
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
102
	tmp |= (1 << 4) | (1 << 0);
81
	tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
103
	WREG32(0x4018, tmp);
82
	WREG32(R300_GB_TILE_CONFIG, tmp);
104
	if (r100_gui_wait_for_idle(rdev)) {
83
	if (r100_gui_wait_for_idle(rdev)) {
105
		printk(KERN_WARNING "Failed to wait GUI idle while "
84
		printk(KERN_WARNING "Failed to wait GUI idle while "
106
		       "programming pipes. Bad things might happen.\n");
85
		       "programming pipes. Bad things might happen.\n");
107
	}
86
	}
Line 108... Line 87...
108
 
87
 
109
	tmp = RREG32(0x170C);
88
	tmp = RREG32(R300_DST_PIPE_CONFIG);
Line 110... Line 89...
110
	WREG32(0x170C, tmp | (1 << 31));
89
	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
111
 
90
 
112
	WREG32(R300_RB2D_DSTCACHE_MODE,
91
	WREG32(R300_RB2D_DSTCACHE_MODE,
113
	       RREG32(R300_RB2D_DSTCACHE_MODE) |
92
	       RREG32(R300_RB2D_DSTCACHE_MODE) |
Line 312... Line 291...
312
 
291
 
313
	/* Initialize clocks */
292
	/* Initialize clocks */
314
	radeon_get_clock_info(rdev->ddev);
293
	radeon_get_clock_info(rdev->ddev);
315
	/* Initialize power management */
294
	/* Initialize power management */
316
	radeon_pm_init(rdev);
295
	radeon_pm_init(rdev);
317
	/* Get vram informations */
-
 
318
	r300_vram_info(rdev);
296
	/* initialize AGP */
319
	/* Initialize memory controller (also test AGP) */
297
	if (rdev->flags & RADEON_IS_AGP) {
320
	r = r420_mc_init(rdev);
298
		r = radeon_agp_init(rdev);
321
	if (r) {
299
	if (r) {
-
 
300
			radeon_agp_disable(rdev);
322
		return r;
301
	}
-
 
302
	}
-
 
303
	/* initialize memory controller */
323
	}
304
	r300_mc_init(rdev);
324
	r420_debugfs(rdev);
305
	r420_debugfs(rdev);
325
	/* Fence driver */
306
	/* Fence driver */
326
//	r = radeon_fence_driver_init(rdev);
307
//	r = radeon_fence_driver_init(rdev);
327
//	if (r) {
308
//	if (r) {