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| Rev 1268 | Rev 1321 | ||
|---|---|---|---|
| Line 167... | Line 167... | ||
| 167 | 167 | ||
| 168 | static int r420_startup(struct radeon_device *rdev) |
168 | static int r420_startup(struct radeon_device *rdev) |
| 169 | { |
169 | { |
| Line -... | Line 170... | ||
| - | 170 | int r; |
|
| - | 171 | ||
| - | 172 | /* set common regs */ |
|
| 170 | int r; |
173 | r100_set_common_regs(rdev); |
| 171 | 174 | /* program mc */ |
|
| 172 | r300_mc_program(rdev); |
175 | r300_mc_program(rdev); |
| 173 | /* Resume clock */ |
176 | /* Resume clock */ |
| 174 | r420_clock_resume(rdev); |
177 | r420_clock_resume(rdev); |
| Line 184... | Line 187... | ||
| 184 | if (r) |
187 | if (r) |
| 185 | return r; |
188 | return r; |
| 186 | } |
189 | } |
| 187 | r420_pipes_init(rdev); |
190 | r420_pipes_init(rdev); |
| 188 | /* Enable IRQ */ |
191 | /* Enable IRQ */ |
| 189 | // rdev->irq.sw_int = true; |
- | |
| 190 | // r100_irq_set(rdev); |
192 | // r100_irq_set(rdev); |
| 191 | /* 1M ring buffer */ |
193 | /* 1M ring buffer */ |
| 192 | // r = r100_cp_init(rdev, 1024 * 1024); |
194 | // r = r100_cp_init(rdev, 1024 * 1024); |
| 193 | // if (r) { |
195 | // if (r) { |
| 194 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
196 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| Line 227... | Line 229... | ||
| 227 | } else { |
229 | } else { |
| 228 | radeon_combios_asic_init(rdev->ddev); |
230 | radeon_combios_asic_init(rdev->ddev); |
| 229 | } |
231 | } |
| 230 | /* Resume clock after posting */ |
232 | /* Resume clock after posting */ |
| 231 | r420_clock_resume(rdev); |
233 | r420_clock_resume(rdev); |
| 232 | - | ||
| - | 234 | /* Initialize surface registers */ |
|
| - | 235 | radeon_surface_init(rdev); |
|
| 233 | return r420_startup(rdev); |
236 | return r420_startup(rdev); |
| 234 | } |
237 | } |
| Line 266... | Line 269... | ||
| 266 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
269 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 267 | RREG32(R_000E40_RBBM_STATUS), |
270 | RREG32(R_000E40_RBBM_STATUS), |
| 268 | RREG32(R_0007C0_CP_STAT)); |
271 | RREG32(R_0007C0_CP_STAT)); |
| 269 | } |
272 | } |
| 270 | /* check if cards are posted or not */ |
273 | /* check if cards are posted or not */ |
| 271 | if (!radeon_card_posted(rdev) && rdev->bios) { |
274 | if (radeon_boot_test_post_card(rdev) == false) |
| 272 | DRM_INFO("GPU not posted. posting now...\n"); |
- | |
| 273 | if (rdev->is_atom_bios) { |
- | |
| 274 | atom_asic_init(rdev->mode_info.atom_context); |
- | |
| 275 | } else { |
275 | return -EINVAL; |
| 276 | radeon_combios_asic_init(rdev->ddev); |
- | |
| 277 | } |
- | |
| 278 | } |
276 | |
| 279 | /* Initialize clocks */ |
277 | /* Initialize clocks */ |
| 280 | radeon_get_clock_info(rdev->ddev); |
278 | radeon_get_clock_info(rdev->ddev); |
| 281 | /* Initialize power management */ |
279 | /* Initialize power management */ |
| 282 | radeon_pm_init(rdev); |
280 | radeon_pm_init(rdev); |
| 283 | /* Get vram informations */ |
281 | /* Get vram informations */ |
| Line 296... | Line 294... | ||
| 296 | // r = radeon_irq_kms_init(rdev); |
294 | // r = radeon_irq_kms_init(rdev); |
| 297 | // if (r) { |
295 | // if (r) { |
| 298 | // return r; |
296 | // return r; |
| 299 | // } |
297 | // } |
| 300 | /* Memory manager */ |
298 | /* Memory manager */ |
| 301 | r = radeon_object_init(rdev); |
299 | r = radeon_bo_init(rdev); |
| 302 | if (r) { |
300 | if (r) { |
| 303 | return r; |
301 | return r; |
| 304 | } |
302 | } |
| - | 303 | if (rdev->family == CHIP_R420) |
|
| - | 304 | r100_enable_bm(rdev); |
|
| - | 305 | ||
| 305 | if (rdev->flags & RADEON_IS_PCIE) { |
306 | if (rdev->flags & RADEON_IS_PCIE) { |
| 306 | r = rv370_pcie_gart_init(rdev); |
307 | r = rv370_pcie_gart_init(rdev); |
| 307 | if (r) |
308 | if (r) |
| 308 | return r; |
309 | return r; |
| 309 | } |
310 | } |