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Rev 1179 Rev 1221
Line 37... Line 37...
37 
	int r;
 37 
	int r;
Line 38... Line 38...
38 
 
 38 
 
39 
	/* Setup GPU memory space */
 39 
	/* Setup GPU memory space */
40 
	rdev->mc.vram_location = 0xFFFFFFFFUL;
 40 
	rdev->mc.vram_location = 0xFFFFFFFFUL;
- 
 
 41 
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
- 
 
 42 
	if (rdev->flags & RADEON_IS_AGP) {
- 
 
 43 
		r = radeon_agp_init(rdev);
- 
 
 44 
		if (r) {
- 
 
 45 
			printk(KERN_WARNING "[drm] Disabling AGP\n");
- 
 
 46 
			rdev->flags &= ~RADEON_IS_AGP;
- 
 
 47 
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
- 
 
 48 
		} else {
- 
 
 49 
			rdev->mc.gtt_location = rdev->mc.agp_base;
- 
 
 50 
		}
41 
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
 51 
	}
42 
	r = radeon_mc_setup(rdev);
 52 
	r = radeon_mc_setup(rdev);
43 
	if (r) {
 53 
	if (r) {
44 
		return r;
 54 
		return r;
45 
	}
 55 
	}
Line 143... Line 153...
143 
}
 153 
}
Line 144... Line 154...
144 
 
 154 
 
145 
static void r420_clock_resume(struct radeon_device *rdev)
 155 
static void r420_clock_resume(struct radeon_device *rdev)
146 
{
 156 
{
- 
 
 157 
	u32 sclk_cntl;
- 
 
 158 
 
- 
 
 159 
	if (radeon_dynclks != -1 && radeon_dynclks)
147 
	u32 sclk_cntl;
 160 
		radeon_atom_set_clock_gating(rdev, 1);
148 
	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 161 
	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
149 
	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 162 
	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
150 
	if (rdev->family == CHIP_R420)
 163 
	if (rdev->family == CHIP_R420)
151 
		sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 164 
		sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
Line 155... Line 168...
155 
static int r420_startup(struct radeon_device *rdev)
 168 
static int r420_startup(struct radeon_device *rdev)
156 
{
 169 
{
157 
	int r;
 170 
	int r;
Line 158... Line 171...
158 
 
 171 
 
- 
 
 172 
	r300_mc_program(rdev);
- 
 
 173 
	/* Resume clock */
159 
	r300_mc_program(rdev);
 174 
	r420_clock_resume(rdev);
160 
	/* Initialize GART (initialize after TTM so we can allocate
 175 
	/* Initialize GART (initialize after TTM so we can allocate
161 
	 * memory through TTM but finalize after TTM) */
 176 
	 * memory through TTM but finalize after TTM) */
162 
	if (rdev->flags & RADEON_IS_PCIE) {
 177 
	if (rdev->flags & RADEON_IS_PCIE) {
163 
		r = rv370_pcie_gart_enable(rdev);
 178 
		r = rv370_pcie_gart_enable(rdev);
Line 172... Line 187...
172 
	r420_pipes_init(rdev);
 187 
	r420_pipes_init(rdev);
173 
	/* Enable IRQ */
 188 
	/* Enable IRQ */
174 
//	rdev->irq.sw_int = true;
 189 
//	rdev->irq.sw_int = true;
175 
//	r100_irq_set(rdev);
 190 
//	r100_irq_set(rdev);
176 
	/* 1M ring buffer */
 191 
	/* 1M ring buffer */
177 
	r = r100_cp_init(rdev, 1024 * 1024);
 192 
//	r = r100_cp_init(rdev, 1024 * 1024);
178 
	if (r) {
 193 
//	if (r) {
179 
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 194 
//		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
180 
		return r;
 195 
//		return r;
181 
	}
 196 
//	}
182 
//	r = r100_wb_init(rdev);
 197 
//	r = r100_wb_init(rdev);
183 
//	if (r) {
 198 
//	if (r) {
184 
//		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 199 
//		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
185 
//	}
 200 
//	}
186 
//	r = r100_ib_init(rdev);
 201 
//	r = r100_ib_init(rdev);
Line 216... Line 231...
216 
	r420_clock_resume(rdev);
 231 
	r420_clock_resume(rdev);
Line 217... Line 232...
217 
 
 232 
 
218 
	return r420_startup(rdev);
 233 
	return r420_startup(rdev);
Line 219... Line -...
219 
}
 - 
 
220 
 
 - 
 
221 
int r420_suspend(struct radeon_device *rdev)
 - 
 
222 
{
 - 
 
223 
	r100_cp_disable(rdev);
 - 
 
224 
//	r100_wb_disable(rdev);
 - 
 
225 
//	r100_irq_disable(rdev);
 - 
 
226 
	if (rdev->flags & RADEON_IS_PCIE)
 - 
 
227 
		rv370_pcie_gart_disable(rdev);
 - 
 
228 
	if (rdev->flags & RADEON_IS_PCI)
 - 
 
229 
		r100_pci_gart_disable(rdev);
 - 
 
Line 230... Line -...
230 
	return 0;
 - 
 
231 
}
 - 
 
232 
 
 - 
 
233 
void r420_fini(struct radeon_device *rdev)
 - 
 
234 
{
 - 
 
235 
	r100_cp_fini(rdev);
 - 
 
236 
//	r100_wb_fini(rdev);
 - 
 
237 
//	r100_ib_fini(rdev);
 - 
 
238 
	radeon_gem_fini(rdev);
 - 
 
239 
	if (rdev->flags & RADEON_IS_PCIE)
 - 
 
240 
		rv370_pcie_gart_fini(rdev);
 - 
 
241 
	if (rdev->flags & RADEON_IS_PCI)
 - 
 
242 
		r100_pci_gart_fini(rdev);
 - 
 
243 
//	radeon_agp_fini(rdev);
 - 
 
244 
//	radeon_irq_kms_fini(rdev);
 - 
 
245 
//	radeon_fence_driver_fini(rdev);
 - 
 
246 
//   radeon_object_fini(rdev);
 - 
 
247 
	if (rdev->is_atom_bios) {
 - 
 
248 
		radeon_atombios_fini(rdev);
 - 
 
249 
	} else {
 - 
 
250 
		radeon_combios_fini(rdev);
 - 
 
251 
	}
 - 
 
Line 252... Line 234...
252 
	kfree(rdev->bios);
 234 
}
253 
	rdev->bios = NULL;
 235 
 
254 
}
 236 
 
Line 255... Line -...
255 
 
 - 
 
256 
int r420_init(struct radeon_device *rdev)
 237 
 
257 
{
 238 
int r420_init(struct radeon_device *rdev)
258 
	int r;
 239 
{
259 
 
 240 
	int r;
260 
	rdev->new_init_path = true;
 241 
 
Line 333... Line 314...
333 
	rdev->accel_working = true;
 314 
	rdev->accel_working = true;
334 
	r = r420_startup(rdev);
 315 
	r = r420_startup(rdev);
335 
	if (r) {
 316 
	if (r) {
336 
		/* Somethings want wront with the accel init stop accel */
 317 
		/* Somethings want wront with the accel init stop accel */
337 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
 318 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
338 
		r420_suspend(rdev);
 319 
//       r420_suspend(rdev);
339 
//		r100_cp_fini(rdev);
 320 
//		r100_cp_fini(rdev);
340 
//		r100_wb_fini(rdev);
 321 
//		r100_wb_fini(rdev);
341 
//		r100_ib_fini(rdev);
 322 
//		r100_ib_fini(rdev);
342 
		if (rdev->flags & RADEON_IS_PCIE)
 323 
		if (rdev->flags & RADEON_IS_PCIE)
343 
			rv370_pcie_gart_fini(rdev);
 324 
			rv370_pcie_gart_fini(rdev);