WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r300.c

 #include
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "radeon_asic.h"
 #include
+#include "r100_track.h"
 #include "r300d.h"
 #include "rv350d.h"
 #include "r300_reg_safe.h"
 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
+	}
 		mb();
+}
 #define R300_PTE_UNSNOOPED (1 << 0)
 #define R300_PTE_WRITEABLE (1 << 2)
 #define R300_PTE_READABLE  (1 << 3)
 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
-int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+			      uint64_t addr, uint32_t flags)
-{
-	void __iomem *ptr = rdev->gart.ptr;
 	if (i < 0 || i > rdev->gart.num_gpu_pages) {
-		return -EINVAL;
+	void __iomem *ptr = rdev->gart.ptr;
-	}
+	addr = (lower_32_bits(addr) >> 8) |
+		((upper_32_bits(addr) & 0xff) << 24);
+	if (flags & RADEON_GART_PAGE_READ)
+		addr |= R300_PTE_READABLE;
+	if (flags & RADEON_GART_PAGE_WRITE)
-	addr = (lower_32_bits(addr) >> 8) |
+		addr |= R300_PTE_WRITEABLE;
-	       ((upper_32_bits(addr) & 0xff) << 24) |
+	if (!(flags & RADEON_GART_PAGE_SNOOP))
-	       R300_PTE_WRITEABLE | R300_PTE_READABLE;
+		addr |= R300_PTE_UNSNOOPED;
 	/* on x86 we want this to be CPU endian, on powerpc
-	 * on powerpc without HW swappers, it'll get swapped on way
-	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
+	 * on powerpc without HW swappers, it'll get swapped on way
-	writel(addr, ((void __iomem *)ptr) + (i * 4));
+	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
-	return 0;
+	writel(addr, ((void __iomem *)ptr) + (i * 4));
+}
 		return -EINVAL;
+	}
 	r = radeon_gart_table_vram_pin(rdev);
 	if (r)
 		return r;
-	radeon_gart_restore(rdev);
 	/* discard memory request outside of configured range */
 	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 			  R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 	radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
 	radeon_ring_write(ring,
 			  R300_GEOMETRY_ROUND_NEAREST |
 			  R300_COLOR_ROUND_NEAREST);
-	radeon_ring_unlock_commit(rdev, ring);
+	radeon_ring_unlock_commit(rdev, ring, false);
+}
 static void r300_errata(struct radeon_device *rdev)
+{
 #else
 	return 0;
 #endif
+}
-#if 0
 static int r300_packet0_check(struct radeon_cs_parser *p,
 		struct radeon_cs_packet *pkt,
 		unsigned idx, unsigned reg)
+{
 			return r;
+		}
 		track->cb[i].robj = reloc->robj;
 		track->cb[i].offset = idx_value;
 		track->cb_dirty = true;
-		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 		break;
 	case R300_ZB_DEPTHOFFSET:
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 		if (r) {
 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 			return r;
+		}
 		track->zb.robj = reloc->robj;
 		track->zb.offset = idx_value;
 		track->zb_dirty = true;
-		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 		break;
 	case R300_TX_OFFSET_0:
 	case R300_TX_OFFSET_0+4:
 	case R300_TX_OFFSET_0+8:
 	case R300_TX_OFFSET_0+12:
 			return r;
+		}
 		if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
 			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
-				  ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
+				  ((idx_value & ~31) + (u32)reloc->gpu_offset);
 		} else {
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+			if (reloc->tiling_flags & RADEON_TILING_MACRO)
 			tile_flags |= R300_TXO_MACRO_TILE;
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+			if (reloc->tiling_flags & RADEON_TILING_MICRO)
 			tile_flags |= R300_TXO_MICRO_TILE;
-		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 			tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
-		tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
+			tmp = idx_value + ((u32)reloc->gpu_offset);
 		tmp |= tile_flags;
 		ib[idx] = tmp;
+		}
 				  idx, reg);
 				radeon_cs_dump_packet(p, pkt);
 			return r;
+		}
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+			if (reloc->tiling_flags & RADEON_TILING_MACRO)
 			tile_flags |= R300_COLOR_TILE_ENABLE;
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+			if (reloc->tiling_flags & RADEON_TILING_MICRO)
 			tile_flags |= R300_COLOR_MICROTILE_ENABLE;
-		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 			tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 		tmp = idx_value & ~(0x7 << 16);
 				  idx, reg);
 				radeon_cs_dump_packet(p, pkt);
 			return r;
+		}
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+			if (reloc->tiling_flags & RADEON_TILING_MACRO)
 			tile_flags |= R300_DEPTHMACROTILE_ENABLE;
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+			if (reloc->tiling_flags & RADEON_TILING_MICRO)
 			tile_flags |= R300_DEPTHMICROTILE_TILED;
-		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 			tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 		tmp = idx_value & ~(0x7 << 16);
 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 					idx, reg);
 			radeon_cs_dump_packet(p, pkt);
 			return r;
+		}
-		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 		break;
 	case 0x4e0c:
 		/* RB3D_COLOR_CHANNEL_MASK */
 		track->color_channel_mask = idx_value;
 		track->cb_dirty = true;
 			return r;
+		}
 		track->aa.robj = reloc->robj;
 		track->aa.offset = idx_value;
 		track->aa_dirty = true;
-		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 		break;
 	case R300_RB3D_AARESOLVE_PITCH:
 		track->aa.pitch = idx_value & 0x3FFE;
 		track->aa_dirty = true;
 		break;
 		if (r) {
 			DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
 			radeon_cs_dump_packet(p, pkt);
 			return r;
+		}
-		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
+		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
 		if (r) {
 			return r;
+		}
 		break;
 			return r;
+		}
 	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 	return 0;
+}
-#endif
 void r300_set_reg_safe(struct radeon_device *rdev)
+{
 	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
 		if (r)
 			return r;
+	}
 	r300_set_reg_safe(rdev);
+	/* Initialize power management */
+	radeon_pm_init(rdev);
 	rdev->accel_working = true;
 	r = r300_startup(rdev);
 	if (r) {
-		/* Somethings want wront with the accel init stop accel */
+		/* Something went wrong with the accel init, so stop accel */
 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
 		if (rdev->flags & RADEON_IS_PCIE)
 			rv370_pcie_gart_fini(rdev);
 		if (rdev->flags & RADEON_IS_PCI)

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r300.c – Rev 3764 → 5078