WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r300.c



	case RADEON_CRTC_GUI_TRIG_VLINE:
		r = r100_cs_packet_parse_vline(p);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
					idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		break;
	case RADEON_DST_PITCH_OFFSET:
	case RADEON_SRC_PITCH_OFFSET:

	case R300_RB3D_COLOROFFSET0:
	case R300_RB3D_COLOROFFSET1:
	case R300_RB3D_COLOROFFSET2:
	case R300_RB3D_COLOROFFSET3:
		i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
					idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		track->cb[i].robj = reloc->robj;
		track->cb[i].offset = idx_value;
		track->cb_dirty = true;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case R300_ZB_DEPTHOFFSET:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
					idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		track->zb.robj = reloc->robj;
		track->zb.offset = idx_value;
		track->zb_dirty = true;

	case R300_TX_OFFSET_0+48:
	case R300_TX_OFFSET_0+52:
	case R300_TX_OFFSET_0+56:
	case R300_TX_OFFSET_0+60:
		i = (reg - R300_TX_OFFSET_0) >> 2;
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
					idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}

 
		if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {

		/* RB3D_COLORPITCH0 */
		/* RB3D_COLORPITCH1 */
		/* RB3D_COLORPITCH2 */
		/* RB3D_COLORPITCH3 */
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
			r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
				radeon_cs_dump_packet(p, pkt);
			return r;
		}

 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)

		track->zb_dirty = true;
		break;
	case 0x4F24:
		/* ZB_DEPTHPITCH */
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
			r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
				radeon_cs_dump_packet(p, pkt);
			return r;
		}

 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)

		tmp = (idx_value >> 22) & 0xF;
		track->textures[i].txdepth = tmp;
		track->tex_dirty = true;
		break;
	case R300_ZB_ZPASS_ADDR:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
					idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case 0x4e0c:

		/* RB3D_BLENDCNTL */
		track->blend_read_enable = !!(idx_value & (1 << 2));
		track->cb_dirty = true;
		break;
	case R300_RB3D_AARESOLVE_OFFSET:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		track->aa.robj = reloc->robj;
		track->aa.offset = idx_value;
		track->aa_dirty = true;

		r = r100_packet3_load_vbpntr(p, pkt, idx);
		if (r)
				return r;
		break;
	case PACKET3_INDX_BUFFER:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		if (r) {

	if (track == NULL)
		return -ENOMEM;
	r100_cs_track_clear(p->rdev, track);
	p->track = track;
	do {
		r = radeon_cs_packet_parse(p, &pkt, p->idx);
		if (r) {
			return r;
		}
		p->idx += pkt.count + 2;
		switch (pkt.type) {
		case RADEON_PACKET_TYPE0:
			r = r100_cs_parse_packet0(p, &pkt,
						  p->rdev->config.r300.reg_safe_bm,
						  p->rdev->config.r300.reg_safe_bm_size,
						  &r300_packet0_check);
			break;
		case RADEON_PACKET_TYPE2:
			break;
		case RADEON_PACKET_TYPE3:
			r = r300_packet3_check(p, &pkt);
			break;
		default:
			DRM_ERROR("Unknown packet type %d !\n", pkt.type);
			return -EINVAL;

		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		return r;
	}

 
	/* Enable IRQ */
	if (!rdev->irq.installed) {
		r = radeon_irq_kms_init(rdev);
		if (r)
			return r;
	}
 
	r100_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
    r = r100_cp_init(rdev, 1024 * 1024);

	r300_mc_init(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
		return r;
 
 
 
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	if (rdev->flags & RADEON_IS_PCIE) {

Rev 3120	Rev 3764
Line 616...	Line 616...
616	case RADEON_CRTC_GUI_TRIG_VLINE:	616	case RADEON_CRTC_GUI_TRIG_VLINE:
617	r = r100_cs_packet_parse_vline(p);	617	r = r100_cs_packet_parse_vline(p);
618	if (r) {	618	if (r) {
619	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	619	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
620	idx, reg);	620	idx, reg);
621	r100_cs_dump_packet(p, pkt);	621	radeon_cs_dump_packet(p, pkt);
622	return r;	622	return r;
623	}	623	}
624	break;	624	break;
625	case RADEON_DST_PITCH_OFFSET:	625	case RADEON_DST_PITCH_OFFSET:
626	case RADEON_SRC_PITCH_OFFSET:	626	case RADEON_SRC_PITCH_OFFSET:
Line 631...	Line 631...
631	case R300_RB3D_COLOROFFSET0:	631	case R300_RB3D_COLOROFFSET0:
632	case R300_RB3D_COLOROFFSET1:	632	case R300_RB3D_COLOROFFSET1:
633	case R300_RB3D_COLOROFFSET2:	633	case R300_RB3D_COLOROFFSET2:
634	case R300_RB3D_COLOROFFSET3:	634	case R300_RB3D_COLOROFFSET3:
635	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;	635	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
636	r = r100_cs_packet_next_reloc(p, &reloc);	636	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
637	if (r) {	637	if (r) {
638	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	638	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
639	idx, reg);	639	idx, reg);
640	r100_cs_dump_packet(p, pkt);	640	radeon_cs_dump_packet(p, pkt);
641	return r;	641	return r;
642	}	642	}
643	track->cb[i].robj = reloc->robj;	643	track->cb[i].robj = reloc->robj;
644	track->cb[i].offset = idx_value;	644	track->cb[i].offset = idx_value;
645	track->cb_dirty = true;	645	track->cb_dirty = true;
646	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	646	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
647	break;	647	break;
648	case R300_ZB_DEPTHOFFSET:	648	case R300_ZB_DEPTHOFFSET:
649	r = r100_cs_packet_next_reloc(p, &reloc);	649	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
650	if (r) {	650	if (r) {
651	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	651	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
652	idx, reg);	652	idx, reg);
653	r100_cs_dump_packet(p, pkt);	653	radeon_cs_dump_packet(p, pkt);
654	return r;	654	return r;
655	}	655	}
656	track->zb.robj = reloc->robj;	656	track->zb.robj = reloc->robj;
657	track->zb.offset = idx_value;	657	track->zb.offset = idx_value;
658	track->zb_dirty = true;	658	track->zb_dirty = true;
Line 673...	Line 673...
673	case R300_TX_OFFSET_0+48:	673	case R300_TX_OFFSET_0+48:
674	case R300_TX_OFFSET_0+52:	674	case R300_TX_OFFSET_0+52:
675	case R300_TX_OFFSET_0+56:	675	case R300_TX_OFFSET_0+56:
676	case R300_TX_OFFSET_0+60:	676	case R300_TX_OFFSET_0+60:
677	i = (reg - R300_TX_OFFSET_0) >> 2;	677	i = (reg - R300_TX_OFFSET_0) >> 2;
678	r = r100_cs_packet_next_reloc(p, &reloc);	678	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
679	if (r) {	679	if (r) {
680	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	680	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
681	idx, reg);	681	idx, reg);
682	r100_cs_dump_packet(p, pkt);	682	radeon_cs_dump_packet(p, pkt);
683	return r;	683	return r;
684	}	684	}
Line 685...	Line 685...
685		685
686	if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {	686	if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
Line 746...	Line 746...
746	/* RB3D_COLORPITCH0 */	746	/* RB3D_COLORPITCH0 */
747	/* RB3D_COLORPITCH1 */	747	/* RB3D_COLORPITCH1 */
748	/* RB3D_COLORPITCH2 */	748	/* RB3D_COLORPITCH2 */
749	/* RB3D_COLORPITCH3 */	749	/* RB3D_COLORPITCH3 */
750	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {	750	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
751	r = r100_cs_packet_next_reloc(p, &reloc);	751	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
752	if (r) {	752	if (r) {
753	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	753	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
754	idx, reg);	754	idx, reg);
755	r100_cs_dump_packet(p, pkt);	755	radeon_cs_dump_packet(p, pkt);
756	return r;	756	return r;
757	}	757	}
Line 758...	Line 758...
758		758
759	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)	759	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
Line 831...	Line 831...
831	track->zb_dirty = true;	831	track->zb_dirty = true;
832	break;	832	break;
833	case 0x4F24:	833	case 0x4F24:
834	/* ZB_DEPTHPITCH */	834	/* ZB_DEPTHPITCH */
835	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {	835	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
836	r = r100_cs_packet_next_reloc(p, &reloc);	836	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
837	if (r) {	837	if (r) {
838	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	838	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
839	idx, reg);	839	idx, reg);
840	r100_cs_dump_packet(p, pkt);	840	radeon_cs_dump_packet(p, pkt);
841	return r;	841	return r;
842	}	842	}
Line 843...	Line 843...
843		843
844	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)	844	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
Line 1046...	Line 1046...
1046	tmp = (idx_value >> 22) & 0xF;	1046	tmp = (idx_value >> 22) & 0xF;
1047	track->textures[i].txdepth = tmp;	1047	track->textures[i].txdepth = tmp;
1048	track->tex_dirty = true;	1048	track->tex_dirty = true;
1049	break;	1049	break;
1050	case R300_ZB_ZPASS_ADDR:	1050	case R300_ZB_ZPASS_ADDR:
1051	r = r100_cs_packet_next_reloc(p, &reloc);	1051	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1052	if (r) {	1052	if (r) {
1053	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	1053	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1054	idx, reg);	1054	idx, reg);
1055	r100_cs_dump_packet(p, pkt);	1055	radeon_cs_dump_packet(p, pkt);
1056	return r;	1056	return r;
1057	}	1057	}
1058	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	1058	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1059	break;	1059	break;
1060	case 0x4e0c:	1060	case 0x4e0c:
Line 1088...	Line 1088...
1088	/* RB3D_BLENDCNTL */	1088	/* RB3D_BLENDCNTL */
1089	track->blend_read_enable = !!(idx_value & (1 << 2));	1089	track->blend_read_enable = !!(idx_value & (1 << 2));
1090	track->cb_dirty = true;	1090	track->cb_dirty = true;
1091	break;	1091	break;
1092	case R300_RB3D_AARESOLVE_OFFSET:	1092	case R300_RB3D_AARESOLVE_OFFSET:
1093	r = r100_cs_packet_next_reloc(p, &reloc);	1093	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1094	if (r) {	1094	if (r) {
1095	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	1095	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1096	idx, reg);	1096	idx, reg);
1097	r100_cs_dump_packet(p, pkt);	1097	radeon_cs_dump_packet(p, pkt);
1098	return r;	1098	return r;
1099	}	1099	}
1100	track->aa.robj = reloc->robj;	1100	track->aa.robj = reloc->robj;
1101	track->aa.offset = idx_value;	1101	track->aa.offset = idx_value;
1102	track->aa_dirty = true;	1102	track->aa_dirty = true;
Line 1157...	Line 1157...
1157	r = r100_packet3_load_vbpntr(p, pkt, idx);	1157	r = r100_packet3_load_vbpntr(p, pkt, idx);
1158	if (r)	1158	if (r)
1159	return r;	1159	return r;
1160	break;	1160	break;
1161	case PACKET3_INDX_BUFFER:	1161	case PACKET3_INDX_BUFFER:
1162	r = r100_cs_packet_next_reloc(p, &reloc);	1162	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1163	if (r) {	1163	if (r) {
1164	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);	1164	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1165	r100_cs_dump_packet(p, pkt);	1165	radeon_cs_dump_packet(p, pkt);
1166	return r;	1166	return r;
1167	}	1167	}
1168	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);	1168	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1169	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);	1169	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1170	if (r) {	1170	if (r) {
Line 1258...	Line 1258...
1258	if (track == NULL)	1258	if (track == NULL)
1259	return -ENOMEM;	1259	return -ENOMEM;
1260	r100_cs_track_clear(p->rdev, track);	1260	r100_cs_track_clear(p->rdev, track);
1261	p->track = track;	1261	p->track = track;
1262	do {	1262	do {
1263	r = r100_cs_packet_parse(p, &pkt, p->idx);	1263	r = radeon_cs_packet_parse(p, &pkt, p->idx);
1264	if (r) {	1264	if (r) {
1265	return r;	1265	return r;
1266	}	1266	}
1267	p->idx += pkt.count + 2;	1267	p->idx += pkt.count + 2;
1268	switch (pkt.type) {	1268	switch (pkt.type) {
1269	case PACKET_TYPE0:	1269	case RADEON_PACKET_TYPE0:
1270	r = r100_cs_parse_packet0(p, &pkt,	1270	r = r100_cs_parse_packet0(p, &pkt,
1271	p->rdev->config.r300.reg_safe_bm,	1271	p->rdev->config.r300.reg_safe_bm,
1272	p->rdev->config.r300.reg_safe_bm_size,	1272	p->rdev->config.r300.reg_safe_bm_size,
1273	&r300_packet0_check);	1273	&r300_packet0_check);
1274	break;	1274	break;
1275	case PACKET_TYPE2:	1275	case RADEON_PACKET_TYPE2:
1276	break;	1276	break;
1277	case PACKET_TYPE3:	1277	case RADEON_PACKET_TYPE3:
1278	r = r300_packet3_check(p, &pkt);	1278	r = r300_packet3_check(p, &pkt);
1279	break;	1279	break;
1280	default:	1280	default:
1281	DRM_ERROR("Unknown packet type %d !\n", pkt.type);	1281	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1282	return -EINVAL;	1282	return -EINVAL;
Line 1385...	Line 1385...
1385	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);	1385	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1386	return r;	1386	return r;
1387	}	1387	}
Line 1388...	Line 1388...
1388		1388
-		1389	/* Enable IRQ */
-		1390	if (!rdev->irq.installed) {
-		1391	r = radeon_irq_kms_init(rdev);
-		1392	if (r)
-		1393	return r;
-		1394	}
1389	/* Enable IRQ */	1395
1390	r100_irq_set(rdev);	1396	r100_irq_set(rdev);
1391	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);	1397	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1392	/* 1M ring buffer */	1398	/* 1M ring buffer */
1393	r = r100_cp_init(rdev, 1024 * 1024);	1399	r = r100_cp_init(rdev, 1024 * 1024);
Line 1460...	Line 1466...
1460	r300_mc_init(rdev);	1466	r300_mc_init(rdev);
1461	/* Fence driver */	1467	/* Fence driver */
1462	r = radeon_fence_driver_init(rdev);	1468	r = radeon_fence_driver_init(rdev);
1463	if (r)	1469	if (r)
1464	return r;	1470	return r;
1465	r = radeon_irq_kms_init(rdev);	-
1466	if (r)	-
1467	return r;	-
1468	/* Memory manager */	1471	/* Memory manager */
1469	r = radeon_bo_init(rdev);	1472	r = radeon_bo_init(rdev);
1470	if (r)	1473	if (r)
1471	return r;	1474	return r;
1472	if (rdev->flags & RADEON_IS_PCIE) {	1475	if (rdev->flags & RADEON_IS_PCIE) {

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r300.c – Rev 3120 → 3764