Rev 1430 | Rev 2005 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1430 | Rev 1963 | ||
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Line 24... | Line 24... | ||
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
- | 29 | #include |
|
29 | #include "drmP.h" |
30 | #include |
30 | #include "drm.h" |
31 | #include |
- | 32 | #include |
|
31 | #include "radeon_reg.h" |
33 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
34 | #include "radeon.h" |
- | 35 | #include "radeon_asic.h" |
|
33 | #include "radeon_drm.h" |
36 | #include "radeon_drm.h" |
Line 34... | Line 37... | ||
34 | 37 | ||
35 | #include "r300d.h" |
38 | #include "r300d.h" |
36 | #include "rv350d.h" |
39 | #include "rv350d.h" |
Line 64... | Line 67... | ||
64 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
67 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
65 | } |
68 | } |
66 | mb(); |
69 | mb(); |
67 | } |
70 | } |
Line -... | Line 71... | ||
- | 71 | ||
- | 72 | #define R300_PTE_WRITEABLE (1 << 2) |
|
- | 73 | #define R300_PTE_READABLE (1 << 3) |
|
68 | 74 | ||
69 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
75 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
70 | { |
76 | { |
Line 71... | Line 77... | ||
71 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
77 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
72 | 78 | ||
73 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
79 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
74 | return -EINVAL; |
80 | return -EINVAL; |
75 | } |
81 | } |
76 | addr = (lower_32_bits(addr) >> 8) | |
82 | addr = (lower_32_bits(addr) >> 8) | |
77 | ((upper_32_bits(addr) & 0xff) << 24) | |
83 | ((upper_32_bits(addr) & 0xff) << 24) | |
78 | 0xc; |
84 | R300_PTE_WRITEABLE | R300_PTE_READABLE; |
79 | /* on x86 we want this to be CPU endian, on powerpc |
85 | /* on x86 we want this to be CPU endian, on powerpc |
80 | * on powerpc without HW swappers, it'll get swapped on way |
86 | * on powerpc without HW swappers, it'll get swapped on way |
81 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
87 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
Line 86... | Line 92... | ||
86 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
92 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
87 | { |
93 | { |
88 | int r; |
94 | int r; |
Line 89... | Line 95... | ||
89 | 95 | ||
90 | if (rdev->gart.table.vram.robj) { |
96 | if (rdev->gart.table.vram.robj) { |
91 | WARN(1, "RV370 PCIE GART already initialized.\n"); |
97 | WARN(1, "RV370 PCIE GART already initialized\n"); |
92 | return 0; |
98 | return 0; |
93 | } |
99 | } |
94 | /* Initialize common gart structure */ |
100 | /* Initialize common gart structure */ |
95 | r = radeon_gart_init(rdev); |
101 | r = radeon_gart_init(rdev); |
Line 130... | Line 136... | ||
130 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
136 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
131 | /* FIXME: setup default page */ |
137 | /* FIXME: setup default page */ |
132 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
138 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
133 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
139 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
134 | /* Clear error */ |
140 | /* Clear error */ |
135 | WREG32_PCIE(0x18, 0); |
141 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
136 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
142 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
137 | tmp |= RADEON_PCIE_TX_GART_EN; |
143 | tmp |= RADEON_PCIE_TX_GART_EN; |
138 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
139 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
145 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
140 | rv370_pcie_gart_tlb_flush(rdev); |
146 | rv370_pcie_gart_tlb_flush(rdev); |
Line 147... | Line 153... | ||
147 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
153 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
148 | { |
154 | { |
149 | u32 tmp; |
155 | u32 tmp; |
150 | int r; |
156 | int r; |
Line -... | Line 157... | ||
- | 157 | ||
- | 158 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); |
|
- | 159 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); |
|
- | 160 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
|
151 | 161 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
|
152 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
162 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
153 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
163 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
154 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
164 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
155 | if (rdev->gart.table.vram.robj) { |
165 | if (rdev->gart.table.vram.robj) { |
Line 162... | Line 172... | ||
162 | } |
172 | } |
163 | } |
173 | } |
Line 164... | Line 174... | ||
164 | 174 | ||
165 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
175 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
- | 176 | { |
|
166 | { |
177 | radeon_gart_fini(rdev); |
167 | rv370_pcie_gart_disable(rdev); |
178 | rv370_pcie_gart_disable(rdev); |
168 | radeon_gart_table_vram_free(rdev); |
- | |
169 | radeon_gart_fini(rdev); |
179 | radeon_gart_table_vram_free(rdev); |
Line 170... | Line 180... | ||
170 | } |
180 | } |
171 | 181 | ||
172 | void r300_fence_ring_emit(struct radeon_device *rdev, |
182 | void r300_fence_ring_emit(struct radeon_device *rdev, |
Line 319... | Line 329... | ||
319 | 329 | ||
320 | void r300_gpu_init(struct radeon_device *rdev) |
330 | void r300_gpu_init(struct radeon_device *rdev) |
321 | { |
331 | { |
Line 322... | Line -... | ||
322 | uint32_t gb_tile_config, tmp; |
- | |
323 | 332 | uint32_t gb_tile_config, tmp; |
|
324 | r100_hdp_reset(rdev); |
333 | |
325 | /* FIXME: rv380 one pipes ? */ |
334 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || |
326 | if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { |
335 | (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { |
327 | /* r300,r350 */ |
336 | /* r300,r350 */ |
328 | rdev->num_gb_pipes = 2; |
337 | rdev->num_gb_pipes = 2; |
329 | } else { |
338 | } else { |
330 | /* rv350,rv370,rv380 */ |
339 | /* rv350,rv370,rv380,r300 AD, r350 AH */ |
331 | rdev->num_gb_pipes = 1; |
340 | rdev->num_gb_pipes = 1; |
332 | } |
341 | } |
333 | rdev->num_z_pipes = 1; |
342 | rdev->num_z_pipes = 1; |
Line 371... | Line 380... | ||
371 | } |
380 | } |
372 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
381 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
373 | rdev->num_gb_pipes, rdev->num_z_pipes); |
382 | rdev->num_gb_pipes, rdev->num_z_pipes); |
374 | } |
383 | } |
Line 375... | Line 384... | ||
375 | 384 | ||
376 | int r300_ga_reset(struct radeon_device *rdev) |
385 | bool r300_gpu_is_lockup(struct radeon_device *rdev) |
377 | { |
386 | { |
378 | uint32_t tmp; |
- | |
379 | bool reinit_cp; |
387 | u32 rbbm_status; |
Line 380... | Line -... | ||
380 | int i; |
- | |
381 | - | ||
382 | reinit_cp = rdev->cp.ready; |
- | |
383 | rdev->cp.ready = false; |
- | |
384 | for (i = 0; i < rdev->usec_timeout; i++) { |
- | |
385 | WREG32(RADEON_CP_CSQ_MODE, 0); |
- | |
386 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
- | |
387 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
- | |
388 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
- | |
389 | udelay(200); |
- | |
390 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
- | |
391 | /* Wait to prevent race in RBBM_STATUS */ |
388 | int r; |
392 | mdelay(1); |
389 | |
393 | tmp = RREG32(RADEON_RBBM_STATUS); |
390 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
394 | if (tmp & ((1 << 20) | (1 << 26))) { |
- | |
395 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); |
- | |
396 | /* GA still busy soft reset it */ |
- | |
397 | WREG32(0x429C, 0x200); |
- | |
398 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
- | |
399 | WREG32(R300_RE_SCISSORS_TL, 0); |
- | |
400 | WREG32(R300_RE_SCISSORS_BR, 0); |
- | |
401 | WREG32(0x24AC, 0); |
- | |
402 | } |
- | |
403 | /* Wait to prevent race in RBBM_STATUS */ |
- | |
404 | mdelay(1); |
- | |
405 | tmp = RREG32(RADEON_RBBM_STATUS); |
391 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { |
406 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
392 | r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); |
407 | break; |
- | |
408 | } |
393 | return false; |
409 | } |
394 | } |
410 | for (i = 0; i < rdev->usec_timeout; i++) { |
- | |
411 | tmp = RREG32(RADEON_RBBM_STATUS); |
- | |
412 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
395 | /* force CP activities */ |
413 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
396 | r = radeon_ring_lock(rdev, 2); |
414 | tmp); |
397 | if (!r) { |
415 | if (reinit_cp) { |
- | |
416 | return r100_cp_init(rdev, rdev->cp.ring_size); |
398 | /* PACKET2 NOP */ |
417 | } |
- | |
418 | return 0; |
399 | radeon_ring_write(rdev, 0x80000000); |
419 | } |
400 | radeon_ring_write(rdev, 0x80000000); |
420 | DRM_UDELAY(1); |
401 | radeon_ring_unlock_commit(rdev); |
421 | } |
402 | } |
422 | tmp = RREG32(RADEON_RBBM_STATUS); |
- | |
423 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
403 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
Line 424... | Line 404... | ||
424 | return -1; |
404 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); |
425 | } |
405 | } |
- | 406 | ||
426 | 407 | int r300_asic_reset(struct radeon_device *rdev) |
|
- | 408 | { |
|
Line 427... | Line -... | ||
427 | int r300_gpu_reset(struct radeon_device *rdev) |
- | |
428 | { |
409 | struct r100_mc_save save; |
429 | uint32_t status; |
- | |
430 | - | ||
431 | /* reset order likely matter */ |
- | |
432 | status = RREG32(RADEON_RBBM_STATUS); |
- | |
433 | /* reset HDP */ |
- | |
434 | r100_hdp_reset(rdev); |
- | |
435 | /* reset rb2d */ |
- | |
436 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
410 | u32 status, tmp; |
437 | r100_rb2d_reset(rdev); |
- | |
438 | } |
- | |
439 | /* reset GA */ |
411 | int ret = 0; |
440 | if (status & ((1 << 20) | (1 << 26))) { |
- | |
441 | r300_ga_reset(rdev); |
- | |
442 | } |
- | |
443 | /* reset CP */ |
412 | |
- | 413 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 414 | if (!G_000E40_GUI_ACTIVE(status)) { |
|
- | 415 | return 0; |
|
- | 416 | } |
|
- | 417 | r100_mc_stop(rdev, &save); |
|
- | 418 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 419 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
|
- | 420 | /* stop CP */ |
|
- | 421 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
|
- | 422 | tmp = RREG32(RADEON_CP_RB_CNTL); |
|
- | 423 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
|
- | 424 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
|
- | 425 | WREG32(RADEON_CP_RB_WPTR, 0); |
|
- | 426 | WREG32(RADEON_CP_RB_CNTL, tmp); |
|
- | 427 | /* save PCI state */ |
|
- | 428 | // pci_save_state(rdev->pdev); |
|
- | 429 | /* disable bus mastering */ |
|
- | 430 | r100_bm_disable(rdev); |
|
- | 431 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
|
- | 432 | S_0000F0_SOFT_RESET_GA(1)); |
|
- | 433 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
|
- | 434 | mdelay(500); |
|
- | 435 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
|
- | 436 | mdelay(1); |
|
- | 437 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 438 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
|
- | 439 | /* resetting the CP seems to be problematic sometimes it end up |
|
- | 440 | * hard locking the computer, but it's necessary for successful |
|
- | 441 | * reset more test & playing is needed on R3XX/R4XX to find a |
|
- | 442 | * reliable (if any solution) |
|
- | 443 | */ |
|
- | 444 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
|
- | 445 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
|
- | 446 | mdelay(500); |
|
- | 447 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
|
- | 448 | mdelay(1); |
|
- | 449 | status = RREG32(R_000E40_RBBM_STATUS); |
|
444 | status = RREG32(RADEON_RBBM_STATUS); |
450 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
445 | if (status & (1 << 16)) { |
451 | /* restore PCI & busmastering */ |
446 | r100_cp_reset(rdev); |
452 | // pci_restore_state(rdev->pdev); |
447 | } |
453 | r100_enable_bm(rdev); |
448 | /* Check if GPU is idle */ |
454 | /* Check if GPU is idle */ |
449 | status = RREG32(RADEON_RBBM_STATUS); |
455 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
450 | if (status & RADEON_RBBM_ACTIVE) { |
456 | dev_err(rdev->dev, "failed to reset GPU\n"); |
- | 457 | rdev->gpu_lockup = true; |
|
451 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
458 | ret = -1; |
452 | return -1; |
459 | } else |
Line 453... | Line -... | ||
453 | } |
- | |
454 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
460 | dev_info(rdev->dev, "GPU reset succeed\n"); |
455 | return 0; |
461 | r100_mc_resume(rdev, &save); |
456 | } |
462 | return ret; |
457 | 463 | } |
|
458 | 464 | ||
Line 477... | Line 483... | ||
477 | r100_vram_init_sizes(rdev); |
483 | r100_vram_init_sizes(rdev); |
478 | base = rdev->mc.aper_base; |
484 | base = rdev->mc.aper_base; |
479 | if (rdev->flags & RADEON_IS_IGP) |
485 | if (rdev->flags & RADEON_IS_IGP) |
480 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
486 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
481 | radeon_vram_location(rdev, &rdev->mc, base); |
487 | radeon_vram_location(rdev, &rdev->mc, base); |
- | 488 | rdev->mc.gtt_base_align = 0; |
|
482 | if (!(rdev->flags & RADEON_IS_AGP)) |
489 | if (!(rdev->flags & RADEON_IS_AGP)) |
483 | radeon_gtt_location(rdev, &rdev->mc); |
490 | radeon_gtt_location(rdev, &rdev->mc); |
- | 491 | radeon_update_bandwidth_info(rdev); |
|
484 | } |
492 | } |
Line 485... | Line 493... | ||
485 | 493 | ||
486 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
494 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
487 | { |
495 | { |
Line 552... | Line 560... | ||
552 | if (!(rdev->flags & RADEON_IS_PCIE)) |
560 | if (!(rdev->flags & RADEON_IS_PCIE)) |
553 | return 0; |
561 | return 0; |
Line 554... | Line 562... | ||
554 | 562 | ||
Line 555... | Line -... | ||
555 | /* FIXME wait for idle */ |
- | |
556 | 563 | /* FIXME wait for idle */ |
|
557 | if (rdev->family < CHIP_R600) |
- | |
558 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
- | |
Line 559... | Line 564... | ||
559 | else |
564 | |
560 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
565 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
561 | 566 | ||
562 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { |
567 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { |
Line 663... | Line 668... | ||
663 | r100_cs_dump_packet(p, pkt); |
668 | r100_cs_dump_packet(p, pkt); |
664 | return r; |
669 | return r; |
665 | } |
670 | } |
666 | track->cb[i].robj = reloc->robj; |
671 | track->cb[i].robj = reloc->robj; |
667 | track->cb[i].offset = idx_value; |
672 | track->cb[i].offset = idx_value; |
- | 673 | track->cb_dirty = true; |
|
668 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
674 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
669 | break; |
675 | break; |
670 | case R300_ZB_DEPTHOFFSET: |
676 | case R300_ZB_DEPTHOFFSET: |
671 | r = r100_cs_packet_next_reloc(p, &reloc); |
677 | r = r100_cs_packet_next_reloc(p, &reloc); |
672 | if (r) { |
678 | if (r) { |
Line 675... | Line 681... | ||
675 | r100_cs_dump_packet(p, pkt); |
681 | r100_cs_dump_packet(p, pkt); |
676 | return r; |
682 | return r; |
677 | } |
683 | } |
678 | track->zb.robj = reloc->robj; |
684 | track->zb.robj = reloc->robj; |
679 | track->zb.offset = idx_value; |
685 | track->zb.offset = idx_value; |
- | 686 | track->zb_dirty = true; |
|
680 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
687 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
681 | break; |
688 | break; |
682 | case R300_TX_OFFSET_0: |
689 | case R300_TX_OFFSET_0: |
683 | case R300_TX_OFFSET_0+4: |
690 | case R300_TX_OFFSET_0+4: |
684 | case R300_TX_OFFSET_0+8: |
691 | case R300_TX_OFFSET_0+8: |
Line 713... | Line 720... | ||
713 | 720 | ||
714 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); |
721 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); |
715 | tmp |= tile_flags; |
722 | tmp |= tile_flags; |
716 | ib[idx] = tmp; |
723 | ib[idx] = tmp; |
- | 724 | track->textures[i].robj = reloc->robj; |
|
717 | track->textures[i].robj = reloc->robj; |
725 | track->tex_dirty = true; |
718 | break; |
726 | break; |
719 | /* Tracked registers */ |
727 | /* Tracked registers */ |
720 | case 0x2084: |
728 | case 0x2084: |
721 | /* VAP_VF_CNTL */ |
729 | /* VAP_VF_CNTL */ |
Line 727... | Line 735... | ||
727 | break; |
735 | break; |
728 | case 0x2134: |
736 | case 0x2134: |
729 | /* VAP_VF_MAX_VTX_INDX */ |
737 | /* VAP_VF_MAX_VTX_INDX */ |
730 | track->max_indx = idx_value & 0x00FFFFFFUL; |
738 | track->max_indx = idx_value & 0x00FFFFFFUL; |
731 | break; |
739 | break; |
- | 740 | case 0x2088: |
|
- | 741 | /* VAP_ALT_NUM_VERTICES - only valid on r500 */ |
|
- | 742 | if (p->rdev->family < CHIP_RV515) |
|
- | 743 | goto fail; |
|
- | 744 | track->vap_alt_nverts = idx_value & 0xFFFFFF; |
|
- | 745 | break; |
|
732 | case 0x43E4: |
746 | case 0x43E4: |
733 | /* SC_SCISSOR1 */ |
747 | /* SC_SCISSOR1 */ |
734 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
748 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
735 | if (p->rdev->family < CHIP_RV515) { |
749 | if (p->rdev->family < CHIP_RV515) { |
736 | track->maxy -= 1440; |
750 | track->maxy -= 1440; |
737 | } |
751 | } |
- | 752 | track->cb_dirty = true; |
|
- | 753 | track->zb_dirty = true; |
|
738 | break; |
754 | break; |
739 | case 0x4E00: |
755 | case 0x4E00: |
740 | /* RB3D_CCTL */ |
756 | /* RB3D_CCTL */ |
- | 757 | if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ |
|
- | 758 | p->rdev->cmask_filp != p->filp) { |
|
- | 759 | DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); |
|
- | 760 | return -EINVAL; |
|
- | 761 | } |
|
741 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
762 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
- | 763 | track->cb_dirty = true; |
|
742 | break; |
764 | break; |
743 | case 0x4E38: |
765 | case 0x4E38: |
744 | case 0x4E3C: |
766 | case 0x4E3C: |
745 | case 0x4E40: |
767 | case 0x4E40: |
746 | case 0x4E44: |
768 | case 0x4E44: |
Line 764... | Line 786... | ||
764 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
786 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
Line 765... | Line 787... | ||
765 | 787 | ||
766 | tmp = idx_value & ~(0x7 << 16); |
788 | tmp = idx_value & ~(0x7 << 16); |
767 | tmp |= tile_flags; |
789 | tmp |= tile_flags; |
768 | ib[idx] = tmp; |
- | |
769 | 790 | ib[idx] = tmp; |
|
770 | i = (reg - 0x4E38) >> 2; |
791 | i = (reg - 0x4E38) >> 2; |
771 | track->cb[i].pitch = idx_value & 0x3FFE; |
792 | track->cb[i].pitch = idx_value & 0x3FFE; |
772 | switch (((idx_value >> 21) & 0xF)) { |
793 | switch (((idx_value >> 21) & 0xF)) { |
773 | case 9: |
794 | case 9: |
Line 779... | Line 800... | ||
779 | case 4: |
800 | case 4: |
780 | case 13: |
801 | case 13: |
781 | case 15: |
802 | case 15: |
782 | track->cb[i].cpp = 2; |
803 | track->cb[i].cpp = 2; |
783 | break; |
804 | break; |
- | 805 | case 5: |
|
- | 806 | if (p->rdev->family < CHIP_RV515) { |
|
- | 807 | DRM_ERROR("Invalid color buffer format (%d)!\n", |
|
- | 808 | ((idx_value >> 21) & 0xF)); |
|
- | 809 | return -EINVAL; |
|
- | 810 | } |
|
- | 811 | /* Pass through. */ |
|
784 | case 6: |
812 | case 6: |
785 | track->cb[i].cpp = 4; |
813 | track->cb[i].cpp = 4; |
786 | break; |
814 | break; |
787 | case 10: |
815 | case 10: |
788 | track->cb[i].cpp = 8; |
816 | track->cb[i].cpp = 8; |
Line 793... | Line 821... | ||
793 | default: |
821 | default: |
794 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
822 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
795 | ((idx_value >> 21) & 0xF)); |
823 | ((idx_value >> 21) & 0xF)); |
796 | return -EINVAL; |
824 | return -EINVAL; |
797 | } |
825 | } |
- | 826 | track->cb_dirty = true; |
|
798 | break; |
827 | break; |
799 | case 0x4F00: |
828 | case 0x4F00: |
800 | /* ZB_CNTL */ |
829 | /* ZB_CNTL */ |
801 | if (idx_value & 2) { |
830 | if (idx_value & 2) { |
802 | track->z_enabled = true; |
831 | track->z_enabled = true; |
803 | } else { |
832 | } else { |
804 | track->z_enabled = false; |
833 | track->z_enabled = false; |
805 | } |
834 | } |
- | 835 | track->zb_dirty = true; |
|
806 | break; |
836 | break; |
807 | case 0x4F10: |
837 | case 0x4F10: |
808 | /* ZB_FORMAT */ |
838 | /* ZB_FORMAT */ |
809 | switch ((idx_value & 0xF)) { |
839 | switch ((idx_value & 0xF)) { |
810 | case 0: |
840 | case 0: |
Line 817... | Line 847... | ||
817 | default: |
847 | default: |
818 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
848 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
819 | (idx_value & 0xF)); |
849 | (idx_value & 0xF)); |
820 | return -EINVAL; |
850 | return -EINVAL; |
821 | } |
851 | } |
- | 852 | track->zb_dirty = true; |
|
822 | break; |
853 | break; |
823 | case 0x4F24: |
854 | case 0x4F24: |
824 | /* ZB_DEPTHPITCH */ |
855 | /* ZB_DEPTHPITCH */ |
825 | r = r100_cs_packet_next_reloc(p, &reloc); |
856 | r = r100_cs_packet_next_reloc(p, &reloc); |
826 | if (r) { |
857 | if (r) { |
Line 840... | Line 871... | ||
840 | tmp = idx_value & ~(0x7 << 16); |
871 | tmp = idx_value & ~(0x7 << 16); |
841 | tmp |= tile_flags; |
872 | tmp |= tile_flags; |
842 | ib[idx] = tmp; |
873 | ib[idx] = tmp; |
Line 843... | Line 874... | ||
843 | 874 | ||
- | 875 | track->zb.pitch = idx_value & 0x3FFC; |
|
844 | track->zb.pitch = idx_value & 0x3FFC; |
876 | track->zb_dirty = true; |
845 | break; |
877 | break; |
- | 878 | case 0x4104: |
|
846 | case 0x4104: |
879 | /* TX_ENABLE */ |
847 | for (i = 0; i < 16; i++) { |
880 | for (i = 0; i < 16; i++) { |
Line 848... | Line 881... | ||
848 | bool enabled; |
881 | bool enabled; |
849 | 882 | ||
850 | enabled = !!(idx_value & (1 << i)); |
883 | enabled = !!(idx_value & (1 << i)); |
- | 884 | track->textures[i].enabled = enabled; |
|
851 | track->textures[i].enabled = enabled; |
885 | } |
852 | } |
886 | track->tex_dirty = true; |
853 | break; |
887 | break; |
854 | case 0x44C0: |
888 | case 0x44C0: |
855 | case 0x44C4: |
889 | case 0x44C4: |
Line 874... | Line 908... | ||
874 | switch ((idx_value & 0x1F)) { |
908 | switch ((idx_value & 0x1F)) { |
875 | case R300_TX_FORMAT_X8: |
909 | case R300_TX_FORMAT_X8: |
876 | case R300_TX_FORMAT_Y4X4: |
910 | case R300_TX_FORMAT_Y4X4: |
877 | case R300_TX_FORMAT_Z3Y3X2: |
911 | case R300_TX_FORMAT_Z3Y3X2: |
878 | track->textures[i].cpp = 1; |
912 | track->textures[i].cpp = 1; |
- | 913 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
|
879 | break; |
914 | break; |
880 | case R300_TX_FORMAT_X16: |
915 | case R300_TX_FORMAT_X16: |
- | 916 | case R300_TX_FORMAT_FL_I16: |
|
881 | case R300_TX_FORMAT_Y8X8: |
917 | case R300_TX_FORMAT_Y8X8: |
882 | case R300_TX_FORMAT_Z5Y6X5: |
918 | case R300_TX_FORMAT_Z5Y6X5: |
883 | case R300_TX_FORMAT_Z6Y5X5: |
919 | case R300_TX_FORMAT_Z6Y5X5: |
884 | case R300_TX_FORMAT_W4Z4Y4X4: |
920 | case R300_TX_FORMAT_W4Z4Y4X4: |
885 | case R300_TX_FORMAT_W1Z5Y5X5: |
921 | case R300_TX_FORMAT_W1Z5Y5X5: |
886 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
922 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
887 | case R300_TX_FORMAT_B8G8_B8G8: |
923 | case R300_TX_FORMAT_B8G8_B8G8: |
888 | case R300_TX_FORMAT_G8R8_G8B8: |
924 | case R300_TX_FORMAT_G8R8_G8B8: |
889 | track->textures[i].cpp = 2; |
925 | track->textures[i].cpp = 2; |
- | 926 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
|
890 | break; |
927 | break; |
891 | case R300_TX_FORMAT_Y16X16: |
928 | case R300_TX_FORMAT_Y16X16: |
- | 929 | case R300_TX_FORMAT_FL_I16A16: |
|
892 | case R300_TX_FORMAT_Z11Y11X10: |
930 | case R300_TX_FORMAT_Z11Y11X10: |
893 | case R300_TX_FORMAT_Z10Y11X11: |
931 | case R300_TX_FORMAT_Z10Y11X11: |
894 | case R300_TX_FORMAT_W8Z8Y8X8: |
932 | case R300_TX_FORMAT_W8Z8Y8X8: |
895 | case R300_TX_FORMAT_W2Z10Y10X10: |
933 | case R300_TX_FORMAT_W2Z10Y10X10: |
896 | case 0x17: |
934 | case 0x17: |
897 | case R300_TX_FORMAT_FL_I32: |
935 | case R300_TX_FORMAT_FL_I32: |
898 | case 0x1e: |
936 | case 0x1e: |
899 | track->textures[i].cpp = 4; |
937 | track->textures[i].cpp = 4; |
- | 938 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
|
900 | break; |
939 | break; |
901 | case R300_TX_FORMAT_W16Z16Y16X16: |
940 | case R300_TX_FORMAT_W16Z16Y16X16: |
902 | case R300_TX_FORMAT_FL_R16G16B16A16: |
941 | case R300_TX_FORMAT_FL_R16G16B16A16: |
903 | case R300_TX_FORMAT_FL_I32A32: |
942 | case R300_TX_FORMAT_FL_I32A32: |
904 | track->textures[i].cpp = 8; |
943 | track->textures[i].cpp = 8; |
- | 944 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
|
905 | break; |
945 | break; |
906 | case R300_TX_FORMAT_FL_R32G32B32A32: |
946 | case R300_TX_FORMAT_FL_R32G32B32A32: |
907 | track->textures[i].cpp = 16; |
947 | track->textures[i].cpp = 16; |
- | 948 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
|
908 | break; |
949 | break; |
909 | case R300_TX_FORMAT_DXT1: |
950 | case R300_TX_FORMAT_DXT1: |
910 | track->textures[i].cpp = 1; |
951 | track->textures[i].cpp = 1; |
911 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
952 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
912 | break; |
953 | break; |
Line 925... | Line 966... | ||
925 | break; |
966 | break; |
926 | default: |
967 | default: |
927 | DRM_ERROR("Invalid texture format %u\n", |
968 | DRM_ERROR("Invalid texture format %u\n", |
928 | (idx_value & 0x1F)); |
969 | (idx_value & 0x1F)); |
929 | return -EINVAL; |
970 | return -EINVAL; |
930 | break; |
- | |
931 | } |
971 | } |
- | 972 | track->tex_dirty = true; |
|
932 | break; |
973 | break; |
933 | case 0x4400: |
974 | case 0x4400: |
934 | case 0x4404: |
975 | case 0x4404: |
935 | case 0x4408: |
976 | case 0x4408: |
936 | case 0x440C: |
977 | case 0x440C: |
Line 954... | Line 995... | ||
954 | } |
995 | } |
955 | tmp = (idx_value >> 3) & 0x7; |
996 | tmp = (idx_value >> 3) & 0x7; |
956 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
997 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
957 | track->textures[i].roundup_h = false; |
998 | track->textures[i].roundup_h = false; |
958 | } |
999 | } |
- | 1000 | track->tex_dirty = true; |
|
959 | break; |
1001 | break; |
960 | case 0x4500: |
1002 | case 0x4500: |
961 | case 0x4504: |
1003 | case 0x4504: |
962 | case 0x4508: |
1004 | case 0x4508: |
963 | case 0x450C: |
1005 | case 0x450C: |
Line 991... | Line 1033... | ||
991 | } |
1033 | } |
992 | } else if (idx_value & (1 << 14)) { |
1034 | } else if (idx_value & (1 << 14)) { |
993 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); |
1035 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); |
994 | return -EINVAL; |
1036 | return -EINVAL; |
995 | } |
1037 | } |
- | 1038 | track->tex_dirty = true; |
|
996 | break; |
1039 | break; |
997 | case 0x4480: |
1040 | case 0x4480: |
998 | case 0x4484: |
1041 | case 0x4484: |
999 | case 0x4488: |
1042 | case 0x4488: |
1000 | case 0x448C: |
1043 | case 0x448C: |
Line 1020... | Line 1063... | ||
1020 | track->textures[i].num_levels = tmp; |
1063 | track->textures[i].num_levels = tmp; |
1021 | tmp = idx_value & (1 << 31); |
1064 | tmp = idx_value & (1 << 31); |
1022 | track->textures[i].use_pitch = !!tmp; |
1065 | track->textures[i].use_pitch = !!tmp; |
1023 | tmp = (idx_value >> 22) & 0xF; |
1066 | tmp = (idx_value >> 22) & 0xF; |
1024 | track->textures[i].txdepth = tmp; |
1067 | track->textures[i].txdepth = tmp; |
- | 1068 | track->tex_dirty = true; |
|
1025 | break; |
1069 | break; |
1026 | case R300_ZB_ZPASS_ADDR: |
1070 | case R300_ZB_ZPASS_ADDR: |
1027 | r = r100_cs_packet_next_reloc(p, &reloc); |
1071 | r = r100_cs_packet_next_reloc(p, &reloc); |
1028 | if (r) { |
1072 | if (r) { |
1029 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1073 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
Line 1034... | Line 1078... | ||
1034 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1078 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1035 | break; |
1079 | break; |
1036 | case 0x4e0c: |
1080 | case 0x4e0c: |
1037 | /* RB3D_COLOR_CHANNEL_MASK */ |
1081 | /* RB3D_COLOR_CHANNEL_MASK */ |
1038 | track->color_channel_mask = idx_value; |
1082 | track->color_channel_mask = idx_value; |
- | 1083 | track->cb_dirty = true; |
|
- | 1084 | break; |
|
- | 1085 | case 0x43a4: |
|
- | 1086 | /* SC_HYPERZ_EN */ |
|
- | 1087 | /* r300c emits this register - we need to disable hyperz for it |
|
- | 1088 | * without complaining */ |
|
- | 1089 | if (p->rdev->hyperz_filp != p->filp) { |
|
- | 1090 | if (idx_value & 0x1) |
|
- | 1091 | ib[idx] = idx_value & ~1; |
|
- | 1092 | } |
|
1039 | break; |
1093 | break; |
1040 | case 0x4d1c: |
1094 | case 0x4f1c: |
1041 | /* ZB_BW_CNTL */ |
1095 | /* ZB_BW_CNTL */ |
1042 | track->fastfill = !!(idx_value & (1 << 2)); |
1096 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
- | 1097 | track->cb_dirty = true; |
|
- | 1098 | track->zb_dirty = true; |
|
- | 1099 | if (p->rdev->hyperz_filp != p->filp) { |
|
- | 1100 | if (idx_value & (R300_HIZ_ENABLE | |
|
- | 1101 | R300_RD_COMP_ENABLE | |
|
- | 1102 | R300_WR_COMP_ENABLE | |
|
- | 1103 | R300_FAST_FILL_ENABLE)) |
|
- | 1104 | goto fail; |
|
- | 1105 | } |
|
1043 | break; |
1106 | break; |
1044 | case 0x4e04: |
1107 | case 0x4e04: |
1045 | /* RB3D_BLENDCNTL */ |
1108 | /* RB3D_BLENDCNTL */ |
1046 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
1109 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
- | 1110 | track->cb_dirty = true; |
|
- | 1111 | break; |
|
- | 1112 | case R300_RB3D_AARESOLVE_OFFSET: |
|
- | 1113 | r = r100_cs_packet_next_reloc(p, &reloc); |
|
- | 1114 | if (r) { |
|
- | 1115 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
|
- | 1116 | idx, reg); |
|
- | 1117 | r100_cs_dump_packet(p, pkt); |
|
- | 1118 | return r; |
|
- | 1119 | } |
|
- | 1120 | track->aa.robj = reloc->robj; |
|
- | 1121 | track->aa.offset = idx_value; |
|
- | 1122 | track->aa_dirty = true; |
|
- | 1123 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
|
- | 1124 | break; |
|
- | 1125 | case R300_RB3D_AARESOLVE_PITCH: |
|
- | 1126 | track->aa.pitch = idx_value & 0x3FFE; |
|
- | 1127 | track->aa_dirty = true; |
|
- | 1128 | break; |
|
- | 1129 | case R300_RB3D_AARESOLVE_CTL: |
|
- | 1130 | track->aaresolve = idx_value & 0x1; |
|
- | 1131 | track->aa_dirty = true; |
|
- | 1132 | break; |
|
- | 1133 | case 0x4f30: /* ZB_MASK_OFFSET */ |
|
- | 1134 | case 0x4f34: /* ZB_ZMASK_PITCH */ |
|
- | 1135 | case 0x4f44: /* ZB_HIZ_OFFSET */ |
|
- | 1136 | case 0x4f54: /* ZB_HIZ_PITCH */ |
|
- | 1137 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) |
|
- | 1138 | goto fail; |
|
- | 1139 | break; |
|
- | 1140 | case 0x4028: |
|
- | 1141 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) |
|
- | 1142 | goto fail; |
|
- | 1143 | /* GB_Z_PEQ_CONFIG */ |
|
- | 1144 | if (p->rdev->family >= CHIP_RV350) |
|
- | 1145 | break; |
|
- | 1146 | goto fail; |
|
1047 | break; |
1147 | break; |
1048 | case 0x4be8: |
1148 | case 0x4be8: |
1049 | /* valid register only on RV530 */ |
1149 | /* valid register only on RV530 */ |
1050 | if (p->rdev->family == CHIP_RV530) |
1150 | if (p->rdev->family == CHIP_RV530) |
1051 | break; |
1151 | break; |
1052 | /* fallthrough do not move */ |
1152 | /* fallthrough do not move */ |
1053 | default: |
1153 | default: |
1054 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
- | |
1055 | reg, idx); |
- | |
1056 | return -EINVAL; |
1154 | goto fail; |
1057 | } |
1155 | } |
1058 | return 0; |
1156 | return 0; |
- | 1157 | fail: |
|
- | 1158 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", |
|
- | 1159 | reg, idx, idx_value); |
|
- | 1160 | return -EINVAL; |
|
1059 | } |
1161 | } |
Line 1060... | Line 1162... | ||
1060 | 1162 | ||
1061 | static int r300_packet3_check(struct radeon_cs_parser *p, |
1163 | static int r300_packet3_check(struct radeon_cs_parser *p, |
1062 | struct radeon_cs_packet *pkt) |
1164 | struct radeon_cs_packet *pkt) |
Line 1146... | Line 1248... | ||
1146 | r = r100_cs_track_check(p->rdev, track); |
1248 | r = r100_cs_track_check(p->rdev, track); |
1147 | if (r) { |
1249 | if (r) { |
1148 | return r; |
1250 | return r; |
1149 | } |
1251 | } |
1150 | break; |
1252 | break; |
- | 1253 | case PACKET3_3D_CLEAR_HIZ: |
|
- | 1254 | case PACKET3_3D_CLEAR_ZMASK: |
|
- | 1255 | if (p->rdev->hyperz_filp != p->filp) |
|
- | 1256 | return -EINVAL; |
|
- | 1257 | break; |
|
- | 1258 | case PACKET3_3D_CLEAR_CMASK: |
|
- | 1259 | if (p->rdev->cmask_filp != p->filp) |
|
- | 1260 | return -EINVAL; |
|
- | 1261 | break; |
|
1151 | case PACKET3_NOP: |
1262 | case PACKET3_NOP: |
1152 | break; |
1263 | break; |
1153 | default: |
1264 | default: |
1154 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
1265 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
1155 | return -EINVAL; |
1266 | return -EINVAL; |
Line 1162... | Line 1273... | ||
1162 | struct radeon_cs_packet pkt; |
1273 | struct radeon_cs_packet pkt; |
1163 | struct r100_cs_track *track; |
1274 | struct r100_cs_track *track; |
1164 | int r; |
1275 | int r; |
Line 1165... | Line 1276... | ||
1165 | 1276 | ||
- | 1277 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
|
- | 1278 | if (track == NULL) |
|
1166 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1279 | return -ENOMEM; |
1167 | r100_cs_track_clear(p->rdev, track); |
1280 | r100_cs_track_clear(p->rdev, track); |
1168 | p->track = track; |
1281 | p->track = track; |
1169 | do { |
1282 | do { |
1170 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
1283 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
Line 1279... | Line 1392... | ||
1279 | if (rdev->flags & RADEON_IS_PCI) { |
1392 | if (rdev->flags & RADEON_IS_PCI) { |
1280 | r = r100_pci_gart_enable(rdev); |
1393 | r = r100_pci_gart_enable(rdev); |
1281 | if (r) |
1394 | if (r) |
1282 | return r; |
1395 | return r; |
1283 | } |
1396 | } |
- | 1397 | ||
- | 1398 | ||
1284 | /* Enable IRQ */ |
1399 | /* Enable IRQ */ |
1285 | // r100_irq_set(rdev); |
1400 | // r100_irq_set(rdev); |
1286 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1401 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1287 | /* 1M ring buffer */ |
1402 | /* 1M ring buffer */ |
1288 | r = r100_cp_init(rdev, 1024 * 1024); |
1403 | r = r100_cp_init(rdev, 1024 * 1024); |
1289 | if (r) { |
1404 | if (r) { |
1290 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
1405 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1291 | return r; |
1406 | return r; |
1292 | } |
1407 | } |
1293 | // r = r100_wb_init(rdev); |
- | |
1294 | // if (r) |
- | |
1295 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
- | |
1296 | // r = r100_ib_init(rdev); |
1408 | // r = r100_ib_init(rdev); |
1297 | // if (r) { |
1409 | // if (r) { |
1298 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
1410 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
1299 | // return r; |
1411 | // return r; |
1300 | // } |
1412 | // } |
Line 1314... | Line 1426... | ||
1314 | /* Initialize scratch registers */ |
1426 | /* Initialize scratch registers */ |
1315 | radeon_scratch_init(rdev); |
1427 | radeon_scratch_init(rdev); |
1316 | /* Initialize surface registers */ |
1428 | /* Initialize surface registers */ |
1317 | radeon_surface_init(rdev); |
1429 | radeon_surface_init(rdev); |
1318 | /* TODO: disable VGA need to use VGA request */ |
1430 | /* TODO: disable VGA need to use VGA request */ |
- | 1431 | /* restore some register to sane defaults */ |
|
- | 1432 | r100_restore_sanity(rdev); |
|
1319 | /* BIOS*/ |
1433 | /* BIOS*/ |
1320 | if (!radeon_get_bios(rdev)) { |
1434 | if (!radeon_get_bios(rdev)) { |
1321 | if (ASIC_IS_AVIVO(rdev)) |
1435 | if (ASIC_IS_AVIVO(rdev)) |
1322 | return -EINVAL; |
1436 | return -EINVAL; |
1323 | } |
1437 | } |
Line 1328... | Line 1442... | ||
1328 | r = radeon_combios_init(rdev); |
1442 | r = radeon_combios_init(rdev); |
1329 | if (r) |
1443 | if (r) |
1330 | return r; |
1444 | return r; |
1331 | } |
1445 | } |
1332 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
1446 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
1333 | if (radeon_gpu_reset(rdev)) { |
1447 | if (radeon_asic_reset(rdev)) { |
1334 | dev_warn(rdev->dev, |
1448 | dev_warn(rdev->dev, |
1335 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1449 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1336 | RREG32(R_000E40_RBBM_STATUS), |
1450 | RREG32(R_000E40_RBBM_STATUS), |
1337 | RREG32(R_0007C0_CP_STAT)); |
1451 | RREG32(R_0007C0_CP_STAT)); |
1338 | } |
1452 | } |
Line 1341... | Line 1455... | ||
1341 | return -EINVAL; |
1455 | return -EINVAL; |
1342 | /* Set asic errata */ |
1456 | /* Set asic errata */ |
1343 | r300_errata(rdev); |
1457 | r300_errata(rdev); |
1344 | /* Initialize clocks */ |
1458 | /* Initialize clocks */ |
1345 | radeon_get_clock_info(rdev->ddev); |
1459 | radeon_get_clock_info(rdev->ddev); |
1346 | /* Initialize power management */ |
- | |
1347 | radeon_pm_init(rdev); |
- | |
1348 | /* initialize AGP */ |
1460 | /* initialize AGP */ |
1349 | if (rdev->flags & RADEON_IS_AGP) { |
1461 | if (rdev->flags & RADEON_IS_AGP) { |
1350 | r = radeon_agp_init(rdev); |
1462 | r = radeon_agp_init(rdev); |
1351 | if (r) { |
1463 | if (r) { |
1352 | radeon_agp_disable(rdev); |
1464 | radeon_agp_disable(rdev); |
Line 1379... | Line 1491... | ||
1379 | rdev->accel_working = true; |
1491 | rdev->accel_working = true; |
1380 | r = r300_startup(rdev); |
1492 | r = r300_startup(rdev); |
1381 | if (r) { |
1493 | if (r) { |
1382 | /* Somethings want wront with the accel init stop accel */ |
1494 | /* Somethings want wront with the accel init stop accel */ |
1383 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
1495 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
1384 | // r100_cp_fini(rdev); |
- | |
1385 | // r100_wb_fini(rdev); |
- | |
1386 | // r100_ib_fini(rdev); |
- | |
1387 | if (rdev->flags & RADEON_IS_PCIE) |
1496 | if (rdev->flags & RADEON_IS_PCIE) |
1388 | rv370_pcie_gart_fini(rdev); |
1497 | rv370_pcie_gart_fini(rdev); |
1389 | if (rdev->flags & RADEON_IS_PCI) |
1498 | if (rdev->flags & RADEON_IS_PCI) |
1390 | r100_pci_gart_fini(rdev); |
1499 | r100_pci_gart_fini(rdev); |
1391 | // radeon_agp_fini(rdev); |
- | |
1392 | rdev->accel_working = false; |
1500 | rdev->accel_working = false; |
1393 | } |
1501 | } |
1394 | return 0; |
1502 | return 0; |
1395 | }>><>><>><>><>><>><>><>>><>>><>><>>>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>> |
1503 | }>><>><>><>><>><>><>><>>><>>><>>><>><>>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>> |