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Line 34... | Line 34... | ||
34 | 34 | ||
35 | #include "r300d.h" |
35 | #include "r300d.h" |
36 | #include "rv350d.h" |
36 | #include "rv350d.h" |
Line 37... | Line 37... | ||
37 | #include "r300_reg_safe.h" |
37 | #include "r300_reg_safe.h" |
- | 38 | ||
- | 39 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 |
|
- | 40 | * |
|
- | 41 | * GPU Errata: |
|
- | 42 | * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL |
|
- | 43 | * using MMIO to flush host path read cache, this lead to HARDLOCKUP. |
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- | 44 | * However, scheduling such write to the ring seems harmless, i suspect |
|
- | 45 | * the CP read collide with the flush somehow, or maybe the MC, hard to |
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Line 38... | Line 46... | ||
38 | 46 | * tell. (Jerome Glisse) |
|
39 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */ |
47 | */ |
40 | 48 | ||
41 | /* |
49 | /* |
Line 172... | Line 180... | ||
172 | radeon_ring_write(rdev, PACKET0(0x4F18, 0)); |
180 | radeon_ring_write(rdev, PACKET0(0x4F18, 0)); |
173 | radeon_ring_write(rdev, (1 << 0)); |
181 | radeon_ring_write(rdev, (1 << 0)); |
174 | /* Wait until IDLE & CLEAN */ |
182 | /* Wait until IDLE & CLEAN */ |
175 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
183 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
176 | radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); |
184 | radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); |
- | 185 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
|
- | 186 | radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | |
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- | 187 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
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- | 188 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
|
- | 189 | radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); |
|
177 | /* Emit fence sequence & fire IRQ */ |
190 | /* Emit fence sequence & fire IRQ */ |
178 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
191 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
179 | radeon_ring_write(rdev, fence->seq); |
192 | radeon_ring_write(rdev, fence->seq); |
180 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
193 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
181 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
194 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
Line 689... | Line 702... | ||
689 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
702 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
690 | idx, reg); |
703 | idx, reg); |
691 | r100_cs_dump_packet(p, pkt); |
704 | r100_cs_dump_packet(p, pkt); |
692 | return r; |
705 | return r; |
693 | } |
706 | } |
- | 707 | ||
- | 708 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
|
- | 709 | tile_flags |= R300_TXO_MACRO_TILE; |
|
- | 710 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
|
- | 711 | tile_flags |= R300_TXO_MICRO_TILE; |
|
- | 712 | ||
694 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
713 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); |
- | 714 | tmp |= tile_flags; |
|
- | 715 | ib[idx] = tmp; |
|
695 | track->textures[i].robj = reloc->robj; |
716 | track->textures[i].robj = reloc->robj; |
696 | break; |
717 | break; |
697 | /* Tracked registers */ |
718 | /* Tracked registers */ |
698 | case 0x2084: |
719 | case 0x2084: |
699 | /* VAP_VF_CNTL */ |
720 | /* VAP_VF_CNTL */ |
Line 855... | Line 876... | ||
855 | case R300_TX_FORMAT_Y8X8: |
876 | case R300_TX_FORMAT_Y8X8: |
856 | case R300_TX_FORMAT_Z5Y6X5: |
877 | case R300_TX_FORMAT_Z5Y6X5: |
857 | case R300_TX_FORMAT_Z6Y5X5: |
878 | case R300_TX_FORMAT_Z6Y5X5: |
858 | case R300_TX_FORMAT_W4Z4Y4X4: |
879 | case R300_TX_FORMAT_W4Z4Y4X4: |
859 | case R300_TX_FORMAT_W1Z5Y5X5: |
880 | case R300_TX_FORMAT_W1Z5Y5X5: |
860 | case R300_TX_FORMAT_DXT1: |
- | |
861 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
881 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
862 | case R300_TX_FORMAT_B8G8_B8G8: |
882 | case R300_TX_FORMAT_B8G8_B8G8: |
863 | case R300_TX_FORMAT_G8R8_G8B8: |
883 | case R300_TX_FORMAT_G8R8_G8B8: |
864 | track->textures[i].cpp = 2; |
884 | track->textures[i].cpp = 2; |
865 | break; |
885 | break; |
Line 869... | Line 889... | ||
869 | case R300_TX_FORMAT_W8Z8Y8X8: |
889 | case R300_TX_FORMAT_W8Z8Y8X8: |
870 | case R300_TX_FORMAT_W2Z10Y10X10: |
890 | case R300_TX_FORMAT_W2Z10Y10X10: |
871 | case 0x17: |
891 | case 0x17: |
872 | case R300_TX_FORMAT_FL_I32: |
892 | case R300_TX_FORMAT_FL_I32: |
873 | case 0x1e: |
893 | case 0x1e: |
874 | case R300_TX_FORMAT_DXT3: |
- | |
875 | case R300_TX_FORMAT_DXT5: |
- | |
876 | track->textures[i].cpp = 4; |
894 | track->textures[i].cpp = 4; |
877 | break; |
895 | break; |
878 | case R300_TX_FORMAT_W16Z16Y16X16: |
896 | case R300_TX_FORMAT_W16Z16Y16X16: |
879 | case R300_TX_FORMAT_FL_R16G16B16A16: |
897 | case R300_TX_FORMAT_FL_R16G16B16A16: |
880 | case R300_TX_FORMAT_FL_I32A32: |
898 | case R300_TX_FORMAT_FL_I32A32: |
881 | track->textures[i].cpp = 8; |
899 | track->textures[i].cpp = 8; |
882 | break; |
900 | break; |
883 | case R300_TX_FORMAT_FL_R32G32B32A32: |
901 | case R300_TX_FORMAT_FL_R32G32B32A32: |
884 | track->textures[i].cpp = 16; |
902 | track->textures[i].cpp = 16; |
885 | break; |
903 | break; |
- | 904 | case R300_TX_FORMAT_DXT1: |
|
- | 905 | track->textures[i].cpp = 1; |
|
- | 906 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
|
- | 907 | break; |
|
- | 908 | case R300_TX_FORMAT_ATI2N: |
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- | 909 | if (p->rdev->family < CHIP_R420) { |
|
- | 910 | DRM_ERROR("Invalid texture format %u\n", |
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- | 911 | (idx_value & 0x1F)); |
|
- | 912 | return -EINVAL; |
|
- | 913 | } |
|
- | 914 | /* The same rules apply as for DXT3/5. */ |
|
- | 915 | /* Pass through. */ |
|
- | 916 | case R300_TX_FORMAT_DXT3: |
|
- | 917 | case R300_TX_FORMAT_DXT5: |
|
- | 918 | track->textures[i].cpp = 1; |
|
- | 919 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
|
- | 920 | break; |
|
886 | default: |
921 | default: |
887 | DRM_ERROR("Invalid texture format %u\n", |
922 | DRM_ERROR("Invalid texture format %u\n", |
888 | (idx_value & 0x1F)); |
923 | (idx_value & 0x1F)); |
889 | return -EINVAL; |
924 | return -EINVAL; |
890 | break; |
925 | break; |
Line 940... | Line 975... | ||
940 | if (p->rdev->family >= CHIP_RV515) { |
975 | if (p->rdev->family >= CHIP_RV515) { |
941 | tmp = ((idx_value >> 15) & 1) << 11; |
976 | tmp = ((idx_value >> 15) & 1) << 11; |
942 | track->textures[i].width_11 = tmp; |
977 | track->textures[i].width_11 = tmp; |
943 | tmp = ((idx_value >> 16) & 1) << 11; |
978 | tmp = ((idx_value >> 16) & 1) << 11; |
944 | track->textures[i].height_11 = tmp; |
979 | track->textures[i].height_11 = tmp; |
- | 980 | ||
- | 981 | /* ATI1N */ |
|
- | 982 | if (idx_value & (1 << 14)) { |
|
- | 983 | /* The same rules apply as for DXT1. */ |
|
- | 984 | track->textures[i].compress_format = |
|
- | 985 | R100_TRACK_COMP_DXT1; |
|
- | 986 | } |
|
- | 987 | } else if (idx_value & (1 << 14)) { |
|
- | 988 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); |
|
- | 989 | return -EINVAL; |
|
945 | } |
990 | } |
946 | break; |
991 | break; |
947 | case 0x4480: |
992 | case 0x4480: |
948 | case 0x4484: |
993 | case 0x4484: |
949 | case 0x4488: |
994 | case 0x4488: |
Line 981... | Line 1026... | ||
981 | r100_cs_dump_packet(p, pkt); |
1026 | r100_cs_dump_packet(p, pkt); |
982 | return r; |
1027 | return r; |
983 | } |
1028 | } |
984 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1029 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
985 | break; |
1030 | break; |
- | 1031 | case 0x4e0c: |
|
- | 1032 | /* RB3D_COLOR_CHANNEL_MASK */ |
|
- | 1033 | track->color_channel_mask = idx_value; |
|
- | 1034 | break; |
|
- | 1035 | case 0x4d1c: |
|
- | 1036 | /* ZB_BW_CNTL */ |
|
- | 1037 | track->fastfill = !!(idx_value & (1 << 2)); |
|
- | 1038 | break; |
|
- | 1039 | case 0x4e04: |
|
- | 1040 | /* RB3D_BLENDCNTL */ |
|
- | 1041 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
|
- | 1042 | break; |
|
986 | case 0x4be8: |
1043 | case 0x4be8: |
987 | /* valid register only on RV530 */ |
1044 | /* valid register only on RV530 */ |
988 | if (p->rdev->family == CHIP_RV530) |
1045 | if (p->rdev->family == CHIP_RV530) |
989 | break; |
1046 | break; |
990 | /* fallthrough do not move */ |
1047 | /* fallthrough do not move */ |
Line 1219... | Line 1276... | ||
1219 | if (r) |
1276 | if (r) |
1220 | return r; |
1277 | return r; |
1221 | } |
1278 | } |
1222 | /* Enable IRQ */ |
1279 | /* Enable IRQ */ |
1223 | // r100_irq_set(rdev); |
1280 | // r100_irq_set(rdev); |
- | 1281 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
|
1224 | /* 1M ring buffer */ |
1282 | /* 1M ring buffer */ |
1225 | // r = r100_cp_init(rdev, 1024 * 1024); |
1283 | // r = r100_cp_init(rdev, 1024 * 1024); |
1226 | // if (r) { |
1284 | // if (r) { |
1227 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
1285 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
1228 | // return r; |
1286 | // return r; |
Line 1278... | Line 1336... | ||
1278 | return -EINVAL; |
1336 | return -EINVAL; |
1279 | /* Set asic errata */ |
1337 | /* Set asic errata */ |
1280 | r300_errata(rdev); |
1338 | r300_errata(rdev); |
1281 | /* Initialize clocks */ |
1339 | /* Initialize clocks */ |
1282 | radeon_get_clock_info(rdev->ddev); |
1340 | radeon_get_clock_info(rdev->ddev); |
- | 1341 | /* Initialize power management */ |
|
- | 1342 | radeon_pm_init(rdev); |
|
1283 | /* Get vram informations */ |
1343 | /* Get vram informations */ |
1284 | r300_vram_info(rdev); |
1344 | r300_vram_info(rdev); |
1285 | /* Initialize memory controller (also test AGP) */ |
1345 | /* Initialize memory controller (also test AGP) */ |
1286 | r = r420_mc_init(rdev); |
1346 | r = r420_mc_init(rdev); |
1287 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
1347 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |